library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cuenta is port (
	clk, reset, etr, set_trgin, trigger, enable: in std_logic;
	add: in std_logic_vector(1 downto 0);
	grp: in std_logic_vector(4 downto 0);
	trg_maxcnt: in std_logic_vector(15 downto 0);
	db_out: out std_logic_vector(15 downto 0);
	end_count: out std_logic
	);
end cuenta;

architecture arch of cuenta is
signal trg_cntin: std_logic_vector(15 downto 0);

begin
end_count <= trg_cntin(15);

--trigger count in
db_out <= trg_cntin when etr='0' and grp(0)='1' and add=3 else (others => 'Z'); --3
process (clk, reset)
begin
	if reset='1' then
	  trg_cntin <= (others =>'1');
	elsif clk'event and clk='1' then
	  if set_trgin='1' then
	    trg_cntin <= trg_maxcnt;
	  elsif enable='1' and trigger='1' and trg_cntin(15)='0' then
	    trg_cntin <= trg_cntin - 1;
	  end if;
	end if;
end process;

end arch;
	
