[COREGEN.VERILOG Component Instantiation.shft16x8]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="shft16x8 YourInstanceName ("
text007="    .CLK(CLK),"
text008="    .D(D),"
text009="    .Q(Q));"
text010=""
text011=" "
type=template
[COREGEN.VHDL Component Instantiation.shft16x8]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component shft16x8"
text005="    port ("
text006="    CLK: IN std_logic;"
text007="    D: IN std_logic_VECTOR(15 downto 0);"
text008="    Q: OUT std_logic_VECTOR(15 downto 0));"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : shft16x8"
text020="        port map ("
text021="            CLK => CLK,"
text022="            D => D,"
text023="            Q => Q);"
text024=" "
type=template
