-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim ctrl_x.ngd ctrl_x_translate.vhd 
-- Input file    : ctrl_x.ngd
-- Output file   : ctrl_x_translate.vhd
-- Design name   : ctrl_x
-- # of Entities : 1
-- Xilinx        : C:/Xilinx6
-- Device        : 2s50epq208-7

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity ctrl_x is
  port (
    trgnim : in STD_LOGIC := 'X'; 
    trgttl : in STD_LOGIC := 'X'; 
    as : in STD_LOGIC := 'X'; 
    robrsttl : in STD_LOGIC := 'X'; 
    lword : in STD_LOGIC := 'X'; 
    done_in : in STD_LOGIC := 'X'; 
    ds0 : in STD_LOGIC := 'X'; 
    ds1 : in STD_LOGIC := 'X'; 
    veto : in STD_LOGIC := 'X'; 
    sysreset : in STD_LOGIC := 'X'; 
    evrsttl : in STD_LOGIC := 'X'; 
    brd_sel : in STD_LOGIC := 'X'; 
    am0 : in STD_LOGIC := 'X'; 
    am1 : in STD_LOGIC := 'X'; 
    am3 : in STD_LOGIC := 'X'; 
    am4 : in STD_LOGIC := 'X'; 
    am5 : in STD_LOGIC := 'X'; 
    fltb : in STD_LOGIC := 'X'; 
    jroberr : in STD_LOGIC := 'X'; 
    iack : in STD_LOGIC := 'X'; 
    write : in STD_LOGIC := 'X'; 
    bcrsttl : in STD_LOGIC := 'X'; 
    iackin : in STD_LOGIC := 'X'; 
    clkin_p : in STD_LOGIC := 'X'; 
    jtdo : in STD_LOGIC := 'X'; 
    tdio : inout STD_LOGIC; 
    mcevrst : out STD_LOGIC; 
    trgttc : out STD_LOGIC; 
    trg_dly_p : out STD_LOGIC; 
    g245 : out STD_LOGIC; 
    mctrg : out STD_LOGIC; 
    diftrg : out STD_LOGIC; 
    dtack : out STD_LOGIC; 
    tp1 : out STD_LOGIC; 
    tp2 : out STD_LOGIC; 
    tp3 : out STD_LOGIC; 
    jtms : out STD_LOGIC; 
    jtrkrst : out STD_LOGIC; 
    difevr : out STD_LOGIC; 
    done_out : out STD_LOGIC; 
    trganal : out STD_LOGIC; 
    difbcr : out STD_LOGIC; 
    jtrktm : out STD_LOGIC; 
    trgled : out STD_LOGIC; 
    locked : out STD_LOGIC; 
    trgros : out STD_LOGIC; 
    jtrkadv : out STD_LOGIC; 
    iackout : out STD_LOGIC; 
    jtck : out STD_LOGIC; 
    jtdi : out STD_LOGIC; 
    intled : out STD_LOGIC; 
    difrst : out STD_LOGIC; 
    mcbcrst : out STD_LOGIC; 
    int_ext : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    add_in : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    plsttl : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    db : inout STD_LOGIC_VECTOR ( 15 downto 0 ); 
    irq : out STD_LOGIC_VECTOR ( 7 downto 1 ); 
    ron : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    pulse : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    jtadd : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    delay_0 : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    delay_1 : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end ctrl_x;

architecture Structure of ctrl_x is
  signal mcevrst_OBUF : STD_LOGIC; 
  signal trgnim_IBUF : STD_LOGIC; 
  signal trgttc_OBUF : STD_LOGIC; 
  signal trg_dly_p_OBUF : STD_LOGIC; 
  signal trgttl_IBUF : STD_LOGIC; 
  signal g245_OBUF : STD_LOGIC; 
  signal as_IBUF : STD_LOGIC; 
  signal mctrg_OBUF : STD_LOGIC; 
  signal robrsttl_IBUF : STD_LOGIC; 
  signal dtack_OBUF : STD_LOGIC; 
  signal lword_IBUF : STD_LOGIC; 
  signal tp1_OBUF : STD_LOGIC; 
  signal done_in_IBUF : STD_LOGIC; 
  signal ds0_IBUFG : STD_LOGIC; 
  signal tp2_OBUF : STD_LOGIC; 
  signal ds1_IBUF : STD_LOGIC; 
  signal tp3_OBUF : STD_LOGIC; 
  signal veto_IBUF : STD_LOGIC; 
  signal sysreset_IBUF : STD_LOGIC; 
  signal v_tmrst : STD_LOGIC; 
  signal I50_N1191 : STD_LOGIC; 
  signal evrsttl_IBUF : STD_LOGIC; 
  signal done_out_OBUF : STD_LOGIC; 
  signal trganal_OBUF : STD_LOGIC; 
  signal I94_N1141 : STD_LOGIC; 
  signal ena_tm : STD_LOGIC; 
  signal locked_OBUF : STD_LOGIC; 
  signal brd_sel_IBUF : STD_LOGIC; 
  signal am0_IBUF : STD_LOGIC; 
  signal am1_IBUF : STD_LOGIC; 
  signal am3_IBUF : STD_LOGIC; 
  signal am4_IBUF : STD_LOGIC; 
  signal am5_IBUF : STD_LOGIC; 
  signal fltb_IBUF : STD_LOGIC; 
  signal jroberr_IBUF : STD_LOGIC; 
  signal v_tmadv : STD_LOGIC; 
  signal iack_IBUF : STD_LOGIC; 
  signal write_IBUF : STD_LOGIC; 
  signal U4_fr8_q : STD_LOGIC; 
  signal bcrsttl_IBUF : STD_LOGIC; 
  signal iackin_IBUF : STD_LOGIC; 
  signal intled_OBUF : STD_LOGIC; 
  signal jtdo_IBUF : STD_LOGIC; 
  signal difrst_OBUF : STD_LOGIC; 
  signal mcbcrst_OBUF : STD_LOGIC; 
  signal CLKIN : STD_LOGIC; 
  signal U6_trigger_n0000_13_cyo : STD_LOGIC; 
  signal v_robrst : STD_LOGIC; 
  signal plsttl_1_IBUF : STD_LOGIC; 
  signal plsttl_0_IBUF : STD_LOGIC; 
  signal int_ext_1_IBUF : STD_LOGIC; 
  signal ds0_clk : STD_LOGIC; 
  signal U6_trigger_n0000_14_cyo : STD_LOGIC; 
  signal U2_fr1_q : STD_LOGIC; 
  signal U3_fr1_q : STD_LOGIC; 
  signal U4_fr1_q : STD_LOGIC; 
  signal v_trg : STD_LOGIC; 
  signal reset : STD_LOGIC; 
  signal not_sysreset : STD_LOGIC; 
  signal CLK : STD_LOGIC; 
  signal add_in_0_IBUF : STD_LOGIC; 
  signal U6_trigger_n0000_18_cyo : STD_LOGIC; 
  signal CLK0 : STD_LOGIC; 
  signal irq_1_OBUF : STD_LOGIC; 
  signal N18193 : STD_LOGIC; 
  signal U2_fr2_q : STD_LOGIC; 
  signal U3_fr2_q : STD_LOGIC; 
  signal U4_fr2_q : STD_LOGIC; 
  signal set_trgin : STD_LOGIC; 
  signal v_evrst : STD_LOGIC; 
  signal trg_bypass : STD_LOGIC; 
  signal v_bcrst : STD_LOGIC; 
  signal U7_U2_M2_count_LPM_COUNTER_3_n0000_4_cyo : STD_LOGIC; 
  signal irq_7_OBUF : STD_LOGIC; 
  signal U6_trigger_n0000_28_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_29_cyo : STD_LOGIC; 
  signal Q_n0020 : STD_LOGIC; 
  signal Q_n0016 : STD_LOGIC; 
  signal Q_n0017 : STD_LOGIC; 
  signal Q_n0022 : STD_LOGIC; 
  signal irq_5_OBUF : STD_LOGIC; 
  signal Q_n0023 : STD_LOGIC; 
  signal Q_n0024 : STD_LOGIC; 
  signal Q_n0025 : STD_LOGIC; 
  signal Q_n0030 : STD_LOGIC; 
  signal Q_n0026 : STD_LOGIC; 
  signal Q_n0031 : STD_LOGIC; 
  signal Q_n0027 : STD_LOGIC; 
  signal Q_n0028 : STD_LOGIC; 
  signal irq_3_OBUF : STD_LOGIC; 
  signal Q_n0029 : STD_LOGIC; 
  signal I66_N1191 : STD_LOGIC; 
  signal U2_fr8_q : STD_LOGIC; 
  signal U3_fr8_q : STD_LOGIC; 
  signal I68_N1141 : STD_LOGIC; 
  signal N18205 : STD_LOGIC; 
  signal irq_2_OBUF : STD_LOGIC; 
  signal U6_trg_cntout_30_rt : STD_LOGIC; 
  signal U6_trigger_n0000_16_cyo : STD_LOGIC; 
  signal Q_n0047 : STD_LOGIC; 
  signal U2_fr9_q : STD_LOGIC; 
  signal add_in_6_IBUF : STD_LOGIC; 
  signal I69_N1141 : STD_LOGIC; 
  signal add_in_5_IBUF : STD_LOGIC; 
  signal add_in_4_IBUF : STD_LOGIC; 
  signal U4_fr9_q : STD_LOGIC; 
  signal add_in_3_IBUF : STD_LOGIC; 
  signal U6_S2_trg_cntin_23 : STD_LOGIC; 
  signal U3_fr9_q : STD_LOGIC; 
  signal U6_trigger_n0000_22_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_25_cyo : STD_LOGIC; 
  signal Q_n0121 : STD_LOGIC; 
  signal I95_N1141 : STD_LOGIC; 
  signal U6_trigger_n0000_19_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_20_cyo : STD_LOGIC; 
  signal U7_U2_M2_count_N6007 : STD_LOGIC; 
  signal irq_6_OBUF : STD_LOGIC; 
  signal Q_n0119 : STD_LOGIC; 
  signal pulse_1_OBUF : STD_LOGIC; 
  signal U6_trigger_n0000_24_cyo : STD_LOGIC; 
  signal U6_S2_trg_cntin_17 : STD_LOGIC; 
  signal add_in_2_IBUF : STD_LOGIC; 
  signal U6_trigger_n0000_30_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_26_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_27_cyo : STD_LOGIC; 
  signal U6_S2_trg_cntin_18 : STD_LOGIC; 
  signal U6_trigger_n0000_23_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_21_cyo : STD_LOGIC; 
  signal Q_n0090 : STD_LOGIC; 
  signal pulse_0_OBUF : STD_LOGIC; 
  signal U6_S2_trg_cntin_19 : STD_LOGIC; 
  signal I67_N1141 : STD_LOGIC; 
  signal Q_n0092 : STD_LOGIC; 
  signal int_ext_0_IBUF : STD_LOGIC; 
  signal add_in_1_IBUF : STD_LOGIC; 
  signal Q_n0093 : STD_LOGIC; 
  signal fltb_reg : STD_LOGIC; 
  signal Q_n0089 : STD_LOGIC; 
  signal U6_trigger_n0000_17_cyo : STD_LOGIC; 
  signal N18196 : STD_LOGIC; 
  signal N18202 : STD_LOGIC; 
  signal N18199 : STD_LOGIC; 
  signal irq_4_OBUF : STD_LOGIC; 
  signal U7_w_reg : STD_LOGIC; 
  signal U7_U3_rdpls : STD_LOGIC; 
  signal U6_trigger_n0000_15_cyo : STD_LOGIC; 
  signal U7_U1_M2_end_count : STD_LOGIC; 
  signal U7_n0000 : STD_LOGIC; 
  signal U7_n0001 : STD_LOGIC; 
  signal U7_U3_M2_count_LPM_COUNTER_1_n0000_2_cyo : STD_LOGIC; 
  signal U7_U3_M2_count_N6071 : STD_LOGIC; 
  signal U7_I12_N1423 : STD_LOGIC; 
  signal U7_U3_M2_count_0_4_N1306 : STD_LOGIC; 
  signal U7_U3_M2_count_N6075 : STD_LOGIC; 
  signal U7_n0006 : STD_LOGIC; 
  signal U7_I11_N1191 : STD_LOGIC; 
  signal U7_I10_N1191 : STD_LOGIC; 
  signal U7_U3_M1_end_count : STD_LOGIC; 
  signal U7_I9_N1191 : STD_LOGIC; 
  signal U7_ck_slow : STD_LOGIC; 
  signal U7_U3_rd : STD_LOGIC; 
  signal U7_read_read_q : STD_LOGIC; 
  signal U7_init_start : STD_LOGIC; 
  signal U7_write_start : STD_LOGIC; 
  signal U7_U1_init : STD_LOGIC; 
  signal U7_read_start : STD_LOGIC; 
  signal U7_U3_M2_end_count : STD_LOGIC; 
  signal U7_r_reg : STD_LOGIC; 
  signal U7_U3_M2_count_N6067 : STD_LOGIC; 
  signal U7_U3_M1_count_0_3_N1306 : STD_LOGIC; 
  signal U7_U3_M1_count_0_3_N1304 : STD_LOGIC; 
  signal U7_U3_M2_count_LPM_COUNTER_1_n0000_3_cyo : STD_LOGIC; 
  signal U7_U3_M2_count_0_4_N1304 : STD_LOGIC; 
  signal U7_ckdiv_LPM_COUNTER_8_n0000_3_cyo : STD_LOGIC; 
  signal U7_ckdiv_LPM_COUNTER_8_n0000_2_cyo : STD_LOGIC; 
  signal U7_ckdiv_LPM_COUNTER_8_n0000_1_cyo : STD_LOGIC; 
  signal N8300 : STD_LOGIC; 
  signal U7_ckdiv_LPM_COUNTER_8_n0000_0_cyo : STD_LOGIC; 
  signal U7_ckdiv_N5871 : STD_LOGIC; 
  signal U7_U1_M2_count_LPM_COUNTER_5_n0000_3_cyo : STD_LOGIC; 
  signal U7_U1_M2_count_N5941 : STD_LOGIC; 
  signal U7_U1_M2_count_N5945 : STD_LOGIC; 
  signal U7_U1_M2_count_LPM_COUNTER_5_n0000_2_cyo : STD_LOGIC; 
  signal U7_U1_M2_count_LPM_COUNTER_5_n0000_1_cyo : STD_LOGIC; 
  signal U7_U1_M1_end_count : STD_LOGIC; 
  signal U7_U1_M2_count_N5937 : STD_LOGIC; 
  signal U7_U1_init_read : STD_LOGIC; 
  signal U7_U1_M1_count_N5922 : STD_LOGIC; 
  signal U7_U1_M1_count_N5918 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_8_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_0_10_N1306 : STD_LOGIC; 
  signal U7_U1_M1_count_0_10_N1304 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_9_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_7_cyo : STD_LOGIC; 
  signal U7_U1_M2_count_LPM_COUNTER_5_n0000_0_cyo : STD_LOGIC; 
  signal U7_U3_M2_count_LPM_COUNTER_1_n0000_1_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_0_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_N5890 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_1_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_N5894 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_2_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_N5898 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_3_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_N5902 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_4_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_N5906 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_5_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_N5910 : STD_LOGIC; 
  signal U7_U1_M1_count_LPM_COUNTER_6_n0000_6_cyo : STD_LOGIC; 
  signal U7_U1_M1_count_N5914 : STD_LOGIC; 
  signal U7_U1_M2_count_N5957 : STD_LOGIC; 
  signal U7_U1_M2_count_N5953 : STD_LOGIC; 
  signal U7_U1_M2_count_LPM_COUNTER_5_n0000_5_cyo : STD_LOGIC; 
  signal U7_U1_M2_count_0_7_N1306 : STD_LOGIC; 
  signal U7_U1_M2_count_0_7_N1304 : STD_LOGIC; 
  signal U7_U1_M2_count_LPM_COUNTER_5_n0000_6_cyo : STD_LOGIC; 
  signal U7_U1_M2_count_LPM_COUNTER_5_n0000_4_cyo : STD_LOGIC; 
  signal U7_U1_M2_count_N5949 : STD_LOGIC; 
  signal U7_U2_M2_count_LPM_COUNTER_3_n0000_3_cyo : STD_LOGIC; 
  signal U7_U2_M2_count_N6003 : STD_LOGIC; 
  signal U7_U2_M2_count_LPM_COUNTER_3_n0000_2_cyo : STD_LOGIC; 
  signal U7_U2_M2_count_N5999 : STD_LOGIC; 
  signal U7_U2_M2_count_LPM_COUNTER_3_n0000_1_cyo : STD_LOGIC; 
  signal U7_U2_M2_count_N5995 : STD_LOGIC; 
  signal U7_U2_w1 : STD_LOGIC; 
  signal U7_U2_M1_end_count : STD_LOGIC; 
  signal U7_U2_M2_end_count : STD_LOGIC; 
  signal U7_U2_w0 : STD_LOGIC; 
  signal U7_U2_M1_count_N5980 : STD_LOGIC; 
  signal U7_U2_M1_count_N5976 : STD_LOGIC; 
  signal U7_U2_M1_count_LPM_COUNTER_4_n0000_2_cyo : STD_LOGIC; 
  signal U7_U2_M1_count_0_4_N1306 : STD_LOGIC; 
  signal U7_U2_M1_count_0_4_N1304 : STD_LOGIC; 
  signal U7_U2_M1_count_LPM_COUNTER_4_n0000_3_cyo : STD_LOGIC; 
  signal U7_U2_M1_count_LPM_COUNTER_4_n0000_1_cyo : STD_LOGIC; 
  signal U7_U2_M2_count_LPM_COUNTER_3_n0000_0_cyo : STD_LOGIC; 
  signal U7_U3_M2_count_LPM_COUNTER_1_n0000_0_cyo : STD_LOGIC; 
  signal U7_U2_M1_count_LPM_COUNTER_4_n0000_0_cyo : STD_LOGIC; 
  signal U7_U2_M1_count_N5972 : STD_LOGIC; 
  signal U7_U2_M2_count_N6015 : STD_LOGIC; 
  signal U7_U2_M2_count_N6011 : STD_LOGIC; 
  signal U7_U2_M2_count_LPM_COUNTER_3_n0000_5_cyo : STD_LOGIC; 
  signal U7_U2_M2_count_0_7_N1306 : STD_LOGIC; 
  signal U7_U2_M2_count_0_7_N1304 : STD_LOGIC; 
  signal U7_U2_M2_count_LPM_COUNTER_3_n0000_6_cyo : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_2 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_1 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_2 : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_1 : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_4 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_5 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_4 : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_5 : STD_LOGIC; 
  signal U5_I10_N1141 : STD_LOGIC; 
  signal U5_n0011 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_3 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_7 : STD_LOGIC; 
  signal U5_I11_N1141 : STD_LOGIC; 
  signal U5_n0009 : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_7 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_3 : STD_LOGIC; 
  signal U5_n0022 : STD_LOGIC; 
  signal U5_n0023 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_6 : STD_LOGIC; 
  signal U5_n0024 : STD_LOGIC; 
  signal U5_n0030 : STD_LOGIC; 
  signal U5_n0025 : STD_LOGIC; 
  signal U5_n0027 : STD_LOGIC; 
  signal U5_q0_0 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_6 : STD_LOGIC; 
  signal U5_q0_1 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_6 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_5 : STD_LOGIC; 
  signal U5_q1_0 : STD_LOGIC; 
  signal U5_q1_1 : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_6 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_7 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_4 : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_3 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_3 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_2 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_3 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_2 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_1 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_2 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_1 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_0 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_1 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_0 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_0 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_6 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_7 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_2 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_7 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_3 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_4 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_5 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_4 : STD_LOGIC; 
  signal U5_conta_1_inst_lut3_5 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_6 : STD_LOGIC; 
  signal U5_conta_0_inst_sum_0 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_1 : STD_LOGIC; 
  signal U5_conta_0_inst_lut3_0 : STD_LOGIC; 
  signal U5_conta_0_inst_cy_0 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_4 : STD_LOGIC; 
  signal U5_conta_1_inst_sum_5 : STD_LOGIC; 
  signal U5_conta_1_inst_cy_7 : STD_LOGIC; 
  signal U7_U4_n0003 : STD_LOGIC; 
  signal U7_U4_crc_in : STD_LOGIC; 
  signal U7_U4_n0007 : STD_LOGIC; 
  signal U7_U4_n0014 : STD_LOGIC; 
  signal U7_U4_n0004 : STD_LOGIC; 
  signal U7_U4_n0008 : STD_LOGIC; 
  signal U7_U4_n0006 : STD_LOGIC; 
  signal U7_U4_n0005 : STD_LOGIC; 
  signal U7_U4_n0009 : STD_LOGIC; 
  signal U7_U4_n0002 : STD_LOGIC; 
  signal U7_U4_n0001 : STD_LOGIC; 
  signal set_trgin_rt : STD_LOGIC; 
  signal U1_d_esc : STD_LOGIC; 
  signal U1_ena_d : STD_LOGIC; 
  signal U1_fq1_q : STD_LOGIC; 
  signal U1_ds_rst : STD_LOGIC; 
  signal U1_not_ds0 : STD_LOGIC; 
  signal U1_fq2_q : STD_LOGIC; 
  signal U1_fds_q : STD_LOGIC; 
  signal U1_d_lec : STD_LOGIC; 
  signal U1_fq8_q : STD_LOGIC; 
  signal U1_fq5_q : STD_LOGIC; 
  signal U1_fq4_q : STD_LOGIC; 
  signal U4_fr4_q : STD_LOGIC; 
  signal U4_s1 : STD_LOGIC; 
  signal U4_fr5_q : STD_LOGIC; 
  signal U4_fr7_q : STD_LOGIC; 
  signal U4_fr6_q : STD_LOGIC; 
  signal U4_s3 : STD_LOGIC; 
  signal U4_fr3_q : STD_LOGIC; 
  signal U4_s2 : STD_LOGIC; 
  signal U3_fr4_q : STD_LOGIC; 
  signal U3_s1 : STD_LOGIC; 
  signal U3_fr5_q : STD_LOGIC; 
  signal U3_fr7_q : STD_LOGIC; 
  signal U3_fr6_q : STD_LOGIC; 
  signal U3_s3 : STD_LOGIC; 
  signal U3_s2 : STD_LOGIC; 
  signal U2_fr4_q : STD_LOGIC; 
  signal U2_s1 : STD_LOGIC; 
  signal U2_fr5_q : STD_LOGIC; 
  signal U2_fr7_q : STD_LOGIC; 
  signal U2_fr6_q : STD_LOGIC; 
  signal U2_s3 : STD_LOGIC; 
  signal U2_s2 : STD_LOGIC; 
  signal N18280 : STD_LOGIC; 
  signal U6_N13972 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_20 : STD_LOGIC; 
  signal U6_N13953 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_23 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_12 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_14 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_12 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_13 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_22 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_20 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_23 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_13 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_21 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_11 : STD_LOGIC; 
  signal U6_S2_I1_N1141 : STD_LOGIC; 
  signal U6_S2_n0005 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_22 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_24 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_15 : STD_LOGIC; 
  signal U6_S2_trg_cntin_22 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_16 : STD_LOGIC; 
  signal U6_S2_trg_cntin_16 : STD_LOGIC; 
  signal U6_S2_trg_cntin_20 : STD_LOGIC; 
  signal U6_S2_trg_cntin_21 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_16 : STD_LOGIC; 
  signal U6_q_in : STD_LOGIC; 
  signal U6_tr_0 : STD_LOGIC; 
  signal U6_tr_1 : STD_LOGIC; 
  signal U6_tr_2 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_21 : STD_LOGIC; 
  signal U6_n0001 : STD_LOGIC; 
  signal U6_n0002 : STD_LOGIC; 
  signal U6_n0004 : STD_LOGIC; 
  signal U6_n0005 : STD_LOGIC; 
  signal U6_n0010 : STD_LOGIC; 
  signal U6_n0006 : STD_LOGIC; 
  signal U6_n0011 : STD_LOGIC; 
  signal U6_n0007 : STD_LOGIC; 
  signal U6_n0012 : STD_LOGIC; 
  signal U6_n0008 : STD_LOGIC; 
  signal U6_n0013 : STD_LOGIC; 
  signal U6_n0009 : STD_LOGIC; 
  signal U6_n0014 : STD_LOGIC; 
  signal U6_n0015 : STD_LOGIC; 
  signal U6_n0016 : STD_LOGIC; 
  signal U6_n0021 : STD_LOGIC; 
  signal U6_n0017 : STD_LOGIC; 
  signal U6_n0022 : STD_LOGIC; 
  signal U6_n0018 : STD_LOGIC; 
  signal U6_n0023 : STD_LOGIC; 
  signal U6_n0019 : STD_LOGIC; 
  signal U6_n0024 : STD_LOGIC; 
  signal U6_n0025 : STD_LOGIC; 
  signal U6_n0030 : STD_LOGIC; 
  signal U6_n0026 : STD_LOGIC; 
  signal U6_n0031 : STD_LOGIC; 
  signal U6_n0027 : STD_LOGIC; 
  signal U6_n0032 : STD_LOGIC; 
  signal U6_n0028 : STD_LOGIC; 
  signal U6_n0033 : STD_LOGIC; 
  signal U6_n0029 : STD_LOGIC; 
  signal U6_n0034 : STD_LOGIC; 
  signal U6_n0035 : STD_LOGIC; 
  signal U6_n0040 : STD_LOGIC; 
  signal U6_n0036 : STD_LOGIC; 
  signal U6_n0041 : STD_LOGIC; 
  signal U6_n0042 : STD_LOGIC; 
  signal U6_n0038 : STD_LOGIC; 
  signal U6_n0043 : STD_LOGIC; 
  signal U6_n0039 : STD_LOGIC; 
  signal U6_n0044 : STD_LOGIC; 
  signal U6_n0045 : STD_LOGIC; 
  signal U6_n0050 : STD_LOGIC; 
  signal U6_n0046 : STD_LOGIC; 
  signal U6_n0051 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_9 : STD_LOGIC; 
  signal U6_n0047 : STD_LOGIC; 
  signal U6_n0052 : STD_LOGIC; 
  signal U6_n0048 : STD_LOGIC; 
  signal U6_n0053 : STD_LOGIC; 
  signal U6_n0049 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_15 : STD_LOGIC; 
  signal U6_n0055 : STD_LOGIC; 
  signal U6_n0060 : STD_LOGIC; 
  signal U6_n0056 : STD_LOGIC; 
  signal U6_n0061 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_21 : STD_LOGIC; 
  signal U6_n0057 : STD_LOGIC; 
  signal U6_n0062 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_16 : STD_LOGIC; 
  signal U6_n0058 : STD_LOGIC; 
  signal U6_n0063 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_18 : STD_LOGIC; 
  signal U6_n0059 : STD_LOGIC; 
  signal U6_n0064 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_10 : STD_LOGIC; 
  signal U6_n0065 : STD_LOGIC; 
  signal U6_n0070 : STD_LOGIC; 
  signal U6_n0066 : STD_LOGIC; 
  signal U6_I77_N1141 : STD_LOGIC; 
  signal U6_n0067 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_12 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_14 : STD_LOGIC; 
  signal U6_I75_N1141 : STD_LOGIC; 
  signal U6_v_0 : STD_LOGIC; 
  signal U6_n0068 : STD_LOGIC; 
  signal U6_n0178 : STD_LOGIC; 
  signal U6_v_1 : STD_LOGIC; 
  signal U6_n0069 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_19 : STD_LOGIC; 
  signal U6_I76_N1141 : STD_LOGIC; 
  signal U6_I74_N1141 : STD_LOGIC; 
  signal U6_I78_N1141 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_18 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_23 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_8 : STD_LOGIC; 
  signal U6_I73_N1141 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_20 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_9 : STD_LOGIC; 
  signal U6_n0127 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_10 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_13 : STD_LOGIC; 
  signal U6_n0195 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_8 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_11 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_10 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_9 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_22 : STD_LOGIC; 
  signal U6_n0144 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_17 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_14 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_19 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_15 : STD_LOGIC; 
  signal U6_n0161 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_17 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_cy_19 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_sum_17 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_18 : STD_LOGIC; 
  signal U6_S2_trg_cntin_inst_lut3_11 : STD_LOGIC; 
  signal U6_N6090 : STD_LOGIC; 
  signal U6_trigger_n0000_0_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_1_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_2_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_3_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_4_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_5_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_6_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_7_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_8_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_9_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_10_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_11_cyo : STD_LOGIC; 
  signal U6_trigger_n0000_12_cyo : STD_LOGIC; 
  signal N16332 : STD_LOGIC; 
  signal CHOICE134 : STD_LOGIC; 
  signal N18300 : STD_LOGIC; 
  signal CHOICE168 : STD_LOGIC; 
  signal N18246 : STD_LOGIC; 
  signal U7_ckdiv_4_rt : STD_LOGIC; 
  signal N18296 : STD_LOGIC; 
  signal N18308 : STD_LOGIC; 
  signal N18292 : STD_LOGIC; 
  signal CHOICE182 : STD_LOGIC; 
  signal CHOICE196 : STD_LOGIC; 
  signal N17042 : STD_LOGIC; 
  signal N18318 : STD_LOGIC; 
  signal N18288 : STD_LOGIC; 
  signal N18304 : STD_LOGIC; 
  signal N18322 : STD_LOGIC; 
  signal N17009 : STD_LOGIC; 
  signal CHOICE178 : STD_LOGIC; 
  signal CHOICE192 : STD_LOGIC; 
  signal CHOICE206 : STD_LOGIC; 
  signal N18249 : STD_LOGIC; 
  signal CHOICE117 : STD_LOGIC; 
  signal N18251 : STD_LOGIC; 
  signal CHOICE210 : STD_LOGIC; 
  signal N18276 : STD_LOGIC; 
  signal N17449 : STD_LOGIC; 
  signal CHOICE163 : STD_LOGIC; 
  signal CHOICE146 : STD_LOGIC; 
  signal N18312 : STD_LOGIC; 
  signal N18253 : STD_LOGIC; 
  signal CHOICE114 : STD_LOGIC; 
  signal CHOICE129 : STD_LOGIC; 
  signal N18255 : STD_LOGIC; 
  signal CHOICE151 : STD_LOGIC; 
  signal N18284 : STD_LOGIC; 
  signal CHOICE346 : STD_LOGIC; 
  signal CHOICE336 : STD_LOGIC; 
  signal U6_trg_cntout_31_rt : STD_LOGIC; 
  signal CHOICE297 : STD_LOGIC; 
  signal CHOICE306 : STD_LOGIC; 
  signal CHOICE332 : STD_LOGIC; 
  signal CHOICE251 : STD_LOGIC; 
  signal CHOICE286 : STD_LOGIC; 
  signal CHOICE321 : STD_LOGIC; 
  signal CHOICE266 : STD_LOGIC; 
  signal CHOICE339 : STD_LOGIC; 
  signal CHOICE348 : STD_LOGIC; 
  signal CHOICE331 : STD_LOGIC; 
  signal CHOICE256 : STD_LOGIC; 
  signal CHOICE277 : STD_LOGIC; 
  signal CHOICE317 : STD_LOGIC; 
  signal CHOICE343 : STD_LOGIC; 
  signal CHOICE324 : STD_LOGIC; 
  signal N18098 : STD_LOGIC; 
  signal N18100 : STD_LOGIC; 
  signal N18102 : STD_LOGIC; 
  signal N18104 : STD_LOGIC; 
  signal N18106 : STD_LOGIC; 
  signal N18108 : STD_LOGIC; 
  signal N18110 : STD_LOGIC; 
  signal N18112 : STD_LOGIC; 
  signal N18114 : STD_LOGIC; 
  signal N18116 : STD_LOGIC; 
  signal N18118 : STD_LOGIC; 
  signal N18120 : STD_LOGIC; 
  signal N18122 : STD_LOGIC; 
  signal N18124 : STD_LOGIC; 
  signal N18126 : STD_LOGIC; 
  signal N18128 : STD_LOGIC; 
  signal N18130 : STD_LOGIC; 
  signal U7_ckdiv_Q_1_rt : STD_LOGIC; 
  signal U7_ckdiv_Q_2_rt : STD_LOGIC; 
  signal U7_ckdiv_Q_3_rt : STD_LOGIC; 
  signal U7_U1_M1_count_Q_0_rt : STD_LOGIC; 
  signal U7_U1_M2_count_Q_0_rt : STD_LOGIC; 
  signal U7_U2_M1_count_Q_0_rt : STD_LOGIC; 
  signal U7_U2_M2_count_Q_0_rt : STD_LOGIC; 
  signal U7_U3_M2_count_Q_0_rt : STD_LOGIC; 
  signal U6_trg_cntout_1_rt : STD_LOGIC; 
  signal U6_trg_cntout_2_rt : STD_LOGIC; 
  signal U6_trg_cntout_3_rt : STD_LOGIC; 
  signal U6_trg_cntout_4_rt : STD_LOGIC; 
  signal U6_trg_cntout_5_rt : STD_LOGIC; 
  signal U6_trg_cntout_6_rt : STD_LOGIC; 
  signal U6_trg_cntout_7_rt : STD_LOGIC; 
  signal U6_trg_cntout_8_rt : STD_LOGIC; 
  signal U6_trg_cntout_9_rt : STD_LOGIC; 
  signal U6_trg_cntout_10_rt : STD_LOGIC; 
  signal U6_trg_cntout_11_rt : STD_LOGIC; 
  signal U6_trg_cntout_12_rt : STD_LOGIC; 
  signal U6_trg_cntout_13_rt : STD_LOGIC; 
  signal U6_trg_cntout_14_rt : STD_LOGIC; 
  signal U6_trg_cntout_15_rt : STD_LOGIC; 
  signal U6_trg_cntout_16_rt : STD_LOGIC; 
  signal U6_trg_cntout_17_rt : STD_LOGIC; 
  signal U6_trg_cntout_18_rt : STD_LOGIC; 
  signal U6_trg_cntout_19_rt : STD_LOGIC; 
  signal U6_trg_cntout_20_rt : STD_LOGIC; 
  signal U6_trg_cntout_21_rt : STD_LOGIC; 
  signal U6_trg_cntout_22_rt : STD_LOGIC; 
  signal U6_trg_cntout_23_rt : STD_LOGIC; 
  signal U6_trg_cntout_24_rt : STD_LOGIC; 
  signal U6_trg_cntout_25_rt : STD_LOGIC; 
  signal U6_trg_cntout_26_rt : STD_LOGIC; 
  signal U6_trg_cntout_27_rt : STD_LOGIC; 
  signal U6_trg_cntout_28_rt : STD_LOGIC; 
  signal U6_trg_cntout_29_rt : STD_LOGIC; 
  signal set_trgin_1 : STD_LOGIC; 
  signal set_trgin_2 : STD_LOGIC; 
  signal reset1_1 : STD_LOGIC; 
  signal reset1_2 : STD_LOGIC; 
  signal N18357 : STD_LOGIC; 
  signal N18359 : STD_LOGIC; 
  signal N18361 : STD_LOGIC; 
  signal N18394 : STD_LOGIC; 
  signal jtag_reg_1_1 : STD_LOGIC; 
  signal ena_tm_1 : STD_LOGIC; 
  signal jtag_reg_0_1 : STD_LOGIC; 
  signal jtag_reg_2_1 : STD_LOGIC; 
  signal ron_reg_6_1 : STD_LOGIC; 
  signal ron_reg_5_1 : STD_LOGIC; 
  signal ron_reg_4_1 : STD_LOGIC; 
  signal ron_reg_3_1 : STD_LOGIC; 
  signal ron_reg_2_1 : STD_LOGIC; 
  signal ron_reg_1_1 : STD_LOGIC; 
  signal ron_reg_0_1 : STD_LOGIC; 
  signal jtag_reg_6_1 : STD_LOGIC; 
  signal jtag_reg_5_1 : STD_LOGIC; 
  signal jtag_reg_4_1 : STD_LOGIC; 
  signal jtag_reg_3_1 : STD_LOGIC; 
  signal U5_pulse_reg0_6_1 : STD_LOGIC; 
  signal U5_pulse_reg0_5_1 : STD_LOGIC; 
  signal U5_pulse_reg0_4_1 : STD_LOGIC; 
  signal U5_pulse_reg0_3_1 : STD_LOGIC; 
  signal U5_pulse_reg0_2_1 : STD_LOGIC; 
  signal U5_pulse_reg0_1_1 : STD_LOGIC; 
  signal U5_pulse_reg0_0_1 : STD_LOGIC; 
  signal U5_pulse_reg1_6_1 : STD_LOGIC; 
  signal U5_pulse_reg1_5_1 : STD_LOGIC; 
  signal U5_pulse_reg1_4_1 : STD_LOGIC; 
  signal U5_pulse_reg1_3_1 : STD_LOGIC; 
  signal U5_pulse_reg1_2_1 : STD_LOGIC; 
  signal U5_pulse_reg1_1_1 : STD_LOGIC; 
  signal U5_pulse_reg1_0_1 : STD_LOGIC; 
  signal U6_tr_dly26_O : STD_LOGIC; 
  signal U6_tr_dly80_O : STD_LOGIC; 
  signal U6_Ker14000_SW1_O : STD_LOGIC; 
  signal U6_Ker14000_SW2_O : STD_LOGIC; 
  signal U6_n00051_O : STD_LOGIC; 
  signal U6_n00061_O : STD_LOGIC; 
  signal U6_n00081_O : STD_LOGIC; 
  signal U6_n00091_O : STD_LOGIC; 
  signal U6_n00101_O : STD_LOGIC; 
  signal U6_n00111_O : STD_LOGIC; 
  signal U6_n00121_O : STD_LOGIC; 
  signal U6_n00131_O : STD_LOGIC; 
  signal U6_n00141_O : STD_LOGIC; 
  signal U6_n00151_O : STD_LOGIC; 
  signal U6_n00161_O : STD_LOGIC; 
  signal U6_n00171_O : STD_LOGIC; 
  signal U6_n00181_O : STD_LOGIC; 
  signal U6_n00191_O : STD_LOGIC; 
  signal U6_n00221_O : STD_LOGIC; 
  signal U6_n00231_O : STD_LOGIC; 
  signal U6_n00241_O : STD_LOGIC; 
  signal U6_n00261_O : STD_LOGIC; 
  signal U6_n00271_O : STD_LOGIC; 
  signal U6_n00281_O : STD_LOGIC; 
  signal U6_n00291_O : STD_LOGIC; 
  signal U6_n00301_O : STD_LOGIC; 
  signal U6_n00311_O : STD_LOGIC; 
  signal U6_n00321_O : STD_LOGIC; 
  signal U6_n00331_O : STD_LOGIC; 
  signal U6_n00341_O : STD_LOGIC; 
  signal U6_n00351_O : STD_LOGIC; 
  signal U6_n00251_O : STD_LOGIC; 
  signal U6_n00041_O : STD_LOGIC; 
  signal U6_n00071_O : STD_LOGIC; 
  signal U6_n00211_O : STD_LOGIC; 
  signal U6_n00361_O : STD_LOGIC; 
  signal U6_S1_F0_N0 : STD_LOGIC; 
  signal U6_S1_F0_N1 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal ron_reg_5_GSR_OR : STD_LOGIC; 
  signal ron_reg_4_GSR_OR : STD_LOGIC; 
  signal ron_reg_3_GSR_OR : STD_LOGIC; 
  signal ron_reg_2_GSR_OR : STD_LOGIC; 
  signal int_vec_2_2_GSR_OR : STD_LOGIC; 
  signal int_vec_2_4_GSR_OR : STD_LOGIC; 
  signal int_vec_2_5_GSR_OR : STD_LOGIC; 
  signal int_vec_2_3_GSR_OR : STD_LOGIC; 
  signal int_vec_2_6_GSR_OR : STD_LOGIC; 
  signal int_vec_1_0_GSR_OR : STD_LOGIC; 
  signal int_lev_2_0_GSR_OR : STD_LOGIC; 
  signal int_ena_0_GSR_OR : STD_LOGIC; 
  signal int_ena_1_GSR_OR : STD_LOGIC; 
  signal U7_U3_M1_count_2_GSR_OR : STD_LOGIC; 
  signal U7_U3_M1_count_3_GSR_OR : STD_LOGIC; 
  signal int_lev_1_1_GSR_OR : STD_LOGIC; 
  signal int_lev_0_0_GSR_OR : STD_LOGIC; 
  signal int_lev_0_1_GSR_OR : STD_LOGIC; 
  signal int_vec_2_0_GSR_OR : STD_LOGIC; 
  signal int_vec_2_1_GSR_OR : STD_LOGIC; 
  signal int_lev_1_0_GSR_OR : STD_LOGIC; 
  signal int_lev_2_1_GSR_OR : STD_LOGIC; 
  signal U1_fq1_q_GSR_OR : STD_LOGIC; 
  signal int_ena_2_GSR_OR : STD_LOGIC; 
  signal trg_bypass_GSR_OR : STD_LOGIC; 
  signal ena_tm_GSR_OR : STD_LOGIC; 
  signal fltb_reg_GSR_OR : STD_LOGIC; 
  signal int_lev_0_2_GSR_OR : STD_LOGIC; 
  signal int_lev_1_2_GSR_OR : STD_LOGIC; 
  signal int_lev_2_2_GSR_OR : STD_LOGIC; 
  signal int_vec_0_7_GSR_OR : STD_LOGIC; 
  signal int_vec_1_7_GSR_OR : STD_LOGIC; 
  signal int_vec_2_7_GSR_OR : STD_LOGIC; 
  signal ron_reg_6_GSR_OR : STD_LOGIC; 
  signal jtag_reg_6_GSR_OR : STD_LOGIC; 
  signal v_bcrst_GSR_OR : STD_LOGIC; 
  signal v_trg_GSR_OR : STD_LOGIC; 
  signal v_robrst_GSR_OR : STD_LOGIC; 
  signal v_evrst_GSR_OR : STD_LOGIC; 
  signal v_pulse_0_GSR_OR : STD_LOGIC; 
  signal v_pulse_1_GSR_OR : STD_LOGIC; 
  signal v_tmadv_GSR_OR : STD_LOGIC; 
  signal v_tmrst_GSR_OR : STD_LOGIC; 
  signal set_trgin_GSR_OR : STD_LOGIC; 
  signal ron_reg_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_0_GSR_OR : STD_LOGIC; 
  signal jtag_reg_5_GSR_OR : STD_LOGIC; 
  signal jtag_reg_4_GSR_OR : STD_LOGIC; 
  signal jtag_reg_3_GSR_OR : STD_LOGIC; 
  signal jtag_reg_2_GSR_OR : STD_LOGIC; 
  signal jtag_reg_1_GSR_OR : STD_LOGIC; 
  signal jtag_reg_0_GSR_OR : STD_LOGIC; 
  signal int_vec_0_6_GSR_OR : STD_LOGIC; 
  signal int_vec_0_5_GSR_OR : STD_LOGIC; 
  signal int_vec_0_4_GSR_OR : STD_LOGIC; 
  signal int_vec_0_3_GSR_OR : STD_LOGIC; 
  signal int_vec_0_2_GSR_OR : STD_LOGIC; 
  signal int_vec_0_1_GSR_OR : STD_LOGIC; 
  signal int_vec_0_0_GSR_OR : STD_LOGIC; 
  signal int_vec_1_6_GSR_OR : STD_LOGIC; 
  signal int_vec_1_5_GSR_OR : STD_LOGIC; 
  signal int_vec_1_4_GSR_OR : STD_LOGIC; 
  signal int_vec_1_3_GSR_OR : STD_LOGIC; 
  signal int_vec_1_2_GSR_OR : STD_LOGIC; 
  signal int_vec_1_1_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_0_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_0_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_3_GSR_OR : STD_LOGIC; 
  signal U7_w_reg_GSR_OR : STD_LOGIC; 
  signal U7_r_reg_GSR_OR : STD_LOGIC; 
  signal U7_read_read_q_GSR_OR : STD_LOGIC; 
  signal U7_ckdiv_4_GSR_OR : STD_LOGIC; 
  signal U7_ckdiv_0_GSR_OR : STD_LOGIC; 
  signal U7_ckdiv_1_GSR_OR : STD_LOGIC; 
  signal U7_ckdiv_2_GSR_OR : STD_LOGIC; 
  signal U7_ckdiv_3_GSR_OR : STD_LOGIC; 
  signal U7_U1_init_read_GSR_OR : STD_LOGIC; 
  signal U7_U1_init_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_2_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_7_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_3_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_8_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_1_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_10_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_9_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_0_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_1_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_2_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_3_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_4_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_5_GSR_OR : STD_LOGIC; 
  signal U7_U1_M1_count_6_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_5_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_4_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_7_GSR_OR : STD_LOGIC; 
  signal U7_U1_M2_count_6_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_2_GSR_OR : STD_LOGIC; 
  signal U7_U2_M1_count_1_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_3_GSR_OR : STD_LOGIC; 
  signal U7_U2_w1_GSR_OR : STD_LOGIC; 
  signal U7_U2_w0_GSR_OR : STD_LOGIC; 
  signal U7_U2_M1_count_2_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_1_GSR_OR : STD_LOGIC; 
  signal U7_U2_M1_count_4_GSR_OR : STD_LOGIC; 
  signal U7_U2_M1_count_3_GSR_OR : STD_LOGIC; 
  signal U7_U2_M1_count_0_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_5_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_4_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_7_GSR_OR : STD_LOGIC; 
  signal U7_U2_M2_count_6_GSR_OR : STD_LOGIC; 
  signal U7_U3_rd_GSR_OR : STD_LOGIC; 
  signal U7_U3_rdpls_GSR_OR : STD_LOGIC; 
  signal U7_U3_M2_count_3_GSR_OR : STD_LOGIC; 
  signal U7_U3_M1_count_0_GSR_OR : STD_LOGIC; 
  signal U7_U3_M2_count_0_GSR_OR : STD_LOGIC; 
  signal U7_U3_M1_count_1_GSR_OR : STD_LOGIC; 
  signal U7_U3_M2_count_4_GSR_OR : STD_LOGIC; 
  signal U7_U3_M2_count_1_GSR_OR : STD_LOGIC; 
  signal U7_U3_M2_count_2_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_13_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_12_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_6_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_11_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_5_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_10_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_9_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_8_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_7_GSR_OR : STD_LOGIC; 
  signal U5_ps1_0_GSR_OR : STD_LOGIC; 
  signal U5_ps2_0_GSR_OR : STD_LOGIC; 
  signal U5_ps2_1_GSR_OR : STD_LOGIC; 
  signal U5_ps1_1_GSR_OR : STD_LOGIC; 
  signal U5_q1_1_GSR_OR : STD_LOGIC; 
  signal U5_q1_0_GSR_OR : STD_LOGIC; 
  signal U5_q0_1_GSR_OR : STD_LOGIC; 
  signal U5_q0_0_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_13_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_0_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_2_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_3_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_4_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_5_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_6_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_7_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_8_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_9_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_10_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_11_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_12_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_0_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_2_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_3_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_4_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_5_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_6_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_7_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_4_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_0_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_1_GSR_OR : STD_LOGIC; 
  signal U7_U4_crc_reg_2_GSR_OR : STD_LOGIC; 
  signal U1_fds_q_GSR_OR : STD_LOGIC; 
  signal U1_fq5_q_GSR_OR : STD_LOGIC; 
  signal U1_fq2_q_GSR_OR : STD_LOGIC; 
  signal U4_fr4_q_GSR_OR : STD_LOGIC; 
  signal U4_fr9_q_GSR_OR : STD_LOGIC; 
  signal U4_fr7_q_GSR_OR : STD_LOGIC; 
  signal U4_fr3_q_GSR_OR : STD_LOGIC; 
  signal U4_fr2_q_GSR_OR : STD_LOGIC; 
  signal U4_fr1_q_GSR_OR : STD_LOGIC; 
  signal U4_fr5_q_GSR_OR : STD_LOGIC; 
  signal U4_fr6_q_GSR_OR : STD_LOGIC; 
  signal U3_fr4_q_GSR_OR : STD_LOGIC; 
  signal U3_fr9_q_GSR_OR : STD_LOGIC; 
  signal U3_fr7_q_GSR_OR : STD_LOGIC; 
  signal U3_fr2_q_GSR_OR : STD_LOGIC; 
  signal U3_fr1_q_GSR_OR : STD_LOGIC; 
  signal U3_fr5_q_GSR_OR : STD_LOGIC; 
  signal U3_fr6_q_GSR_OR : STD_LOGIC; 
  signal U2_fr4_q_GSR_OR : STD_LOGIC; 
  signal U2_fr9_q_GSR_OR : STD_LOGIC; 
  signal U2_fr7_q_GSR_OR : STD_LOGIC; 
  signal U2_fr2_q_GSR_OR : STD_LOGIC; 
  signal U2_fr1_q_GSR_OR : STD_LOGIC; 
  signal U2_fr5_q_GSR_OR : STD_LOGIC; 
  signal U2_fr6_q_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_14_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_13_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_12_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_4_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_11_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_5_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_10_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_8_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_6_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_7_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_8_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_9_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_10_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_11_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_12_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_13_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_14_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_0_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_1_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_2_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_3_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_4_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_5_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_6_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_5_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_7_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_6_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_7_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_8_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_9_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_4_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_3_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_2_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_1_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_0_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_10_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_9_GSR_OR : STD_LOGIC; 
  signal U6_q_in_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_0_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_1_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_2_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_3_GSR_OR : STD_LOGIC; 
  signal U6_tr_0_GSR_OR : STD_LOGIC; 
  signal U6_tr_1_GSR_OR : STD_LOGIC; 
  signal U6_v_0_GSR_OR : STD_LOGIC; 
  signal U6_v_1_GSR_OR : STD_LOGIC; 
  signal U6_trg_delay_15_GSR_OR : STD_LOGIC; 
  signal U6_trg_maxcnt_15_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_31_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_30_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_29_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_28_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_27_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_26_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_25_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_24_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_23_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_22_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_21_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_20_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_19_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_18_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_17_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_16_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_15_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_14_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_13_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_12_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_11_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_10_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_9_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_8_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_7_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_6_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_5_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_4_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_3_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_2_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_1_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntout_0_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_31_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_30_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_29_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_28_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_27_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_26_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_25_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_24_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_23_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_22_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_21_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_20_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_19_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_18_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_17_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_16_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_15_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_14_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_13_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_12_GSR_OR : STD_LOGIC; 
  signal U6_trg_cntoutreg_11_GSR_OR : STD_LOGIC; 
  signal set_trgin_1_GSR_OR : STD_LOGIC; 
  signal set_trgin_2_GSR_OR : STD_LOGIC; 
  signal jtag_reg_1_1_GSR_OR : STD_LOGIC; 
  signal ena_tm_1_GSR_OR : STD_LOGIC; 
  signal jtag_reg_0_1_GSR_OR : STD_LOGIC; 
  signal jtag_reg_2_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_6_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_5_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_4_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_3_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_2_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_1_1_GSR_OR : STD_LOGIC; 
  signal ron_reg_0_1_GSR_OR : STD_LOGIC; 
  signal jtag_reg_6_1_GSR_OR : STD_LOGIC; 
  signal jtag_reg_5_1_GSR_OR : STD_LOGIC; 
  signal jtag_reg_4_1_GSR_OR : STD_LOGIC; 
  signal jtag_reg_3_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_6_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_5_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_4_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_3_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_2_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_1_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg0_0_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_6_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_5_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_4_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_3_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_2_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_1_1_GSR_OR : STD_LOGIC; 
  signal U5_pulse_reg1_0_1_GSR_OR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal db_0_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_1_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_2_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_3_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_4_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_5_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_6_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_7_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_8_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal tdio_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_9_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_10_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_11_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_12_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_13_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_14_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal db_15_IOBUF_OBUFT_GTS_AND : STD_LOGIC; 
  signal delay_1_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_1_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_1_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_1_4_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_1_5_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_1_6_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_0_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_0_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_1_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal mcevrst_OBUF_GTS_TRI : STD_LOGIC; 
  signal trgttc_OBUF_GTS_TRI : STD_LOGIC; 
  signal trg_dly_p_OBUF_GTS_TRI : STD_LOGIC; 
  signal g245_OBUF_GTS_TRI : STD_LOGIC; 
  signal mctrg_OBUF_GTS_TRI : STD_LOGIC; 
  signal diftrg_OBUF_GTS_TRI : STD_LOGIC; 
  signal dtack_OBUF_GTS_TRI : STD_LOGIC; 
  signal tp1_OBUF_GTS_TRI : STD_LOGIC; 
  signal tp2_OBUF_GTS_TRI : STD_LOGIC; 
  signal tp3_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtms_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtrkrst_OBUF_GTS_TRI : STD_LOGIC; 
  signal difevr_OBUF_GTS_TRI : STD_LOGIC; 
  signal done_out_OBUF_GTS_TRI : STD_LOGIC; 
  signal trganal_OBUF_GTS_TRI : STD_LOGIC; 
  signal difbcr_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtrktm_OBUF_GTS_TRI : STD_LOGIC; 
  signal trgled_OBUF_GTS_TRI : STD_LOGIC; 
  signal locked_OBUF_GTS_TRI : STD_LOGIC; 
  signal trgros_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtrkadv_OBUF_GTS_TRI : STD_LOGIC; 
  signal iackout_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtck_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtdi_OBUF_GTS_TRI : STD_LOGIC; 
  signal intled_OBUF_GTS_TRI : STD_LOGIC; 
  signal difrst_OBUF_GTS_TRI : STD_LOGIC; 
  signal mcbcrst_OBUF_GTS_TRI : STD_LOGIC; 
  signal irq_7_OBUF_GTS_TRI : STD_LOGIC; 
  signal irq_6_OBUF_GTS_TRI : STD_LOGIC; 
  signal irq_5_OBUF_GTS_TRI : STD_LOGIC; 
  signal irq_4_OBUF_GTS_TRI : STD_LOGIC; 
  signal irq_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal irq_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal irq_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal ron_6_OBUF_GTS_TRI : STD_LOGIC; 
  signal ron_5_OBUF_GTS_TRI : STD_LOGIC; 
  signal ron_4_OBUF_GTS_TRI : STD_LOGIC; 
  signal ron_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal ron_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal ron_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal ron_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal pulse_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal pulse_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtadd_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtadd_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtadd_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal jtadd_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_0_6_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_0_5_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_0_4_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_0_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal delay_0_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal U8_GTS_IN : STD_LOGIC; 
  signal NlwInverterSignal_I95_0_T : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwInverterSignal_I69_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I70_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I88_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I87_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I86_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I85_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I93_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I84_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I83_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I82_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I92_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I91_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I90_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I81_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I80_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I79_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I78_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I89_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I77_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I76_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I75_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I74_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I73_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I72_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I71_0_T : STD_LOGIC; 
  signal NlwInverterSignal_add_int_1_C : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NlwInverterSignal_add_int_0_C : STD_LOGIC; 
  signal NlwInverterSignal_grp_4_C : STD_LOGIC; 
  signal NlwInverterSignal_grp_3_C : STD_LOGIC; 
  signal NlwInverterSignal_grp_2_C : STD_LOGIC; 
  signal NlwInverterSignal_grp_1_C : STD_LOGIC; 
  signal NLW_U11_CLK90_UNCONNECTED : STD_LOGIC; 
  signal NLW_U11_CLK180_UNCONNECTED : STD_LOGIC; 
  signal NLW_U11_CLK270_UNCONNECTED : STD_LOGIC; 
  signal NLW_U11_CLK2X_UNCONNECTED : STD_LOGIC; 
  signal NLW_U11_CLKDV_UNCONNECTED : STD_LOGIC; 
  signal NLW_U11_CLK2X180_UNCONNECTED : STD_LOGIC; 
  signal NlwInverterSignal_add_int_2_C : STD_LOGIC; 
  signal NlwInverterSignal_I51_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I52_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I53_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I54_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I55_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I56_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I57_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I58_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I59_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I60_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I61_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I62_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I63_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I64_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I65_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I66_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_0_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_15_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_14_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_13_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_12_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_11_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_10_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_9_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_8_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_7_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_6_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_5_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_4_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_3_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_2_T : STD_LOGIC; 
  signal NlwInverterSignal_I95_1_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_15_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_14_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_13_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_12_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_11_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_10_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_9_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_8_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_7_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_6_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_5_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_4_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_3_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_2_T : STD_LOGIC; 
  signal NlwInverterSignal_I94_1_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_15_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_14_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_13_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_12_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_11_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_10_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_9_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_8_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_7_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_6_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_5_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_4_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_3_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_2_T : STD_LOGIC; 
  signal NlwInverterSignal_I69_1_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_15_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_14_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_13_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_12_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_11_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_10_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_9_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_8_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_7_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_6_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_5_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_4_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_3_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_2_T : STD_LOGIC; 
  signal NlwInverterSignal_I68_1_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_15_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_14_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_13_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_12_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_11_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_10_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_9_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_8_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_7_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_6_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_5_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_4_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_3_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_2_T : STD_LOGIC; 
  signal NlwInverterSignal_I67_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_7_T : STD_LOGIC; 
  signal NlwInverterSignal_grp_0_C : STD_LOGIC; 
  signal NlwInverterSignal_U7_I12_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I11_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U7_I10_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I11_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U5_I10_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I78_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I77_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I76_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I75_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_6_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_5_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I74_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_I73_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_1_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_4_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_2_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_3_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_0_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_15_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_14_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_13_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_12_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_11_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_10_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_9_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_8_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_7_T : STD_LOGIC; 
  signal NlwInverterSignal_U6_S2_I1_6_T : STD_LOGIC; 
  signal NlwInverterSignal_db_0_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_0_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_1_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_1_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_2_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_2_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_3_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_3_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_4_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_4_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_5_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_5_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_6_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_6_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_7_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_7_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_8_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_8_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tdio_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tdio_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_9_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_9_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_10_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_10_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_11_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_11_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_12_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_12_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_13_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_13_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_14_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_14_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_db_15_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_db_15_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_delay_1_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_1_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_1_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_1_4_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_1_5_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_1_6_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_0_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_0_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_1_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_mcevrst_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_trgttc_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_trg_dly_p_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_g245_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_mctrg_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_diftrg_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_dtack_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tp1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tp2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_tp3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtms_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtrkrst_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_difevr_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_done_out_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_trganal_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_difbcr_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtrktm_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_trgled_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_locked_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_trgros_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtrkadv_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_iackout_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtck_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtdi_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_intled_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_difrst_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_mcbcrst_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_irq_7_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_irq_6_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_irq_5_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_irq_4_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_irq_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_irq_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_irq_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_ron_6_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_ron_5_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_ron_4_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_ron_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_ron_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_ron_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_ron_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_pulse_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_pulse_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtadd_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtadd_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtadd_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_jtadd_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_0_6_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_0_5_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_0_4_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_0_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_delay_0_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal grp : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U5_pulse_reg1 : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal jtag_reg : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal v_pulse : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal int_lev_0 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal int_vec_1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal db_out : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal int_lev_2 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U5_pulse_reg0 : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal int_vec_2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U6_S2_trg_cntin : STD_LOGIC_VECTOR ( 15 downto 8 ); 
  signal int_vec_0 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal ron_reg : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Q_n0019 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U7_U2_M2_count_n0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal int_ena : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal add_int : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal etr_ivec : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal int_lev_1 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U7_U3_M2_count_n0000 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U7_U3_M2_count : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U7_U4_crc_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U7_U2_M2_count : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U7_U3_M1_count : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U7_ckdiv : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U7_U3_M1_count_n0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U7_ckdiv_n0000 : STD_LOGIC_VECTOR ( 4 downto 1 ); 
  signal U7_U1_M1_count : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal U7_U1_M1_count_n0000 : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal U7_U1_M2_count : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U7_U1_M2_count_n0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U7_U2_M1_count : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U7_U2_M1_count_n0000 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U5_conta_0 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U5_conta_1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U5_ps1 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U5_ps2 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U5_psync : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U5_pulse_in : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U6_trg_maxcnt : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U6_trg_cntout : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U6_n0000 : STD_LOGIC_VECTOR ( 31 downto 1 ); 
  signal U6_trg_cntoutreg : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U6_trg_shift : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U6_trg_delay : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  XST_GND : X_ZERO
    port map (
      O => tp3_OBUF
    );
  Mmux_n0019_Result_2_1 : X_LUT4
    generic map(
      INIT => X"DC10"
    )
    port map (
      ADR0 => U4_fr9_q,
      ADR1 => Q_n0020,
      ADR2 => int_ena(2),
      ADR3 => N18102,
      O => Q_n0019(2)
    );
  I95_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_0_T,
      O => db_out(15)
    );
  irq_4_32 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => U2_fr9_q,
      ADR1 => int_lev_0(0),
      ADR2 => int_lev_0(1),
      ADR3 => int_lev_0(2),
      O => CHOICE168
    );
  not_sysreset1 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => sysreset_IBUF,
      O => not_sysreset,
      ADR1 => GND
    );
  U6_S2_trg_cntin_inst_sum_16_0 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_16,
      I1 => U6_S2_trg_cntin_inst_cy_17,
      O => U6_S2_trg_cntin_inst_sum_16
    );
  U6_S2_trg_cntin_inst_lut3_171 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(9),
      ADR2 => U6_S2_trg_cntin_17,
      O => U6_S2_trg_cntin_inst_lut3_17
    );
  I69_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I69_0_T,
      O => db_out(15)
    );
  I70_0 : X_TRI
    port map (
      I => int_vec_0(7),
      CTL => NlwInverterSignal_I70_0_T,
      O => db_out(7)
    );
  I88_0 : X_TRI
    port map (
      I => int_vec_2(5),
      CTL => NlwInverterSignal_I88_0_T,
      O => db_out(5)
    );
  I94_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_0_T,
      O => db_out(15)
    );
  I87_0 : X_TRI
    port map (
      I => int_vec_2(6),
      CTL => NlwInverterSignal_I87_0_T,
      O => db_out(6)
    );
  I86_0 : X_TRI
    port map (
      I => int_vec_2(7),
      CTL => NlwInverterSignal_I86_0_T,
      O => db_out(7)
    );
  I85_0 : X_TRI
    port map (
      I => int_vec_1(0),
      CTL => NlwInverterSignal_I85_0_T,
      O => db_out(0)
    );
  I93_0 : X_TRI
    port map (
      I => int_vec_2(0),
      CTL => NlwInverterSignal_I93_0_T,
      O => db_out(0)
    );
  I84_0 : X_TRI
    port map (
      I => int_vec_1(1),
      CTL => NlwInverterSignal_I84_0_T,
      O => db_out(1)
    );
  I83_0 : X_TRI
    port map (
      I => int_vec_1(2),
      CTL => NlwInverterSignal_I83_0_T,
      O => db_out(2)
    );
  I82_0 : X_TRI
    port map (
      I => int_vec_1(3),
      CTL => NlwInverterSignal_I82_0_T,
      O => db_out(3)
    );
  I92_0 : X_TRI
    port map (
      I => int_vec_2(1),
      CTL => NlwInverterSignal_I92_0_T,
      O => db_out(1)
    );
  I91_0 : X_TRI
    port map (
      I => int_vec_2(2),
      CTL => NlwInverterSignal_I91_0_T,
      O => db_out(2)
    );
  I90_0 : X_TRI
    port map (
      I => int_vec_2(3),
      CTL => NlwInverterSignal_I90_0_T,
      O => db_out(3)
    );
  I81_0 : X_TRI
    port map (
      I => int_vec_1(4),
      CTL => NlwInverterSignal_I81_0_T,
      O => db_out(4)
    );
  I80_0 : X_TRI
    port map (
      I => int_vec_1(5),
      CTL => NlwInverterSignal_I80_0_T,
      O => db_out(5)
    );
  I79_0 : X_TRI
    port map (
      I => int_vec_1(6),
      CTL => NlwInverterSignal_I79_0_T,
      O => db_out(6)
    );
  I78_0 : X_TRI
    port map (
      I => int_vec_1(7),
      CTL => NlwInverterSignal_I78_0_T,
      O => db_out(7)
    );
  I89_0 : X_TRI
    port map (
      I => int_vec_2(4),
      CTL => NlwInverterSignal_I89_0_T,
      O => db_out(4)
    );
  I77_0 : X_TRI
    port map (
      I => int_vec_0(0),
      CTL => NlwInverterSignal_I77_0_T,
      O => db_out(0)
    );
  I76_0 : X_TRI
    port map (
      I => int_vec_0(1),
      CTL => NlwInverterSignal_I76_0_T,
      O => db_out(1)
    );
  I75_0 : X_TRI
    port map (
      I => int_vec_0(2),
      CTL => NlwInverterSignal_I75_0_T,
      O => db_out(2)
    );
  I74_0 : X_TRI
    port map (
      I => int_vec_0(3),
      CTL => NlwInverterSignal_I74_0_T,
      O => db_out(3)
    );
  ron_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => Q_n0016,
      RST => ron_reg_5_GSR_OR,
      CLK => CLK,
      O => ron_reg(5),
      SET => GND
    );
  ron_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0016,
      RST => ron_reg_4_GSR_OR,
      CLK => CLK,
      O => ron_reg(4),
      SET => GND
    );
  ron_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0016,
      RST => ron_reg_3_GSR_OR,
      CLK => CLK,
      O => ron_reg(3),
      SET => GND
    );
  Q_n01211 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => fltb_IBUF,
      O => Q_n0121,
      ADR1 => GND
    );
  Q_n01191 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => jroberr_IBUF,
      O => Q_n0119,
      ADR1 => GND
    );
  ron_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => Q_n0016,
      RST => ron_reg_2_GSR_OR,
      CLK => CLK,
      O => ron_reg(2),
      SET => GND
    );
  Q_n00931 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => grp(2),
      ADR2 => add_int(0),
      ADR3 => add_int(1),
      O => Q_n0093
    );
  Q_n00921 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => grp(2),
      ADR2 => add_int(1),
      ADR3 => tp2_OBUF,
      O => Q_n0092
    );
  U7_U3_M2_count_4_N13041 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_rd,
      O => U7_U3_M2_count_0_4_N1304,
      ADR1 => GND
    );
  Q_n00891 : X_LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      ADR0 => N18357,
      ADR1 => fltb_IBUF,
      O => Q_n0089
    );
  int_vec_2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => Q_n0093,
      RST => int_vec_2_2_GSR_OR,
      CLK => CLK,
      O => int_vec_2(2),
      SET => GND
    );
  I73_0 : X_TRI
    port map (
      I => int_vec_0(4),
      CTL => NlwInverterSignal_I73_0_T,
      O => db_out(4)
    );
  I72_0 : X_TRI
    port map (
      I => int_vec_0(5),
      CTL => NlwInverterSignal_I72_0_T,
      O => db_out(5)
    );
  I71_0 : X_TRI
    port map (
      I => int_vec_0(6),
      CTL => NlwInverterSignal_I71_0_T,
      O => db_out(6)
    );
  int_vec_2_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0093,
      RST => int_vec_2_4_GSR_OR,
      CLK => CLK,
      O => int_vec_2(4),
      SET => GND
    );
  int_vec_2_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => Q_n0093,
      RST => int_vec_2_5_GSR_OR,
      CLK => CLK,
      O => int_vec_2(5),
      SET => GND
    );
  int_vec_2_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0093,
      RST => int_vec_2_3_GSR_OR,
      CLK => CLK,
      O => int_vec_2(3),
      SET => GND
    );
  int_vec_2_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => Q_n0093,
      RST => int_vec_2_6_GSR_OR,
      CLK => CLK,
      O => int_vec_2(6),
      SET => GND
    );
  I50_N11911 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => U1_fq5_q,
      ADR1 => U2_fr1_q,
      ADR2 => U3_fr1_q,
      ADR3 => U4_fr1_q,
      O => I50_N1191
    );
  int_vec_1_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => Q_n0092,
      RST => int_vec_1_0_GSR_OR,
      CLK => CLK,
      O => int_vec_1(0),
      SET => GND
    );
  add_int_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => add_in_1_IBUF,
      CLK => NlwInverterSignal_add_int_1_C,
      O => add_int(1),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  int_lev_2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18114,
      CE => Q_n0093,
      RST => int_lev_2_0_GSR_OR,
      CLK => CLK,
      O => int_lev_2(0),
      SET => GND
    );
  Q_n0018_0_11 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => add_in_2_IBUF,
      ADR1 => add_in_6_IBUF,
      ADR2 => add_in_5_IBUF,
      ADR3 => add_in_4_IBUF,
      O => N18193
    );
  Q_n0018_1_11 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => add_in_2_IBUF,
      ADR1 => add_in_4_IBUF,
      ADR2 => add_in_6_IBUF,
      ADR3 => add_in_5_IBUF,
      O => N18196
    );
  Q_n0018_2_11 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => add_in_3_IBUF,
      ADR1 => add_in_4_IBUF,
      ADR2 => add_in_6_IBUF,
      ADR3 => add_in_5_IBUF,
      O => N18199
    );
  int_ena_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0019(0),
      RST => int_ena_0_GSR_OR,
      CLK => CLK,
      O => int_ena(0),
      CE => VCC,
      SET => GND
    );
  int_ena_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0019(1),
      RST => int_ena_1_GSR_OR,
      CLK => CLK,
      O => int_ena(1),
      CE => VCC,
      SET => GND
    );
  Q_n00171 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => grp(3),
      ADR2 => add_int(0),
      ADR3 => add_int(1),
      O => Q_n0017
    );
  Q_n00161 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => grp(3),
      ADR2 => add_int(1),
      ADR3 => tp2_OBUF,
      O => Q_n0016
    );
  Q_n00471 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => add_int(1),
      ADR2 => tp2_OBUF,
      ADR3 => grp(3),
      O => Q_n0047
    );
  U7_U3_M1_count_LPM_COUNTER_2_n0000_1_xor11 : X_LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      ADR0 => U7_U3_M1_count(1),
      ADR1 => U7_U3_M1_count(0),
      O => U7_U3_M1_count_n0000(1)
    );
  U7_U3_M1_count_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U3_M1_count_n0000(2),
      CE => U7_U3_M1_count_0_3_N1306,
      SET => U7_U3_M1_count_2_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M1_count(2),
      RST => GND
    );
  U7_U3_M1_count_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U3_M1_count_n0000(3),
      CE => U7_U3_M1_count_0_3_N1306,
      RST => U7_U3_M1_count_3_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M1_count(3),
      SET => GND
    );
  U6_trg_cntout_29_rt_1 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(29),
      O => U6_trg_cntout_29_rt,
      ADR1 => GND
    );
  add_int_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => add_in_0_IBUF,
      CLK => NlwInverterSignal_add_int_0_C,
      O => add_int(0),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  int_lev_1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18118,
      CE => Q_n0092,
      RST => int_lev_1_1_GSR_OR,
      CLK => CLK,
      O => int_lev_1(1),
      SET => GND
    );
  int_lev_0_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18114,
      CE => Q_n0090,
      RST => int_lev_0_0_GSR_OR,
      CLK => CLK,
      O => int_lev_0(0),
      SET => GND
    );
  int_lev_0_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18118,
      CE => Q_n0090,
      RST => int_lev_0_1_GSR_OR,
      CLK => CLK,
      O => int_lev_0(1),
      SET => GND
    );
  int_vec_2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => Q_n0093,
      RST => int_vec_2_0_GSR_OR,
      CLK => CLK,
      O => int_vec_2(0),
      SET => GND
    );
  int_vec_2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => Q_n0093,
      RST => int_vec_2_1_GSR_OR,
      CLK => CLK,
      O => int_vec_2(1),
      SET => GND
    );
  I66_N11911 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => grp(0),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => U1_fq5_q,
      O => I66_N1191
    );
  Q_n00311 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18114,
      O => Q_n0031
    );
  Q_n00301 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18112,
      O => Q_n0030
    );
  Q_n00291 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18110,
      O => Q_n0029
    );
  Q_n00281 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18108,
      O => Q_n0028
    );
  Q_n00271 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18106,
      O => Q_n0027
    );
  Q_n00261 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18104,
      O => Q_n0026
    );
  Q_n00251 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18102,
      O => Q_n0025
    );
  Q_n00241 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18100,
      O => Q_n0024
    );
  Q_n00231 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0047,
      ADR1 => N18098,
      O => Q_n0023
    );
  Q_n00221 : X_LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      ADR0 => N18108,
      ADR1 => Q_n0020,
      O => Q_n0022
    );
  U7_U3_M2_count_4_N13061 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_M2_count(4),
      O => U7_U3_M2_count_0_4_N1306,
      ADR1 => GND
    );
  grp_4 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18205,
      SRST => add_in_2_IBUF,
      CLK => NlwInverterSignal_grp_4_C,
      O => grp(4),
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  grp_3 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18202,
      SRST => add_in_4_IBUF,
      CLK => NlwInverterSignal_grp_3_C,
      O => grp(3),
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  Q_n00901 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => grp(2),
      O => Q_n0090
    );
  U7_n00001 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => grp(4),
      O => U7_n0000
    );
  grp_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18199,
      SRST => add_in_2_IBUF,
      CLK => NlwInverterSignal_grp_2_C,
      O => grp(2),
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  grp_1 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18196,
      SRST => add_in_3_IBUF,
      CLK => NlwInverterSignal_grp_1_C,
      O => grp(1),
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_4_xor : X_XOR2
    port map (
      I0 => N18246,
      I1 => U7_U3_M2_count_LPM_COUNTER_1_n0000_3_cyo,
      O => U7_U3_M2_count_n0000(4)
    );
  reset1 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0020,
      ADR1 => N18122,
      O => reset
    );
  intled1 : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => U3_fr9_q,
      ADR1 => U4_fr9_q,
      ADR2 => U2_fr9_q,
      O => intled_OBUF
    );
  done_out1 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => done_in_IBUF,
      O => done_out_OBUF,
      ADR1 => GND
    );
  mcevrst1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => v_evrst,
      ADR1 => evrsttl_IBUF,
      O => mcevrst_OBUF
    );
  difrst1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => v_robrst,
      ADR1 => robrsttl_IBUF,
      O => difrst_OBUF
    );
  mcbcrst1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => v_bcrst,
      ADR1 => bcrsttl_IBUF,
      O => mcbcrst_OBUF
    );
  Q_n0018_3_11 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => add_in_2_IBUF,
      ADR1 => add_in_6_IBUF,
      ADR2 => add_in_5_IBUF,
      ADR3 => add_in_3_IBUF,
      O => N18202
    );
  int_lev_1_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18114,
      CE => Q_n0092,
      RST => int_lev_1_0_GSR_OR,
      CLK => CLK,
      O => int_lev_1(0),
      SET => GND
    );
  int_lev_2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18118,
      CE => Q_n0093,
      RST => int_lev_2_1_GSR_OR,
      CLK => CLK,
      O => int_lev_2(1),
      SET => GND
    );
  U7_U2_M1_count_4_N130611 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M1_count(4),
      O => N18253,
      ADR1 => GND
    );
  irq_5_33_SW0 : X_LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      ADR0 => int_lev_1(1),
      ADR1 => int_lev_1(2),
      ADR2 => U3_fr9_q,
      O => N18308
    );
  irq_3_33 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => int_lev_1(0),
      ADR1 => N18288,
      ADR2 => CHOICE182,
      ADR3 => CHOICE178,
      O => irq_3_OBUF
    );
  irq_1_44 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => int_lev_1(0),
      ADR1 => N18292,
      ADR2 => CHOICE134,
      ADR3 => CHOICE129,
      O => irq_1_OBUF
    );
  irq_5_23 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => int_lev_0(0),
      ADR1 => U2_fr9_q,
      ADR2 => int_lev_0(1),
      ADR3 => int_lev_0(2),
      O => CHOICE196
    );
  irq_2_32 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => U2_fr9_q,
      ADR1 => int_lev_0(2),
      ADR2 => int_lev_0(0),
      ADR3 => int_lev_0(1),
      O => CHOICE151
    );
  irq_5_15 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => int_lev_2(0),
      ADR1 => U4_fr9_q,
      ADR2 => int_lev_2(1),
      ADR3 => int_lev_2(2),
      O => CHOICE192
    );
  U10 : X_CKBUF
    port map (
      I => clkin_p,
      O => CLKIN
    );
  U11 : X_CLKDLLE
    port map (
      CLKIN => CLKIN,
      CLKFB => CLK,
      RST => tp3_OBUF,
      CLK0 => CLK0,
      CLK90 => NLW_U11_CLK90_UNCONNECTED,
      CLK180 => NLW_U11_CLK180_UNCONNECTED,
      CLK270 => NLW_U11_CLK270_UNCONNECTED,
      CLK2X => NLW_U11_CLK2X_UNCONNECTED,
      CLKDV => NLW_U11_CLKDV_UNCONNECTED,
      LOCKED => locked_OBUF,
      CLK2X180 => NLW_U11_CLK2X180_UNCONNECTED
    );
  U12 : X_CKBUF
    port map (
      I => CLK0,
      O => CLK
    );
  U13 : X_CKBUF
    port map (
      I => ds0_IBUFG,
      O => ds0_clk
    );
  U1_fq1_q_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U1_d_esc,
      RST => U1_fq1_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U1_fq1_q
    );
  U2_s145 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => int_lev_0(0),
      ADR2 => add_int(2),
      ADR3 => int_lev_0(2),
      O => CHOICE317
    );
  U3_s145 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => int_lev_1(0),
      ADR2 => add_int(2),
      ADR3 => int_lev_1(2),
      O => CHOICE277
    );
  U6_tr_dly54 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U6_trg_shift(3),
      ADR1 => U6_trg_delay(3),
      ADR2 => U6_trg_shift(2),
      ADR3 => U6_trg_delay(2),
      O => CHOICE339
    );
  U5_conta_0_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_0,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(0)
    );
  U6_n00011 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => grp(0),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => tp2_OBUF,
      O => U6_n0001
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_3_xor : X_XOR2
    port map (
      I0 => U7_U3_M2_count_N6075,
      I1 => U7_U3_M2_count_LPM_COUNTER_1_n0000_2_cyo,
      O => U7_U3_M2_count_n0000(3)
    );
  add_int_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => add_in_2_IBUF,
      CLK => NlwInverterSignal_add_int_2_C,
      O => add_int(2),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  trgttc1 : X_LUT3
    generic map(
      INIT => X"4F"
    )
    port map (
      ADR0 => U6_q_in,
      ADR1 => trg_bypass,
      ADR2 => trg_dly_p_OBUF,
      O => trgttc_OBUF
    );
  int_ena_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0019(2),
      RST => int_ena_2_GSR_OR,
      CLK => CLK,
      O => int_ena(2),
      CE => VCC,
      SET => GND
    );
  trg_bypass_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0020,
      RST => trg_bypass_GSR_OR,
      CLK => CLK,
      O => trg_bypass,
      SET => GND
    );
  ena_tm_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0020,
      RST => ena_tm_GSR_OR,
      CLK => CLK,
      O => ena_tm,
      SET => GND
    );
  fltb_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0022,
      CE => Q_n0089,
      RST => fltb_reg_GSR_OR,
      CLK => CLK,
      O => fltb_reg,
      SET => GND
    );
  int_lev_0_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18120,
      CE => Q_n0090,
      RST => int_lev_0_2_GSR_OR,
      CLK => CLK,
      O => int_lev_0(2),
      SET => GND
    );
  int_lev_1_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18120,
      CE => Q_n0092,
      RST => int_lev_1_2_GSR_OR,
      CLK => CLK,
      O => int_lev_1(2),
      SET => GND
    );
  int_lev_2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18120,
      CE => Q_n0093,
      RST => int_lev_2_2_GSR_OR,
      CLK => CLK,
      O => int_lev_2(2),
      SET => GND
    );
  int_vec_0_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18112,
      CE => Q_n0090,
      RST => int_vec_0_7_GSR_OR,
      CLK => CLK,
      O => int_vec_0(7),
      SET => GND
    );
  int_vec_1_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18112,
      CE => Q_n0092,
      RST => int_vec_1_7_GSR_OR,
      CLK => CLK,
      O => int_vec_1(7),
      SET => GND
    );
  int_vec_2_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18112,
      CE => Q_n0093,
      RST => int_vec_2_7_GSR_OR,
      CLK => CLK,
      O => int_vec_2(7),
      SET => GND
    );
  ron_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => Q_n0016,
      RST => ron_reg_6_GSR_OR,
      CLK => CLK,
      O => ron_reg(6),
      SET => GND
    );
  jtag_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => Q_n0017,
      RST => jtag_reg_6_GSR_OR,
      CLK => CLK,
      O => jtag_reg(6),
      SET => GND
    );
  v_bcrst_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0023,
      RST => v_bcrst_GSR_OR,
      CLK => CLK,
      O => v_bcrst,
      CE => VCC,
      SET => GND
    );
  v_trg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0024,
      RST => v_trg_GSR_OR,
      CLK => CLK,
      O => v_trg,
      CE => VCC,
      SET => GND
    );
  v_robrst_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0025,
      RST => v_robrst_GSR_OR,
      CLK => CLK,
      O => v_robrst,
      CE => VCC,
      SET => GND
    );
  v_evrst_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0026,
      RST => v_evrst_GSR_OR,
      CLK => CLK,
      O => v_evrst,
      CE => VCC,
      SET => GND
    );
  v_pulse_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0027,
      RST => v_pulse_0_GSR_OR,
      CLK => CLK,
      O => v_pulse(0),
      CE => VCC,
      SET => GND
    );
  v_pulse_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0028,
      RST => v_pulse_1_GSR_OR,
      CLK => CLK,
      O => v_pulse(1),
      CE => VCC,
      SET => GND
    );
  v_tmadv_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0029,
      RST => v_tmadv_GSR_OR,
      CLK => CLK,
      O => v_tmadv,
      CE => VCC,
      SET => GND
    );
  v_tmrst_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0030,
      RST => v_tmrst_GSR_OR,
      CLK => CLK,
      O => v_tmrst,
      CE => VCC,
      SET => GND
    );
  set_trgin_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0031,
      RST => set_trgin_GSR_OR,
      CLK => CLK,
      O => set_trgin,
      CE => VCC,
      SET => GND
    );
  I51_0 : X_TRI
    port map (
      I => int_ena(2),
      CTL => NlwInverterSignal_I51_0_T,
      O => db_out(2)
    );
  I52_0 : X_TRI
    port map (
      I => int_ena(1),
      CTL => NlwInverterSignal_I52_0_T,
      O => db_out(1)
    );
  I53_0 : X_TRI
    port map (
      I => int_ena(0),
      CTL => NlwInverterSignal_I53_0_T,
      O => db_out(0)
    );
  I54_0 : X_TRI
    port map (
      I => trg_bypass,
      CTL => NlwInverterSignal_I54_0_T,
      O => db_out(3)
    );
  I55_0 : X_TRI
    port map (
      I => ena_tm,
      CTL => NlwInverterSignal_I55_0_T,
      O => db_out(4)
    );
  I56_0 : X_TRI
    port map (
      I => Q_n0119,
      CTL => NlwInverterSignal_I56_0_T,
      O => db_out(7)
    );
  I57_0 : X_TRI
    port map (
      I => Q_n0121,
      CTL => NlwInverterSignal_I57_0_T,
      O => db_out(6)
    );
  I58_0 : X_TRI
    port map (
      I => fltb_reg,
      CTL => NlwInverterSignal_I58_0_T,
      O => db_out(5)
    );
  I59_0 : X_TRI
    port map (
      I => U6_S2_trg_cntin_23,
      CTL => NlwInverterSignal_I59_0_T,
      O => db_out(10)
    );
  I60_0 : X_TRI
    port map (
      I => int_ext_1_IBUF,
      CTL => NlwInverterSignal_I60_0_T,
      O => db_out(9)
    );
  I61_0 : X_TRI
    port map (
      I => int_ext_0_IBUF,
      CTL => NlwInverterSignal_I61_0_T,
      O => db_out(8)
    );
  I62_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I62_0_T,
      O => db_out(15)
    );
  I63_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I63_0_T,
      O => db_out(14)
    );
  I64_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I64_0_T,
      O => db_out(13)
    );
  I65_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I65_0_T,
      O => db_out(12)
    );
  I66_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I66_0_T,
      O => db_out(11)
    );
  I67_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I67_0_T,
      O => db_out(15)
    );
  I68_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I68_0_T,
      O => db_out(15)
    );
  I95_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(3),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => U1_fq5_q,
      O => I95_N1141
    );
  I95_15 : X_TRI
    port map (
      I => jtag_reg(0),
      CTL => NlwInverterSignal_I95_15_T,
      O => db_out(0)
    );
  I95_14 : X_TRI
    port map (
      I => jtag_reg(1),
      CTL => NlwInverterSignal_I95_14_T,
      O => db_out(1)
    );
  I95_13 : X_TRI
    port map (
      I => jtag_reg(2),
      CTL => NlwInverterSignal_I95_13_T,
      O => db_out(2)
    );
  I95_12 : X_TRI
    port map (
      I => jtag_reg(3),
      CTL => NlwInverterSignal_I95_12_T,
      O => db_out(3)
    );
  I95_11 : X_TRI
    port map (
      I => jtag_reg(4),
      CTL => NlwInverterSignal_I95_11_T,
      O => db_out(4)
    );
  I95_10 : X_TRI
    port map (
      I => jtag_reg(5),
      CTL => NlwInverterSignal_I95_10_T,
      O => db_out(5)
    );
  I95_9 : X_TRI
    port map (
      I => jtag_reg(6),
      CTL => NlwInverterSignal_I95_9_T,
      O => db_out(6)
    );
  I95_8 : X_TRI
    port map (
      I => jtdo_IBUF,
      CTL => NlwInverterSignal_I95_8_T,
      O => db_out(7)
    );
  I95_7 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_7_T,
      O => db_out(8)
    );
  I95_6 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_6_T,
      O => db_out(9)
    );
  I95_5 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_5_T,
      O => db_out(10)
    );
  I95_4 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_4_T,
      O => db_out(11)
    );
  I95_3 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_3_T,
      O => db_out(12)
    );
  I95_2 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_2_T,
      O => db_out(13)
    );
  I95_1 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I95_1_T,
      O => db_out(14)
    );
  I94_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(3),
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => U1_fq5_q,
      O => I94_N1141
    );
  I94_15 : X_TRI
    port map (
      I => ron_reg(0),
      CTL => NlwInverterSignal_I94_15_T,
      O => db_out(0)
    );
  I94_14 : X_TRI
    port map (
      I => ron_reg(1),
      CTL => NlwInverterSignal_I94_14_T,
      O => db_out(1)
    );
  I94_13 : X_TRI
    port map (
      I => ron_reg(2),
      CTL => NlwInverterSignal_I94_13_T,
      O => db_out(2)
    );
  I94_12 : X_TRI
    port map (
      I => ron_reg(3),
      CTL => NlwInverterSignal_I94_12_T,
      O => db_out(3)
    );
  I94_11 : X_TRI
    port map (
      I => ron_reg(4),
      CTL => NlwInverterSignal_I94_11_T,
      O => db_out(4)
    );
  I94_10 : X_TRI
    port map (
      I => ron_reg(5),
      CTL => NlwInverterSignal_I94_10_T,
      O => db_out(5)
    );
  I94_9 : X_TRI
    port map (
      I => ron_reg(6),
      CTL => NlwInverterSignal_I94_9_T,
      O => db_out(6)
    );
  I94_8 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_8_T,
      O => db_out(7)
    );
  I94_7 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_7_T,
      O => db_out(8)
    );
  I94_6 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_6_T,
      O => db_out(9)
    );
  I94_5 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_5_T,
      O => db_out(10)
    );
  I94_4 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_4_T,
      O => db_out(11)
    );
  I94_3 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_3_T,
      O => db_out(12)
    );
  I94_2 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_2_T,
      O => db_out(13)
    );
  I94_1 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I94_1_T,
      O => db_out(14)
    );
  I69_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(2),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => U1_fq5_q,
      O => I69_N1141
    );
  I69_15 : X_TRI
    port map (
      I => int_vec_2(0),
      CTL => NlwInverterSignal_I69_15_T,
      O => db_out(0)
    );
  I69_14 : X_TRI
    port map (
      I => int_vec_2(1),
      CTL => NlwInverterSignal_I69_14_T,
      O => db_out(1)
    );
  I69_13 : X_TRI
    port map (
      I => int_vec_2(2),
      CTL => NlwInverterSignal_I69_13_T,
      O => db_out(2)
    );
  I69_12 : X_TRI
    port map (
      I => int_vec_2(3),
      CTL => NlwInverterSignal_I69_12_T,
      O => db_out(3)
    );
  I69_11 : X_TRI
    port map (
      I => int_vec_2(4),
      CTL => NlwInverterSignal_I69_11_T,
      O => db_out(4)
    );
  I69_10 : X_TRI
    port map (
      I => int_vec_2(5),
      CTL => NlwInverterSignal_I69_10_T,
      O => db_out(5)
    );
  I69_9 : X_TRI
    port map (
      I => int_vec_2(6),
      CTL => NlwInverterSignal_I69_9_T,
      O => db_out(6)
    );
  I69_8 : X_TRI
    port map (
      I => int_vec_2(7),
      CTL => NlwInverterSignal_I69_8_T,
      O => db_out(7)
    );
  I69_7 : X_TRI
    port map (
      I => int_lev_2(0),
      CTL => NlwInverterSignal_I69_7_T,
      O => db_out(8)
    );
  I69_6 : X_TRI
    port map (
      I => int_lev_2(1),
      CTL => NlwInverterSignal_I69_6_T,
      O => db_out(9)
    );
  I69_5 : X_TRI
    port map (
      I => int_lev_2(2),
      CTL => NlwInverterSignal_I69_5_T,
      O => db_out(10)
    );
  I69_4 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I69_4_T,
      O => db_out(11)
    );
  I69_3 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I69_3_T,
      O => db_out(12)
    );
  I69_2 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I69_2_T,
      O => db_out(13)
    );
  I69_1 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I69_1_T,
      O => db_out(14)
    );
  I68_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(2),
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => U1_fq5_q,
      O => I68_N1141
    );
  I68_15 : X_TRI
    port map (
      I => int_vec_1(0),
      CTL => NlwInverterSignal_I68_15_T,
      O => db_out(0)
    );
  I68_14 : X_TRI
    port map (
      I => int_vec_1(1),
      CTL => NlwInverterSignal_I68_14_T,
      O => db_out(1)
    );
  I68_13 : X_TRI
    port map (
      I => int_vec_1(2),
      CTL => NlwInverterSignal_I68_13_T,
      O => db_out(2)
    );
  I68_12 : X_TRI
    port map (
      I => int_vec_1(3),
      CTL => NlwInverterSignal_I68_12_T,
      O => db_out(3)
    );
  I68_11 : X_TRI
    port map (
      I => int_vec_1(4),
      CTL => NlwInverterSignal_I68_11_T,
      O => db_out(4)
    );
  I68_10 : X_TRI
    port map (
      I => int_vec_1(5),
      CTL => NlwInverterSignal_I68_10_T,
      O => db_out(5)
    );
  I68_9 : X_TRI
    port map (
      I => int_vec_1(6),
      CTL => NlwInverterSignal_I68_9_T,
      O => db_out(6)
    );
  I68_8 : X_TRI
    port map (
      I => int_vec_1(7),
      CTL => NlwInverterSignal_I68_8_T,
      O => db_out(7)
    );
  I68_7 : X_TRI
    port map (
      I => int_lev_1(0),
      CTL => NlwInverterSignal_I68_7_T,
      O => db_out(8)
    );
  I68_6 : X_TRI
    port map (
      I => int_lev_1(1),
      CTL => NlwInverterSignal_I68_6_T,
      O => db_out(9)
    );
  I68_5 : X_TRI
    port map (
      I => int_lev_1(2),
      CTL => NlwInverterSignal_I68_5_T,
      O => db_out(10)
    );
  I68_4 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I68_4_T,
      O => db_out(11)
    );
  I68_3 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I68_3_T,
      O => db_out(12)
    );
  I68_2 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I68_2_T,
      O => db_out(13)
    );
  I68_1 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I68_1_T,
      O => db_out(14)
    );
  I67_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => grp(2),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => U1_fq5_q,
      O => I67_N1141
    );
  I67_15 : X_TRI
    port map (
      I => int_vec_0(0),
      CTL => NlwInverterSignal_I67_15_T,
      O => db_out(0)
    );
  I67_14 : X_TRI
    port map (
      I => int_vec_0(1),
      CTL => NlwInverterSignal_I67_14_T,
      O => db_out(1)
    );
  I67_13 : X_TRI
    port map (
      I => int_vec_0(2),
      CTL => NlwInverterSignal_I67_13_T,
      O => db_out(2)
    );
  I67_12 : X_TRI
    port map (
      I => int_vec_0(3),
      CTL => NlwInverterSignal_I67_12_T,
      O => db_out(3)
    );
  I67_11 : X_TRI
    port map (
      I => int_vec_0(4),
      CTL => NlwInverterSignal_I67_11_T,
      O => db_out(4)
    );
  I67_10 : X_TRI
    port map (
      I => int_vec_0(5),
      CTL => NlwInverterSignal_I67_10_T,
      O => db_out(5)
    );
  I67_9 : X_TRI
    port map (
      I => int_vec_0(6),
      CTL => NlwInverterSignal_I67_9_T,
      O => db_out(6)
    );
  I67_8 : X_TRI
    port map (
      I => int_vec_0(7),
      CTL => NlwInverterSignal_I67_8_T,
      O => db_out(7)
    );
  I67_7 : X_TRI
    port map (
      I => int_lev_0(0),
      CTL => NlwInverterSignal_I67_7_T,
      O => db_out(8)
    );
  I67_6 : X_TRI
    port map (
      I => int_lev_0(1),
      CTL => NlwInverterSignal_I67_6_T,
      O => db_out(9)
    );
  I67_5 : X_TRI
    port map (
      I => int_lev_0(2),
      CTL => NlwInverterSignal_I67_5_T,
      O => db_out(10)
    );
  I67_4 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I67_4_T,
      O => db_out(11)
    );
  I67_3 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I67_3_T,
      O => db_out(12)
    );
  I67_2 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I67_2_T,
      O => db_out(13)
    );
  I67_1 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_I67_1_T,
      O => db_out(14)
    );
  ron_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => Q_n0016,
      RST => ron_reg_1_GSR_OR,
      CLK => CLK,
      O => ron_reg(1),
      SET => GND
    );
  ron_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => Q_n0016,
      RST => ron_reg_0_GSR_OR,
      CLK => CLK,
      O => ron_reg(0),
      SET => GND
    );
  jtag_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => Q_n0017,
      RST => jtag_reg_5_GSR_OR,
      CLK => CLK,
      O => jtag_reg(5),
      SET => GND
    );
  jtag_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0017,
      RST => jtag_reg_4_GSR_OR,
      CLK => CLK,
      O => jtag_reg(4),
      SET => GND
    );
  jtag_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0017,
      RST => jtag_reg_3_GSR_OR,
      CLK => CLK,
      O => jtag_reg(3),
      SET => GND
    );
  jtag_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => Q_n0017,
      RST => jtag_reg_2_GSR_OR,
      CLK => CLK,
      O => jtag_reg(2),
      SET => GND
    );
  jtag_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => Q_n0017,
      RST => jtag_reg_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg(1),
      SET => GND
    );
  jtag_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => Q_n0017,
      RST => jtag_reg_0_GSR_OR,
      CLK => CLK,
      O => jtag_reg(0),
      SET => GND
    );
  int_vec_0_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => Q_n0090,
      RST => int_vec_0_6_GSR_OR,
      CLK => CLK,
      O => int_vec_0(6),
      SET => GND
    );
  int_vec_0_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => Q_n0090,
      RST => int_vec_0_5_GSR_OR,
      CLK => CLK,
      O => int_vec_0(5),
      SET => GND
    );
  int_vec_0_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0090,
      RST => int_vec_0_4_GSR_OR,
      CLK => CLK,
      O => int_vec_0(4),
      SET => GND
    );
  int_vec_0_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0090,
      RST => int_vec_0_3_GSR_OR,
      CLK => CLK,
      O => int_vec_0(3),
      SET => GND
    );
  int_vec_0_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => Q_n0090,
      RST => int_vec_0_2_GSR_OR,
      CLK => CLK,
      O => int_vec_0(2),
      SET => GND
    );
  int_vec_0_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => Q_n0090,
      RST => int_vec_0_1_GSR_OR,
      CLK => CLK,
      O => int_vec_0(1),
      SET => GND
    );
  int_vec_0_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => Q_n0090,
      RST => int_vec_0_0_GSR_OR,
      CLK => CLK,
      O => int_vec_0(0),
      SET => GND
    );
  int_vec_1_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => Q_n0092,
      RST => int_vec_1_6_GSR_OR,
      CLK => CLK,
      O => int_vec_1(6),
      SET => GND
    );
  int_vec_1_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => Q_n0092,
      RST => int_vec_1_5_GSR_OR,
      CLK => CLK,
      O => int_vec_1(5),
      SET => GND
    );
  int_vec_1_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0092,
      RST => int_vec_1_4_GSR_OR,
      CLK => CLK,
      O => int_vec_1(4),
      SET => GND
    );
  int_vec_1_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0092,
      RST => int_vec_1_3_GSR_OR,
      CLK => CLK,
      O => int_vec_1(3),
      SET => GND
    );
  int_vec_1_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => Q_n0092,
      RST => int_vec_1_2_GSR_OR,
      CLK => CLK,
      O => int_vec_1(2),
      SET => GND
    );
  int_vec_1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => Q_n0092,
      RST => int_vec_1_1_GSR_OR,
      CLK => CLK,
      O => int_vec_1(1),
      SET => GND
    );
  delay_1_2_OBUF : X_BUF
    port map (
      I => U5_pulse_reg1_2_1,
      O => delay_1_2_OBUF_GTS_TRI
    );
  U7_I12_1 : X_TRI
    port map (
      I => U7_U4_crc_reg(6),
      CTL => NlwInverterSignal_U7_I12_1_T,
      O => db_out(6)
    );
  U7_I12_2 : X_TRI
    port map (
      I => U7_U4_crc_reg(5),
      CTL => NlwInverterSignal_U7_I12_2_T,
      O => db_out(5)
    );
  U7_I12_3 : X_TRI
    port map (
      I => U7_U4_crc_reg(4),
      CTL => NlwInverterSignal_U7_I12_3_T,
      O => db_out(4)
    );
  U7_I12_4 : X_TRI
    port map (
      I => U7_U4_crc_reg(3),
      CTL => NlwInverterSignal_U7_I12_4_T,
      O => db_out(3)
    );
  U7_n00061 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => grp(4),
      O => U7_n0006
    );
  U7_I12_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => add_int(1),
      ADR2 => U1_fq5_q,
      ADR3 => grp(4),
      O => U7_I12_N1423
    );
  U7_I12_5 : X_TRI
    port map (
      I => U7_U4_crc_reg(2),
      CTL => NlwInverterSignal_U7_I12_5_T,
      O => db_out(2)
    );
  U7_I12_6 : X_TRI
    port map (
      I => U7_U4_crc_reg(1),
      CTL => NlwInverterSignal_U7_I12_6_T,
      O => db_out(1)
    );
  U7_I12_7 : X_TRI
    port map (
      I => U7_U4_crc_reg(0),
      CTL => NlwInverterSignal_U7_I12_7_T,
      O => db_out(0)
    );
  U7_n00011 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => U7_U1_M2_end_count,
      ADR1 => U7_U3_M2_end_count,
      O => U7_n0001
    );
  grp_0 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18193,
      SRST => add_in_3_IBUF,
      CLK => NlwInverterSignal_grp_0_C,
      O => grp(0),
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  U6_S2_trg_cntin_inst_cy_19_13 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_18,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_17,
      O => U6_S2_trg_cntin_inst_cy_19
    );
  U7_read_start1 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => U7_n0006,
      ADR1 => N18102,
      O => U7_read_start
    );
  U7_write_start1 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => U7_n0006,
      ADR1 => N18100,
      O => U7_write_start
    );
  U7_init_start1 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => U7_n0006,
      ADR1 => N18098,
      O => U7_init_start
    );
  U7_I12_0 : X_TRI
    port map (
      I => U7_U4_crc_reg(7),
      CTL => NlwInverterSignal_U7_I12_0_T,
      O => db_out(7)
    );
  U7_I11_0 : X_TRI
    port map (
      I => U7_r_reg,
      CTL => NlwInverterSignal_U7_I11_0_T,
      O => db_out(0)
    );
  U7_I10_0 : X_TRI
    port map (
      I => U7_w_reg,
      CTL => NlwInverterSignal_U7_I10_0_T,
      O => db_out(0)
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_3_xor : X_XOR2
    port map (
      I0 => U7_ckdiv_Q_3_rt,
      I1 => U7_ckdiv_LPM_COUNTER_8_n0000_2_cyo,
      O => U7_ckdiv_n0000(3)
    );
  U7_CK1 : X_CKBUF
    port map (
      I => U7_ckdiv(4),
      O => U7_ck_slow
    );
  U7_U1_M2_count_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M2_count_n0000(0),
      CE => U7_U1_M2_count_0_7_N1306,
      SET => U7_U1_M2_count_0_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(0),
      RST => GND
    );
  U7_U2_M2_count_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U2_M2_count_n0000(0),
      CE => U7_U2_M2_count_0_7_N1306,
      SET => U7_U2_M2_count_0_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(0),
      RST => GND
    );
  Mmux_n0019_Result_1_1 : X_LUT4
    generic map(
      INIT => X"DC10"
    )
    port map (
      ADR0 => U3_fr9_q,
      ADR1 => Q_n0020,
      ADR2 => int_ena(1),
      ADR3 => N18100,
      O => Q_n0019(1)
    );
  U7_U4_crc_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0005,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_3_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(3),
      SET => GND
    );
  U7_w_reg_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => U7_n0000,
      RST => U7_w_reg_GSR_OR,
      CLK => CLK,
      O => U7_w_reg,
      SET => GND
    );
  U7_r_reg_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18116,
      CE => U7_n0001,
      RST => U7_r_reg_GSR_OR,
      CLK => CLK,
      O => U7_r_reg,
      SET => GND
    );
  U7_read_read_q_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U3_M2_end_count,
      RST => U7_read_read_q_GSR_OR,
      CLK => CLK,
      O => U7_read_read_q,
      CE => VCC,
      SET => GND
    );
  U7_I11_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => add_int(1),
      ADR2 => U1_fq5_q,
      ADR3 => grp(4),
      O => U7_I11_N1191
    );
  U7_I10_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => U1_fq5_q,
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => grp(4),
      O => U7_I10_N1191
    );
  U6_n0161_17 : X_LUT4
    generic map(
      INIT => X"CCCE"
    )
    port map (
      ADR0 => U1_fq2_q,
      ADR1 => set_trgin,
      ADR2 => U1_fq4_q,
      ADR3 => N18318,
      O => U6_n0161
    );
  U7_ckdiv_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_ckdiv_n0000(4),
      RST => U7_ckdiv_4_GSR_OR,
      CLK => CLK,
      O => U7_ckdiv(4),
      CE => VCC,
      SET => GND
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_4_xor : X_XOR2
    port map (
      I0 => U7_ckdiv_4_rt,
      I1 => U7_ckdiv_LPM_COUNTER_8_n0000_3_cyo,
      O => U7_ckdiv_n0000(4)
    );
  U7_ckdiv_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_ckdiv_N5871,
      RST => U7_ckdiv_0_GSR_OR,
      CLK => CLK,
      O => U7_ckdiv(0),
      CE => VCC,
      SET => GND
    );
  U7_ckdiv_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_ckdiv_n0000(1),
      RST => U7_ckdiv_1_GSR_OR,
      CLK => CLK,
      O => U7_ckdiv(1),
      CE => VCC,
      SET => GND
    );
  U7_ckdiv_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_ckdiv_n0000(2),
      RST => U7_ckdiv_2_GSR_OR,
      CLK => CLK,
      O => U7_ckdiv(2),
      CE => VCC,
      SET => GND
    );
  U7_ckdiv_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_ckdiv_n0000(3),
      RST => U7_ckdiv_3_GSR_OR,
      CLK => CLK,
      O => U7_ckdiv(3),
      CE => VCC,
      SET => GND
    );
  XST_VCC : X_ONE
    port map (
      O => N8300
    );
  Mmux_n0019_Result_0_1 : X_LUT4
    generic map(
      INIT => X"DC10"
    )
    port map (
      ADR0 => U2_fr9_q,
      ADR1 => Q_n0020,
      ADR2 => int_ena(0),
      ADR3 => N18098,
      O => Q_n0019(0)
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_0_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_ckdiv(0),
      O => U7_ckdiv_N5871,
      ADR1 => GND
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_0_cy : X_MUX2
    port map (
      IB => tp3_OBUF,
      IA => N8300,
      SEL => U7_ckdiv_N5871,
      O => U7_ckdiv_LPM_COUNTER_8_n0000_0_cyo
    );
  delay_1_1_OBUF : X_BUF
    port map (
      I => U5_pulse_reg1_1_1,
      O => delay_1_1_OBUF_GTS_TRI
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_1_cy : X_MUX2
    port map (
      IB => U7_ckdiv_LPM_COUNTER_8_n0000_0_cyo,
      IA => tp3_OBUF,
      SEL => U7_ckdiv_Q_1_rt,
      O => U7_ckdiv_LPM_COUNTER_8_n0000_1_cyo
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_1_xor : X_XOR2
    port map (
      I0 => U7_ckdiv_Q_1_rt,
      I1 => U7_ckdiv_LPM_COUNTER_8_n0000_0_cyo,
      O => U7_ckdiv_n0000(1)
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_2_cy : X_MUX2
    port map (
      IB => U7_ckdiv_LPM_COUNTER_8_n0000_1_cyo,
      IA => tp3_OBUF,
      SEL => U7_ckdiv_Q_2_rt,
      O => U7_ckdiv_LPM_COUNTER_8_n0000_2_cyo
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_2_xor : X_XOR2
    port map (
      I0 => U7_ckdiv_Q_2_rt,
      I1 => U7_ckdiv_LPM_COUNTER_8_n0000_1_cyo,
      O => U7_ckdiv_n0000(2)
    );
  U7_ckdiv_LPM_COUNTER_8_n0000_3_cy : X_MUX2
    port map (
      IB => U7_ckdiv_LPM_COUNTER_8_n0000_2_cyo,
      IA => tp3_OBUF,
      SEL => U7_ckdiv_Q_3_rt,
      O => U7_ckdiv_LPM_COUNTER_8_n0000_3_cyo
    );
  U7_U1_init_read_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U7_U1_M1_end_count,
      RST => U7_U1_init_read_GSR_OR,
      CLK => CLK,
      O => U7_U1_init_read,
      SET => GND
    );
  U7_U1_init_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U7_init_start,
      RST => U7_U1_init_GSR_OR,
      CLK => CLK,
      O => U7_U1_init,
      SET => GND
    );
  U7_U1_M2_count_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M2_count_n0000(2),
      CE => U7_U1_M2_count_0_7_N1306,
      RST => U7_U1_M2_count_2_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(2),
      SET => GND
    );
  U7_U1_M1_count_7 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M1_count_n0000(7),
      CE => U7_U1_M1_count_0_10_N1306,
      SET => U7_U1_M1_count_7_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(7),
      RST => GND
    );
  U7_U1_M2_count_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M2_count_n0000(3),
      CE => U7_U1_M2_count_0_7_N1306,
      RST => U7_U1_M2_count_3_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(3),
      SET => GND
    );
  U7_U1_M1_end_count_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M1_count(10),
      CLK => U7_ck_slow,
      O => U7_U1_M1_end_count,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  U7_U1_M1_count_10_N13041 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_init,
      O => U7_U1_M1_count_0_10_N1304,
      ADR1 => GND
    );
  U7_U1_M1_count_10_N13061 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(10),
      O => U7_U1_M1_count_0_10_N1306,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_10_xor : X_XOR2
    port map (
      I0 => N18249,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_9_cyo,
      O => U7_U1_M1_count_n0000(10)
    );
  U7_U1_M1_count_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M1_count_n0000(8),
      CE => U7_U1_M1_count_0_10_N1306,
      RST => U7_U1_M1_count_8_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(8),
      SET => GND
    );
  U7_U1_M2_count_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M2_count_n0000(1),
      CE => U7_U1_M2_count_0_7_N1306,
      SET => U7_U1_M2_count_1_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(1),
      RST => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_0_cy : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => U7_U1_M1_count_Q_0_rt,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_0_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_0_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_Q_0_rt,
      I1 => N8300,
      O => U7_U1_M1_count_n0000(0)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_1_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(1),
      O => U7_U1_M1_count_N5890,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_1_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_0_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5890,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_1_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_1_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5890,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_0_cyo,
      O => U7_U1_M1_count_n0000(1)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_2_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(2),
      O => U7_U1_M1_count_N5894,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_2_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_1_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5894,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_2_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_2_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5894,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_1_cyo,
      O => U7_U1_M1_count_n0000(2)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_3_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(3),
      O => U7_U1_M1_count_N5898,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_3_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_2_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5898,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_3_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_3_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5898,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_2_cyo,
      O => U7_U1_M1_count_n0000(3)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_4_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(4),
      O => U7_U1_M1_count_N5902,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_4_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_3_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5902,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_4_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_4_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5902,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_3_cyo,
      O => U7_U1_M1_count_n0000(4)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_5_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(5),
      O => U7_U1_M1_count_N5906,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_5_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_4_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5906,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_5_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_5_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5906,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_4_cyo,
      O => U7_U1_M1_count_n0000(5)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_6_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(6),
      O => U7_U1_M1_count_N5910,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_6_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_5_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5910,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_6_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_6_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5910,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_5_cyo,
      O => U7_U1_M1_count_n0000(6)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_7_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(7),
      O => U7_U1_M1_count_N5914,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_7_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_6_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5914,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_7_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_7_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5914,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_6_cyo,
      O => U7_U1_M1_count_n0000(7)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_8_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(8),
      O => U7_U1_M1_count_N5918,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_8_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_7_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5918,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_8_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_8_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5918,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_7_cyo,
      O => U7_U1_M1_count_n0000(8)
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_9_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(9),
      O => U7_U1_M1_count_N5922,
      ADR1 => GND
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_9_cy : X_MUX2
    port map (
      IB => U7_U1_M1_count_LPM_COUNTER_6_n0000_8_cyo,
      IA => N8300,
      SEL => U7_U1_M1_count_N5922,
      O => U7_U1_M1_count_LPM_COUNTER_6_n0000_9_cyo
    );
  U7_U1_M1_count_LPM_COUNTER_6_n0000_9_xor : X_XOR2
    port map (
      I0 => U7_U1_M1_count_N5922,
      I1 => U7_U1_M1_count_LPM_COUNTER_6_n0000_8_cyo,
      O => U7_U1_M1_count_n0000(9)
    );
  delay_1_3_OBUF : X_BUF
    port map (
      I => U5_pulse_reg1_3_1,
      O => delay_1_3_OBUF_GTS_TRI
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_3_cy : X_MUX2
    port map (
      IB => U7_U3_M2_count_LPM_COUNTER_1_n0000_2_cyo,
      IA => N8300,
      SEL => U7_U3_M2_count_N6075,
      O => U7_U3_M2_count_LPM_COUNTER_1_n0000_3_cyo
    );
  U7_U1_M1_count_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M1_count_n0000(10),
      CE => U7_U1_M1_count_0_10_N1306,
      RST => U7_U1_M1_count_10_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(10),
      SET => GND
    );
  U7_U1_M1_count_9 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M1_count_n0000(9),
      CE => U7_U1_M1_count_0_10_N1306,
      SET => U7_U1_M1_count_9_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(9),
      RST => GND
    );
  U7_U1_M1_count_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M1_count_n0000(0),
      CE => U7_U1_M1_count_0_10_N1306,
      SET => U7_U1_M1_count_0_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(0),
      RST => GND
    );
  U7_U1_M1_count_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M1_count_n0000(1),
      CE => U7_U1_M1_count_0_10_N1306,
      RST => U7_U1_M1_count_1_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(1),
      SET => GND
    );
  U7_U1_M1_count_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M1_count_n0000(2),
      CE => U7_U1_M1_count_0_10_N1306,
      SET => U7_U1_M1_count_2_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(2),
      RST => GND
    );
  U7_U1_M1_count_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M1_count_n0000(3),
      CE => U7_U1_M1_count_0_10_N1306,
      SET => U7_U1_M1_count_3_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(3),
      RST => GND
    );
  U7_U1_M1_count_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M1_count_n0000(4),
      CE => U7_U1_M1_count_0_10_N1306,
      RST => U7_U1_M1_count_4_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(4),
      SET => GND
    );
  U7_U1_M1_count_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M1_count_n0000(5),
      CE => U7_U1_M1_count_0_10_N1306,
      SET => U7_U1_M1_count_5_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(5),
      RST => GND
    );
  U7_U1_M1_count_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M1_count_n0000(6),
      CE => U7_U1_M1_count_0_10_N1306,
      SET => U7_U1_M1_count_6_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M1_count(6),
      RST => GND
    );
  U7_U1_M2_end_count_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M2_count(7),
      CLK => U7_ck_slow,
      O => U7_U1_M2_end_count,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  U7_U1_M2_count_7_N13041 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_init_read,
      O => U7_U1_M2_count_0_7_N1304,
      ADR1 => GND
    );
  U7_U1_M2_count_7_N13061 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(7),
      O => U7_U1_M2_count_0_7_N1306,
      ADR1 => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_7_xor : X_XOR2
    port map (
      I0 => N18251,
      I1 => U7_U1_M2_count_LPM_COUNTER_5_n0000_6_cyo,
      O => U7_U1_M2_count_n0000(7)
    );
  U7_U1_M2_count_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M2_count_n0000(5),
      CE => U7_U1_M2_count_0_7_N1306,
      RST => U7_U1_M2_count_5_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(5),
      SET => GND
    );
  U7_U1_M2_count_4 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M2_count_n0000(4),
      CE => U7_U1_M2_count_0_7_N1306,
      SET => U7_U1_M2_count_4_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(4),
      RST => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_0_cy : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => U7_U1_M2_count_Q_0_rt,
      O => U7_U1_M2_count_LPM_COUNTER_5_n0000_0_cyo
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_0_xor : X_XOR2
    port map (
      I0 => U7_U1_M2_count_Q_0_rt,
      I1 => N8300,
      O => U7_U1_M2_count_n0000(0)
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_1_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(1),
      O => U7_U1_M2_count_N5937,
      ADR1 => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_1_cy : X_MUX2
    port map (
      IB => U7_U1_M2_count_LPM_COUNTER_5_n0000_0_cyo,
      IA => N8300,
      SEL => U7_U1_M2_count_N5937,
      O => U7_U1_M2_count_LPM_COUNTER_5_n0000_1_cyo
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_1_xor : X_XOR2
    port map (
      I0 => U7_U1_M2_count_N5937,
      I1 => U7_U1_M2_count_LPM_COUNTER_5_n0000_0_cyo,
      O => U7_U1_M2_count_n0000(1)
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_2_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(2),
      O => U7_U1_M2_count_N5941,
      ADR1 => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_2_cy : X_MUX2
    port map (
      IB => U7_U1_M2_count_LPM_COUNTER_5_n0000_1_cyo,
      IA => N8300,
      SEL => U7_U1_M2_count_N5941,
      O => U7_U1_M2_count_LPM_COUNTER_5_n0000_2_cyo
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_2_xor : X_XOR2
    port map (
      I0 => U7_U1_M2_count_N5941,
      I1 => U7_U1_M2_count_LPM_COUNTER_5_n0000_1_cyo,
      O => U7_U1_M2_count_n0000(2)
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_3_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(3),
      O => U7_U1_M2_count_N5945,
      ADR1 => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_3_cy : X_MUX2
    port map (
      IB => U7_U1_M2_count_LPM_COUNTER_5_n0000_2_cyo,
      IA => N8300,
      SEL => U7_U1_M2_count_N5945,
      O => U7_U1_M2_count_LPM_COUNTER_5_n0000_3_cyo
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_3_xor : X_XOR2
    port map (
      I0 => U7_U1_M2_count_N5945,
      I1 => U7_U1_M2_count_LPM_COUNTER_5_n0000_2_cyo,
      O => U7_U1_M2_count_n0000(3)
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_4_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(4),
      O => U7_U1_M2_count_N5949,
      ADR1 => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_4_cy : X_MUX2
    port map (
      IB => U7_U1_M2_count_LPM_COUNTER_5_n0000_3_cyo,
      IA => N8300,
      SEL => U7_U1_M2_count_N5949,
      O => U7_U1_M2_count_LPM_COUNTER_5_n0000_4_cyo
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_4_xor : X_XOR2
    port map (
      I0 => U7_U1_M2_count_N5949,
      I1 => U7_U1_M2_count_LPM_COUNTER_5_n0000_3_cyo,
      O => U7_U1_M2_count_n0000(4)
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_5_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(5),
      O => U7_U1_M2_count_N5953,
      ADR1 => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_5_cy : X_MUX2
    port map (
      IB => U7_U1_M2_count_LPM_COUNTER_5_n0000_4_cyo,
      IA => N8300,
      SEL => U7_U1_M2_count_N5953,
      O => U7_U1_M2_count_LPM_COUNTER_5_n0000_5_cyo
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_5_xor : X_XOR2
    port map (
      I0 => U7_U1_M2_count_N5953,
      I1 => U7_U1_M2_count_LPM_COUNTER_5_n0000_4_cyo,
      O => U7_U1_M2_count_n0000(5)
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_6_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(6),
      O => U7_U1_M2_count_N5957,
      ADR1 => GND
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_6_cy : X_MUX2
    port map (
      IB => U7_U1_M2_count_LPM_COUNTER_5_n0000_5_cyo,
      IA => N8300,
      SEL => U7_U1_M2_count_N5957,
      O => U7_U1_M2_count_LPM_COUNTER_5_n0000_6_cyo
    );
  U7_U1_M2_count_LPM_COUNTER_5_n0000_6_xor : X_XOR2
    port map (
      I0 => U7_U1_M2_count_N5957,
      I1 => U7_U1_M2_count_LPM_COUNTER_5_n0000_5_cyo,
      O => U7_U1_M2_count_n0000(6)
    );
  delay_1_4_OBUF : X_BUF
    port map (
      I => U5_pulse_reg1_4_1,
      O => delay_1_4_OBUF_GTS_TRI
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_3_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_M2_count(3),
      O => U7_U3_M2_count_N6075,
      ADR1 => GND
    );
  U7_U1_M2_count_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U1_M2_count_n0000(7),
      CE => U7_U1_M2_count_0_7_N1306,
      RST => U7_U1_M2_count_7_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(7),
      SET => GND
    );
  U7_U1_M2_count_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U1_M2_count_n0000(6),
      CE => U7_U1_M2_count_0_7_N1306,
      SET => U7_U1_M2_count_6_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U1_M2_count(6),
      RST => GND
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_2_xor : X_XOR2
    port map (
      I0 => U7_U3_M2_count_N6071,
      I1 => U7_U3_M2_count_LPM_COUNTER_1_n0000_1_cyo,
      O => U7_U3_M2_count_n0000(2)
    );
  U7_U2_M2_count_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M2_count_n0000(2),
      CE => U7_U2_M2_count_0_7_N1306,
      RST => U7_U2_M2_count_2_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(2),
      SET => GND
    );
  U7_U3_M2_end_count_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U3_M2_count(4),
      CLK => U7_ck_slow,
      O => U7_U3_M2_end_count,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  U7_U2_M1_count_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U2_M1_count_n0000(1),
      CE => U7_U2_M1_count_0_4_N1306,
      SET => U7_U2_M1_count_1_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M1_count(1),
      RST => GND
    );
  U7_U2_M2_count_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M2_count_n0000(3),
      CE => U7_U2_M2_count_0_7_N1306,
      RST => U7_U2_M2_count_3_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(3),
      SET => GND
    );
  U7_U2_w1_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U7_write_start,
      RST => U7_U2_w1_GSR_OR,
      CLK => CLK,
      O => U7_U2_w1,
      SET => GND
    );
  U7_U2_w0_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U7_write_start,
      RST => U7_U2_w0_GSR_OR,
      CLK => CLK,
      O => U7_U2_w0,
      SET => GND
    );
  U7_U2_M1_end_count_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M1_count(4),
      CLK => U7_ck_slow,
      O => U7_U2_M1_end_count,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  U7_U2_M1_count_4_N13041 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_w1,
      O => U7_U2_M1_count_0_4_N1304,
      ADR1 => GND
    );
  U7_U2_M1_count_4_N13061 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M1_count(4),
      O => U7_U2_M1_count_0_4_N1306,
      ADR1 => GND
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_4_xor : X_XOR2
    port map (
      I0 => N18253,
      I1 => U7_U2_M1_count_LPM_COUNTER_4_n0000_3_cyo,
      O => U7_U2_M1_count_n0000(4)
    );
  U7_U2_M1_count_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M1_count_n0000(2),
      CE => U7_U2_M1_count_0_4_N1306,
      RST => U7_U2_M1_count_2_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M1_count(2),
      SET => GND
    );
  U7_U2_M2_count_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U2_M2_count_n0000(1),
      CE => U7_U2_M2_count_0_7_N1306,
      SET => U7_U2_M2_count_1_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(1),
      RST => GND
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_0_cy : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => U7_U2_M1_count_Q_0_rt,
      O => U7_U2_M1_count_LPM_COUNTER_4_n0000_0_cyo
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_0_xor : X_XOR2
    port map (
      I0 => U7_U2_M1_count_Q_0_rt,
      I1 => N8300,
      O => U7_U2_M1_count_n0000(0)
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_1_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M1_count(1),
      O => U7_U2_M1_count_N5972,
      ADR1 => GND
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_1_cy : X_MUX2
    port map (
      IB => U7_U2_M1_count_LPM_COUNTER_4_n0000_0_cyo,
      IA => N8300,
      SEL => U7_U2_M1_count_N5972,
      O => U7_U2_M1_count_LPM_COUNTER_4_n0000_1_cyo
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_1_xor : X_XOR2
    port map (
      I0 => U7_U2_M1_count_N5972,
      I1 => U7_U2_M1_count_LPM_COUNTER_4_n0000_0_cyo,
      O => U7_U2_M1_count_n0000(1)
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_2_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M1_count(2),
      O => U7_U2_M1_count_N5976,
      ADR1 => GND
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_2_cy : X_MUX2
    port map (
      IB => U7_U2_M1_count_LPM_COUNTER_4_n0000_1_cyo,
      IA => N8300,
      SEL => U7_U2_M1_count_N5976,
      O => U7_U2_M1_count_LPM_COUNTER_4_n0000_2_cyo
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_2_xor : X_XOR2
    port map (
      I0 => U7_U2_M1_count_N5976,
      I1 => U7_U2_M1_count_LPM_COUNTER_4_n0000_1_cyo,
      O => U7_U2_M1_count_n0000(2)
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_3_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M1_count(3),
      O => U7_U2_M1_count_N5980,
      ADR1 => GND
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_3_cy : X_MUX2
    port map (
      IB => U7_U2_M1_count_LPM_COUNTER_4_n0000_2_cyo,
      IA => N8300,
      SEL => U7_U2_M1_count_N5980,
      O => U7_U2_M1_count_LPM_COUNTER_4_n0000_3_cyo
    );
  U7_U2_M1_count_LPM_COUNTER_4_n0000_3_xor : X_XOR2
    port map (
      I0 => U7_U2_M1_count_N5980,
      I1 => U7_U2_M1_count_LPM_COUNTER_4_n0000_2_cyo,
      O => U7_U2_M1_count_n0000(3)
    );
  delay_1_5_OBUF : X_BUF
    port map (
      I => U5_pulse_reg1_5_1,
      O => delay_1_5_OBUF_GTS_TRI
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_2_cy : X_MUX2
    port map (
      IB => U7_U3_M2_count_LPM_COUNTER_1_n0000_1_cyo,
      IA => N8300,
      SEL => U7_U3_M2_count_N6071,
      O => U7_U3_M2_count_LPM_COUNTER_1_n0000_2_cyo
    );
  U7_U2_M1_count_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M1_count_n0000(4),
      CE => U7_U2_M1_count_0_4_N1306,
      RST => U7_U2_M1_count_4_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M1_count(4),
      SET => GND
    );
  U7_U2_M1_count_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U2_M1_count_n0000(3),
      CE => U7_U2_M1_count_0_4_N1306,
      SET => U7_U2_M1_count_3_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M1_count(3),
      RST => GND
    );
  U7_U2_M1_count_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U2_M1_count_n0000(0),
      CE => U7_U2_M1_count_0_4_N1306,
      SET => U7_U2_M1_count_0_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M1_count(0),
      RST => GND
    );
  U7_U2_M2_end_count_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M2_count(7),
      CLK => U7_ck_slow,
      O => U7_U2_M2_end_count,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  U7_U2_M2_count_7_N13041 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_w0,
      O => U7_U2_M2_count_0_7_N1304,
      ADR1 => GND
    );
  U7_U2_M2_count_7_N13061 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(7),
      O => U7_U2_M2_count_0_7_N1306,
      ADR1 => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_7_xor : X_XOR2
    port map (
      I0 => N18255,
      I1 => U7_U2_M2_count_LPM_COUNTER_3_n0000_6_cyo,
      O => U7_U2_M2_count_n0000(7)
    );
  U7_U2_M2_count_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U2_M2_count_n0000(5),
      CE => U7_U2_M2_count_0_7_N1306,
      SET => U7_U2_M2_count_5_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(5),
      RST => GND
    );
  U7_U2_M2_count_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M2_count_n0000(4),
      CE => U7_U2_M2_count_0_7_N1306,
      RST => U7_U2_M2_count_4_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(4),
      SET => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_0_cy : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => U7_U2_M2_count_Q_0_rt,
      O => U7_U2_M2_count_LPM_COUNTER_3_n0000_0_cyo
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_0_xor : X_XOR2
    port map (
      I0 => U7_U2_M2_count_Q_0_rt,
      I1 => N8300,
      O => U7_U2_M2_count_n0000(0)
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_1_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(1),
      O => U7_U2_M2_count_N5995,
      ADR1 => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_1_cy : X_MUX2
    port map (
      IB => U7_U2_M2_count_LPM_COUNTER_3_n0000_0_cyo,
      IA => N8300,
      SEL => U7_U2_M2_count_N5995,
      O => U7_U2_M2_count_LPM_COUNTER_3_n0000_1_cyo
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_1_xor : X_XOR2
    port map (
      I0 => U7_U2_M2_count_N5995,
      I1 => U7_U2_M2_count_LPM_COUNTER_3_n0000_0_cyo,
      O => U7_U2_M2_count_n0000(1)
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_2_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(2),
      O => U7_U2_M2_count_N5999,
      ADR1 => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_2_cy : X_MUX2
    port map (
      IB => U7_U2_M2_count_LPM_COUNTER_3_n0000_1_cyo,
      IA => N8300,
      SEL => U7_U2_M2_count_N5999,
      O => U7_U2_M2_count_LPM_COUNTER_3_n0000_2_cyo
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_2_xor : X_XOR2
    port map (
      I0 => U7_U2_M2_count_N5999,
      I1 => U7_U2_M2_count_LPM_COUNTER_3_n0000_1_cyo,
      O => U7_U2_M2_count_n0000(2)
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_3_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(3),
      O => U7_U2_M2_count_N6003,
      ADR1 => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_3_cy : X_MUX2
    port map (
      IB => U7_U2_M2_count_LPM_COUNTER_3_n0000_2_cyo,
      IA => N8300,
      SEL => U7_U2_M2_count_N6003,
      O => U7_U2_M2_count_LPM_COUNTER_3_n0000_3_cyo
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_3_xor : X_XOR2
    port map (
      I0 => U7_U2_M2_count_N6003,
      I1 => U7_U2_M2_count_LPM_COUNTER_3_n0000_2_cyo,
      O => U7_U2_M2_count_n0000(3)
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_4_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(4),
      O => U7_U2_M2_count_N6007,
      ADR1 => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_4_cy : X_MUX2
    port map (
      IB => U7_U2_M2_count_LPM_COUNTER_3_n0000_3_cyo,
      IA => N8300,
      SEL => U7_U2_M2_count_N6007,
      O => U7_U2_M2_count_LPM_COUNTER_3_n0000_4_cyo
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_4_xor : X_XOR2
    port map (
      I0 => U7_U2_M2_count_N6007,
      I1 => U7_U2_M2_count_LPM_COUNTER_3_n0000_3_cyo,
      O => U7_U2_M2_count_n0000(4)
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_5_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(5),
      O => U7_U2_M2_count_N6011,
      ADR1 => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_5_cy : X_MUX2
    port map (
      IB => U7_U2_M2_count_LPM_COUNTER_3_n0000_4_cyo,
      IA => N8300,
      SEL => U7_U2_M2_count_N6011,
      O => U7_U2_M2_count_LPM_COUNTER_3_n0000_5_cyo
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_5_xor : X_XOR2
    port map (
      I0 => U7_U2_M2_count_N6011,
      I1 => U7_U2_M2_count_LPM_COUNTER_3_n0000_4_cyo,
      O => U7_U2_M2_count_n0000(5)
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_6_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(6),
      O => U7_U2_M2_count_N6015,
      ADR1 => GND
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_6_cy : X_MUX2
    port map (
      IB => U7_U2_M2_count_LPM_COUNTER_3_n0000_5_cyo,
      IA => N8300,
      SEL => U7_U2_M2_count_N6015,
      O => U7_U2_M2_count_LPM_COUNTER_3_n0000_6_cyo
    );
  U7_U2_M2_count_LPM_COUNTER_3_n0000_6_xor : X_XOR2
    port map (
      I0 => U7_U2_M2_count_N6015,
      I1 => U7_U2_M2_count_LPM_COUNTER_3_n0000_5_cyo,
      O => U7_U2_M2_count_n0000(6)
    );
  delay_1_6_OBUF : X_BUF
    port map (
      I => U5_pulse_reg1_6_1,
      O => delay_1_6_OBUF_GTS_TRI
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_2_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_M2_count(2),
      O => U7_U3_M2_count_N6071,
      ADR1 => GND
    );
  U7_U2_M2_count_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U2_M2_count_n0000(7),
      CE => U7_U2_M2_count_0_7_N1306,
      RST => U7_U2_M2_count_7_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(7),
      SET => GND
    );
  U7_U2_M2_count_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U2_M2_count_n0000(6),
      CE => U7_U2_M2_count_0_7_N1306,
      SET => U7_U2_M2_count_6_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U2_M2_count(6),
      RST => GND
    );
  U7_U3_rd_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U7_U3_M1_end_count,
      RST => U7_U3_rd_GSR_OR,
      CLK => CLK,
      O => U7_U3_rd,
      SET => GND
    );
  U7_U3_rdpls_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U7_read_start,
      RST => U7_U3_rdpls_GSR_OR,
      CLK => CLK,
      O => U7_U3_rdpls,
      SET => GND
    );
  U7_U3_M2_count_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U3_M2_count_n0000(3),
      CE => U7_U3_M2_count_0_4_N1306,
      RST => U7_U3_M2_count_3_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M2_count(3),
      SET => GND
    );
  U7_U3_M1_count_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U3_M1_count_n0000(0),
      CE => U7_U3_M1_count_0_3_N1306,
      SET => U7_U3_M1_count_0_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M1_count(0),
      RST => GND
    );
  U7_U3_M2_count_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U3_M2_count_n0000(0),
      CE => U7_U3_M2_count_0_4_N1306,
      SET => U7_U3_M2_count_0_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M2_count(0),
      RST => GND
    );
  U7_U3_M1_end_count_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U3_M1_count(3),
      CLK => U7_ck_slow,
      O => U7_U3_M1_end_count,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  U7_U3_M1_count_3_N13041 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_rdpls,
      O => U7_U3_M1_count_0_3_N1304,
      ADR1 => GND
    );
  U7_U3_M1_count_3_N13061 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_M1_count(3),
      O => U7_U3_M1_count_0_3_N1306,
      ADR1 => GND
    );
  U7_U3_M1_count_LPM_COUNTER_2_n0000_3_xor11 : X_LUT4
    generic map(
      INIT => X"AAA9"
    )
    port map (
      ADR0 => U7_U3_M1_count(3),
      ADR1 => U7_U3_M1_count(2),
      ADR2 => U7_U3_M1_count(1),
      ADR3 => U7_U3_M1_count(0),
      O => U7_U3_M1_count_n0000(3)
    );
  U7_U3_M1_count_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U3_M1_count_n0000(1),
      CE => U7_U3_M1_count_0_3_N1306,
      RST => U7_U3_M1_count_1_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M1_count(1),
      SET => GND
    );
  U7_U3_M2_count_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U3_M2_count_n0000(4),
      CE => U7_U3_M2_count_0_4_N1306,
      RST => U7_U3_M2_count_4_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M2_count(4),
      SET => GND
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_1_xor : X_XOR2
    port map (
      I0 => U7_U3_M2_count_N6067,
      I1 => U7_U3_M2_count_LPM_COUNTER_1_n0000_0_cyo,
      O => U7_U3_M2_count_n0000(1)
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_1_cy : X_MUX2
    port map (
      IB => U7_U3_M2_count_LPM_COUNTER_1_n0000_0_cyo,
      IA => N8300,
      SEL => U7_U3_M2_count_N6067,
      O => U7_U3_M2_count_LPM_COUNTER_1_n0000_1_cyo
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_1_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_M2_count(1),
      O => U7_U3_M2_count_N6067,
      ADR1 => GND
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_0_xor : X_XOR2
    port map (
      I0 => U7_U3_M2_count_Q_0_rt,
      I1 => N8300,
      O => U7_U3_M2_count_n0000(0)
    );
  U7_U3_M1_count_LPM_COUNTER_2_n0000_0_xor11 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_M1_count(0),
      O => U7_U3_M1_count_n0000(0),
      ADR1 => GND
    );
  U7_U3_M2_count_LPM_COUNTER_1_n0000_0_cy : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => U7_U3_M2_count_Q_0_rt,
      O => U7_U3_M2_count_LPM_COUNTER_1_n0000_0_cyo
    );
  U7_U3_M1_count_LPM_COUNTER_2_n0000_2_xor11 : X_LUT3
    generic map(
      INIT => X"A9"
    )
    port map (
      ADR0 => U7_U3_M1_count(2),
      ADR1 => U7_U3_M1_count(0),
      ADR2 => U7_U3_M1_count(1),
      O => U7_U3_M1_count_n0000(2)
    );
  U7_U3_M2_count_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U3_M2_count_n0000(1),
      CE => U7_U3_M2_count_0_4_N1306,
      SET => U7_U3_M2_count_1_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M2_count(1),
      RST => GND
    );
  U7_U3_M2_count_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U7_U3_M2_count_n0000(2),
      CE => U7_U3_M2_count_0_4_N1306,
      SET => U7_U3_M2_count_2_GSR_OR,
      CLK => U7_ck_slow,
      O => U7_U3_M2_count(2),
      RST => GND
    );
  U5_conta_0_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_1,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(1)
    );
  U5_conta_0_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_5,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(5)
    );
  U5_pulse_reg1_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18126,
      CE => U5_n0025,
      RST => U5_pulse_reg1_13_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(13),
      SET => GND
    );
  U5_n00371 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => U5_q1_1,
      ADR1 => U5_conta_1(7),
      O => pulse_1_OBUF
    );
  U5_n00351 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => U5_q0_1,
      ADR1 => U5_conta_0(7),
      O => pulse_0_OBUF
    );
  U5_n00301 : X_LUT3
    generic map(
      INIT => X"4F"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_conta_1(7),
      O => U5_n0030
    );
  U5_n00271 : X_LUT3
    generic map(
      INIT => X"4F"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_conta_0(7),
      O => U5_n0027
    );
  U5_n00251 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => grp(3),
      O => U5_n0025
    );
  U5_n00241 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => grp(2),
      ADR2 => add_int(0),
      ADR3 => add_int(1),
      O => U5_n0024
    );
  U5_n00231 : X_LUT3
    generic map(
      INIT => X"8A"
    )
    port map (
      ADR0 => U5_conta_1(7),
      ADR1 => U5_ps2(1),
      ADR2 => U5_ps1(1),
      O => U5_n0023
    );
  U5_n00221 : X_LUT3
    generic map(
      INIT => X"8A"
    )
    port map (
      ADR0 => U5_conta_0(7),
      ADR1 => U5_ps2(0),
      ADR2 => U5_ps1(0),
      O => U5_n0022
    );
  U5_pulse_reg0_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18124,
      CE => U5_n0024,
      RST => U5_pulse_reg0_12_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(12),
      SET => GND
    );
  U5_pulse_reg0_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => U5_n0024,
      RST => U5_pulse_reg0_6_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(6),
      SET => GND
    );
  U5_pulse_reg0_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18122,
      CE => U5_n0024,
      RST => U5_pulse_reg0_11_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(11),
      SET => GND
    );
  U5_pulse_reg0_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => U5_n0024,
      RST => U5_pulse_reg0_5_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(5),
      SET => GND
    );
  U5_pulse_reg0_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18120,
      CE => U5_n0024,
      RST => U5_pulse_reg0_10_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(10),
      SET => GND
    );
  U5_pulse_reg0_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18118,
      CE => U5_n0024,
      RST => U5_pulse_reg0_9_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(9),
      SET => GND
    );
  U5_pulse_reg0_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18114,
      CE => U5_n0024,
      RST => U5_pulse_reg0_8_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(8),
      SET => GND
    );
  U5_pulse_reg0_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18112,
      CE => U5_n0024,
      RST => U5_pulse_reg0_7_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(7),
      SET => GND
    );
  U5_n00111 : X_LUT3
    generic map(
      INIT => X"8A"
    )
    port map (
      ADR0 => U5_q1_0,
      ADR1 => U5_ps2(1),
      ADR2 => U5_ps1(1),
      O => U5_n0011
    );
  U5_ps1_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_pulse_in(0),
      RST => U5_ps1_0_GSR_OR,
      CLK => CLK,
      O => U5_ps1(0),
      CE => VCC,
      SET => GND
    );
  U5_n00091 : X_LUT3
    generic map(
      INIT => X"8A"
    )
    port map (
      ADR0 => U5_q0_0,
      ADR1 => U5_ps2(0),
      ADR2 => U5_ps1(0),
      O => U5_n0009
    );
  U5_ps2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_ps1(0),
      RST => U5_ps2_0_GSR_OR,
      CLK => CLK,
      O => U5_ps2(0),
      CE => VCC,
      SET => GND
    );
  U5_pulse_in_0_1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => v_pulse(0),
      ADR1 => plsttl_0_IBUF,
      O => U5_pulse_in(0)
    );
  U5_pulse_in_1_1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => v_pulse(1),
      ADR1 => plsttl_1_IBUF,
      O => U5_pulse_in(1)
    );
  U5_psync_1_1 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      O => U5_psync(1)
    );
  U5_psync_0_1 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      O => U5_psync(0)
    );
  U5_I11_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_U5_I11_0_T,
      O => db_out(15)
    );
  U5_I10_0 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_U5_I10_0_T,
      O => db_out(15)
    );
  U5_ps2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_ps1(1),
      RST => U5_ps2_1_GSR_OR,
      CLK => CLK,
      O => U5_ps2(1),
      CE => VCC,
      SET => GND
    );
  U5_ps1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_pulse_in(1),
      RST => U5_ps1_1_GSR_OR,
      CLK => CLK,
      O => U5_ps1(1),
      CE => VCC,
      SET => GND
    );
  U5_q1_1_30 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U5_n0011,
      SET => U5_q1_1_GSR_OR,
      CLK => CLK,
      O => U5_q1_1,
      CE => VCC,
      RST => GND
    );
  U5_q1_0_31 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U5_n0023,
      SET => U5_q1_0_GSR_OR,
      CLK => CLK,
      O => U5_q1_0,
      CE => VCC,
      RST => GND
    );
  U5_q0_1_32 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U5_n0009,
      SET => U5_q0_1_GSR_OR,
      CLK => CLK,
      O => U5_q0_1,
      CE => VCC,
      RST => GND
    );
  U5_q0_0_33 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U5_n0022,
      SET => U5_q0_0_GSR_OR,
      CLK => CLK,
      O => U5_q0_0,
      CE => VCC,
      RST => GND
    );
  U5_conta_1_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_6,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(6)
    );
  U5_pulse_reg0_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18126,
      CE => U5_n0024,
      RST => U5_pulse_reg0_13_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(13),
      SET => GND
    );
  U5_I11_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => U1_fq5_q,
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => grp(3),
      O => U5_I11_N1141
    );
  U5_I11_15 : X_TRI
    port map (
      I => U5_pulse_reg1(0),
      CTL => NlwInverterSignal_U5_I11_15_T,
      O => db_out(0)
    );
  U5_I11_14 : X_TRI
    port map (
      I => U5_pulse_reg1(1),
      CTL => NlwInverterSignal_U5_I11_14_T,
      O => db_out(1)
    );
  U5_I11_13 : X_TRI
    port map (
      I => U5_pulse_reg1(2),
      CTL => NlwInverterSignal_U5_I11_13_T,
      O => db_out(2)
    );
  U5_I11_12 : X_TRI
    port map (
      I => U5_pulse_reg1(3),
      CTL => NlwInverterSignal_U5_I11_12_T,
      O => db_out(3)
    );
  U5_I11_11 : X_TRI
    port map (
      I => U5_pulse_reg1(4),
      CTL => NlwInverterSignal_U5_I11_11_T,
      O => db_out(4)
    );
  U5_I11_10 : X_TRI
    port map (
      I => U5_pulse_reg1(5),
      CTL => NlwInverterSignal_U5_I11_10_T,
      O => db_out(5)
    );
  U5_I11_9 : X_TRI
    port map (
      I => U5_pulse_reg1(6),
      CTL => NlwInverterSignal_U5_I11_9_T,
      O => db_out(6)
    );
  U5_I11_8 : X_TRI
    port map (
      I => U5_pulse_reg1(7),
      CTL => NlwInverterSignal_U5_I11_8_T,
      O => db_out(7)
    );
  U5_I11_7 : X_TRI
    port map (
      I => U5_pulse_reg1(8),
      CTL => NlwInverterSignal_U5_I11_7_T,
      O => db_out(8)
    );
  U5_I11_6 : X_TRI
    port map (
      I => U5_pulse_reg1(9),
      CTL => NlwInverterSignal_U5_I11_6_T,
      O => db_out(9)
    );
  U5_I11_5 : X_TRI
    port map (
      I => U5_pulse_reg1(10),
      CTL => NlwInverterSignal_U5_I11_5_T,
      O => db_out(10)
    );
  U5_I11_4 : X_TRI
    port map (
      I => U5_pulse_reg1(11),
      CTL => NlwInverterSignal_U5_I11_4_T,
      O => db_out(11)
    );
  U5_I11_3 : X_TRI
    port map (
      I => U5_pulse_reg1(12),
      CTL => NlwInverterSignal_U5_I11_3_T,
      O => db_out(12)
    );
  U5_I11_2 : X_TRI
    port map (
      I => U5_pulse_reg1(13),
      CTL => NlwInverterSignal_U5_I11_2_T,
      O => db_out(13)
    );
  U5_I11_1 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_U5_I11_1_T,
      O => db_out(14)
    );
  U5_I10_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => add_int(1),
      ADR2 => U1_fq5_q,
      ADR3 => grp(2),
      O => U5_I10_N1141
    );
  U5_I10_15 : X_TRI
    port map (
      I => U5_pulse_reg0(0),
      CTL => NlwInverterSignal_U5_I10_15_T,
      O => db_out(0)
    );
  U5_I10_14 : X_TRI
    port map (
      I => U5_pulse_reg0(1),
      CTL => NlwInverterSignal_U5_I10_14_T,
      O => db_out(1)
    );
  U5_I10_13 : X_TRI
    port map (
      I => U5_pulse_reg0(2),
      CTL => NlwInverterSignal_U5_I10_13_T,
      O => db_out(2)
    );
  U5_I10_12 : X_TRI
    port map (
      I => U5_pulse_reg0(3),
      CTL => NlwInverterSignal_U5_I10_12_T,
      O => db_out(3)
    );
  U5_I10_11 : X_TRI
    port map (
      I => U5_pulse_reg0(4),
      CTL => NlwInverterSignal_U5_I10_11_T,
      O => db_out(4)
    );
  U5_I10_10 : X_TRI
    port map (
      I => U5_pulse_reg0(5),
      CTL => NlwInverterSignal_U5_I10_10_T,
      O => db_out(5)
    );
  U5_I10_9 : X_TRI
    port map (
      I => U5_pulse_reg0(6),
      CTL => NlwInverterSignal_U5_I10_9_T,
      O => db_out(6)
    );
  U5_I10_8 : X_TRI
    port map (
      I => U5_pulse_reg0(7),
      CTL => NlwInverterSignal_U5_I10_8_T,
      O => db_out(7)
    );
  U5_I10_7 : X_TRI
    port map (
      I => U5_pulse_reg0(8),
      CTL => NlwInverterSignal_U5_I10_7_T,
      O => db_out(8)
    );
  U5_I10_6 : X_TRI
    port map (
      I => U5_pulse_reg0(9),
      CTL => NlwInverterSignal_U5_I10_6_T,
      O => db_out(9)
    );
  U5_I10_5 : X_TRI
    port map (
      I => U5_pulse_reg0(10),
      CTL => NlwInverterSignal_U5_I10_5_T,
      O => db_out(10)
    );
  U5_I10_4 : X_TRI
    port map (
      I => U5_pulse_reg0(11),
      CTL => NlwInverterSignal_U5_I10_4_T,
      O => db_out(11)
    );
  U5_I10_3 : X_TRI
    port map (
      I => U5_pulse_reg0(12),
      CTL => NlwInverterSignal_U5_I10_3_T,
      O => db_out(12)
    );
  U5_I10_2 : X_TRI
    port map (
      I => U5_pulse_reg0(13),
      CTL => NlwInverterSignal_U5_I10_2_T,
      O => db_out(13)
    );
  U5_I10_1 : X_TRI
    port map (
      I => tp3_OBUF,
      CTL => NlwInverterSignal_U5_I10_1_T,
      O => db_out(14)
    );
  U5_pulse_reg1_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => U5_n0025,
      RST => U5_pulse_reg1_0_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(0),
      SET => GND
    );
  U5_pulse_reg1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => U5_n0025,
      RST => U5_pulse_reg1_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(1),
      SET => GND
    );
  U5_pulse_reg1_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => U5_n0025,
      RST => U5_pulse_reg1_2_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(2),
      SET => GND
    );
  U5_pulse_reg1_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => U5_n0025,
      RST => U5_pulse_reg1_3_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(3),
      SET => GND
    );
  U5_pulse_reg1_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => U5_n0025,
      RST => U5_pulse_reg1_4_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(4),
      SET => GND
    );
  U5_pulse_reg1_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => U5_n0025,
      RST => U5_pulse_reg1_5_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(5),
      SET => GND
    );
  U5_pulse_reg1_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => U5_n0025,
      RST => U5_pulse_reg1_6_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(6),
      SET => GND
    );
  U5_pulse_reg1_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18112,
      CE => U5_n0025,
      RST => U5_pulse_reg1_7_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(7),
      SET => GND
    );
  U5_pulse_reg1_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18114,
      CE => U5_n0025,
      RST => U5_pulse_reg1_8_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(8),
      SET => GND
    );
  U5_pulse_reg1_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18118,
      CE => U5_n0025,
      RST => U5_pulse_reg1_9_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(9),
      SET => GND
    );
  U5_pulse_reg1_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18120,
      CE => U5_n0025,
      RST => U5_pulse_reg1_10_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(10),
      SET => GND
    );
  U5_pulse_reg1_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18122,
      CE => U5_n0025,
      RST => U5_pulse_reg1_11_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(11),
      SET => GND
    );
  U5_pulse_reg1_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18124,
      CE => U5_n0025,
      RST => U5_pulse_reg1_12_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1(12),
      SET => GND
    );
  U5_pulse_reg0_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => U5_n0024,
      RST => U5_pulse_reg0_0_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(0),
      SET => GND
    );
  U5_pulse_reg0_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => U5_n0024,
      RST => U5_pulse_reg0_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(1),
      SET => GND
    );
  U5_pulse_reg0_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => U5_n0024,
      RST => U5_pulse_reg0_2_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(2),
      SET => GND
    );
  U5_pulse_reg0_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => U5_n0024,
      RST => U5_pulse_reg0_3_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(3),
      SET => GND
    );
  U5_pulse_reg0_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => U5_n0024,
      RST => U5_pulse_reg0_4_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0(4),
      SET => GND
    );
  U5_conta_1_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_7,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(7)
    );
  U5_conta_0_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_2,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(2)
    );
  U5_conta_1_inst_cy_0_34 : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => U5_psync(1),
      O => U5_conta_1_inst_cy_0
    );
  U5_conta_0_inst_lut3_71 : X_LUT3
    generic map(
      INIT => X"4F"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_conta_0(7),
      O => U5_conta_0_inst_lut3_7
    );
  U5_conta_1_inst_cy_1_35 : X_MUX2
    port map (
      IB => U5_conta_1_inst_cy_0,
      IA => N8300,
      SEL => U5_conta_1_inst_lut3_0,
      O => U5_conta_1_inst_cy_1
    );
  U5_conta_1_inst_sum_0_36 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_0,
      I1 => U5_conta_1_inst_cy_0,
      O => U5_conta_1_inst_sum_0
    );
  U5_conta_0_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_pulse_reg0(7),
      ADR3 => U5_conta_0(0),
      O => U5_conta_0_inst_lut3_0
    );
  U5_conta_1_inst_cy_2_37 : X_MUX2
    port map (
      IB => U5_conta_1_inst_cy_1,
      IA => N8300,
      SEL => U5_conta_1_inst_lut3_1,
      O => U5_conta_1_inst_cy_2
    );
  U5_conta_1_inst_sum_1_38 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_1,
      I1 => U5_conta_1_inst_cy_1,
      O => U5_conta_1_inst_sum_1
    );
  U5_conta_0_inst_lut3_11 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_pulse_reg0(8),
      ADR3 => U5_conta_0(1),
      O => U5_conta_0_inst_lut3_1
    );
  U5_conta_1_inst_cy_3_39 : X_MUX2
    port map (
      IB => U5_conta_1_inst_cy_2,
      IA => N8300,
      SEL => U5_conta_1_inst_lut3_2,
      O => U5_conta_1_inst_cy_3
    );
  U5_conta_1_inst_sum_2_40 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_2,
      I1 => U5_conta_1_inst_cy_2,
      O => U5_conta_1_inst_sum_2
    );
  U5_conta_0_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_pulse_reg0(9),
      ADR3 => U5_conta_0(2),
      O => U5_conta_0_inst_lut3_2
    );
  U5_conta_1_inst_cy_4_41 : X_MUX2
    port map (
      IB => U5_conta_1_inst_cy_3,
      IA => N8300,
      SEL => U5_conta_1_inst_lut3_3,
      O => U5_conta_1_inst_cy_4
    );
  U5_conta_1_inst_sum_3_42 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_3,
      I1 => U5_conta_1_inst_cy_3,
      O => U5_conta_1_inst_sum_3
    );
  U5_conta_0_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_pulse_reg0(10),
      ADR3 => U5_conta_0(3),
      O => U5_conta_0_inst_lut3_3
    );
  U5_conta_1_inst_cy_5_43 : X_MUX2
    port map (
      IB => U5_conta_1_inst_cy_4,
      IA => N8300,
      SEL => U5_conta_1_inst_lut3_4,
      O => U5_conta_1_inst_cy_5
    );
  U5_conta_1_inst_sum_4_44 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_4,
      I1 => U5_conta_1_inst_cy_4,
      O => U5_conta_1_inst_sum_4
    );
  U5_conta_0_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_pulse_reg0(11),
      ADR3 => U5_conta_0(4),
      O => U5_conta_0_inst_lut3_4
    );
  U5_conta_1_inst_cy_6_45 : X_MUX2
    port map (
      IB => U5_conta_1_inst_cy_5,
      IA => N8300,
      SEL => U5_conta_1_inst_lut3_5,
      O => U5_conta_1_inst_cy_6
    );
  U5_conta_1_inst_sum_5_46 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_5,
      I1 => U5_conta_1_inst_cy_5,
      O => U5_conta_1_inst_sum_5
    );
  U5_conta_0_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_pulse_reg0(12),
      ADR3 => U5_conta_0(5),
      O => U5_conta_0_inst_lut3_5
    );
  U5_conta_1_inst_cy_7_47 : X_MUX2
    port map (
      IB => U5_conta_1_inst_cy_6,
      IA => N8300,
      SEL => U5_conta_1_inst_lut3_6,
      O => U5_conta_1_inst_cy_7
    );
  U5_conta_1_inst_sum_6_48 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_6,
      I1 => U5_conta_1_inst_cy_6,
      O => U5_conta_1_inst_sum_6
    );
  set_trgin_rt_49 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => set_trgin,
      O => set_trgin_rt,
      ADR1 => GND
    );
  U5_conta_0_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_4,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(4)
    );
  U5_conta_1_inst_sum_7_50 : X_XOR2
    port map (
      I0 => U5_conta_1_inst_lut3_7,
      I1 => U5_conta_1_inst_cy_7,
      O => U5_conta_1_inst_sum_7
    );
  U5_conta_1_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_0,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(0)
    );
  U5_conta_1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_1,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(1)
    );
  U5_conta_1_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_2,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(2)
    );
  U5_conta_1_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_3,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(3)
    );
  U5_conta_1_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_4,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(4)
    );
  U5_conta_1_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_1_inst_sum_5,
      CE => U5_n0030,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_1(5)
    );
  U5_conta_0_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_6,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(6)
    );
  U5_conta_0_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_7,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(7)
    );
  U5_conta_0_inst_cy_0_51 : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => U5_psync(0),
      O => U5_conta_0_inst_cy_0
    );
  U5_conta_1_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_pulse_reg1(7),
      ADR3 => U5_conta_1(0),
      O => U5_conta_1_inst_lut3_0
    );
  U5_conta_0_inst_cy_1_52 : X_MUX2
    port map (
      IB => U5_conta_0_inst_cy_0,
      IA => N8300,
      SEL => U5_conta_0_inst_lut3_0,
      O => U5_conta_0_inst_cy_1
    );
  U5_conta_0_inst_sum_0_53 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_0,
      I1 => U5_conta_0_inst_cy_0,
      O => U5_conta_0_inst_sum_0
    );
  U5_conta_1_inst_lut3_11 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_pulse_reg1(8),
      ADR3 => U5_conta_1(1),
      O => U5_conta_1_inst_lut3_1
    );
  U5_conta_0_inst_cy_2_54 : X_MUX2
    port map (
      IB => U5_conta_0_inst_cy_1,
      IA => N8300,
      SEL => U5_conta_0_inst_lut3_1,
      O => U5_conta_0_inst_cy_2
    );
  U5_conta_0_inst_sum_1_55 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_1,
      I1 => U5_conta_0_inst_cy_1,
      O => U5_conta_0_inst_sum_1
    );
  U5_conta_1_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_pulse_reg1(9),
      ADR3 => U5_conta_1(2),
      O => U5_conta_1_inst_lut3_2
    );
  U5_conta_0_inst_cy_3_56 : X_MUX2
    port map (
      IB => U5_conta_0_inst_cy_2,
      IA => N8300,
      SEL => U5_conta_0_inst_lut3_2,
      O => U5_conta_0_inst_cy_3
    );
  U5_conta_0_inst_sum_2_57 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_2,
      I1 => U5_conta_0_inst_cy_2,
      O => U5_conta_0_inst_sum_2
    );
  U5_conta_1_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_pulse_reg1(10),
      ADR3 => U5_conta_1(3),
      O => U5_conta_1_inst_lut3_3
    );
  U5_conta_0_inst_cy_4_58 : X_MUX2
    port map (
      IB => U5_conta_0_inst_cy_3,
      IA => N8300,
      SEL => U5_conta_0_inst_lut3_3,
      O => U5_conta_0_inst_cy_4
    );
  U5_conta_0_inst_sum_3_59 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_3,
      I1 => U5_conta_0_inst_cy_3,
      O => U5_conta_0_inst_sum_3
    );
  U5_conta_1_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_pulse_reg1(11),
      ADR3 => U5_conta_1(4),
      O => U5_conta_1_inst_lut3_4
    );
  U5_conta_0_inst_cy_5_60 : X_MUX2
    port map (
      IB => U5_conta_0_inst_cy_4,
      IA => N8300,
      SEL => U5_conta_0_inst_lut3_4,
      O => U5_conta_0_inst_cy_5
    );
  U5_conta_0_inst_sum_4_61 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_4,
      I1 => U5_conta_0_inst_cy_4,
      O => U5_conta_0_inst_sum_4
    );
  U5_conta_1_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_pulse_reg1(12),
      ADR3 => U5_conta_1(5),
      O => U5_conta_1_inst_lut3_5
    );
  U5_conta_0_inst_cy_6_62 : X_MUX2
    port map (
      IB => U5_conta_0_inst_cy_5,
      IA => N8300,
      SEL => U5_conta_0_inst_lut3_5,
      O => U5_conta_0_inst_cy_6
    );
  U5_conta_0_inst_sum_5_63 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_5,
      I1 => U5_conta_0_inst_cy_5,
      O => U5_conta_0_inst_sum_5
    );
  U5_conta_1_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_pulse_reg1(13),
      ADR3 => U5_conta_1(6),
      O => U5_conta_1_inst_lut3_6
    );
  U5_conta_0_inst_cy_7_64 : X_MUX2
    port map (
      IB => U5_conta_0_inst_cy_6,
      IA => N8300,
      SEL => U5_conta_0_inst_lut3_6,
      O => U5_conta_0_inst_cy_7
    );
  U5_conta_0_inst_sum_6_65 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_6,
      I1 => U5_conta_0_inst_cy_6,
      O => U5_conta_0_inst_sum_6
    );
  U5_conta_1_inst_lut3_71 : X_LUT3
    generic map(
      INIT => X"4F"
    )
    port map (
      ADR0 => U5_ps2(1),
      ADR1 => U5_ps1(1),
      ADR2 => U5_conta_1(7),
      O => U5_conta_1_inst_lut3_7
    );
  U5_conta_0_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U5_conta_0_inst_sum_3,
      CE => U5_n0027,
      RST => GSR,
      SET => reset,
      CLK => CLK,
      O => U5_conta_0(3)
    );
  U5_conta_0_inst_sum_7_66 : X_XOR2
    port map (
      I0 => U5_conta_0_inst_lut3_7,
      I1 => U5_conta_0_inst_cy_7,
      O => U5_conta_0_inst_sum_7
    );
  U7_U4_n00141 : X_LUT3
    generic map(
      INIT => X"F2"
    )
    port map (
      ADR0 => U7_read_read_q,
      ADR1 => U7_U3_M2_end_count,
      ADR2 => N18359,
      O => U7_U4_n0014
    );
  U7_U4_crc_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0003,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_5_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(5),
      SET => GND
    );
  U7_U4_crc_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0002,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_6_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(6),
      SET => GND
    );
  U7_U4_crc_reg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0001,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_7_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(7),
      SET => GND
    );
  U7_U4_crc_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0004,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_4_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(4),
      SET => GND
    );
  U7_U4_Mxor_crc_in_Result1 : X_LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      ADR0 => U7_U4_crc_reg(0),
      ADR1 => U7_r_reg,
      O => U7_U4_crc_in
    );
  U7_U4_Mmux_n0008_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => U7_U4_crc_reg(1),
      ADR2 => N18098,
      O => U7_U4_n0008
    );
  U7_U4_Mmux_n0007_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => U7_U4_crc_reg(2),
      ADR2 => N18100,
      O => U7_U4_n0007
    );
  U7_U4_Mmux_n0006_Result1 : X_LUT4
    generic map(
      INIT => X"8DD8"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => N18102,
      ADR2 => U7_U4_crc_in,
      ADR3 => U7_U4_crc_reg(3),
      O => U7_U4_n0006
    );
  U7_U4_Mmux_n0005_Result1 : X_LUT4
    generic map(
      INIT => X"8DD8"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => N18104,
      ADR2 => U7_U4_crc_in,
      ADR3 => U7_U4_crc_reg(4),
      O => U7_U4_n0005
    );
  U7_U4_Mmux_n0004_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => U7_U4_crc_reg(5),
      ADR2 => N18106,
      O => U7_U4_n0004
    );
  U7_U4_Mmux_n0003_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => U7_U4_crc_reg(6),
      ADR2 => N18108,
      O => U7_U4_n0003
    );
  U7_U4_Mmux_n0002_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => U7_U4_crc_reg(7),
      ADR2 => N18110,
      O => U7_U4_n0002
    );
  U1_d_lec1 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => write_IBUF,
      ADR1 => U1_fds_q,
      ADR2 => CHOICE251,
      ADR3 => CHOICE256,
      O => U1_d_lec
    );
  U7_U4_crc_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0008,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_0_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(0),
      SET => GND
    );
  U7_U4_crc_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0007,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_1_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(1),
      SET => GND
    );
  U7_U4_crc_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U7_U4_n0006,
      CE => U7_U4_n0014,
      RST => U7_U4_crc_reg_2_GSR_OR,
      CLK => CLK,
      O => U7_U4_crc_reg(2),
      SET => GND
    );
  U1_fq8_q_67 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_not_ds0,
      CE => N8300,
      RST => GSR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U1_fq8_q
    );
  U1_not_ds01 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => ds0_IBUFG,
      O => U1_not_ds0,
      ADR1 => GND
    );
  U1_dtack1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U1_fq4_q,
      ADR1 => U4_fr2_q,
      ADR2 => U2_fr2_q,
      ADR3 => U3_fr2_q,
      O => dtack_OBUF
    );
  U1_fds_q_68 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_fq8_q,
      CE => N8300,
      RST => U1_fds_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U1_fds_q
    );
  U1_etr1 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U1_fq5_q,
      O => tp1_OBUF,
      ADR1 => GND
    );
  irq_7_9 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => int_lev_2(2),
      ADR1 => U4_fr9_q,
      ADR2 => int_lev_2(0),
      ADR3 => int_lev_2(1),
      O => CHOICE114
    );
  U1_ena_d1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => U1_fq2_q,
      ADR1 => U1_fq5_q,
      O => U1_ena_d
    );
  U6_Ker14000_SW0 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => add_int(1),
      ADR1 => grp(1),
      ADR2 => U1_fq4_q,
      ADR3 => U1_fq2_q,
      O => N17449
    );
  U1_fq4_q_69 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_ena_d,
      CE => N8300,
      RST => GSR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U1_fq4_q
    );
  U1_d_esc1 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => CHOICE251,
      ADR1 => U1_fds_q,
      ADR2 => write_IBUF,
      ADR3 => CHOICE256,
      O => U1_d_esc
    );
  U1_fq5_q_70 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N8300,
      CE => U1_d_lec,
      RST => U1_fq5_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U1_fq5_q
    );
  U1_fq2_q_71 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_fq1_q,
      CE => N8300,
      RST => U1_fq2_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U1_fq2_q
    );
  U3_s118 : X_LUT4
    generic map(
      INIT => X"4004"
    )
    port map (
      ADR0 => iack_IBUF,
      ADR1 => U3_fr4_q,
      ADR2 => add_int(1),
      ADR3 => int_lev_1(1),
      O => CHOICE266
    );
  U1_ds_rst1 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => ds0_IBUFG,
      ADR1 => ds1_IBUF,
      O => U1_ds_rst
    );
  U6_S2_trg_cntin_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_8,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(8)
    );
  U6_S2_trg_cntin_inst_lut3_181 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(10),
      ADR2 => U6_S2_trg_cntin_18,
      O => U6_S2_trg_cntin_inst_lut3_18
    );
  U6_S2_trg_cntin_inst_lut3_191 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(11),
      ADR2 => U6_S2_trg_cntin_19,
      O => U6_S2_trg_cntin_inst_lut3_19
    );
  U6_S2_trg_cntin_inst_lut3_211 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(13),
      ADR2 => U6_S2_trg_cntin_21,
      O => U6_S2_trg_cntin_inst_lut3_21
    );
  U6_S2_trg_cntin_inst_lut3_201 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(12),
      ADR2 => U6_S2_trg_cntin_20,
      O => U6_S2_trg_cntin_inst_lut3_20
    );
  U6_S2_trg_cntin_inst_lut3_231 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(15),
      ADR2 => U6_S2_trg_cntin_23,
      O => U6_S2_trg_cntin_inst_lut3_23
    );
  U6_S2_trg_cntin_inst_lut3_221 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(14),
      ADR2 => U6_S2_trg_cntin_22,
      O => U6_S2_trg_cntin_inst_lut3_22
    );
  U4_s21 : X_LUT4
    generic map(
      INIT => X"5444"
    )
    port map (
      ADR0 => U4_fr2_q,
      ADR1 => U4_fr9_q,
      ADR2 => int_ena(2),
      ADR3 => U6_S2_trg_cntin_23,
      O => U4_s2
    );
  U4_fr4_q_72 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_fr9_q,
      CE => U4_fr3_q,
      RST => U4_fr4_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr4_q
    );
  U4_fr9_q_73 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_s2,
      CE => N8300,
      RST => U4_fr9_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr9_q
    );
  U4_fr8_q_74 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_s1,
      CE => U4_fr7_q,
      RST => GSR,
      SET => as_IBUF,
      CLK => CLK,
      O => U4_fr8_q
    );
  U4_fr7_q_75 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_fr6_q,
      CE => N8300,
      RST => U4_fr7_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr7_q
    );
  U4_fr3_q_76 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => ds0_IBUFG,
      CE => N8300,
      RST => U4_fr3_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr3_q
    );
  U4_fr2_q_77 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_s1,
      CE => U4_fr7_q,
      RST => U4_fr2_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr2_q
    );
  U4_fr1_q_78 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_s1,
      CE => U4_fr6_q,
      RST => U4_fr1_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr1_q
    );
  U4_fr5_q_79 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_s3,
      CE => N8300,
      RST => U4_fr5_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr5_q
    );
  U4_fr6_q_80 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U4_fr5_q,
      CE => N8300,
      RST => U4_fr6_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U4_fr6_q
    );
  U4_s31 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U3_fr8_q,
      O => U4_s3,
      ADR1 => GND
    );
  U4_etr_ivec1 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U4_fr1_q,
      O => etr_ivec(2),
      ADR1 => GND
    );
  U6_S2_trg_cntin_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_9,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(9)
    );
  U6_S2_trg_cntin_inst_cy_20_81 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_19,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_18,
      O => U6_S2_trg_cntin_inst_cy_20
    );
  U6_S2_trg_cntin_inst_cy_21_82 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_20,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_19,
      O => U6_S2_trg_cntin_inst_cy_21
    );
  U6_S2_trg_cntin_inst_cy_23_83 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_22,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_21,
      O => U6_S2_trg_cntin_inst_cy_23
    );
  U6_S2_trg_cntin_inst_cy_22_84 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_21,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_20,
      O => U6_S2_trg_cntin_inst_cy_22
    );
  U6_S2_trg_cntin_19_85 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_19,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_19
    );
  U6_S2_trg_cntin_inst_cy_24_86 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_23,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_22,
      O => U6_S2_trg_cntin_inst_cy_24
    );
  U3_s21 : X_LUT4
    generic map(
      INIT => X"5444"
    )
    port map (
      ADR0 => U3_fr2_q,
      ADR1 => U3_fr9_q,
      ADR2 => int_ena(1),
      ADR3 => int_ext_1_IBUF,
      O => U3_s2
    );
  U3_fr4_q_87 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_fr9_q,
      CE => U4_fr3_q,
      RST => U3_fr4_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U3_fr4_q
    );
  U3_fr9_q_88 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_s2,
      CE => N8300,
      RST => U3_fr9_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U3_fr9_q
    );
  U3_fr8_q_89 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_s1,
      CE => U3_fr7_q,
      RST => GSR,
      SET => as_IBUF,
      CLK => CLK,
      O => U3_fr8_q
    );
  U3_fr7_q_90 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_fr6_q,
      CE => N8300,
      RST => U3_fr7_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U3_fr7_q
    );
  delay_0_0_OBUF : X_BUF
    port map (
      I => U5_pulse_reg0_0_1,
      O => delay_0_0_OBUF_GTS_TRI
    );
  U3_fr2_q_91 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_s1,
      CE => U3_fr7_q,
      RST => U3_fr2_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U3_fr2_q
    );
  U3_fr1_q_92 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_s1,
      CE => U3_fr6_q,
      RST => U3_fr1_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U3_fr1_q
    );
  U3_fr5_q_93 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_s3,
      CE => N8300,
      RST => U3_fr5_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U3_fr5_q
    );
  U3_fr6_q_94 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_fr5_q,
      CE => N8300,
      RST => U3_fr6_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U3_fr6_q
    );
  U3_s31 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U2_fr8_q,
      O => U3_s3,
      ADR1 => GND
    );
  U3_etr_ivec1 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U3_fr1_q,
      O => etr_ivec(1),
      ADR1 => GND
    );
  U6_S2_trg_cntin_inst_sum_23_95 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_23,
      I1 => U6_S2_trg_cntin_inst_cy_24,
      O => U6_S2_trg_cntin_inst_sum_23
    );
  U6_S2_trg_cntin_inst_sum_17_96 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_17,
      I1 => U6_S2_trg_cntin_inst_cy_18,
      O => U6_S2_trg_cntin_inst_sum_17
    );
  U6_S2_trg_cntin_inst_sum_18_97 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_18,
      I1 => U6_S2_trg_cntin_inst_cy_19,
      O => U6_S2_trg_cntin_inst_sum_18
    );
  U6_S2_trg_cntin_inst_sum_20_98 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_20,
      I1 => U6_S2_trg_cntin_inst_cy_21,
      O => U6_S2_trg_cntin_inst_sum_20
    );
  U6_S2_trg_cntin_inst_sum_19_99 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_19,
      I1 => U6_S2_trg_cntin_inst_cy_20,
      O => U6_S2_trg_cntin_inst_sum_19
    );
  U6_S2_trg_cntin_inst_sum_22_100 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_22,
      I1 => U6_S2_trg_cntin_inst_cy_23,
      O => U6_S2_trg_cntin_inst_sum_22
    );
  U6_S2_trg_cntin_inst_sum_21_101 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_21,
      I1 => U6_S2_trg_cntin_inst_cy_22,
      O => U6_S2_trg_cntin_inst_sum_21
    );
  U2_s21 : X_LUT4
    generic map(
      INIT => X"5444"
    )
    port map (
      ADR0 => U2_fr2_q,
      ADR1 => U2_fr9_q,
      ADR2 => int_ena(0),
      ADR3 => int_ext_0_IBUF,
      O => U2_s2
    );
  U2_fr4_q_102 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fr9_q,
      CE => U4_fr3_q,
      RST => U2_fr4_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U2_fr4_q
    );
  U2_fr9_q_103 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_s2,
      CE => N8300,
      RST => U2_fr9_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U2_fr9_q
    );
  U2_fr8_q_104 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_s1,
      CE => U2_fr7_q,
      RST => GSR,
      SET => as_IBUF,
      CLK => CLK,
      O => U2_fr8_q
    );
  U2_fr7_q_105 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fr6_q,
      CE => N8300,
      RST => U2_fr7_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U2_fr7_q
    );
  delay_0_1_OBUF : X_BUF
    port map (
      I => U5_pulse_reg0_1_1,
      O => delay_0_1_OBUF_GTS_TRI
    );
  U2_fr2_q_106 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_s1,
      CE => U2_fr7_q,
      RST => U2_fr2_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U2_fr2_q
    );
  U2_fr1_q_107 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_s1,
      CE => U2_fr6_q,
      RST => U2_fr1_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U2_fr1_q
    );
  U2_fr5_q_108 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_s3,
      CE => N8300,
      RST => U2_fr5_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U2_fr5_q
    );
  U2_fr6_q_109 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fr5_q,
      CE => N8300,
      RST => U2_fr6_q_GSR_OR,
      SET => tp3_OBUF,
      CLK => CLK,
      O => U2_fr6_q
    );
  U2_s31 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => iackin_IBUF,
      O => U2_s3,
      ADR1 => GND
    );
  U2_etr_ivec1 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U2_fr1_q,
      O => etr_ivec(0),
      ADR1 => GND
    );
  U6_n01951 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => U6_S2_trg_cntin_23,
      ADR1 => U6_v_0,
      ADR2 => U6_v_1,
      ADR3 => set_trgin,
      O => U6_n0195
    );
  U6_n0161_SW1 : X_LUT3
    generic map(
      INIT => X"BF"
    )
    port map (
      ADR0 => add_int(1),
      ADR1 => add_int(0),
      ADR2 => grp(1),
      O => N18318
    );
  U6_trigger_n0000_31_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_31_rt,
      I1 => U6_trigger_n0000_30_cyo,
      O => U6_n0000(31)
    );
  U6_Mmux_n0070_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18098,
      ADR2 => U6_trg_cntout(0),
      O => U6_n0070
    );
  irq_2_44_SW0 : X_LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      ADR0 => int_lev_1(0),
      ADR1 => int_lev_1(1),
      ADR2 => U3_fr9_q,
      O => N18304
    );
  U6_n01441 : X_LUT4
    generic map(
      INIT => X"CCCE"
    )
    port map (
      ADR0 => trg_dly_p_OBUF,
      ADR1 => N18276,
      ADR2 => N17449,
      ADR3 => U6_q_in,
      O => U6_n0144
    );
  U6_n01271 : X_LUT4
    generic map(
      INIT => X"CCCE"
    )
    port map (
      ADR0 => trg_dly_p_OBUF,
      ADR1 => N18280,
      ADR2 => N17449,
      ADR3 => U6_q_in,
      O => U6_n0127
    );
  U6_trg_delay_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18128,
      CE => U6_n0001,
      RST => U6_trg_delay_14_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(14),
      SET => GND
    );
  U6_I73_2 : X_TRI
    port map (
      I => U6_trg_delay(13),
      CTL => NlwInverterSignal_U6_I73_2_T,
      O => db_out(13)
    );
  U6_trg_delay_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18126,
      CE => U6_n0001,
      RST => U6_trg_delay_13_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(13),
      SET => GND
    );
  U6_I73_3 : X_TRI
    port map (
      I => U6_trg_delay(12),
      CTL => NlwInverterSignal_U6_I73_3_T,
      O => db_out(12)
    );
  U6_trg_delay_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18124,
      CE => U6_n0001,
      RST => U6_trg_delay_12_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(12),
      SET => GND
    );
  U6_I73_4 : X_TRI
    port map (
      I => U6_trg_delay(11),
      CTL => NlwInverterSignal_U6_I73_4_T,
      O => db_out(11)
    );
  U6_trg_cntoutreg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0066,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_4_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(4),
      SET => GND
    );
  U6_trg_delay_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18122,
      CE => U6_n0001,
      RST => U6_trg_delay_11_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(11),
      SET => GND
    );
  U6_I73_5 : X_TRI
    port map (
      I => U6_trg_delay(10),
      CTL => NlwInverterSignal_U6_I73_5_T,
      O => db_out(10)
    );
  U6_trg_cntoutreg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0065,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_5_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(5),
      SET => GND
    );
  U6_trg_delay_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18120,
      CE => U6_n0001,
      RST => U6_trg_delay_10_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(10),
      SET => GND
    );
  U6_I73_6 : X_TRI
    port map (
      I => U6_trg_delay(9),
      CTL => NlwInverterSignal_U6_I73_6_T,
      O => db_out(9)
    );
  U6_trg_delay_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18114,
      CE => U6_n0001,
      RST => U6_trg_delay_8_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(8),
      SET => GND
    );
  U6_I73_8 : X_TRI
    port map (
      I => U6_trg_delay(7),
      CTL => NlwInverterSignal_U6_I73_8_T,
      O => db_out(7)
    );
  U6_I73_7 : X_TRI
    port map (
      I => U6_trg_delay(8),
      CTL => NlwInverterSignal_U6_I73_7_T,
      O => db_out(8)
    );
  U6_trg_maxcnt_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_6_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(6),
      SET => GND
    );
  U6_trg_maxcnt_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18112,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_7_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(7),
      SET => GND
    );
  U6_trg_maxcnt_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18114,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_8_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(8),
      SET => GND
    );
  U6_trg_maxcnt_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18118,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_9_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(9),
      SET => GND
    );
  U6_trg_maxcnt_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18120,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_10_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(10),
      SET => GND
    );
  U6_trg_maxcnt_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18122,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_11_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(11),
      SET => GND
    );
  U6_trg_maxcnt_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18124,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_12_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(12),
      SET => GND
    );
  U6_trg_maxcnt_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18126,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_13_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(13),
      SET => GND
    );
  U6_trg_maxcnt_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18128,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_14_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(14),
      SET => GND
    );
  U6_trg_delay_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => U6_n0001,
      RST => U6_trg_delay_0_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(0),
      SET => GND
    );
  U6_trg_delay_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => U6_n0001,
      RST => U6_trg_delay_1_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(1),
      SET => GND
    );
  U6_trg_delay_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => U6_n0001,
      RST => U6_trg_delay_2_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(2),
      SET => GND
    );
  U6_trg_delay_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => U6_n0001,
      RST => U6_trg_delay_3_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(3),
      SET => GND
    );
  U6_trg_delay_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => U6_n0001,
      RST => U6_trg_delay_4_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(4),
      SET => GND
    );
  U6_trg_delay_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => U6_n0001,
      RST => U6_trg_delay_5_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(5),
      SET => GND
    );
  U6_trg_delay_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => U6_n0001,
      RST => U6_trg_delay_6_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(6),
      SET => GND
    );
  U6_trg_maxcnt_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_5_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(5),
      SET => GND
    );
  U6_trg_delay_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18112,
      CE => U6_n0001,
      RST => U6_trg_delay_7_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(7),
      SET => GND
    );
  U6_S2_trg_cntin_18_110 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_18,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_18
    );
  U6_trg_cntoutreg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0064,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_6_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(6),
      SET => GND
    );
  U6_trg_cntoutreg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0063,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_7_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(7),
      SET => GND
    );
  U6_S2_trg_cntin_16_111 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_16,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_16
    );
  U6_trg_cntoutreg_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0062,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_8_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(8),
      SET => GND
    );
  U6_trg_cntoutreg_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0061,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_9_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(9),
      SET => GND
    );
  U6_n00021 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => grp(0),
      ADR2 => add_int(0),
      ADR3 => add_int(1),
      O => U6_n0002
    );
  irq_6_15 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => int_lev_2(2),
      ADR1 => U4_fr9_q,
      ADR2 => int_lev_2(0),
      ADR3 => int_lev_2(1),
      O => CHOICE206
    );
  U6_S2_trg_cntin_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_12,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(12)
    );
  U6_trg_maxcnt_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_4_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(4),
      SET => GND
    );
  U6_trg_maxcnt_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_3_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(3),
      SET => GND
    );
  U6_trg_maxcnt_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_2_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(2),
      SET => GND
    );
  U6_trg_maxcnt_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_1_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(1),
      SET => GND
    );
  U6_trg_maxcnt_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_0_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(0),
      SET => GND
    );
  U6_I73_1 : X_TRI
    port map (
      I => U6_trg_delay(14),
      CTL => NlwInverterSignal_U6_I73_1_T,
      O => db_out(14)
    );
  U6_trg_cntoutreg_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0060,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_10_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(10),
      SET => GND
    );
  U7_U4_Mmux_n0001_Result1 : X_LUT4
    generic map(
      INIT => X"8DD8"
    )
    port map (
      ADR0 => U7_U4_n0009,
      ADR1 => N18112,
      ADR2 => U7_U4_crc_reg(0),
      ADR3 => U7_r_reg,
      O => U7_U4_n0001
    );
  U6_S2_trg_cntin_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_11,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(11)
    );
  U6_S2_trg_cntin_17_112 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_17,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_17
    );
  U6_S2_trg_cntin_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_10,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(10)
    );
  U6_S2_trg_cntin_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_15,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(15)
    );
  U6_S2_trg_cntin_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_13,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(13)
    );
  U6_S2_trg_cntin_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_14,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin(14)
    );
  U6_tr_dly92 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE321,
      ADR1 => CHOICE324,
      ADR2 => CHOICE332,
      ADR3 => CHOICE348,
      O => trg_dly_p_OBUF
    );
  U6_trg_delay_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18118,
      CE => U6_n0001,
      RST => U6_trg_delay_9_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(9),
      SET => GND
    );
  U6_tr_21 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => U6_tr_1,
      ADR1 => U6_tr_0,
      O => U6_tr_2
    );
  U6_trigger_out1 : X_LUT3
    generic map(
      INIT => X"8A"
    )
    port map (
      ADR0 => trg_dly_p_OBUF,
      ADR1 => U6_q_in,
      ADR2 => trg_bypass,
      O => mctrg_OBUF
    );
  U6_Mmux_n0069_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18100,
      ADR2 => U6_trg_cntout(1),
      O => U6_n0069
    );
  U6_Mmux_n0068_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18102,
      ADR2 => U6_trg_cntout(2),
      O => U6_n0068
    );
  U6_Mmux_n0067_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18104,
      ADR2 => U6_trg_cntout(3),
      O => U6_n0067
    );
  U6_Mmux_n0066_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18106,
      ADR2 => U6_trg_cntout(4),
      O => U6_n0066
    );
  U6_Mmux_n0065_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18108,
      ADR2 => U6_trg_cntout(5),
      O => U6_n0065
    );
  U6_Mmux_n0064_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18110,
      ADR2 => U6_trg_cntout(6),
      O => U6_n0064
    );
  U6_Mmux_n0063_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18112,
      ADR2 => U6_trg_cntout(7),
      O => U6_n0063
    );
  U6_Mmux_n0062_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18114,
      ADR2 => U6_trg_cntout(8),
      O => U6_n0062
    );
  U6_Mmux_n0061_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18118,
      ADR2 => U6_trg_cntout(9),
      O => U6_n0061
    );
  U6_Mmux_n0060_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18120,
      ADR2 => U6_trg_cntout(10),
      O => U6_n0060
    );
  U6_Mmux_n0059_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18122,
      ADR2 => U6_trg_cntout(11),
      O => U6_n0059
    );
  U6_Mmux_n0058_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18124,
      ADR2 => U6_trg_cntout(12),
      O => U6_n0058
    );
  U6_Mmux_n0057_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18126,
      ADR2 => U6_trg_cntout(13),
      O => U6_n0057
    );
  U6_Mmux_n0056_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18128,
      ADR2 => U6_trg_cntout(14),
      O => U6_n0056
    );
  U6_Mmux_n0055_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18130,
      ADR2 => U6_trg_cntout(15),
      O => U6_n0055
    );
  U6_Mmux_n0053_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18098,
      ADR2 => U6_trg_cntout(16),
      O => U6_n0053
    );
  U6_Mmux_n0052_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18100,
      ADR2 => U6_trg_cntout(17),
      O => U6_n0052
    );
  U6_Mmux_n0051_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18102,
      ADR2 => U6_trg_cntout(18),
      O => U6_n0051
    );
  U6_Mmux_n0050_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18104,
      ADR2 => U6_trg_cntout(19),
      O => U6_n0050
    );
  U6_Mmux_n0049_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18106,
      ADR2 => U6_trg_cntout(20),
      O => U6_n0049
    );
  U6_Mmux_n0048_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18108,
      ADR2 => U6_trg_cntout(21),
      O => U6_n0048
    );
  U6_Mmux_n0047_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18110,
      ADR2 => U6_trg_cntout(22),
      O => U6_n0047
    );
  U6_Mmux_n0046_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18112,
      ADR2 => U6_trg_cntout(23),
      O => U6_n0046
    );
  U6_Mmux_n0045_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18114,
      ADR2 => U6_trg_cntout(24),
      O => U6_n0045
    );
  U6_Mmux_n0044_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18118,
      ADR2 => U6_trg_cntout(25),
      O => U6_n0044
    );
  U6_Mmux_n0043_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18120,
      ADR2 => U6_trg_cntout(26),
      O => U6_n0043
    );
  U6_Mmux_n0042_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18122,
      ADR2 => U6_trg_cntout(27),
      O => U6_n0042
    );
  U6_Mmux_n0041_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18124,
      ADR2 => U6_trg_cntout(28),
      O => U6_n0041
    );
  U6_Mmux_n0040_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18126,
      ADR2 => U6_trg_cntout(29),
      O => U6_n0040
    );
  U6_Mmux_n0039_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18128,
      ADR2 => U6_trg_cntout(30),
      O => U6_n0039
    );
  U6_Mmux_n0038_Result1 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => set_trgin_1,
      ADR1 => N18130,
      ADR2 => U6_trg_cntout(31),
      O => U6_n0038
    );
  U6_I78_0 : X_TRI
    port map (
      I => U6_trg_cntoutreg(31),
      CTL => NlwInverterSignal_U6_I78_0_T,
      O => db_out(15)
    );
  U6_I77_0 : X_TRI
    port map (
      I => U6_trg_cntoutreg(15),
      CTL => NlwInverterSignal_U6_I77_0_T,
      O => db_out(15)
    );
  U6_I76_0 : X_TRI
    port map (
      I => U6_trg_cntout(31),
      CTL => NlwInverterSignal_U6_I76_0_T,
      O => db_out(15)
    );
  U6_I75_0 : X_TRI
    port map (
      I => U6_trg_cntout(15),
      CTL => NlwInverterSignal_U6_I75_0_T,
      O => db_out(15)
    );
  U6_I74_0 : X_TRI
    port map (
      I => U6_trg_maxcnt(15),
      CTL => NlwInverterSignal_U6_I74_0_T,
      O => db_out(15)
    );
  U6_I73_0 : X_TRI
    port map (
      I => U6_trg_delay(15),
      CTL => NlwInverterSignal_U6_I73_0_T,
      O => db_out(15)
    );
  U6_q_in_113 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => set_trgin_1,
      CE => U6_n0195,
      RST => U6_q_in_GSR_OR,
      CLK => CLK,
      O => U6_q_in,
      SET => GND
    );
  U6_trg_cntoutreg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0070,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_0_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(0),
      SET => GND
    );
  U6_trg_cntoutreg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0069,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_1_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(1),
      SET => GND
    );
  U6_trg_cntoutreg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0068,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_2_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(2),
      SET => GND
    );
  U6_trg_cntoutreg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0067,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_3_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(3),
      SET => GND
    );
  U6_S2_I1_5 : X_TRI
    port map (
      I => U6_S2_trg_cntin_18,
      CTL => NlwInverterSignal_U6_S2_I1_5_T,
      O => db_out(10)
    );
  U6_tr_0_114 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => trganal_OBUF,
      RST => U6_tr_0_GSR_OR,
      CLK => CLK,
      O => U6_tr_0,
      CE => VCC,
      SET => GND
    );
  U6_tr_1_115 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_tr_0,
      RST => U6_tr_1_GSR_OR,
      CLK => CLK,
      O => U6_tr_1,
      CE => VCC,
      SET => GND
    );
  U6_v_0_116 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => veto_IBUF,
      RST => U6_v_0_GSR_OR,
      CLK => CLK,
      O => U6_v_0,
      CE => VCC,
      SET => GND
    );
  U6_v_1_117 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_v_0,
      RST => U6_v_1_GSR_OR,
      CLK => CLK,
      O => U6_v_1,
      CE => VCC,
      SET => GND
    );
  U6_trg_delay_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18130,
      CE => U6_n0001,
      RST => U6_trg_delay_15_GSR_OR,
      CLK => CLK,
      O => U6_trg_delay(15),
      SET => GND
    );
  U6_trg_maxcnt_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18130,
      CE => U6_n0002,
      RST => U6_trg_maxcnt_15_GSR_OR,
      CLK => CLK,
      O => U6_trg_maxcnt(15),
      SET => GND
    );
  U6_trg_cntout_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0004,
      CE => U6_n0127,
      RST => U6_trg_cntout_31_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(31),
      SET => GND
    );
  U6_trg_cntout_30 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0005,
      CE => U6_n0127,
      RST => U6_trg_cntout_30_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(30),
      SET => GND
    );
  U6_trg_cntout_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0006,
      CE => U6_n0127,
      RST => U6_trg_cntout_29_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(29),
      SET => GND
    );
  U6_trg_cntout_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0007,
      CE => U6_n0127,
      RST => U6_trg_cntout_28_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(28),
      SET => GND
    );
  U6_trg_cntout_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0008,
      CE => U6_n0127,
      RST => U6_trg_cntout_27_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(27),
      SET => GND
    );
  U6_trg_cntout_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0009,
      CE => U6_n0127,
      RST => U6_trg_cntout_26_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(26),
      SET => GND
    );
  U6_trg_cntout_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0010,
      CE => U6_n0127,
      RST => U6_trg_cntout_25_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(25),
      SET => GND
    );
  U6_trg_cntout_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0011,
      CE => U6_n0127,
      RST => U6_trg_cntout_24_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(24),
      SET => GND
    );
  U6_trg_cntout_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0012,
      CE => U6_n0127,
      RST => U6_trg_cntout_23_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(23),
      SET => GND
    );
  U6_trg_cntout_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0013,
      CE => U6_n0127,
      RST => U6_trg_cntout_22_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(22),
      SET => GND
    );
  U6_trg_cntout_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0014,
      CE => U6_n0127,
      RST => U6_trg_cntout_21_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(21),
      SET => GND
    );
  U6_trg_cntout_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0015,
      CE => U6_n0127,
      RST => U6_trg_cntout_20_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(20),
      SET => GND
    );
  U6_trg_cntout_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0016,
      CE => U6_n0127,
      RST => U6_trg_cntout_19_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(19),
      SET => GND
    );
  U6_trg_cntout_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0017,
      CE => U6_n0127,
      RST => U6_trg_cntout_18_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(18),
      SET => GND
    );
  U6_trg_cntout_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0018,
      CE => U6_n0127,
      RST => U6_trg_cntout_17_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(17),
      SET => GND
    );
  U6_trg_cntout_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0019,
      CE => U6_n0127,
      RST => U6_trg_cntout_16_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(16),
      SET => GND
    );
  U6_trg_cntout_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0021,
      CE => U6_n0144,
      RST => U6_trg_cntout_15_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(15),
      SET => GND
    );
  U6_trg_cntout_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0022,
      CE => U6_n0144,
      RST => U6_trg_cntout_14_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(14),
      SET => GND
    );
  U6_trg_cntout_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0023,
      CE => U6_n0144,
      RST => U6_trg_cntout_13_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(13),
      SET => GND
    );
  U6_trg_cntout_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0024,
      CE => U6_n0144,
      RST => U6_trg_cntout_12_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(12),
      SET => GND
    );
  U6_trg_cntout_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0025,
      CE => U6_n0144,
      RST => U6_trg_cntout_11_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(11),
      SET => GND
    );
  U6_trg_cntout_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0026,
      CE => U6_n0144,
      RST => U6_trg_cntout_10_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(10),
      SET => GND
    );
  U6_trg_cntout_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0027,
      CE => U6_n0144,
      RST => U6_trg_cntout_9_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(9),
      SET => GND
    );
  U6_trg_cntout_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0028,
      CE => U6_n0144,
      RST => U6_trg_cntout_8_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(8),
      SET => GND
    );
  U6_trg_cntout_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0029,
      CE => U6_n0144,
      RST => U6_trg_cntout_7_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(7),
      SET => GND
    );
  U6_trg_cntout_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0030,
      CE => U6_n0144,
      RST => U6_trg_cntout_6_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(6),
      SET => GND
    );
  U6_trg_cntout_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0031,
      CE => U6_n0144,
      RST => U6_trg_cntout_5_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(5),
      SET => GND
    );
  U6_trg_cntout_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0032,
      CE => U6_n0144,
      RST => U6_trg_cntout_4_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(4),
      SET => GND
    );
  U6_trg_cntout_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0033,
      CE => U6_n0144,
      RST => U6_trg_cntout_3_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(3),
      SET => GND
    );
  U6_trg_cntout_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0034,
      CE => U6_n0144,
      RST => U6_trg_cntout_2_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(2),
      SET => GND
    );
  U6_trg_cntout_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0035,
      CE => U6_n0144,
      RST => U6_trg_cntout_1_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(1),
      SET => GND
    );
  U6_trg_cntout_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0036,
      CE => U6_n0144,
      RST => U6_trg_cntout_0_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntout(0),
      SET => GND
    );
  U6_trg_cntoutreg_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0038,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_31_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(31),
      SET => GND
    );
  U6_trg_cntoutreg_30 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0039,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_30_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(30),
      SET => GND
    );
  U6_trg_cntoutreg_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0040,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_29_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(29),
      SET => GND
    );
  U6_trg_cntoutreg_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0041,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_28_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(28),
      SET => GND
    );
  U6_trg_cntoutreg_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0042,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_27_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(27),
      SET => GND
    );
  U6_trg_cntoutreg_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0043,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_26_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(26),
      SET => GND
    );
  U6_trg_cntoutreg_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0044,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_25_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(25),
      SET => GND
    );
  U6_trg_cntoutreg_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0045,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_24_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(24),
      SET => GND
    );
  U6_trg_cntoutreg_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0046,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_23_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(23),
      SET => GND
    );
  U6_trg_cntoutreg_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0047,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_22_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(22),
      SET => GND
    );
  U6_trg_cntoutreg_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0048,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_21_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(21),
      SET => GND
    );
  U6_trg_cntoutreg_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0049,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_20_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(20),
      SET => GND
    );
  U6_trg_cntoutreg_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0050,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_19_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(19),
      SET => GND
    );
  U6_trg_cntoutreg_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0051,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_18_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(18),
      SET => GND
    );
  U6_trg_cntoutreg_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0052,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_17_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(17),
      SET => GND
    );
  U6_trg_cntoutreg_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0053,
      CE => U6_n0161,
      RST => U6_trg_cntoutreg_16_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(16),
      SET => GND
    );
  U6_trg_cntoutreg_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0055,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_15_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(15),
      SET => GND
    );
  U6_trg_cntoutreg_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0056,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_14_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(14),
      SET => GND
    );
  U6_trg_cntoutreg_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0057,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_13_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(13),
      SET => GND
    );
  U6_trg_cntoutreg_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0058,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_12_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(12),
      SET => GND
    );
  U6_trg_cntoutreg_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_n0059,
      CE => U6_n0178,
      RST => U6_trg_cntoutreg_11_GSR_OR,
      CLK => CLK,
      O => U6_trg_cntoutreg(11),
      SET => GND
    );
  U6_I78_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(1),
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => U1_fq5_q,
      O => U6_I78_N1141
    );
  U6_I78_15 : X_TRI
    port map (
      I => U6_trg_cntoutreg(16),
      CTL => NlwInverterSignal_U6_I78_15_T,
      O => db_out(0)
    );
  U6_I78_14 : X_TRI
    port map (
      I => U6_trg_cntoutreg(17),
      CTL => NlwInverterSignal_U6_I78_14_T,
      O => db_out(1)
    );
  U6_I78_13 : X_TRI
    port map (
      I => U6_trg_cntoutreg(18),
      CTL => NlwInverterSignal_U6_I78_13_T,
      O => db_out(2)
    );
  U6_I78_12 : X_TRI
    port map (
      I => U6_trg_cntoutreg(19),
      CTL => NlwInverterSignal_U6_I78_12_T,
      O => db_out(3)
    );
  U6_I78_11 : X_TRI
    port map (
      I => U6_trg_cntoutreg(20),
      CTL => NlwInverterSignal_U6_I78_11_T,
      O => db_out(4)
    );
  U6_I78_10 : X_TRI
    port map (
      I => U6_trg_cntoutreg(21),
      CTL => NlwInverterSignal_U6_I78_10_T,
      O => db_out(5)
    );
  U6_I78_9 : X_TRI
    port map (
      I => U6_trg_cntoutreg(22),
      CTL => NlwInverterSignal_U6_I78_9_T,
      O => db_out(6)
    );
  U6_I78_8 : X_TRI
    port map (
      I => U6_trg_cntoutreg(23),
      CTL => NlwInverterSignal_U6_I78_8_T,
      O => db_out(7)
    );
  U6_I78_7 : X_TRI
    port map (
      I => U6_trg_cntoutreg(24),
      CTL => NlwInverterSignal_U6_I78_7_T,
      O => db_out(8)
    );
  U6_I78_6 : X_TRI
    port map (
      I => U6_trg_cntoutreg(25),
      CTL => NlwInverterSignal_U6_I78_6_T,
      O => db_out(9)
    );
  U6_I78_5 : X_TRI
    port map (
      I => U6_trg_cntoutreg(26),
      CTL => NlwInverterSignal_U6_I78_5_T,
      O => db_out(10)
    );
  U6_I78_4 : X_TRI
    port map (
      I => U6_trg_cntoutreg(27),
      CTL => NlwInverterSignal_U6_I78_4_T,
      O => db_out(11)
    );
  U6_I78_3 : X_TRI
    port map (
      I => U6_trg_cntoutreg(28),
      CTL => NlwInverterSignal_U6_I78_3_T,
      O => db_out(12)
    );
  U6_I78_2 : X_TRI
    port map (
      I => U6_trg_cntoutreg(29),
      CTL => NlwInverterSignal_U6_I78_2_T,
      O => db_out(13)
    );
  U6_I78_1 : X_TRI
    port map (
      I => U6_trg_cntoutreg(30),
      CTL => NlwInverterSignal_U6_I78_1_T,
      O => db_out(14)
    );
  U6_I77_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => U1_fq5_q,
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => grp(1),
      O => U6_I77_N1141
    );
  U6_I77_15 : X_TRI
    port map (
      I => U6_trg_cntoutreg(0),
      CTL => NlwInverterSignal_U6_I77_15_T,
      O => db_out(0)
    );
  U6_I77_14 : X_TRI
    port map (
      I => U6_trg_cntoutreg(1),
      CTL => NlwInverterSignal_U6_I77_14_T,
      O => db_out(1)
    );
  U6_I77_13 : X_TRI
    port map (
      I => U6_trg_cntoutreg(2),
      CTL => NlwInverterSignal_U6_I77_13_T,
      O => db_out(2)
    );
  U6_I77_12 : X_TRI
    port map (
      I => U6_trg_cntoutreg(3),
      CTL => NlwInverterSignal_U6_I77_12_T,
      O => db_out(3)
    );
  U6_I77_11 : X_TRI
    port map (
      I => U6_trg_cntoutreg(4),
      CTL => NlwInverterSignal_U6_I77_11_T,
      O => db_out(4)
    );
  U6_I77_10 : X_TRI
    port map (
      I => U6_trg_cntoutreg(5),
      CTL => NlwInverterSignal_U6_I77_10_T,
      O => db_out(5)
    );
  U6_I77_9 : X_TRI
    port map (
      I => U6_trg_cntoutreg(6),
      CTL => NlwInverterSignal_U6_I77_9_T,
      O => db_out(6)
    );
  U6_I77_8 : X_TRI
    port map (
      I => U6_trg_cntoutreg(7),
      CTL => NlwInverterSignal_U6_I77_8_T,
      O => db_out(7)
    );
  U6_I77_7 : X_TRI
    port map (
      I => U6_trg_cntoutreg(8),
      CTL => NlwInverterSignal_U6_I77_7_T,
      O => db_out(8)
    );
  U6_I77_6 : X_TRI
    port map (
      I => U6_trg_cntoutreg(9),
      CTL => NlwInverterSignal_U6_I77_6_T,
      O => db_out(9)
    );
  U6_I77_5 : X_TRI
    port map (
      I => U6_trg_cntoutreg(10),
      CTL => NlwInverterSignal_U6_I77_5_T,
      O => db_out(10)
    );
  U6_I77_4 : X_TRI
    port map (
      I => U6_trg_cntoutreg(11),
      CTL => NlwInverterSignal_U6_I77_4_T,
      O => db_out(11)
    );
  U6_I77_3 : X_TRI
    port map (
      I => U6_trg_cntoutreg(12),
      CTL => NlwInverterSignal_U6_I77_3_T,
      O => db_out(12)
    );
  U6_I77_2 : X_TRI
    port map (
      I => U6_trg_cntoutreg(13),
      CTL => NlwInverterSignal_U6_I77_2_T,
      O => db_out(13)
    );
  U6_I77_1 : X_TRI
    port map (
      I => U6_trg_cntoutreg(14),
      CTL => NlwInverterSignal_U6_I77_1_T,
      O => db_out(14)
    );
  U6_I76_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => grp(1),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => U1_fq5_q,
      O => U6_I76_N1141
    );
  U6_I76_15 : X_TRI
    port map (
      I => U6_trg_cntout(16),
      CTL => NlwInverterSignal_U6_I76_15_T,
      O => db_out(0)
    );
  U6_I76_14 : X_TRI
    port map (
      I => U6_trg_cntout(17),
      CTL => NlwInverterSignal_U6_I76_14_T,
      O => db_out(1)
    );
  U6_I76_13 : X_TRI
    port map (
      I => U6_trg_cntout(18),
      CTL => NlwInverterSignal_U6_I76_13_T,
      O => db_out(2)
    );
  U6_I76_12 : X_TRI
    port map (
      I => U6_trg_cntout(19),
      CTL => NlwInverterSignal_U6_I76_12_T,
      O => db_out(3)
    );
  U6_I76_11 : X_TRI
    port map (
      I => U6_trg_cntout(20),
      CTL => NlwInverterSignal_U6_I76_11_T,
      O => db_out(4)
    );
  U6_I76_10 : X_TRI
    port map (
      I => U6_trg_cntout(21),
      CTL => NlwInverterSignal_U6_I76_10_T,
      O => db_out(5)
    );
  U6_I76_9 : X_TRI
    port map (
      I => U6_trg_cntout(22),
      CTL => NlwInverterSignal_U6_I76_9_T,
      O => db_out(6)
    );
  U6_I76_8 : X_TRI
    port map (
      I => U6_trg_cntout(23),
      CTL => NlwInverterSignal_U6_I76_8_T,
      O => db_out(7)
    );
  U6_I76_7 : X_TRI
    port map (
      I => U6_trg_cntout(24),
      CTL => NlwInverterSignal_U6_I76_7_T,
      O => db_out(8)
    );
  U6_I76_6 : X_TRI
    port map (
      I => U6_trg_cntout(25),
      CTL => NlwInverterSignal_U6_I76_6_T,
      O => db_out(9)
    );
  U6_I76_5 : X_TRI
    port map (
      I => U6_trg_cntout(26),
      CTL => NlwInverterSignal_U6_I76_5_T,
      O => db_out(10)
    );
  U6_I76_4 : X_TRI
    port map (
      I => U6_trg_cntout(27),
      CTL => NlwInverterSignal_U6_I76_4_T,
      O => db_out(11)
    );
  U6_I76_3 : X_TRI
    port map (
      I => U6_trg_cntout(28),
      CTL => NlwInverterSignal_U6_I76_3_T,
      O => db_out(12)
    );
  U6_I76_2 : X_TRI
    port map (
      I => U6_trg_cntout(29),
      CTL => NlwInverterSignal_U6_I76_2_T,
      O => db_out(13)
    );
  U6_I76_1 : X_TRI
    port map (
      I => U6_trg_cntout(30),
      CTL => NlwInverterSignal_U6_I76_1_T,
      O => db_out(14)
    );
  U6_I75_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(1),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => U1_fq5_q,
      O => U6_I75_N1141
    );
  U6_I75_15 : X_TRI
    port map (
      I => U6_trg_cntout(0),
      CTL => NlwInverterSignal_U6_I75_15_T,
      O => db_out(0)
    );
  U6_I75_14 : X_TRI
    port map (
      I => U6_trg_cntout(1),
      CTL => NlwInverterSignal_U6_I75_14_T,
      O => db_out(1)
    );
  U6_I75_13 : X_TRI
    port map (
      I => U6_trg_cntout(2),
      CTL => NlwInverterSignal_U6_I75_13_T,
      O => db_out(2)
    );
  U6_I75_12 : X_TRI
    port map (
      I => U6_trg_cntout(3),
      CTL => NlwInverterSignal_U6_I75_12_T,
      O => db_out(3)
    );
  U6_I75_11 : X_TRI
    port map (
      I => U6_trg_cntout(4),
      CTL => NlwInverterSignal_U6_I75_11_T,
      O => db_out(4)
    );
  U6_I75_10 : X_TRI
    port map (
      I => U6_trg_cntout(5),
      CTL => NlwInverterSignal_U6_I75_10_T,
      O => db_out(5)
    );
  U6_I75_9 : X_TRI
    port map (
      I => U6_trg_cntout(6),
      CTL => NlwInverterSignal_U6_I75_9_T,
      O => db_out(6)
    );
  U6_I75_8 : X_TRI
    port map (
      I => U6_trg_cntout(7),
      CTL => NlwInverterSignal_U6_I75_8_T,
      O => db_out(7)
    );
  U6_I75_7 : X_TRI
    port map (
      I => U6_trg_cntout(8),
      CTL => NlwInverterSignal_U6_I75_7_T,
      O => db_out(8)
    );
  U6_I75_6 : X_TRI
    port map (
      I => U6_trg_cntout(9),
      CTL => NlwInverterSignal_U6_I75_6_T,
      O => db_out(9)
    );
  U6_I75_5 : X_TRI
    port map (
      I => U6_trg_cntout(10),
      CTL => NlwInverterSignal_U6_I75_5_T,
      O => db_out(10)
    );
  U6_I75_4 : X_TRI
    port map (
      I => U6_trg_cntout(11),
      CTL => NlwInverterSignal_U6_I75_4_T,
      O => db_out(11)
    );
  U6_I75_3 : X_TRI
    port map (
      I => U6_trg_cntout(12),
      CTL => NlwInverterSignal_U6_I75_3_T,
      O => db_out(12)
    );
  U6_I75_2 : X_TRI
    port map (
      I => U6_trg_cntout(13),
      CTL => NlwInverterSignal_U6_I75_2_T,
      O => db_out(13)
    );
  U6_I75_1 : X_TRI
    port map (
      I => U6_trg_cntout(14),
      CTL => NlwInverterSignal_U6_I75_1_T,
      O => db_out(14)
    );
  U6_I74_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(0),
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => U1_fq5_q,
      O => U6_I74_N1141
    );
  U6_I74_15 : X_TRI
    port map (
      I => U6_trg_maxcnt(0),
      CTL => NlwInverterSignal_U6_I74_15_T,
      O => db_out(0)
    );
  U6_I74_14 : X_TRI
    port map (
      I => U6_trg_maxcnt(1),
      CTL => NlwInverterSignal_U6_I74_14_T,
      O => db_out(1)
    );
  U6_I74_13 : X_TRI
    port map (
      I => U6_trg_maxcnt(2),
      CTL => NlwInverterSignal_U6_I74_13_T,
      O => db_out(2)
    );
  U6_I74_12 : X_TRI
    port map (
      I => U6_trg_maxcnt(3),
      CTL => NlwInverterSignal_U6_I74_12_T,
      O => db_out(3)
    );
  U6_I74_11 : X_TRI
    port map (
      I => U6_trg_maxcnt(4),
      CTL => NlwInverterSignal_U6_I74_11_T,
      O => db_out(4)
    );
  U6_I74_10 : X_TRI
    port map (
      I => U6_trg_maxcnt(5),
      CTL => NlwInverterSignal_U6_I74_10_T,
      O => db_out(5)
    );
  U6_I74_9 : X_TRI
    port map (
      I => U6_trg_maxcnt(6),
      CTL => NlwInverterSignal_U6_I74_9_T,
      O => db_out(6)
    );
  U6_I74_8 : X_TRI
    port map (
      I => U6_trg_maxcnt(7),
      CTL => NlwInverterSignal_U6_I74_8_T,
      O => db_out(7)
    );
  U6_I74_7 : X_TRI
    port map (
      I => U6_trg_maxcnt(8),
      CTL => NlwInverterSignal_U6_I74_7_T,
      O => db_out(8)
    );
  U6_I74_6 : X_TRI
    port map (
      I => U6_trg_maxcnt(9),
      CTL => NlwInverterSignal_U6_I74_6_T,
      O => db_out(9)
    );
  U6_I74_5 : X_TRI
    port map (
      I => U6_trg_maxcnt(10),
      CTL => NlwInverterSignal_U6_I74_5_T,
      O => db_out(10)
    );
  U6_I74_4 : X_TRI
    port map (
      I => U6_trg_maxcnt(11),
      CTL => NlwInverterSignal_U6_I74_4_T,
      O => db_out(11)
    );
  U6_I74_3 : X_TRI
    port map (
      I => U6_trg_maxcnt(12),
      CTL => NlwInverterSignal_U6_I74_3_T,
      O => db_out(12)
    );
  U6_I74_2 : X_TRI
    port map (
      I => U6_trg_maxcnt(13),
      CTL => NlwInverterSignal_U6_I74_2_T,
      O => db_out(13)
    );
  U6_I74_1 : X_TRI
    port map (
      I => U6_trg_maxcnt(14),
      CTL => NlwInverterSignal_U6_I74_1_T,
      O => db_out(14)
    );
  U6_I73_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => grp(0),
      ADR1 => add_int(1),
      ADR2 => add_int(0),
      ADR3 => U1_fq5_q,
      O => U6_I73_N1141
    );
  U6_I73_15 : X_TRI
    port map (
      I => U6_trg_delay(0),
      CTL => NlwInverterSignal_U6_I73_15_T,
      O => db_out(0)
    );
  U6_I73_14 : X_TRI
    port map (
      I => U6_trg_delay(1),
      CTL => NlwInverterSignal_U6_I73_14_T,
      O => db_out(1)
    );
  U6_I73_13 : X_TRI
    port map (
      I => U6_trg_delay(2),
      CTL => NlwInverterSignal_U6_I73_13_T,
      O => db_out(2)
    );
  U6_I73_12 : X_TRI
    port map (
      I => U6_trg_delay(3),
      CTL => NlwInverterSignal_U6_I73_12_T,
      O => db_out(3)
    );
  U6_I73_11 : X_TRI
    port map (
      I => U6_trg_delay(4),
      CTL => NlwInverterSignal_U6_I73_11_T,
      O => db_out(4)
    );
  U6_I73_10 : X_TRI
    port map (
      I => U6_trg_delay(5),
      CTL => NlwInverterSignal_U6_I73_10_T,
      O => db_out(5)
    );
  U6_I73_9 : X_TRI
    port map (
      I => U6_trg_delay(6),
      CTL => NlwInverterSignal_U6_I73_9_T,
      O => db_out(6)
    );
  U6_Ker139511 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => add_int(1),
      ADR1 => add_int(0),
      ADR2 => N18361,
      ADR3 => grp(1),
      O => U6_N13953
    );
  U6_trigger_n0000_0_lut : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U6_trg_cntout(0),
      O => U6_N6090,
      ADR1 => GND
    );
  U6_trigger_n0000_0_cy : X_MUX2
    port map (
      IB => tp3_OBUF,
      IA => N8300,
      SEL => U6_N6090,
      O => U6_trigger_n0000_0_cyo
    );
  delay_1_0_OBUF : X_BUF
    port map (
      I => U5_pulse_reg1_0_1,
      O => delay_1_0_OBUF_GTS_TRI
    );
  U6_trigger_n0000_1_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_0_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_1_rt,
      O => U6_trigger_n0000_1_cyo
    );
  U6_trigger_n0000_1_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_1_rt,
      I1 => U6_trigger_n0000_0_cyo,
      O => U6_n0000(1)
    );
  U6_trigger_n0000_2_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_1_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_2_rt,
      O => U6_trigger_n0000_2_cyo
    );
  U6_trigger_n0000_2_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_2_rt,
      I1 => U6_trigger_n0000_1_cyo,
      O => U6_n0000(2)
    );
  U6_trigger_n0000_3_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_2_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_3_rt,
      O => U6_trigger_n0000_3_cyo
    );
  U6_trigger_n0000_3_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_3_rt,
      I1 => U6_trigger_n0000_2_cyo,
      O => U6_n0000(3)
    );
  U6_trigger_n0000_4_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_3_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_4_rt,
      O => U6_trigger_n0000_4_cyo
    );
  U6_trigger_n0000_4_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_4_rt,
      I1 => U6_trigger_n0000_3_cyo,
      O => U6_n0000(4)
    );
  U6_trigger_n0000_5_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_4_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_5_rt,
      O => U6_trigger_n0000_5_cyo
    );
  U6_trigger_n0000_5_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_5_rt,
      I1 => U6_trigger_n0000_4_cyo,
      O => U6_n0000(5)
    );
  U6_trigger_n0000_6_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_5_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_6_rt,
      O => U6_trigger_n0000_6_cyo
    );
  U6_trigger_n0000_6_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_6_rt,
      I1 => U6_trigger_n0000_5_cyo,
      O => U6_n0000(6)
    );
  U6_trigger_n0000_7_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_6_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_7_rt,
      O => U6_trigger_n0000_7_cyo
    );
  U6_trigger_n0000_7_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_7_rt,
      I1 => U6_trigger_n0000_6_cyo,
      O => U6_n0000(7)
    );
  U6_trigger_n0000_8_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_7_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_8_rt,
      O => U6_trigger_n0000_8_cyo
    );
  U6_trigger_n0000_8_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_8_rt,
      I1 => U6_trigger_n0000_7_cyo,
      O => U6_n0000(8)
    );
  U6_trigger_n0000_9_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_8_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_9_rt,
      O => U6_trigger_n0000_9_cyo
    );
  U6_trigger_n0000_9_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_9_rt,
      I1 => U6_trigger_n0000_8_cyo,
      O => U6_n0000(9)
    );
  U6_trigger_n0000_10_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_9_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_10_rt,
      O => U6_trigger_n0000_10_cyo
    );
  U6_trigger_n0000_10_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_10_rt,
      I1 => U6_trigger_n0000_9_cyo,
      O => U6_n0000(10)
    );
  U6_trigger_n0000_11_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_10_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_11_rt,
      O => U6_trigger_n0000_11_cyo
    );
  U6_trigger_n0000_11_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_11_rt,
      I1 => U6_trigger_n0000_10_cyo,
      O => U6_n0000(11)
    );
  U6_trigger_n0000_12_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_11_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_12_rt,
      O => U6_trigger_n0000_12_cyo
    );
  U6_trigger_n0000_12_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_12_rt,
      I1 => U6_trigger_n0000_11_cyo,
      O => U6_n0000(12)
    );
  U6_trigger_n0000_13_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_12_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_13_rt,
      O => U6_trigger_n0000_13_cyo
    );
  U6_trigger_n0000_13_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_13_rt,
      I1 => U6_trigger_n0000_12_cyo,
      O => U6_n0000(13)
    );
  U6_trigger_n0000_14_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_13_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_14_rt,
      O => U6_trigger_n0000_14_cyo
    );
  U6_trigger_n0000_14_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_14_rt,
      I1 => U6_trigger_n0000_13_cyo,
      O => U6_n0000(14)
    );
  U6_trigger_n0000_15_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_14_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_15_rt,
      O => U6_trigger_n0000_15_cyo
    );
  U6_trigger_n0000_15_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_15_rt,
      I1 => U6_trigger_n0000_14_cyo,
      O => U6_n0000(15)
    );
  U6_trigger_n0000_16_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_15_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_16_rt,
      O => U6_trigger_n0000_16_cyo
    );
  U6_trigger_n0000_16_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_16_rt,
      I1 => U6_trigger_n0000_15_cyo,
      O => U6_n0000(16)
    );
  U6_trigger_n0000_17_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_16_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_17_rt,
      O => U6_trigger_n0000_17_cyo
    );
  U6_trigger_n0000_17_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_17_rt,
      I1 => U6_trigger_n0000_16_cyo,
      O => U6_n0000(17)
    );
  U6_trigger_n0000_18_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_17_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_18_rt,
      O => U6_trigger_n0000_18_cyo
    );
  U6_trigger_n0000_18_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_18_rt,
      I1 => U6_trigger_n0000_17_cyo,
      O => U6_n0000(18)
    );
  U6_trigger_n0000_19_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_18_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_19_rt,
      O => U6_trigger_n0000_19_cyo
    );
  U6_trigger_n0000_19_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_19_rt,
      I1 => U6_trigger_n0000_18_cyo,
      O => U6_n0000(19)
    );
  U6_trigger_n0000_20_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_19_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_20_rt,
      O => U6_trigger_n0000_20_cyo
    );
  U6_trigger_n0000_20_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_20_rt,
      I1 => U6_trigger_n0000_19_cyo,
      O => U6_n0000(20)
    );
  U6_trigger_n0000_21_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_20_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_21_rt,
      O => U6_trigger_n0000_21_cyo
    );
  U6_trigger_n0000_21_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_21_rt,
      I1 => U6_trigger_n0000_20_cyo,
      O => U6_n0000(21)
    );
  U6_trigger_n0000_22_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_21_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_22_rt,
      O => U6_trigger_n0000_22_cyo
    );
  U6_trigger_n0000_22_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_22_rt,
      I1 => U6_trigger_n0000_21_cyo,
      O => U6_n0000(22)
    );
  U6_trigger_n0000_23_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_22_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_23_rt,
      O => U6_trigger_n0000_23_cyo
    );
  U6_trigger_n0000_23_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_23_rt,
      I1 => U6_trigger_n0000_22_cyo,
      O => U6_n0000(23)
    );
  U6_trigger_n0000_24_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_23_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_24_rt,
      O => U6_trigger_n0000_24_cyo
    );
  U6_trigger_n0000_24_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_24_rt,
      I1 => U6_trigger_n0000_23_cyo,
      O => U6_n0000(24)
    );
  U6_trigger_n0000_25_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_24_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_25_rt,
      O => U6_trigger_n0000_25_cyo
    );
  U6_trigger_n0000_25_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_25_rt,
      I1 => U6_trigger_n0000_24_cyo,
      O => U6_n0000(25)
    );
  U6_trigger_n0000_26_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_25_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_26_rt,
      O => U6_trigger_n0000_26_cyo
    );
  U6_trigger_n0000_26_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_26_rt,
      I1 => U6_trigger_n0000_25_cyo,
      O => U6_n0000(26)
    );
  U6_trigger_n0000_27_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_26_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_27_rt,
      O => U6_trigger_n0000_27_cyo
    );
  U6_trigger_n0000_27_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_27_rt,
      I1 => U6_trigger_n0000_26_cyo,
      O => U6_n0000(27)
    );
  U6_trigger_n0000_28_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_27_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_28_rt,
      O => U6_trigger_n0000_28_cyo
    );
  U6_trigger_n0000_28_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_28_rt,
      I1 => U6_trigger_n0000_27_cyo,
      O => U6_n0000(28)
    );
  U6_trigger_n0000_29_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_28_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_29_rt,
      O => U6_trigger_n0000_29_cyo
    );
  U6_trigger_n0000_29_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_29_rt,
      I1 => U6_trigger_n0000_28_cyo,
      O => U6_n0000(29)
    );
  U6_trigger_n0000_30_cy : X_MUX2
    port map (
      IB => U6_trigger_n0000_29_cyo,
      IA => tp3_OBUF,
      SEL => U6_trg_cntout_30_rt,
      O => U6_trigger_n0000_30_cyo
    );
  U6_trigger_n0000_30_xor : X_XOR2
    port map (
      I0 => U6_trg_cntout_30_rt,
      I1 => U6_trigger_n0000_29_cyo,
      O => U6_n0000(30)
    );
  U6_S2_trg_cntin_20_118 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_20,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_20
    );
  U6_S2_n00051 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => U6_S2_trg_cntin_23,
      ADR1 => U6_q_in,
      ADR2 => trg_dly_p_OBUF,
      ADR3 => set_trgin,
      O => U6_S2_n0005
    );
  U6_S2_I1_1 : X_TRI
    port map (
      I => U6_S2_trg_cntin_22,
      CTL => NlwInverterSignal_U6_S2_I1_1_T,
      O => db_out(14)
    );
  U6_S2_I1_4 : X_TRI
    port map (
      I => U6_S2_trg_cntin_19,
      CTL => NlwInverterSignal_U6_S2_I1_4_T,
      O => db_out(11)
    );
  U6_S2_I1_2 : X_TRI
    port map (
      I => U6_S2_trg_cntin_21,
      CTL => NlwInverterSignal_U6_S2_I1_2_T,
      O => db_out(13)
    );
  U6_S2_I1_3 : X_TRI
    port map (
      I => U6_S2_trg_cntin_20,
      CTL => NlwInverterSignal_U6_S2_I1_3_T,
      O => db_out(12)
    );
  U6_S2_I1_0 : X_TRI
    port map (
      I => U6_S2_trg_cntin_23,
      CTL => NlwInverterSignal_U6_S2_I1_0_T,
      O => db_out(15)
    );
  U6_S2_trg_cntin_21_119 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_21,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_21
    );
  U6_S2_I1_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => add_int(1),
      ADR2 => U1_fq5_q,
      ADR3 => grp(0),
      O => U6_S2_I1_N1141
    );
  U6_S2_I1_15 : X_TRI
    port map (
      I => U6_S2_trg_cntin(8),
      CTL => NlwInverterSignal_U6_S2_I1_15_T,
      O => db_out(0)
    );
  U6_S2_I1_14 : X_TRI
    port map (
      I => U6_S2_trg_cntin(9),
      CTL => NlwInverterSignal_U6_S2_I1_14_T,
      O => db_out(1)
    );
  U6_S2_I1_13 : X_TRI
    port map (
      I => U6_S2_trg_cntin(10),
      CTL => NlwInverterSignal_U6_S2_I1_13_T,
      O => db_out(2)
    );
  U6_S2_I1_12 : X_TRI
    port map (
      I => U6_S2_trg_cntin(11),
      CTL => NlwInverterSignal_U6_S2_I1_12_T,
      O => db_out(3)
    );
  U6_S2_I1_11 : X_TRI
    port map (
      I => U6_S2_trg_cntin(12),
      CTL => NlwInverterSignal_U6_S2_I1_11_T,
      O => db_out(4)
    );
  U6_S2_I1_10 : X_TRI
    port map (
      I => U6_S2_trg_cntin(13),
      CTL => NlwInverterSignal_U6_S2_I1_10_T,
      O => db_out(5)
    );
  U6_S2_I1_9 : X_TRI
    port map (
      I => U6_S2_trg_cntin(14),
      CTL => NlwInverterSignal_U6_S2_I1_9_T,
      O => db_out(6)
    );
  U6_S2_I1_8 : X_TRI
    port map (
      I => U6_S2_trg_cntin(15),
      CTL => NlwInverterSignal_U6_S2_I1_8_T,
      O => db_out(7)
    );
  U6_S2_I1_7 : X_TRI
    port map (
      I => U6_S2_trg_cntin_16,
      CTL => NlwInverterSignal_U6_S2_I1_7_T,
      O => db_out(8)
    );
  U6_S2_I1_6 : X_TRI
    port map (
      I => U6_S2_trg_cntin_17,
      CTL => NlwInverterSignal_U6_S2_I1_6_T,
      O => db_out(9)
    );
  U6_S2_trg_cntin_22_120 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_22,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_22
    );
  U6_S2_trg_cntin_23_121 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U6_S2_trg_cntin_inst_sum_23,
      CE => U6_S2_n0005,
      RST => GSR,
      SET => reset1_2,
      CLK => CLK,
      O => U6_S2_trg_cntin_23
    );
  U6_S2_trg_cntin_inst_cy_9_122 : X_MUX2
    port map (
      IB => N8300,
      IA => tp3_OBUF,
      SEL => set_trgin_rt,
      O => U6_S2_trg_cntin_inst_cy_9
    );
  U6_S2_trg_cntin_inst_lut3_81 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(0),
      ADR2 => U6_S2_trg_cntin(8),
      O => U6_S2_trg_cntin_inst_lut3_8
    );
  U6_S2_trg_cntin_inst_cy_10_123 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_9,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_8,
      O => U6_S2_trg_cntin_inst_cy_10
    );
  U6_S2_trg_cntin_inst_sum_8_124 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_8,
      I1 => U6_S2_trg_cntin_inst_cy_9,
      O => U6_S2_trg_cntin_inst_sum_8
    );
  U6_S2_trg_cntin_inst_lut3_91 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(1),
      ADR2 => U6_S2_trg_cntin(9),
      O => U6_S2_trg_cntin_inst_lut3_9
    );
  U6_S2_trg_cntin_inst_cy_11_125 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_10,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_9,
      O => U6_S2_trg_cntin_inst_cy_11
    );
  U6_S2_trg_cntin_inst_sum_9_126 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_9,
      I1 => U6_S2_trg_cntin_inst_cy_10,
      O => U6_S2_trg_cntin_inst_sum_9
    );
  U6_S2_trg_cntin_inst_lut3_101 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(2),
      ADR2 => U6_S2_trg_cntin(10),
      O => U6_S2_trg_cntin_inst_lut3_10
    );
  U6_S2_trg_cntin_inst_cy_12_127 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_11,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_10,
      O => U6_S2_trg_cntin_inst_cy_12
    );
  U6_S2_trg_cntin_inst_sum_10_128 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_10,
      I1 => U6_S2_trg_cntin_inst_cy_11,
      O => U6_S2_trg_cntin_inst_sum_10
    );
  U6_S2_trg_cntin_inst_lut3_111 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(3),
      ADR2 => U6_S2_trg_cntin(11),
      O => U6_S2_trg_cntin_inst_lut3_11
    );
  U6_S2_trg_cntin_inst_cy_13_129 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_12,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_11,
      O => U6_S2_trg_cntin_inst_cy_13
    );
  U6_S2_trg_cntin_inst_sum_11_130 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_11,
      I1 => U6_S2_trg_cntin_inst_cy_12,
      O => U6_S2_trg_cntin_inst_sum_11
    );
  U6_S2_trg_cntin_inst_lut3_121 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(4),
      ADR2 => U6_S2_trg_cntin(12),
      O => U6_S2_trg_cntin_inst_lut3_12
    );
  U6_S2_trg_cntin_inst_cy_14_131 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_13,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_12,
      O => U6_S2_trg_cntin_inst_cy_14
    );
  U6_S2_trg_cntin_inst_sum_12_132 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_12,
      I1 => U6_S2_trg_cntin_inst_cy_13,
      O => U6_S2_trg_cntin_inst_sum_12
    );
  U6_S2_trg_cntin_inst_lut3_131 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(5),
      ADR2 => U6_S2_trg_cntin(13),
      O => U6_S2_trg_cntin_inst_lut3_13
    );
  U6_S2_trg_cntin_inst_cy_15_133 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_14,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_13,
      O => U6_S2_trg_cntin_inst_cy_15
    );
  U6_S2_trg_cntin_inst_sum_13_134 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_13,
      I1 => U6_S2_trg_cntin_inst_cy_14,
      O => U6_S2_trg_cntin_inst_sum_13
    );
  U6_S2_trg_cntin_inst_lut3_141 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(6),
      ADR2 => U6_S2_trg_cntin(14),
      O => U6_S2_trg_cntin_inst_lut3_14
    );
  U6_S2_trg_cntin_inst_cy_16_135 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_15,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_14,
      O => U6_S2_trg_cntin_inst_cy_16
    );
  U6_S2_trg_cntin_inst_sum_14_136 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_14,
      I1 => U6_S2_trg_cntin_inst_cy_15,
      O => U6_S2_trg_cntin_inst_sum_14
    );
  U6_S2_trg_cntin_inst_lut3_151 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(7),
      ADR2 => U6_S2_trg_cntin(15),
      O => U6_S2_trg_cntin_inst_lut3_15
    );
  U6_S2_trg_cntin_inst_cy_17_137 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_16,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_15,
      O => U6_S2_trg_cntin_inst_cy_17
    );
  U6_S2_trg_cntin_inst_sum_15_138 : X_XOR2
    port map (
      I0 => U6_S2_trg_cntin_inst_lut3_15,
      I1 => U6_S2_trg_cntin_inst_cy_16,
      O => U6_S2_trg_cntin_inst_sum_15
    );
  U6_S2_trg_cntin_inst_lut3_161 : X_LUT3
    generic map(
      INIT => X"27"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_trg_maxcnt(8),
      ADR2 => U6_S2_trg_cntin_16,
      O => U6_S2_trg_cntin_inst_lut3_16
    );
  U6_S2_trg_cntin_inst_cy_18_139 : X_MUX2
    port map (
      IB => U6_S2_trg_cntin_inst_cy_17,
      IA => N8300,
      SEL => U6_S2_trg_cntin_inst_lut3_16,
      O => U6_S2_trg_cntin_inst_cy_18
    );
  U1_g245_SW0 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => U1_fq5_q,
      ADR1 => U1_fq1_q,
      O => N16332
    );
  U1_g245 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => U4_fr1_q,
      ADR1 => U2_fr1_q,
      ADR2 => U3_fr1_q,
      ADR3 => N16332,
      O => g245_OBUF
    );
  irq_4_21 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => U4_fr9_q,
      ADR1 => int_lev_2(0),
      ADR2 => int_lev_2(1),
      ADR3 => int_lev_2(2),
      O => CHOICE163
    );
  irq_2_21 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => U4_fr9_q,
      ADR1 => int_lev_2(2),
      ADR2 => int_lev_2(0),
      ADR3 => int_lev_2(1),
      O => CHOICE146
    );
  irq_4_44_SW0 : X_LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      ADR0 => int_lev_1(1),
      ADR1 => int_lev_1(2),
      ADR2 => U3_fr9_q,
      O => N18312
    );
  U7_ckdiv_4_rt_140 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_ckdiv(4),
      O => U7_ckdiv_4_rt,
      ADR1 => GND
    );
  irq_7_14 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => int_lev_0(2),
      ADR1 => U2_fr9_q,
      ADR2 => int_lev_0(0),
      ADR3 => int_lev_0(1),
      O => CHOICE117
    );
  irq_1_21 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => int_lev_2(0),
      ADR1 => int_lev_2(2),
      ADR2 => int_lev_2(1),
      ADR3 => U4_fr9_q,
      O => CHOICE129
    );
  irq_7_22_SW0 : X_LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      ADR0 => int_lev_1(0),
      ADR1 => int_lev_1(1),
      ADR2 => U3_fr9_q,
      O => N18296
    );
  trigger_in : X_LUT4
    generic map(
      INIT => X"8ACF"
    )
    port map (
      ADR0 => v_trg,
      ADR1 => trg_bypass,
      ADR2 => veto_IBUF,
      ADR3 => N17009,
      O => trganal_OBUF
    );
  trigger_in_SW0 : X_LUT2
    generic map(
      INIT => X"1"
    )
    port map (
      ADR0 => trgnim_IBUF,
      ADR1 => trgttl_IBUF,
      O => N17009
    );
  irq_3_33_SW0 : X_LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      ADR0 => int_lev_1(2),
      ADR1 => int_lev_1(1),
      ADR2 => U3_fr9_q,
      O => N18288
    );
  irq_7_22 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => int_lev_1(2),
      ADR1 => N18296,
      ADR2 => CHOICE117,
      ADR3 => CHOICE114,
      O => irq_7_OBUF
    );
  irq_6_33 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => int_lev_1(2),
      ADR1 => N18300,
      ADR2 => CHOICE210,
      ADR3 => CHOICE206,
      O => irq_6_OBUF
    );
  irq_2_44 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => CHOICE151,
      ADR1 => N18304,
      ADR2 => int_lev_1(2),
      ADR3 => CHOICE146,
      O => irq_2_OBUF
    );
  irq_3_15 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => int_lev_2(0),
      ADR1 => U4_fr9_q,
      ADR2 => int_lev_2(2),
      ADR3 => int_lev_2(1),
      O => CHOICE178
    );
  irq_3_23 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => int_lev_0(0),
      ADR1 => U2_fr9_q,
      ADR2 => int_lev_0(2),
      ADR3 => int_lev_0(1),
      O => CHOICE182
    );
  irq_6_33_SW0 : X_LUT3
    generic map(
      INIT => X"40"
    )
    port map (
      ADR0 => int_lev_1(0),
      ADR1 => int_lev_1(1),
      ADR2 => U3_fr9_q,
      O => N18300
    );
  U7_U1_M1_count_10_N130611 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M1_count(10),
      O => N18249,
      ADR1 => GND
    );
  U7_U3_M2_count_4_N130611 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U3_M2_count(4),
      O => N18246,
      ADR1 => GND
    );
  irq_6_23 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => int_lev_0(2),
      ADR1 => U2_fr9_q,
      ADR2 => int_lev_0(0),
      ADR3 => int_lev_0(1),
      O => CHOICE210
    );
  irq_5_33 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => int_lev_1(0),
      ADR1 => N18308,
      ADR2 => CHOICE196,
      ADR3 => CHOICE192,
      O => irq_5_OBUF
    );
  U5_conta_0_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => U5_ps2(0),
      ADR1 => U5_ps1(0),
      ADR2 => U5_pulse_reg0(13),
      ADR3 => U5_conta_0(6),
      O => U5_conta_0_inst_lut3_6
    );
  U7_I9_EnableTr_INV : X_LUT4
    generic map(
      INIT => X"0207"
    )
    port map (
      ADR0 => U7_w_reg,
      ADR1 => U7_U2_w1,
      ADR2 => N17042,
      ADR3 => U7_U2_w0,
      O => U7_I9_N1191
    );
  U7_I9_EnableTr_INV_SW0 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => U7_U1_init,
      ADR1 => U7_U3_rdpls,
      O => N17042
    );
  U6_n0178_141 : X_LUT4
    generic map(
      INIT => X"CCCE"
    )
    port map (
      ADR0 => U1_fq2_q,
      ADR1 => set_trgin,
      ADR2 => U1_fq4_q,
      ADR3 => N18322,
      O => U6_n0178
    );
  U6_n0178_SW1 : X_LUT3
    generic map(
      INIT => X"EF"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => add_int(1),
      ADR2 => grp(1),
      O => N18322
    );
  irq_1_32 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => int_lev_0(0),
      ADR1 => int_lev_0(2),
      ADR2 => int_lev_0(1),
      ADR3 => U2_fr9_q,
      O => CHOICE134
    );
  irq_4_44 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => CHOICE168,
      ADR1 => N18312,
      ADR2 => int_lev_1(0),
      ADR3 => CHOICE163,
      O => irq_4_OBUF
    );
  irq_1_44_SW0 : X_LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      ADR0 => int_lev_1(2),
      ADR1 => U3_fr9_q,
      ADR2 => int_lev_1(1),
      O => N18292
    );
  U7_U1_M2_count_7_N130611 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U1_M2_count(7),
      O => N18251,
      ADR1 => GND
    );
  U4_s145 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => add_int(0),
      ADR1 => int_lev_2(0),
      ADR2 => add_int(2),
      ADR3 => int_lev_2(2),
      O => CHOICE297
    );
  U2_s146 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => CHOICE306,
      ADR1 => CHOICE317,
      O => U2_s1
    );
  U6_tr_dly49 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U6_trg_shift(5),
      ADR1 => U6_trg_delay(5),
      ADR2 => U6_trg_shift(4),
      ADR3 => U6_trg_delay(4),
      O => CHOICE336
    );
  U4_s118 : X_LUT4
    generic map(
      INIT => X"4004"
    )
    port map (
      ADR0 => iack_IBUF,
      ADR1 => U4_fr4_q,
      ADR2 => add_int(1),
      ADR3 => int_lev_2(1),
      O => CHOICE286
    );
  U6_tr_dly9 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U6_trg_shift(11),
      ADR1 => U6_trg_delay(11),
      ADR2 => U6_trg_shift(10),
      ADR3 => U6_trg_delay(10),
      O => CHOICE324
    );
  U6_tr_dly71 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U6_trg_shift(15),
      ADR1 => U6_trg_delay(15),
      ADR2 => U6_trg_shift(14),
      ADR3 => U6_trg_delay(14),
      O => CHOICE346
    );
  U6_tr_dly4 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U6_trg_shift(13),
      ADR1 => U6_trg_delay(13),
      ADR2 => U6_trg_shift(12),
      ADR3 => U6_trg_delay(12),
      O => CHOICE321
    );
  U7_U2_M2_count_7_N130611 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => U7_U2_M2_count(7),
      O => N18255,
      ADR1 => GND
    );
  U6_tr_dly21_SW0 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => U6_trg_shift(8),
      ADR1 => U6_trg_delay(8),
      O => N18284
    );
  U2_s118 : X_LUT4
    generic map(
      INIT => X"4004"
    )
    port map (
      ADR0 => iack_IBUF,
      ADR1 => U2_fr4_q,
      ADR2 => add_int(1),
      ADR3 => int_lev_0(1),
      O => CHOICE306
    );
  U1_Ker111937 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => iack_IBUF,
      ADR1 => am5_IBUF,
      ADR2 => am4_IBUF,
      ADR3 => am3_IBUF,
      O => CHOICE251
    );
  U4_s146 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => CHOICE286,
      ADR1 => CHOICE297,
      O => U4_s1
    );
  U6_trg_cntout_31_rt_142 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(31),
      O => U6_trg_cntout_31_rt,
      ADR1 => GND
    );
  U6_tr_dly27 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U6_trg_shift(9),
      ADR1 => U6_trg_delay(9),
      ADR2 => CHOICE331,
      ADR3 => N18284,
      O => CHOICE332
    );
  U6_tr_dly66 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U6_trg_shift(1),
      ADR1 => U6_trg_delay(1),
      ADR2 => U6_trg_shift(0),
      ADR3 => U6_trg_delay(0),
      O => CHOICE343
    );
  U6_trg_cntout_30_rt_143 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(30),
      O => U6_trg_cntout_30_rt,
      ADR1 => GND
    );
  U3_s146 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => CHOICE266,
      ADR1 => CHOICE277,
      O => U3_s1
    );
  U1_Ker1119318 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => am0_IBUF,
      ADR1 => brd_sel_IBUF,
      ADR2 => am1_IBUF,
      ADR3 => lword_IBUF,
      O => CHOICE256
    );
  trgnim_IBUF_144 : X_BUF
    port map (
      I => trgnim,
      O => trgnim_IBUF
    );
  trgttl_IBUF_145 : X_BUF
    port map (
      I => trgttl,
      O => trgttl_IBUF
    );
  as_IBUF_146 : X_BUF
    port map (
      I => as,
      O => as_IBUF
    );
  robrsttl_IBUF_147 : X_BUF
    port map (
      I => robrsttl,
      O => robrsttl_IBUF
    );
  lword_IBUF_148 : X_BUF
    port map (
      I => lword,
      O => lword_IBUF
    );
  done_in_IBUF_149 : X_BUF
    port map (
      I => done_in,
      O => done_in_IBUF
    );
  ds0_IBUFG_150 : X_CKBUF
    port map (
      I => ds0,
      O => ds0_IBUFG
    );
  ds1_IBUF_151 : X_BUF
    port map (
      I => ds1,
      O => ds1_IBUF
    );
  veto_IBUF_152 : X_BUF
    port map (
      I => veto,
      O => veto_IBUF
    );
  sysreset_IBUF_153 : X_BUF
    port map (
      I => sysreset,
      O => sysreset_IBUF
    );
  evrsttl_IBUF_154 : X_BUF
    port map (
      I => evrsttl,
      O => evrsttl_IBUF
    );
  brd_sel_IBUF_155 : X_BUF
    port map (
      I => brd_sel,
      O => brd_sel_IBUF
    );
  am0_IBUF_156 : X_BUF
    port map (
      I => am0,
      O => am0_IBUF
    );
  am1_IBUF_157 : X_BUF
    port map (
      I => am1,
      O => am1_IBUF
    );
  am3_IBUF_158 : X_BUF
    port map (
      I => am3,
      O => am3_IBUF
    );
  am4_IBUF_159 : X_BUF
    port map (
      I => am4,
      O => am4_IBUF
    );
  am5_IBUF_160 : X_BUF
    port map (
      I => am5,
      O => am5_IBUF
    );
  fltb_IBUF_161 : X_BUF
    port map (
      I => fltb,
      O => fltb_IBUF
    );
  jroberr_IBUF_162 : X_BUF
    port map (
      I => jroberr,
      O => jroberr_IBUF
    );
  iack_IBUF_163 : X_BUF
    port map (
      I => iack,
      O => iack_IBUF
    );
  write_IBUF_164 : X_BUF
    port map (
      I => write,
      O => write_IBUF
    );
  bcrsttl_IBUF_165 : X_BUF
    port map (
      I => bcrsttl,
      O => bcrsttl_IBUF
    );
  iackin_IBUF_166 : X_BUF
    port map (
      I => iackin,
      O => iackin_IBUF
    );
  jtdo_IBUF_167 : X_BUF
    port map (
      I => jtdo,
      O => jtdo_IBUF
    );
  int_ext_1_IBUF_168 : X_BUF
    port map (
      I => int_ext(1),
      O => int_ext_1_IBUF
    );
  int_ext_0_IBUF_169 : X_BUF
    port map (
      I => int_ext(0),
      O => int_ext_0_IBUF
    );
  add_in_6_IBUF_170 : X_BUF
    port map (
      I => add_in(6),
      O => add_in_6_IBUF
    );
  add_in_5_IBUF_171 : X_BUF
    port map (
      I => add_in(5),
      O => add_in_5_IBUF
    );
  add_in_4_IBUF_172 : X_BUF
    port map (
      I => add_in(4),
      O => add_in_4_IBUF
    );
  add_in_3_IBUF_173 : X_BUF
    port map (
      I => add_in(3),
      O => add_in_3_IBUF
    );
  add_in_2_IBUF_174 : X_BUF
    port map (
      I => add_in(2),
      O => add_in_2_IBUF
    );
  add_in_1_IBUF_175 : X_BUF
    port map (
      I => add_in(1),
      O => add_in_1_IBUF
    );
  add_in_0_IBUF_176 : X_BUF
    port map (
      I => add_in(0),
      O => add_in_0_IBUF
    );
  plsttl_1_IBUF_177 : X_BUF
    port map (
      I => plsttl(1),
      O => plsttl_1_IBUF
    );
  plsttl_0_IBUF_178 : X_BUF
    port map (
      I => plsttl(0),
      O => plsttl_0_IBUF
    );
  mcevrst_OBUF_179 : X_BUF
    port map (
      I => mcevrst_OBUF,
      O => mcevrst_OBUF_GTS_TRI
    );
  trgttc_OBUF_180 : X_BUF
    port map (
      I => trgttc_OBUF,
      O => trgttc_OBUF_GTS_TRI
    );
  trg_dly_p_OBUF_181 : X_BUF
    port map (
      I => trg_dly_p_OBUF,
      O => trg_dly_p_OBUF_GTS_TRI
    );
  g245_OBUF_182 : X_BUF
    port map (
      I => g245_OBUF,
      O => g245_OBUF_GTS_TRI
    );
  mctrg_OBUF_183 : X_BUF
    port map (
      I => mctrg_OBUF,
      O => mctrg_OBUF_GTS_TRI
    );
  diftrg_OBUF : X_BUF
    port map (
      I => mctrg_OBUF,
      O => diftrg_OBUF_GTS_TRI
    );
  dtack_OBUF_184 : X_BUF
    port map (
      I => dtack_OBUF,
      O => dtack_OBUF_GTS_TRI
    );
  tp1_OBUF_185 : X_BUF
    port map (
      I => tp1_OBUF,
      O => tp1_OBUF_GTS_TRI
    );
  tp2_OBUF_186 : X_BUF
    port map (
      I => tp2_OBUF,
      O => tp2_OBUF_GTS_TRI
    );
  tp3_OBUF_187 : X_BUF
    port map (
      I => tp3_OBUF,
      O => tp3_OBUF_GTS_TRI
    );
  jtms_OBUF : X_BUF
    port map (
      I => jtag_reg_1_1,
      O => jtms_OBUF_GTS_TRI
    );
  jtrkrst_OBUF : X_BUF
    port map (
      I => v_tmrst,
      O => jtrkrst_OBUF_GTS_TRI
    );
  difevr_OBUF : X_BUF
    port map (
      I => mcevrst_OBUF,
      O => difevr_OBUF_GTS_TRI
    );
  done_out_OBUF_188 : X_BUF
    port map (
      I => done_out_OBUF,
      O => done_out_OBUF_GTS_TRI
    );
  trganal_OBUF_189 : X_BUF
    port map (
      I => trganal_OBUF,
      O => trganal_OBUF_GTS_TRI
    );
  difbcr_OBUF : X_BUF
    port map (
      I => mcbcrst_OBUF,
      O => difbcr_OBUF_GTS_TRI
    );
  jtrktm_OBUF : X_BUF
    port map (
      I => ena_tm_1,
      O => jtrktm_OBUF_GTS_TRI
    );
  trgled_OBUF : X_BUF
    port map (
      I => mctrg_OBUF,
      O => trgled_OBUF_GTS_TRI
    );
  locked_OBUF_190 : X_BUF
    port map (
      I => locked_OBUF,
      O => locked_OBUF_GTS_TRI
    );
  trgros_OBUF : X_BUF
    port map (
      I => mctrg_OBUF,
      O => trgros_OBUF_GTS_TRI
    );
  jtrkadv_OBUF : X_BUF
    port map (
      I => v_tmadv,
      O => jtrkadv_OBUF_GTS_TRI
    );
  iackout_OBUF : X_BUF
    port map (
      I => U4_fr8_q,
      O => iackout_OBUF_GTS_TRI
    );
  jtck_OBUF : X_BUF
    port map (
      I => jtag_reg_0_1,
      O => jtck_OBUF_GTS_TRI
    );
  jtdi_OBUF : X_BUF
    port map (
      I => jtag_reg_2_1,
      O => jtdi_OBUF_GTS_TRI
    );
  intled_OBUF_191 : X_BUF
    port map (
      I => intled_OBUF,
      O => intled_OBUF_GTS_TRI
    );
  difrst_OBUF_192 : X_BUF
    port map (
      I => difrst_OBUF,
      O => difrst_OBUF_GTS_TRI
    );
  mcbcrst_OBUF_193 : X_BUF
    port map (
      I => mcbcrst_OBUF,
      O => mcbcrst_OBUF_GTS_TRI
    );
  irq_7_OBUF_194 : X_BUF
    port map (
      I => irq_7_OBUF,
      O => irq_7_OBUF_GTS_TRI
    );
  irq_6_OBUF_195 : X_BUF
    port map (
      I => irq_6_OBUF,
      O => irq_6_OBUF_GTS_TRI
    );
  irq_5_OBUF_196 : X_BUF
    port map (
      I => irq_5_OBUF,
      O => irq_5_OBUF_GTS_TRI
    );
  irq_4_OBUF_197 : X_BUF
    port map (
      I => irq_4_OBUF,
      O => irq_4_OBUF_GTS_TRI
    );
  irq_3_OBUF_198 : X_BUF
    port map (
      I => irq_3_OBUF,
      O => irq_3_OBUF_GTS_TRI
    );
  irq_2_OBUF_199 : X_BUF
    port map (
      I => irq_2_OBUF,
      O => irq_2_OBUF_GTS_TRI
    );
  irq_1_OBUF_200 : X_BUF
    port map (
      I => irq_1_OBUF,
      O => irq_1_OBUF_GTS_TRI
    );
  ron_6_OBUF : X_BUF
    port map (
      I => ron_reg_6_1,
      O => ron_6_OBUF_GTS_TRI
    );
  ron_5_OBUF : X_BUF
    port map (
      I => ron_reg_5_1,
      O => ron_5_OBUF_GTS_TRI
    );
  ron_4_OBUF : X_BUF
    port map (
      I => ron_reg_4_1,
      O => ron_4_OBUF_GTS_TRI
    );
  ron_3_OBUF : X_BUF
    port map (
      I => ron_reg_3_1,
      O => ron_3_OBUF_GTS_TRI
    );
  ron_2_OBUF : X_BUF
    port map (
      I => ron_reg_2_1,
      O => ron_2_OBUF_GTS_TRI
    );
  ron_1_OBUF : X_BUF
    port map (
      I => ron_reg_1_1,
      O => ron_1_OBUF_GTS_TRI
    );
  ron_0_OBUF : X_BUF
    port map (
      I => ron_reg_0_1,
      O => ron_0_OBUF_GTS_TRI
    );
  pulse_1_OBUF_201 : X_BUF
    port map (
      I => pulse_1_OBUF,
      O => pulse_1_OBUF_GTS_TRI
    );
  pulse_0_OBUF_202 : X_BUF
    port map (
      I => pulse_0_OBUF,
      O => pulse_0_OBUF_GTS_TRI
    );
  jtadd_3_OBUF : X_BUF
    port map (
      I => jtag_reg_6_1,
      O => jtadd_3_OBUF_GTS_TRI
    );
  jtadd_2_OBUF : X_BUF
    port map (
      I => jtag_reg_5_1,
      O => jtadd_2_OBUF_GTS_TRI
    );
  jtadd_1_OBUF : X_BUF
    port map (
      I => jtag_reg_4_1,
      O => jtadd_1_OBUF_GTS_TRI
    );
  jtadd_0_OBUF : X_BUF
    port map (
      I => jtag_reg_3_1,
      O => jtadd_0_OBUF_GTS_TRI
    );
  delay_0_6_OBUF : X_BUF
    port map (
      I => U5_pulse_reg0_6_1,
      O => delay_0_6_OBUF_GTS_TRI
    );
  delay_0_5_OBUF : X_BUF
    port map (
      I => U5_pulse_reg0_5_1,
      O => delay_0_5_OBUF_GTS_TRI
    );
  delay_0_4_OBUF : X_BUF
    port map (
      I => U5_pulse_reg0_4_1,
      O => delay_0_4_OBUF_GTS_TRI
    );
  delay_0_3_OBUF : X_BUF
    port map (
      I => U5_pulse_reg0_3_1,
      O => delay_0_3_OBUF_GTS_TRI
    );
  delay_0_2_OBUF : X_BUF
    port map (
      I => U5_pulse_reg0_2_1,
      O => delay_0_2_OBUF_GTS_TRI
    );
  U7_ckdiv_Q_1_rt_203 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_ckdiv(1),
      O => U7_ckdiv_Q_1_rt,
      ADR1 => GND
    );
  U7_ckdiv_Q_2_rt_204 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_ckdiv(2),
      O => U7_ckdiv_Q_2_rt,
      ADR1 => GND
    );
  U7_ckdiv_Q_3_rt_205 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_ckdiv(3),
      O => U7_ckdiv_Q_3_rt,
      ADR1 => GND
    );
  U7_U1_M1_count_Q_0_rt_206 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_U1_M1_count(0),
      O => U7_U1_M1_count_Q_0_rt,
      ADR1 => GND
    );
  U7_U1_M2_count_Q_0_rt_207 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_U1_M2_count(0),
      O => U7_U1_M2_count_Q_0_rt,
      ADR1 => GND
    );
  U7_U2_M1_count_Q_0_rt_208 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_U2_M1_count(0),
      O => U7_U2_M1_count_Q_0_rt,
      ADR1 => GND
    );
  U7_U2_M2_count_Q_0_rt_209 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_U2_M2_count(0),
      O => U7_U2_M2_count_Q_0_rt,
      ADR1 => GND
    );
  U7_U3_M2_count_Q_0_rt_210 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U7_U3_M2_count(0),
      O => U7_U3_M2_count_Q_0_rt,
      ADR1 => GND
    );
  U6_trg_cntout_1_rt_211 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(1),
      O => U6_trg_cntout_1_rt,
      ADR1 => GND
    );
  U6_trg_cntout_2_rt_212 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(2),
      O => U6_trg_cntout_2_rt,
      ADR1 => GND
    );
  U6_trg_cntout_3_rt_213 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(3),
      O => U6_trg_cntout_3_rt,
      ADR1 => GND
    );
  U6_trg_cntout_4_rt_214 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(4),
      O => U6_trg_cntout_4_rt,
      ADR1 => GND
    );
  U6_trg_cntout_5_rt_215 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(5),
      O => U6_trg_cntout_5_rt,
      ADR1 => GND
    );
  U6_trg_cntout_6_rt_216 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(6),
      O => U6_trg_cntout_6_rt,
      ADR1 => GND
    );
  U6_trg_cntout_7_rt_217 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(7),
      O => U6_trg_cntout_7_rt,
      ADR1 => GND
    );
  U6_trg_cntout_8_rt_218 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(8),
      O => U6_trg_cntout_8_rt,
      ADR1 => GND
    );
  U6_trg_cntout_9_rt_219 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(9),
      O => U6_trg_cntout_9_rt,
      ADR1 => GND
    );
  U6_trg_cntout_10_rt_220 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(10),
      O => U6_trg_cntout_10_rt,
      ADR1 => GND
    );
  U6_trg_cntout_11_rt_221 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(11),
      O => U6_trg_cntout_11_rt,
      ADR1 => GND
    );
  U6_trg_cntout_12_rt_222 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(12),
      O => U6_trg_cntout_12_rt,
      ADR1 => GND
    );
  U6_trg_cntout_13_rt_223 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(13),
      O => U6_trg_cntout_13_rt,
      ADR1 => GND
    );
  U6_trg_cntout_14_rt_224 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(14),
      O => U6_trg_cntout_14_rt,
      ADR1 => GND
    );
  U6_trg_cntout_15_rt_225 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(15),
      O => U6_trg_cntout_15_rt,
      ADR1 => GND
    );
  U6_trg_cntout_16_rt_226 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(16),
      O => U6_trg_cntout_16_rt,
      ADR1 => GND
    );
  U6_trg_cntout_17_rt_227 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(17),
      O => U6_trg_cntout_17_rt,
      ADR1 => GND
    );
  U6_trg_cntout_18_rt_228 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(18),
      O => U6_trg_cntout_18_rt,
      ADR1 => GND
    );
  U6_trg_cntout_19_rt_229 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(19),
      O => U6_trg_cntout_19_rt,
      ADR1 => GND
    );
  U6_trg_cntout_20_rt_230 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(20),
      O => U6_trg_cntout_20_rt,
      ADR1 => GND
    );
  U6_trg_cntout_21_rt_231 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(21),
      O => U6_trg_cntout_21_rt,
      ADR1 => GND
    );
  U6_trg_cntout_22_rt_232 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(22),
      O => U6_trg_cntout_22_rt,
      ADR1 => GND
    );
  U6_trg_cntout_23_rt_233 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(23),
      O => U6_trg_cntout_23_rt,
      ADR1 => GND
    );
  U6_trg_cntout_24_rt_234 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(24),
      O => U6_trg_cntout_24_rt,
      ADR1 => GND
    );
  U6_trg_cntout_25_rt_235 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(25),
      O => U6_trg_cntout_25_rt,
      ADR1 => GND
    );
  U6_trg_cntout_26_rt_236 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(26),
      O => U6_trg_cntout_26_rt,
      ADR1 => GND
    );
  U6_trg_cntout_27_rt_237 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(27),
      O => U6_trg_cntout_27_rt,
      ADR1 => GND
    );
  U6_trg_cntout_28_rt_238 : X_LUT2
    generic map(
      INIT => X"A"
    )
    port map (
      ADR0 => U6_trg_cntout(28),
      O => U6_trg_cntout_28_rt,
      ADR1 => GND
    );
  Q_n0018_4_11 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => add_in_4_IBUF,
      ADR1 => add_in_3_IBUF,
      ADR2 => add_in_6_IBUF,
      ADR3 => add_in_5_IBUF,
      O => N18205
    );
  set_trgin_1_239 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0031,
      RST => set_trgin_1_GSR_OR,
      CLK => CLK,
      O => set_trgin_1,
      CE => VCC,
      SET => GND
    );
  set_trgin_2_240 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0031,
      RST => set_trgin_2_GSR_OR,
      CLK => CLK,
      O => set_trgin_2,
      CE => VCC,
      SET => GND
    );
  reset1_1_241 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0020,
      ADR1 => N18122,
      O => reset1_1
    );
  reset1_2_242 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => Q_n0020,
      ADR1 => N18122,
      O => reset1_2
    );
  jtag_reg_1_1_243 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => Q_n0017,
      RST => jtag_reg_1_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg_1_1,
      SET => GND
    );
  ena_tm_1_244 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0020,
      RST => ena_tm_1_GSR_OR,
      CLK => CLK,
      O => ena_tm_1,
      SET => GND
    );
  jtag_reg_0_1_245 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => Q_n0017,
      RST => jtag_reg_0_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg_0_1,
      SET => GND
    );
  jtag_reg_2_1_246 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => Q_n0017,
      RST => jtag_reg_2_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg_2_1,
      SET => GND
    );
  ron_reg_6_1_247 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => Q_n0016,
      RST => ron_reg_6_1_GSR_OR,
      CLK => CLK,
      O => ron_reg_6_1,
      SET => GND
    );
  ron_reg_5_1_248 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => Q_n0016,
      RST => ron_reg_5_1_GSR_OR,
      CLK => CLK,
      O => ron_reg_5_1,
      SET => GND
    );
  ron_reg_4_1_249 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0016,
      RST => ron_reg_4_1_GSR_OR,
      CLK => CLK,
      O => ron_reg_4_1,
      SET => GND
    );
  ron_reg_3_1_250 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0016,
      RST => ron_reg_3_1_GSR_OR,
      CLK => CLK,
      O => ron_reg_3_1,
      SET => GND
    );
  ron_reg_2_1_251 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => Q_n0016,
      RST => ron_reg_2_1_GSR_OR,
      CLK => CLK,
      O => ron_reg_2_1,
      SET => GND
    );
  ron_reg_1_1_252 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => Q_n0016,
      RST => ron_reg_1_1_GSR_OR,
      CLK => CLK,
      O => ron_reg_1_1,
      SET => GND
    );
  ron_reg_0_1_253 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => Q_n0016,
      RST => ron_reg_0_1_GSR_OR,
      CLK => CLK,
      O => ron_reg_0_1,
      SET => GND
    );
  jtag_reg_6_1_254 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => Q_n0017,
      RST => jtag_reg_6_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg_6_1,
      SET => GND
    );
  jtag_reg_5_1_255 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => Q_n0017,
      RST => jtag_reg_5_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg_5_1,
      SET => GND
    );
  jtag_reg_4_1_256 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => Q_n0017,
      RST => jtag_reg_4_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg_4_1,
      SET => GND
    );
  jtag_reg_3_1_257 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => Q_n0017,
      RST => jtag_reg_3_1_GSR_OR,
      CLK => CLK,
      O => jtag_reg_3_1,
      SET => GND
    );
  U5_pulse_reg0_6_1_258 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => U5_n0024,
      RST => U5_pulse_reg0_6_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0_6_1,
      SET => GND
    );
  U5_pulse_reg0_5_1_259 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => U5_n0024,
      RST => U5_pulse_reg0_5_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0_5_1,
      SET => GND
    );
  U5_pulse_reg0_4_1_260 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => U5_n0024,
      RST => U5_pulse_reg0_4_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0_4_1,
      SET => GND
    );
  U5_pulse_reg0_3_1_261 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => U5_n0024,
      RST => U5_pulse_reg0_3_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0_3_1,
      SET => GND
    );
  U5_pulse_reg0_2_1_262 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => U5_n0024,
      RST => U5_pulse_reg0_2_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0_2_1,
      SET => GND
    );
  U5_pulse_reg0_1_1_263 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => U5_n0024,
      RST => U5_pulse_reg0_1_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0_1_1,
      SET => GND
    );
  U5_pulse_reg0_0_1_264 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => U5_n0024,
      RST => U5_pulse_reg0_0_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg0_0_1,
      SET => GND
    );
  U5_pulse_reg1_6_1_265 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18110,
      CE => U5_n0025,
      RST => U5_pulse_reg1_6_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1_6_1,
      SET => GND
    );
  U5_pulse_reg1_5_1_266 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18108,
      CE => U5_n0025,
      RST => U5_pulse_reg1_5_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1_5_1,
      SET => GND
    );
  U5_pulse_reg1_4_1_267 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18106,
      CE => U5_n0025,
      RST => U5_pulse_reg1_4_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1_4_1,
      SET => GND
    );
  U5_pulse_reg1_3_1_268 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18104,
      CE => U5_n0025,
      RST => U5_pulse_reg1_3_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1_3_1,
      SET => GND
    );
  U5_pulse_reg1_2_1_269 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18102,
      CE => U5_n0025,
      RST => U5_pulse_reg1_2_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1_2_1,
      SET => GND
    );
  U5_pulse_reg1_1_1_270 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18100,
      CE => U5_n0025,
      RST => U5_pulse_reg1_1_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1_1_1,
      SET => GND
    );
  U5_pulse_reg1_0_1_271 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N18098,
      CE => U5_n0025,
      RST => U5_pulse_reg1_0_1_GSR_OR,
      CLK => CLK,
      O => U5_pulse_reg1_0_1,
      SET => GND
    );
  U6_tr_dly26_LUT4_L_BUF : X_BUF
    port map (
      I => U6_tr_dly26_O,
      O => CHOICE331
    );
  U6_tr_dly26 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U6_trg_shift(7),
      ADR1 => U6_trg_delay(7),
      ADR2 => U6_trg_shift(6),
      ADR3 => U6_trg_delay(6),
      O => U6_tr_dly26_O
    );
  U6_tr_dly80_LUT4_L_BUF : X_BUF
    port map (
      I => U6_tr_dly80_O,
      O => CHOICE348
    );
  U6_tr_dly80 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE336,
      ADR1 => CHOICE339,
      ADR2 => CHOICE343,
      ADR3 => CHOICE346,
      O => U6_tr_dly80_O
    );
  U6_Ker14000_SW1_LUT2_L_BUF : X_BUF
    port map (
      I => U6_Ker14000_SW1_O,
      O => N18276
    );
  U6_Ker14000_SW1 : X_LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_N13953,
      O => U6_Ker14000_SW1_O
    );
  U6_Ker14000_SW2_LUT2_L_BUF : X_BUF
    port map (
      I => U6_Ker14000_SW2_O,
      O => N18280
    );
  U6_Ker14000_SW2 : X_LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_N13972,
      O => U6_Ker14000_SW2_O
    );
  U6_Ker139701_LUT4_D_BUF : X_BUF
    port map (
      I => U6_N13972,
      O => N18394
    );
  U6_Ker139701 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => add_int(1),
      ADR1 => tp2_OBUF,
      ADR2 => grp(1),
      ADR3 => add_int(0),
      O => U6_N13972
    );
  U6_n00051_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00051_O,
      O => U6_n0005
    );
  U6_n00051 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_n0000(30),
      ADR2 => U6_N13972,
      ADR3 => N18128,
      O => U6_n00051_O
    );
  U6_n00061_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00061_O,
      O => U6_n0006
    );
  U6_n00061 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_n0000(29),
      ADR2 => U6_N13972,
      ADR3 => N18126,
      O => U6_n00061_O
    );
  U6_n00081_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00081_O,
      O => U6_n0008
    );
  U6_n00081 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_n0000(27),
      ADR2 => U6_N13972,
      ADR3 => N18122,
      O => U6_n00081_O
    );
  U6_n00091_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00091_O,
      O => U6_n0009
    );
  U6_n00091 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(26),
      ADR2 => U6_N13972,
      ADR3 => N18120,
      O => U6_n00091_O
    );
  U6_n00101_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00101_O,
      O => U6_n0010
    );
  U6_n00101 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(25),
      ADR2 => U6_N13972,
      ADR3 => N18118,
      O => U6_n00101_O
    );
  U6_n00111_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00111_O,
      O => U6_n0011
    );
  U6_n00111 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(24),
      ADR2 => U6_N13972,
      ADR3 => N18114,
      O => U6_n00111_O
    );
  U6_n00121_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00121_O,
      O => U6_n0012
    );
  U6_n00121 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(23),
      ADR2 => U6_N13972,
      ADR3 => N18112,
      O => U6_n00121_O
    );
  U6_n00131_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00131_O,
      O => U6_n0013
    );
  U6_n00131 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(22),
      ADR2 => U6_N13972,
      ADR3 => N18110,
      O => U6_n00131_O
    );
  U6_n00141_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00141_O,
      O => U6_n0014
    );
  U6_n00141 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(21),
      ADR2 => U6_N13972,
      ADR3 => N18108,
      O => U6_n00141_O
    );
  U6_n00151_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00151_O,
      O => U6_n0015
    );
  U6_n00151 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(20),
      ADR2 => U6_N13972,
      ADR3 => N18106,
      O => U6_n00151_O
    );
  U6_n00161_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00161_O,
      O => U6_n0016
    );
  U6_n00161 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(19),
      ADR2 => U6_N13972,
      ADR3 => N18104,
      O => U6_n00161_O
    );
  U6_n00171_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00171_O,
      O => U6_n0017
    );
  U6_n00171 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(18),
      ADR2 => U6_N13972,
      ADR3 => N18102,
      O => U6_n00171_O
    );
  U6_n00181_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00181_O,
      O => U6_n0018
    );
  U6_n00181 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(17),
      ADR2 => U6_N13972,
      ADR3 => N18100,
      O => U6_n00181_O
    );
  U6_n00191_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00191_O,
      O => U6_n0019
    );
  U6_n00191 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(16),
      ADR2 => U6_N13972,
      ADR3 => N18098,
      O => U6_n00191_O
    );
  U6_n00221_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00221_O,
      O => U6_n0022
    );
  U6_n00221 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(14),
      ADR2 => U6_N13953,
      ADR3 => N18128,
      O => U6_n00221_O
    );
  U6_n00231_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00231_O,
      O => U6_n0023
    );
  U6_n00231 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(13),
      ADR2 => U6_N13953,
      ADR3 => N18126,
      O => U6_n00231_O
    );
  U6_n00241_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00241_O,
      O => U6_n0024
    );
  U6_n00241 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(12),
      ADR2 => U6_N13953,
      ADR3 => N18124,
      O => U6_n00241_O
    );
  U6_n00261_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00261_O,
      O => U6_n0026
    );
  U6_n00261 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(10),
      ADR2 => U6_N13953,
      ADR3 => N18120,
      O => U6_n00261_O
    );
  U6_n00271_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00271_O,
      O => U6_n0027
    );
  U6_n00271 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(9),
      ADR2 => U6_N13953,
      ADR3 => N18118,
      O => U6_n00271_O
    );
  U6_n00281_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00281_O,
      O => U6_n0028
    );
  U6_n00281 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(8),
      ADR2 => U6_N13953,
      ADR3 => N18114,
      O => U6_n00281_O
    );
  U6_n00291_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00291_O,
      O => U6_n0029
    );
  U6_n00291 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(7),
      ADR2 => U6_N13953,
      ADR3 => N18112,
      O => U6_n00291_O
    );
  U6_n00301_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00301_O,
      O => U6_n0030
    );
  U6_n00301 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(6),
      ADR2 => U6_N13953,
      ADR3 => N18110,
      O => U6_n00301_O
    );
  U6_n00311_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00311_O,
      O => U6_n0031
    );
  U6_n00311 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(5),
      ADR2 => U6_N13953,
      ADR3 => N18108,
      O => U6_n00311_O
    );
  U6_n00321_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00321_O,
      O => U6_n0032
    );
  U6_n00321 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(4),
      ADR2 => U6_N13953,
      ADR3 => N18106,
      O => U6_n00321_O
    );
  U6_n00331_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00331_O,
      O => U6_n0033
    );
  U6_n00331 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(3),
      ADR2 => U6_N13953,
      ADR3 => N18104,
      O => U6_n00331_O
    );
  U6_n00341_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00341_O,
      O => U6_n0034
    );
  U6_n00341 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(2),
      ADR2 => U6_N13953,
      ADR3 => N18102,
      O => U6_n00341_O
    );
  U6_n00351_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00351_O,
      O => U6_n0035
    );
  U6_n00351 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(1),
      ADR2 => U6_N13953,
      ADR3 => N18100,
      O => U6_n00351_O
    );
  U6_n00251_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00251_O,
      O => U6_n0025
    );
  U6_n00251 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(11),
      ADR2 => U6_N13953,
      ADR3 => N18122,
      O => U6_n00251_O
    );
  U6_n00041_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00041_O,
      O => U6_n0004
    );
  U6_n00041 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_n0000(31),
      ADR2 => U6_N13972,
      ADR3 => N18130,
      O => U6_n00041_O
    );
  U6_n00071_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00071_O,
      O => U6_n0007
    );
  U6_n00071 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin,
      ADR1 => U6_n0000(28),
      ADR2 => N18394,
      ADR3 => N18124,
      O => U6_n00071_O
    );
  U6_n00211_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00211_O,
      O => U6_n0021
    );
  U6_n00211 : X_LUT4
    generic map(
      INIT => X"4540"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_n0000(15),
      ADR2 => U6_N13953,
      ADR3 => N18130,
      O => U6_n00211_O
    );
  U1_enw1_LUT2_D_BUF : X_BUF
    port map (
      I => tp2_OBUF,
      O => N18361
    );
  U1_enw1 : X_LUT2
    generic map(
      INIT => X"4"
    )
    port map (
      ADR0 => U1_fq4_q,
      ADR1 => U1_fq2_q,
      O => tp2_OBUF
    );
  U7_U4_n00091_LUT4_D_BUF : X_BUF
    port map (
      I => U7_U4_n0009,
      O => N18359
    );
  U7_U4_n00091 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => grp(4),
      ADR2 => add_int(0),
      ADR3 => add_int(1),
      O => U7_U4_n0009
    );
  Q_n00201_LUT4_D_BUF : X_BUF
    port map (
      I => Q_n0020,
      O => N18357
    );
  Q_n00201 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => tp2_OBUF,
      ADR1 => add_int(0),
      ADR2 => add_int(1),
      ADR3 => grp(0),
      O => Q_n0020
    );
  U6_n00361_LUT4_L_BUF : X_BUF
    port map (
      I => U6_n00361_O,
      O => U6_n0036
    );
  U6_n00361 : X_LUT4
    generic map(
      INIT => X"1510"
    )
    port map (
      ADR0 => set_trgin_2,
      ADR1 => U6_trg_cntout(0),
      ADR2 => U6_N13953,
      ADR3 => N18098,
      O => U6_n00361_O
    );
  db_out_6_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  db_out_3_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  db_out_8_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  db_out_7_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  db_out_15_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  db_out_0_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  db_out_1_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  db_out_2_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  db_out_4_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  db_out_5_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  db_out_9_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  db_out_11_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  db_out_12_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  db_out_10_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  db_out_13_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  db_out_14_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  db_15_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_15_IOBUF_OBUFT_GTS_AND,
      I => db_out(15),
      O => db(15)
    );
  db_15_IOBUF_IBUF : X_BUF
    port map (
      I => db(15),
      O => N18130
    );
  db_14_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_14_IOBUF_OBUFT_GTS_AND,
      I => db_out(14),
      O => db(14)
    );
  db_14_IOBUF_IBUF : X_BUF
    port map (
      I => db(14),
      O => N18128
    );
  db_13_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_13_IOBUF_OBUFT_GTS_AND,
      I => db_out(13),
      O => db(13)
    );
  db_13_IOBUF_IBUF : X_BUF
    port map (
      I => db(13),
      O => N18126
    );
  db_12_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_12_IOBUF_OBUFT_GTS_AND,
      I => db_out(12),
      O => db(12)
    );
  db_12_IOBUF_IBUF : X_BUF
    port map (
      I => db(12),
      O => N18124
    );
  db_11_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_11_IOBUF_OBUFT_GTS_AND,
      I => db_out(11),
      O => db(11)
    );
  db_11_IOBUF_IBUF : X_BUF
    port map (
      I => db(11),
      O => N18122
    );
  db_10_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_10_IOBUF_OBUFT_GTS_AND,
      I => db_out(10),
      O => db(10)
    );
  db_10_IOBUF_IBUF : X_BUF
    port map (
      I => db(10),
      O => N18120
    );
  db_9_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_9_IOBUF_OBUFT_GTS_AND,
      I => db_out(9),
      O => db(9)
    );
  db_9_IOBUF_IBUF : X_BUF
    port map (
      I => db(9),
      O => N18118
    );
  db_8_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_8_IOBUF_OBUFT_GTS_AND,
      I => db_out(8),
      O => db(8)
    );
  db_8_IOBUF_IBUF : X_BUF
    port map (
      I => db(8),
      O => N18114
    );
  db_7_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_7_IOBUF_OBUFT_GTS_AND,
      I => db_out(7),
      O => db(7)
    );
  db_7_IOBUF_IBUF : X_BUF
    port map (
      I => db(7),
      O => N18112
    );
  db_6_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_6_IOBUF_OBUFT_GTS_AND,
      I => db_out(6),
      O => db(6)
    );
  db_6_IOBUF_IBUF : X_BUF
    port map (
      I => db(6),
      O => N18110
    );
  db_5_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_5_IOBUF_OBUFT_GTS_AND,
      I => db_out(5),
      O => db(5)
    );
  db_5_IOBUF_IBUF : X_BUF
    port map (
      I => db(5),
      O => N18108
    );
  db_4_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_4_IOBUF_OBUFT_GTS_AND,
      I => db_out(4),
      O => db(4)
    );
  db_4_IOBUF_IBUF : X_BUF
    port map (
      I => db(4),
      O => N18106
    );
  db_3_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_3_IOBUF_OBUFT_GTS_AND,
      I => db_out(3),
      O => db(3)
    );
  db_3_IOBUF_IBUF : X_BUF
    port map (
      I => db(3),
      O => N18104
    );
  db_2_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_2_IOBUF_OBUFT_GTS_AND,
      I => db_out(2),
      O => db(2)
    );
  db_2_IOBUF_IBUF : X_BUF
    port map (
      I => db(2),
      O => N18102
    );
  db_1_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_1_IOBUF_OBUFT_GTS_AND,
      I => db_out(1),
      O => db(1)
    );
  db_1_IOBUF_IBUF : X_BUF
    port map (
      I => db(1),
      O => N18100
    );
  db_0_IOBUF_OBUFT : X_TRI
    port map (
      CTL => db_0_IOBUF_OBUFT_GTS_AND,
      I => db_out(0),
      O => db(0)
    );
  db_0_IOBUF_IBUF : X_BUF
    port map (
      I => db(0),
      O => N18098
    );
  tdio_IOBUF_OBUFT : X_TRI
    port map (
      CTL => tdio_IOBUF_OBUFT_GTS_AND,
      I => tp3_OBUF,
      O => tdio
    );
  tdio_IOBUF_IBUF : X_BUF
    port map (
      I => tdio,
      O => N18116
    );
  U6_S1_F0_BU35 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(14),
      Q => U6_trg_shift(15),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU33 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(13),
      Q => U6_trg_shift(14),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU31 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(12),
      Q => U6_trg_shift(13),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU29 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(11),
      Q => U6_trg_shift(12),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU27 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(10),
      Q => U6_trg_shift(11),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU25 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(9),
      Q => U6_trg_shift(10),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU23 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(8),
      Q => U6_trg_shift(9),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU21 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(7),
      Q => U6_trg_shift(8),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU19 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(6),
      Q => U6_trg_shift(7),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU17 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(5),
      Q => U6_trg_shift(6),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU15 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(4),
      Q => U6_trg_shift(5),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU13 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(3),
      Q => U6_trg_shift(4),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU11 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(2),
      Q => U6_trg_shift(3),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU9 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(1),
      Q => U6_trg_shift(2),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU7 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_trg_shift(0),
      Q => U6_trg_shift(1),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_BU5 : X_SRL16E
    generic map(
      INIT => X"0000"
    )
    port map (
      CE => U6_S1_F0_N1,
      D => U6_tr_2,
      Q => U6_trg_shift(0),
      CLK => CLK,
      A0 => U6_S1_F0_N1,
      A1 => U6_S1_F0_N1,
      A2 => U6_S1_F0_N1,
      A3 => U6_S1_F0_N0
    );
  U6_S1_F0_GND : X_ZERO
    port map (
      O => U6_S1_F0_N0
    );
  U6_S1_F0_VCC : X_ONE
    port map (
      O => U6_S1_F0_N1
    );
  ron_reg_5_GSR_OR_325 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_5_GSR_OR
    );
  ron_reg_4_GSR_OR_326 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_4_GSR_OR
    );
  ron_reg_3_GSR_OR_327 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_3_GSR_OR
    );
  ron_reg_2_GSR_OR_328 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_2_GSR_OR
    );
  int_vec_2_2_GSR_OR_329 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_2_GSR_OR
    );
  int_vec_2_4_GSR_OR_330 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_4_GSR_OR
    );
  int_vec_2_5_GSR_OR_331 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_5_GSR_OR
    );
  int_vec_2_3_GSR_OR_332 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_3_GSR_OR
    );
  int_vec_2_6_GSR_OR_333 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_6_GSR_OR
    );
  int_vec_1_0_GSR_OR_334 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_0_GSR_OR
    );
  int_lev_2_0_GSR_OR_335 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_2_0_GSR_OR
    );
  int_ena_0_GSR_OR_336 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_ena_0_GSR_OR
    );
  int_ena_1_GSR_OR_337 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_ena_1_GSR_OR
    );
  U7_U3_M1_count_2_GSR_OR_338 : X_OR2
    port map (
      I0 => U7_U3_M1_count_0_3_N1304,
      I1 => GSR,
      O => U7_U3_M1_count_2_GSR_OR
    );
  U7_U3_M1_count_3_GSR_OR_339 : X_OR2
    port map (
      I0 => U7_U3_M1_count_0_3_N1304,
      I1 => GSR,
      O => U7_U3_M1_count_3_GSR_OR
    );
  int_lev_1_1_GSR_OR_340 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_1_1_GSR_OR
    );
  int_lev_0_0_GSR_OR_341 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_0_0_GSR_OR
    );
  int_lev_0_1_GSR_OR_342 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_0_1_GSR_OR
    );
  int_vec_2_0_GSR_OR_343 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_0_GSR_OR
    );
  int_vec_2_1_GSR_OR_344 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_1_GSR_OR
    );
  int_lev_1_0_GSR_OR_345 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_1_0_GSR_OR
    );
  int_lev_2_1_GSR_OR_346 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_2_1_GSR_OR
    );
  U1_fq1_q_GSR_OR_347 : X_OR2
    port map (
      I0 => U1_ds_rst,
      I1 => GSR,
      O => U1_fq1_q_GSR_OR
    );
  int_ena_2_GSR_OR_348 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_ena_2_GSR_OR
    );
  trg_bypass_GSR_OR_349 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => trg_bypass_GSR_OR
    );
  ena_tm_GSR_OR_350 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ena_tm_GSR_OR
    );
  fltb_reg_GSR_OR_351 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => fltb_reg_GSR_OR
    );
  int_lev_0_2_GSR_OR_352 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_0_2_GSR_OR
    );
  int_lev_1_2_GSR_OR_353 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_1_2_GSR_OR
    );
  int_lev_2_2_GSR_OR_354 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_lev_2_2_GSR_OR
    );
  int_vec_0_7_GSR_OR_355 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_7_GSR_OR
    );
  int_vec_1_7_GSR_OR_356 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_7_GSR_OR
    );
  int_vec_2_7_GSR_OR_357 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_2_7_GSR_OR
    );
  ron_reg_6_GSR_OR_358 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_6_GSR_OR
    );
  jtag_reg_6_GSR_OR_359 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_6_GSR_OR
    );
  v_bcrst_GSR_OR_360 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_bcrst_GSR_OR
    );
  v_trg_GSR_OR_361 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_trg_GSR_OR
    );
  v_robrst_GSR_OR_362 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_robrst_GSR_OR
    );
  v_evrst_GSR_OR_363 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_evrst_GSR_OR
    );
  v_pulse_0_GSR_OR_364 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_pulse_0_GSR_OR
    );
  v_pulse_1_GSR_OR_365 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_pulse_1_GSR_OR
    );
  v_tmadv_GSR_OR_366 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_tmadv_GSR_OR
    );
  v_tmrst_GSR_OR_367 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => v_tmrst_GSR_OR
    );
  set_trgin_GSR_OR_368 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => set_trgin_GSR_OR
    );
  ron_reg_1_GSR_OR_369 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_1_GSR_OR
    );
  ron_reg_0_GSR_OR_370 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_0_GSR_OR
    );
  jtag_reg_5_GSR_OR_371 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_5_GSR_OR
    );
  jtag_reg_4_GSR_OR_372 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_4_GSR_OR
    );
  jtag_reg_3_GSR_OR_373 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_3_GSR_OR
    );
  jtag_reg_2_GSR_OR_374 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_2_GSR_OR
    );
  jtag_reg_1_GSR_OR_375 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_1_GSR_OR
    );
  jtag_reg_0_GSR_OR_376 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_0_GSR_OR
    );
  int_vec_0_6_GSR_OR_377 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_6_GSR_OR
    );
  int_vec_0_5_GSR_OR_378 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_5_GSR_OR
    );
  int_vec_0_4_GSR_OR_379 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_4_GSR_OR
    );
  int_vec_0_3_GSR_OR_380 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_3_GSR_OR
    );
  int_vec_0_2_GSR_OR_381 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_2_GSR_OR
    );
  int_vec_0_1_GSR_OR_382 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_1_GSR_OR
    );
  int_vec_0_0_GSR_OR_383 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_0_0_GSR_OR
    );
  int_vec_1_6_GSR_OR_384 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_6_GSR_OR
    );
  int_vec_1_5_GSR_OR_385 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_5_GSR_OR
    );
  int_vec_1_4_GSR_OR_386 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_4_GSR_OR
    );
  int_vec_1_3_GSR_OR_387 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_3_GSR_OR
    );
  int_vec_1_2_GSR_OR_388 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_2_GSR_OR
    );
  int_vec_1_1_GSR_OR_389 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => int_vec_1_1_GSR_OR
    );
  U7_U1_M2_count_0_GSR_OR_390 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_0_GSR_OR
    );
  U7_U2_M2_count_0_GSR_OR_391 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_0_GSR_OR
    );
  U7_U4_crc_reg_3_GSR_OR_392 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_3_GSR_OR
    );
  U7_w_reg_GSR_OR_393 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_w_reg_GSR_OR
    );
  U7_r_reg_GSR_OR_394 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_r_reg_GSR_OR
    );
  U7_read_read_q_GSR_OR_395 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_read_read_q_GSR_OR
    );
  U7_ckdiv_4_GSR_OR_396 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_ckdiv_4_GSR_OR
    );
  U7_ckdiv_0_GSR_OR_397 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_ckdiv_0_GSR_OR
    );
  U7_ckdiv_1_GSR_OR_398 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_ckdiv_1_GSR_OR
    );
  U7_ckdiv_2_GSR_OR_399 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_ckdiv_2_GSR_OR
    );
  U7_ckdiv_3_GSR_OR_400 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U7_ckdiv_3_GSR_OR
    );
  U7_U1_init_read_GSR_OR_401 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U1_init_read_GSR_OR
    );
  U7_U1_init_GSR_OR_402 : X_OR2
    port map (
      I0 => U7_U1_M1_end_count,
      I1 => GSR,
      O => U7_U1_init_GSR_OR
    );
  U7_U1_M2_count_2_GSR_OR_403 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_2_GSR_OR
    );
  U7_U1_M1_count_7_GSR_OR_404 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_7_GSR_OR
    );
  U7_U1_M2_count_3_GSR_OR_405 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_3_GSR_OR
    );
  U7_U1_M1_count_8_GSR_OR_406 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_8_GSR_OR
    );
  U7_U1_M2_count_1_GSR_OR_407 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_1_GSR_OR
    );
  U7_U1_M1_count_10_GSR_OR_408 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_10_GSR_OR
    );
  U7_U1_M1_count_9_GSR_OR_409 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_9_GSR_OR
    );
  U7_U1_M1_count_0_GSR_OR_410 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_0_GSR_OR
    );
  U7_U1_M1_count_1_GSR_OR_411 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_1_GSR_OR
    );
  U7_U1_M1_count_2_GSR_OR_412 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_2_GSR_OR
    );
  U7_U1_M1_count_3_GSR_OR_413 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_3_GSR_OR
    );
  U7_U1_M1_count_4_GSR_OR_414 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_4_GSR_OR
    );
  U7_U1_M1_count_5_GSR_OR_415 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_5_GSR_OR
    );
  U7_U1_M1_count_6_GSR_OR_416 : X_OR2
    port map (
      I0 => U7_U1_M1_count_0_10_N1304,
      I1 => GSR,
      O => U7_U1_M1_count_6_GSR_OR
    );
  U7_U1_M2_count_5_GSR_OR_417 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_5_GSR_OR
    );
  U7_U1_M2_count_4_GSR_OR_418 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_4_GSR_OR
    );
  U7_U1_M2_count_7_GSR_OR_419 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_7_GSR_OR
    );
  U7_U1_M2_count_6_GSR_OR_420 : X_OR2
    port map (
      I0 => U7_U1_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U1_M2_count_6_GSR_OR
    );
  U7_U2_M2_count_2_GSR_OR_421 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_2_GSR_OR
    );
  U7_U2_M1_count_1_GSR_OR_422 : X_OR2
    port map (
      I0 => U7_U2_M1_count_0_4_N1304,
      I1 => GSR,
      O => U7_U2_M1_count_1_GSR_OR
    );
  U7_U2_M2_count_3_GSR_OR_423 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_3_GSR_OR
    );
  U7_U2_w1_GSR_OR_424 : X_OR2
    port map (
      I0 => U7_U2_M1_end_count,
      I1 => GSR,
      O => U7_U2_w1_GSR_OR
    );
  U7_U2_w0_GSR_OR_425 : X_OR2
    port map (
      I0 => U7_U2_M2_end_count,
      I1 => GSR,
      O => U7_U2_w0_GSR_OR
    );
  U7_U2_M1_count_2_GSR_OR_426 : X_OR2
    port map (
      I0 => U7_U2_M1_count_0_4_N1304,
      I1 => GSR,
      O => U7_U2_M1_count_2_GSR_OR
    );
  U7_U2_M2_count_1_GSR_OR_427 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_1_GSR_OR
    );
  U7_U2_M1_count_4_GSR_OR_428 : X_OR2
    port map (
      I0 => U7_U2_M1_count_0_4_N1304,
      I1 => GSR,
      O => U7_U2_M1_count_4_GSR_OR
    );
  U7_U2_M1_count_3_GSR_OR_429 : X_OR2
    port map (
      I0 => U7_U2_M1_count_0_4_N1304,
      I1 => GSR,
      O => U7_U2_M1_count_3_GSR_OR
    );
  U7_U2_M1_count_0_GSR_OR_430 : X_OR2
    port map (
      I0 => U7_U2_M1_count_0_4_N1304,
      I1 => GSR,
      O => U7_U2_M1_count_0_GSR_OR
    );
  U7_U2_M2_count_5_GSR_OR_431 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_5_GSR_OR
    );
  U7_U2_M2_count_4_GSR_OR_432 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_4_GSR_OR
    );
  U7_U2_M2_count_7_GSR_OR_433 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_7_GSR_OR
    );
  U7_U2_M2_count_6_GSR_OR_434 : X_OR2
    port map (
      I0 => U7_U2_M2_count_0_7_N1304,
      I1 => GSR,
      O => U7_U2_M2_count_6_GSR_OR
    );
  U7_U3_rd_GSR_OR_435 : X_OR2
    port map (
      I0 => U7_U3_M2_end_count,
      I1 => GSR,
      O => U7_U3_rd_GSR_OR
    );
  U7_U3_rdpls_GSR_OR_436 : X_OR2
    port map (
      I0 => U7_U3_M1_end_count,
      I1 => GSR,
      O => U7_U3_rdpls_GSR_OR
    );
  U7_U3_M2_count_3_GSR_OR_437 : X_OR2
    port map (
      I0 => U7_U3_M2_count_0_4_N1304,
      I1 => GSR,
      O => U7_U3_M2_count_3_GSR_OR
    );
  U7_U3_M1_count_0_GSR_OR_438 : X_OR2
    port map (
      I0 => U7_U3_M1_count_0_3_N1304,
      I1 => GSR,
      O => U7_U3_M1_count_0_GSR_OR
    );
  U7_U3_M2_count_0_GSR_OR_439 : X_OR2
    port map (
      I0 => U7_U3_M2_count_0_4_N1304,
      I1 => GSR,
      O => U7_U3_M2_count_0_GSR_OR
    );
  U7_U3_M1_count_1_GSR_OR_440 : X_OR2
    port map (
      I0 => U7_U3_M1_count_0_3_N1304,
      I1 => GSR,
      O => U7_U3_M1_count_1_GSR_OR
    );
  U7_U3_M2_count_4_GSR_OR_441 : X_OR2
    port map (
      I0 => U7_U3_M2_count_0_4_N1304,
      I1 => GSR,
      O => U7_U3_M2_count_4_GSR_OR
    );
  U7_U3_M2_count_1_GSR_OR_442 : X_OR2
    port map (
      I0 => U7_U3_M2_count_0_4_N1304,
      I1 => GSR,
      O => U7_U3_M2_count_1_GSR_OR
    );
  U7_U3_M2_count_2_GSR_OR_443 : X_OR2
    port map (
      I0 => U7_U3_M2_count_0_4_N1304,
      I1 => GSR,
      O => U7_U3_M2_count_2_GSR_OR
    );
  U5_pulse_reg1_13_GSR_OR_444 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_13_GSR_OR
    );
  U5_pulse_reg0_12_GSR_OR_445 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_12_GSR_OR
    );
  U5_pulse_reg0_6_GSR_OR_446 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_6_GSR_OR
    );
  U5_pulse_reg0_11_GSR_OR_447 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_11_GSR_OR
    );
  U5_pulse_reg0_5_GSR_OR_448 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_5_GSR_OR
    );
  U5_pulse_reg0_10_GSR_OR_449 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_10_GSR_OR
    );
  U5_pulse_reg0_9_GSR_OR_450 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_9_GSR_OR
    );
  U5_pulse_reg0_8_GSR_OR_451 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_8_GSR_OR
    );
  U5_pulse_reg0_7_GSR_OR_452 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_7_GSR_OR
    );
  U5_ps1_0_GSR_OR_453 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U5_ps1_0_GSR_OR
    );
  U5_ps2_0_GSR_OR_454 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U5_ps2_0_GSR_OR
    );
  U5_ps2_1_GSR_OR_455 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U5_ps2_1_GSR_OR
    );
  U5_ps1_1_GSR_OR_456 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U5_ps1_1_GSR_OR
    );
  U5_q1_1_GSR_OR_457 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_q1_1_GSR_OR
    );
  U5_q1_0_GSR_OR_458 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_q1_0_GSR_OR
    );
  U5_q0_1_GSR_OR_459 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_q0_1_GSR_OR
    );
  U5_q0_0_GSR_OR_460 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_q0_0_GSR_OR
    );
  U5_pulse_reg0_13_GSR_OR_461 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_13_GSR_OR
    );
  U5_pulse_reg1_0_GSR_OR_462 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_0_GSR_OR
    );
  U5_pulse_reg1_1_GSR_OR_463 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_1_GSR_OR
    );
  U5_pulse_reg1_2_GSR_OR_464 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_2_GSR_OR
    );
  U5_pulse_reg1_3_GSR_OR_465 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_3_GSR_OR
    );
  U5_pulse_reg1_4_GSR_OR_466 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_4_GSR_OR
    );
  U5_pulse_reg1_5_GSR_OR_467 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_5_GSR_OR
    );
  U5_pulse_reg1_6_GSR_OR_468 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_6_GSR_OR
    );
  U5_pulse_reg1_7_GSR_OR_469 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_7_GSR_OR
    );
  U5_pulse_reg1_8_GSR_OR_470 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_8_GSR_OR
    );
  U5_pulse_reg1_9_GSR_OR_471 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_9_GSR_OR
    );
  U5_pulse_reg1_10_GSR_OR_472 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_10_GSR_OR
    );
  U5_pulse_reg1_11_GSR_OR_473 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_11_GSR_OR
    );
  U5_pulse_reg1_12_GSR_OR_474 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_12_GSR_OR
    );
  U5_pulse_reg0_0_GSR_OR_475 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_0_GSR_OR
    );
  U5_pulse_reg0_1_GSR_OR_476 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_1_GSR_OR
    );
  U5_pulse_reg0_2_GSR_OR_477 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_2_GSR_OR
    );
  U5_pulse_reg0_3_GSR_OR_478 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_3_GSR_OR
    );
  U5_pulse_reg0_4_GSR_OR_479 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_4_GSR_OR
    );
  U7_U4_crc_reg_5_GSR_OR_480 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_5_GSR_OR
    );
  U7_U4_crc_reg_6_GSR_OR_481 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_6_GSR_OR
    );
  U7_U4_crc_reg_7_GSR_OR_482 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_7_GSR_OR
    );
  U7_U4_crc_reg_4_GSR_OR_483 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_4_GSR_OR
    );
  U7_U4_crc_reg_0_GSR_OR_484 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_0_GSR_OR
    );
  U7_U4_crc_reg_1_GSR_OR_485 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_1_GSR_OR
    );
  U7_U4_crc_reg_2_GSR_OR_486 : X_OR2
    port map (
      I0 => U7_U1_M2_end_count,
      I1 => GSR,
      O => U7_U4_crc_reg_2_GSR_OR
    );
  U1_fds_q_GSR_OR_487 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U1_fds_q_GSR_OR
    );
  U1_fq5_q_GSR_OR_488 : X_OR2
    port map (
      I0 => U1_ds_rst,
      I1 => GSR,
      O => U1_fq5_q_GSR_OR
    );
  U1_fq2_q_GSR_OR_489 : X_OR2
    port map (
      I0 => U1_ds_rst,
      I1 => GSR,
      O => U1_fq2_q_GSR_OR
    );
  U4_fr4_q_GSR_OR_490 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U4_fr4_q_GSR_OR
    );
  U4_fr9_q_GSR_OR_491 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U4_fr9_q_GSR_OR
    );
  U4_fr7_q_GSR_OR_492 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U4_fr7_q_GSR_OR
    );
  U4_fr3_q_GSR_OR_493 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U4_fr3_q_GSR_OR
    );
  U4_fr2_q_GSR_OR_494 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U4_fr2_q_GSR_OR
    );
  U4_fr1_q_GSR_OR_495 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U4_fr1_q_GSR_OR
    );
  U4_fr5_q_GSR_OR_496 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U4_fr5_q_GSR_OR
    );
  U4_fr6_q_GSR_OR_497 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U4_fr6_q_GSR_OR
    );
  U3_fr4_q_GSR_OR_498 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U3_fr4_q_GSR_OR
    );
  U3_fr9_q_GSR_OR_499 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U3_fr9_q_GSR_OR
    );
  U3_fr7_q_GSR_OR_500 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U3_fr7_q_GSR_OR
    );
  U3_fr2_q_GSR_OR_501 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U3_fr2_q_GSR_OR
    );
  U3_fr1_q_GSR_OR_502 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U3_fr1_q_GSR_OR
    );
  U3_fr5_q_GSR_OR_503 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U3_fr5_q_GSR_OR
    );
  U3_fr6_q_GSR_OR_504 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U3_fr6_q_GSR_OR
    );
  U2_fr4_q_GSR_OR_505 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U2_fr4_q_GSR_OR
    );
  U2_fr9_q_GSR_OR_506 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => U2_fr9_q_GSR_OR
    );
  U2_fr7_q_GSR_OR_507 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U2_fr7_q_GSR_OR
    );
  U2_fr2_q_GSR_OR_508 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U2_fr2_q_GSR_OR
    );
  U2_fr1_q_GSR_OR_509 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U2_fr1_q_GSR_OR
    );
  U2_fr5_q_GSR_OR_510 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U2_fr5_q_GSR_OR
    );
  U2_fr6_q_GSR_OR_511 : X_OR2
    port map (
      I0 => ds0_IBUFG,
      I1 => GSR,
      O => U2_fr6_q_GSR_OR
    );
  U6_trg_delay_14_GSR_OR_512 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_14_GSR_OR
    );
  U6_trg_delay_13_GSR_OR_513 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_13_GSR_OR
    );
  U6_trg_delay_12_GSR_OR_514 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_12_GSR_OR
    );
  U6_trg_cntoutreg_4_GSR_OR_515 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_4_GSR_OR
    );
  U6_trg_delay_11_GSR_OR_516 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_11_GSR_OR
    );
  U6_trg_cntoutreg_5_GSR_OR_517 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_5_GSR_OR
    );
  U6_trg_delay_10_GSR_OR_518 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_10_GSR_OR
    );
  U6_trg_delay_8_GSR_OR_519 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_8_GSR_OR
    );
  U6_trg_maxcnt_6_GSR_OR_520 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_6_GSR_OR
    );
  U6_trg_maxcnt_7_GSR_OR_521 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_7_GSR_OR
    );
  U6_trg_maxcnt_8_GSR_OR_522 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_8_GSR_OR
    );
  U6_trg_maxcnt_9_GSR_OR_523 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_9_GSR_OR
    );
  U6_trg_maxcnt_10_GSR_OR_524 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_10_GSR_OR
    );
  U6_trg_maxcnt_11_GSR_OR_525 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_11_GSR_OR
    );
  U6_trg_maxcnt_12_GSR_OR_526 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_12_GSR_OR
    );
  U6_trg_maxcnt_13_GSR_OR_527 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_13_GSR_OR
    );
  U6_trg_maxcnt_14_GSR_OR_528 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_14_GSR_OR
    );
  U6_trg_delay_0_GSR_OR_529 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_0_GSR_OR
    );
  U6_trg_delay_1_GSR_OR_530 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_1_GSR_OR
    );
  U6_trg_delay_2_GSR_OR_531 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_2_GSR_OR
    );
  U6_trg_delay_3_GSR_OR_532 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_3_GSR_OR
    );
  U6_trg_delay_4_GSR_OR_533 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_4_GSR_OR
    );
  U6_trg_delay_5_GSR_OR_534 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_5_GSR_OR
    );
  U6_trg_delay_6_GSR_OR_535 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_6_GSR_OR
    );
  U6_trg_maxcnt_5_GSR_OR_536 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_5_GSR_OR
    );
  U6_trg_delay_7_GSR_OR_537 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_7_GSR_OR
    );
  U6_trg_cntoutreg_6_GSR_OR_538 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_6_GSR_OR
    );
  U6_trg_cntoutreg_7_GSR_OR_539 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_7_GSR_OR
    );
  U6_trg_cntoutreg_8_GSR_OR_540 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_8_GSR_OR
    );
  U6_trg_cntoutreg_9_GSR_OR_541 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_9_GSR_OR
    );
  U6_trg_maxcnt_4_GSR_OR_542 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_4_GSR_OR
    );
  U6_trg_maxcnt_3_GSR_OR_543 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_3_GSR_OR
    );
  U6_trg_maxcnt_2_GSR_OR_544 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_2_GSR_OR
    );
  U6_trg_maxcnt_1_GSR_OR_545 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_1_GSR_OR
    );
  U6_trg_maxcnt_0_GSR_OR_546 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_0_GSR_OR
    );
  U6_trg_cntoutreg_10_GSR_OR_547 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_10_GSR_OR
    );
  U6_trg_delay_9_GSR_OR_548 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_9_GSR_OR
    );
  U6_q_in_GSR_OR_549 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_q_in_GSR_OR
    );
  U6_trg_cntoutreg_0_GSR_OR_550 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_0_GSR_OR
    );
  U6_trg_cntoutreg_1_GSR_OR_551 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_1_GSR_OR
    );
  U6_trg_cntoutreg_2_GSR_OR_552 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_2_GSR_OR
    );
  U6_trg_cntoutreg_3_GSR_OR_553 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_3_GSR_OR
    );
  U6_tr_0_GSR_OR_554 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_tr_0_GSR_OR
    );
  U6_tr_1_GSR_OR_555 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_tr_1_GSR_OR
    );
  U6_v_0_GSR_OR_556 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_v_0_GSR_OR
    );
  U6_v_1_GSR_OR_557 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_v_1_GSR_OR
    );
  U6_trg_delay_15_GSR_OR_558 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_delay_15_GSR_OR
    );
  U6_trg_maxcnt_15_GSR_OR_559 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_maxcnt_15_GSR_OR
    );
  U6_trg_cntout_31_GSR_OR_560 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_31_GSR_OR
    );
  U6_trg_cntout_30_GSR_OR_561 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_30_GSR_OR
    );
  U6_trg_cntout_29_GSR_OR_562 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_29_GSR_OR
    );
  U6_trg_cntout_28_GSR_OR_563 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_28_GSR_OR
    );
  U6_trg_cntout_27_GSR_OR_564 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_27_GSR_OR
    );
  U6_trg_cntout_26_GSR_OR_565 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_26_GSR_OR
    );
  U6_trg_cntout_25_GSR_OR_566 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_25_GSR_OR
    );
  U6_trg_cntout_24_GSR_OR_567 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_24_GSR_OR
    );
  U6_trg_cntout_23_GSR_OR_568 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_23_GSR_OR
    );
  U6_trg_cntout_22_GSR_OR_569 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_22_GSR_OR
    );
  U6_trg_cntout_21_GSR_OR_570 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_21_GSR_OR
    );
  U6_trg_cntout_20_GSR_OR_571 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_20_GSR_OR
    );
  U6_trg_cntout_19_GSR_OR_572 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_19_GSR_OR
    );
  U6_trg_cntout_18_GSR_OR_573 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_18_GSR_OR
    );
  U6_trg_cntout_17_GSR_OR_574 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_17_GSR_OR
    );
  U6_trg_cntout_16_GSR_OR_575 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_16_GSR_OR
    );
  U6_trg_cntout_15_GSR_OR_576 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_15_GSR_OR
    );
  U6_trg_cntout_14_GSR_OR_577 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_14_GSR_OR
    );
  U6_trg_cntout_13_GSR_OR_578 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_13_GSR_OR
    );
  U6_trg_cntout_12_GSR_OR_579 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_12_GSR_OR
    );
  U6_trg_cntout_11_GSR_OR_580 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_11_GSR_OR
    );
  U6_trg_cntout_10_GSR_OR_581 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_10_GSR_OR
    );
  U6_trg_cntout_9_GSR_OR_582 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_9_GSR_OR
    );
  U6_trg_cntout_8_GSR_OR_583 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_8_GSR_OR
    );
  U6_trg_cntout_7_GSR_OR_584 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_7_GSR_OR
    );
  U6_trg_cntout_6_GSR_OR_585 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_6_GSR_OR
    );
  U6_trg_cntout_5_GSR_OR_586 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_5_GSR_OR
    );
  U6_trg_cntout_4_GSR_OR_587 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_4_GSR_OR
    );
  U6_trg_cntout_3_GSR_OR_588 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_3_GSR_OR
    );
  U6_trg_cntout_2_GSR_OR_589 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_2_GSR_OR
    );
  U6_trg_cntout_1_GSR_OR_590 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_1_GSR_OR
    );
  U6_trg_cntout_0_GSR_OR_591 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U6_trg_cntout_0_GSR_OR
    );
  U6_trg_cntoutreg_31_GSR_OR_592 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_31_GSR_OR
    );
  U6_trg_cntoutreg_30_GSR_OR_593 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_30_GSR_OR
    );
  U6_trg_cntoutreg_29_GSR_OR_594 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_29_GSR_OR
    );
  U6_trg_cntoutreg_28_GSR_OR_595 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_28_GSR_OR
    );
  U6_trg_cntoutreg_27_GSR_OR_596 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_27_GSR_OR
    );
  U6_trg_cntoutreg_26_GSR_OR_597 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_26_GSR_OR
    );
  U6_trg_cntoutreg_25_GSR_OR_598 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_25_GSR_OR
    );
  U6_trg_cntoutreg_24_GSR_OR_599 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_24_GSR_OR
    );
  U6_trg_cntoutreg_23_GSR_OR_600 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_23_GSR_OR
    );
  U6_trg_cntoutreg_22_GSR_OR_601 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_22_GSR_OR
    );
  U6_trg_cntoutreg_21_GSR_OR_602 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_21_GSR_OR
    );
  U6_trg_cntoutreg_20_GSR_OR_603 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_20_GSR_OR
    );
  U6_trg_cntoutreg_19_GSR_OR_604 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_19_GSR_OR
    );
  U6_trg_cntoutreg_18_GSR_OR_605 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_18_GSR_OR
    );
  U6_trg_cntoutreg_17_GSR_OR_606 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_17_GSR_OR
    );
  U6_trg_cntoutreg_16_GSR_OR_607 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_16_GSR_OR
    );
  U6_trg_cntoutreg_15_GSR_OR_608 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_15_GSR_OR
    );
  U6_trg_cntoutreg_14_GSR_OR_609 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_14_GSR_OR
    );
  U6_trg_cntoutreg_13_GSR_OR_610 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_13_GSR_OR
    );
  U6_trg_cntoutreg_12_GSR_OR_611 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_12_GSR_OR
    );
  U6_trg_cntoutreg_11_GSR_OR_612 : X_OR2
    port map (
      I0 => reset1_1,
      I1 => GSR,
      O => U6_trg_cntoutreg_11_GSR_OR
    );
  set_trgin_1_GSR_OR_613 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => set_trgin_1_GSR_OR
    );
  set_trgin_2_GSR_OR_614 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => set_trgin_2_GSR_OR
    );
  jtag_reg_1_1_GSR_OR_615 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_1_1_GSR_OR
    );
  ena_tm_1_GSR_OR_616 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ena_tm_1_GSR_OR
    );
  jtag_reg_0_1_GSR_OR_617 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_0_1_GSR_OR
    );
  jtag_reg_2_1_GSR_OR_618 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_2_1_GSR_OR
    );
  ron_reg_6_1_GSR_OR_619 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_6_1_GSR_OR
    );
  ron_reg_5_1_GSR_OR_620 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_5_1_GSR_OR
    );
  ron_reg_4_1_GSR_OR_621 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_4_1_GSR_OR
    );
  ron_reg_3_1_GSR_OR_622 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_3_1_GSR_OR
    );
  ron_reg_2_1_GSR_OR_623 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_2_1_GSR_OR
    );
  ron_reg_1_1_GSR_OR_624 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_1_1_GSR_OR
    );
  ron_reg_0_1_GSR_OR_625 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => ron_reg_0_1_GSR_OR
    );
  jtag_reg_6_1_GSR_OR_626 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_6_1_GSR_OR
    );
  jtag_reg_5_1_GSR_OR_627 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_5_1_GSR_OR
    );
  jtag_reg_4_1_GSR_OR_628 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_4_1_GSR_OR
    );
  jtag_reg_3_1_GSR_OR_629 : X_OR2
    port map (
      I0 => reset,
      I1 => GSR,
      O => jtag_reg_3_1_GSR_OR
    );
  U5_pulse_reg0_6_1_GSR_OR_630 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_6_1_GSR_OR
    );
  U5_pulse_reg0_5_1_GSR_OR_631 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_5_1_GSR_OR
    );
  U5_pulse_reg0_4_1_GSR_OR_632 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_4_1_GSR_OR
    );
  U5_pulse_reg0_3_1_GSR_OR_633 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_3_1_GSR_OR
    );
  U5_pulse_reg0_2_1_GSR_OR_634 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_2_1_GSR_OR
    );
  U5_pulse_reg0_1_1_GSR_OR_635 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_1_1_GSR_OR
    );
  U5_pulse_reg0_0_1_GSR_OR_636 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg0_0_1_GSR_OR
    );
  U5_pulse_reg1_6_1_GSR_OR_637 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_6_1_GSR_OR
    );
  U5_pulse_reg1_5_1_GSR_OR_638 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_5_1_GSR_OR
    );
  U5_pulse_reg1_4_1_GSR_OR_639 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_4_1_GSR_OR
    );
  U5_pulse_reg1_3_1_GSR_OR_640 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_3_1_GSR_OR
    );
  U5_pulse_reg1_2_1_GSR_OR_641 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_2_1_GSR_OR
    );
  U5_pulse_reg1_1_1_GSR_OR_642 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_1_1_GSR_OR
    );
  U5_pulse_reg1_0_1_GSR_OR_643 : X_OR2
    port map (
      I0 => reset1_2,
      I1 => GSR,
      O => U5_pulse_reg1_0_1_GSR_OR
    );
  db_0_IOBUF_OBUFT_GTS_AND_644 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_0_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_0_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_0_IOBUF_OBUFT_GTS_AND
    );
  db_1_IOBUF_OBUFT_GTS_AND_645 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_1_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_1_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_1_IOBUF_OBUFT_GTS_AND
    );
  db_2_IOBUF_OBUFT_GTS_AND_646 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_2_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_2_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_2_IOBUF_OBUFT_GTS_AND
    );
  db_3_IOBUF_OBUFT_GTS_AND_647 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_3_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_3_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_3_IOBUF_OBUFT_GTS_AND
    );
  db_4_IOBUF_OBUFT_GTS_AND_648 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_4_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_4_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_4_IOBUF_OBUFT_GTS_AND
    );
  db_5_IOBUF_OBUFT_GTS_AND_649 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_5_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_5_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_5_IOBUF_OBUFT_GTS_AND
    );
  db_6_IOBUF_OBUFT_GTS_AND_650 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_6_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_6_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_6_IOBUF_OBUFT_GTS_AND
    );
  db_7_IOBUF_OBUFT_GTS_AND_651 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_7_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_7_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_7_IOBUF_OBUFT_GTS_AND
    );
  db_8_IOBUF_OBUFT_GTS_AND_652 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_8_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_8_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_8_IOBUF_OBUFT_GTS_AND
    );
  tdio_IOBUF_OBUFT_GTS_AND_653 : X_AND2
    port map (
      I0 => NlwInverterSignal_tdio_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_tdio_IOBUF_OBUFT_GTS_AND_IN1,
      O => tdio_IOBUF_OBUFT_GTS_AND
    );
  db_9_IOBUF_OBUFT_GTS_AND_654 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_9_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_9_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_9_IOBUF_OBUFT_GTS_AND
    );
  db_10_IOBUF_OBUFT_GTS_AND_655 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_10_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_10_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_10_IOBUF_OBUFT_GTS_AND
    );
  db_11_IOBUF_OBUFT_GTS_AND_656 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_11_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_11_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_11_IOBUF_OBUFT_GTS_AND
    );
  db_12_IOBUF_OBUFT_GTS_AND_657 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_12_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_12_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_12_IOBUF_OBUFT_GTS_AND
    );
  db_13_IOBUF_OBUFT_GTS_AND_658 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_13_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_13_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_13_IOBUF_OBUFT_GTS_AND
    );
  db_14_IOBUF_OBUFT_GTS_AND_659 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_14_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_14_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_14_IOBUF_OBUFT_GTS_AND
    );
  db_15_IOBUF_OBUFT_GTS_AND_660 : X_AND2
    port map (
      I0 => NlwInverterSignal_db_15_IOBUF_OBUFT_GTS_AND_IN0,
      I1 => NlwInverterSignal_db_15_IOBUF_OBUFT_GTS_AND_IN1,
      O => db_15_IOBUF_OBUFT_GTS_AND
    );
  delay_1_2_OBUF_GTS_TRI_661 : X_TRI
    port map (
      I => delay_1_2_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_1_2_OBUF_GTS_TRI_CTL,
      O => delay_1(2)
    );
  delay_1_1_OBUF_GTS_TRI_662 : X_TRI
    port map (
      I => delay_1_1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_1_1_OBUF_GTS_TRI_CTL,
      O => delay_1(1)
    );
  delay_1_3_OBUF_GTS_TRI_663 : X_TRI
    port map (
      I => delay_1_3_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_1_3_OBUF_GTS_TRI_CTL,
      O => delay_1(3)
    );
  delay_1_4_OBUF_GTS_TRI_664 : X_TRI
    port map (
      I => delay_1_4_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_1_4_OBUF_GTS_TRI_CTL,
      O => delay_1(4)
    );
  delay_1_5_OBUF_GTS_TRI_665 : X_TRI
    port map (
      I => delay_1_5_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_1_5_OBUF_GTS_TRI_CTL,
      O => delay_1(5)
    );
  delay_1_6_OBUF_GTS_TRI_666 : X_TRI
    port map (
      I => delay_1_6_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_1_6_OBUF_GTS_TRI_CTL,
      O => delay_1(6)
    );
  delay_0_0_OBUF_GTS_TRI_667 : X_TRI
    port map (
      I => delay_0_0_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_0_0_OBUF_GTS_TRI_CTL,
      O => delay_0(0)
    );
  delay_0_1_OBUF_GTS_TRI_668 : X_TRI
    port map (
      I => delay_0_1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_0_1_OBUF_GTS_TRI_CTL,
      O => delay_0(1)
    );
  delay_1_0_OBUF_GTS_TRI_669 : X_TRI
    port map (
      I => delay_1_0_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_1_0_OBUF_GTS_TRI_CTL,
      O => delay_1(0)
    );
  mcevrst_OBUF_GTS_TRI_670 : X_TRI
    port map (
      I => mcevrst_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_mcevrst_OBUF_GTS_TRI_CTL,
      O => mcevrst
    );
  trgttc_OBUF_GTS_TRI_671 : X_TRI
    port map (
      I => trgttc_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_trgttc_OBUF_GTS_TRI_CTL,
      O => trgttc
    );
  trg_dly_p_OBUF_GTS_TRI_672 : X_TRI
    port map (
      I => trg_dly_p_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_trg_dly_p_OBUF_GTS_TRI_CTL,
      O => trg_dly_p
    );
  g245_OBUF_GTS_TRI_673 : X_TRI
    port map (
      I => g245_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_g245_OBUF_GTS_TRI_CTL,
      O => g245
    );
  mctrg_OBUF_GTS_TRI_674 : X_TRI
    port map (
      I => mctrg_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_mctrg_OBUF_GTS_TRI_CTL,
      O => mctrg
    );
  diftrg_OBUF_GTS_TRI_675 : X_TRI
    port map (
      I => diftrg_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_diftrg_OBUF_GTS_TRI_CTL,
      O => diftrg
    );
  dtack_OBUF_GTS_TRI_676 : X_TRI
    port map (
      I => dtack_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_dtack_OBUF_GTS_TRI_CTL,
      O => dtack
    );
  tp1_OBUF_GTS_TRI_677 : X_TRI
    port map (
      I => tp1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_tp1_OBUF_GTS_TRI_CTL,
      O => tp1
    );
  tp2_OBUF_GTS_TRI_678 : X_TRI
    port map (
      I => tp2_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_tp2_OBUF_GTS_TRI_CTL,
      O => tp2
    );
  tp3_OBUF_GTS_TRI_679 : X_TRI
    port map (
      I => tp3_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_tp3_OBUF_GTS_TRI_CTL,
      O => tp3
    );
  jtms_OBUF_GTS_TRI_680 : X_TRI
    port map (
      I => jtms_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtms_OBUF_GTS_TRI_CTL,
      O => jtms
    );
  jtrkrst_OBUF_GTS_TRI_681 : X_TRI
    port map (
      I => jtrkrst_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtrkrst_OBUF_GTS_TRI_CTL,
      O => jtrkrst
    );
  difevr_OBUF_GTS_TRI_682 : X_TRI
    port map (
      I => difevr_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_difevr_OBUF_GTS_TRI_CTL,
      O => difevr
    );
  done_out_OBUF_GTS_TRI_683 : X_TRI
    port map (
      I => done_out_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_done_out_OBUF_GTS_TRI_CTL,
      O => done_out
    );
  trganal_OBUF_GTS_TRI_684 : X_TRI
    port map (
      I => trganal_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_trganal_OBUF_GTS_TRI_CTL,
      O => trganal
    );
  difbcr_OBUF_GTS_TRI_685 : X_TRI
    port map (
      I => difbcr_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_difbcr_OBUF_GTS_TRI_CTL,
      O => difbcr
    );
  jtrktm_OBUF_GTS_TRI_686 : X_TRI
    port map (
      I => jtrktm_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtrktm_OBUF_GTS_TRI_CTL,
      O => jtrktm
    );
  trgled_OBUF_GTS_TRI_687 : X_TRI
    port map (
      I => trgled_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_trgled_OBUF_GTS_TRI_CTL,
      O => trgled
    );
  locked_OBUF_GTS_TRI_688 : X_TRI
    port map (
      I => locked_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_locked_OBUF_GTS_TRI_CTL,
      O => locked
    );
  trgros_OBUF_GTS_TRI_689 : X_TRI
    port map (
      I => trgros_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_trgros_OBUF_GTS_TRI_CTL,
      O => trgros
    );
  jtrkadv_OBUF_GTS_TRI_690 : X_TRI
    port map (
      I => jtrkadv_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtrkadv_OBUF_GTS_TRI_CTL,
      O => jtrkadv
    );
  iackout_OBUF_GTS_TRI_691 : X_TRI
    port map (
      I => iackout_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_iackout_OBUF_GTS_TRI_CTL,
      O => iackout
    );
  jtck_OBUF_GTS_TRI_692 : X_TRI
    port map (
      I => jtck_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtck_OBUF_GTS_TRI_CTL,
      O => jtck
    );
  jtdi_OBUF_GTS_TRI_693 : X_TRI
    port map (
      I => jtdi_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtdi_OBUF_GTS_TRI_CTL,
      O => jtdi
    );
  intled_OBUF_GTS_TRI_694 : X_TRI
    port map (
      I => intled_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_intled_OBUF_GTS_TRI_CTL,
      O => intled
    );
  difrst_OBUF_GTS_TRI_695 : X_TRI
    port map (
      I => difrst_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_difrst_OBUF_GTS_TRI_CTL,
      O => difrst
    );
  mcbcrst_OBUF_GTS_TRI_696 : X_TRI
    port map (
      I => mcbcrst_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_mcbcrst_OBUF_GTS_TRI_CTL,
      O => mcbcrst
    );
  irq_7_OBUF_GTS_TRI_697 : X_TRI
    port map (
      I => irq_7_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_irq_7_OBUF_GTS_TRI_CTL,
      O => irq(7)
    );
  irq_6_OBUF_GTS_TRI_698 : X_TRI
    port map (
      I => irq_6_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_irq_6_OBUF_GTS_TRI_CTL,
      O => irq(6)
    );
  irq_5_OBUF_GTS_TRI_699 : X_TRI
    port map (
      I => irq_5_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_irq_5_OBUF_GTS_TRI_CTL,
      O => irq(5)
    );
  irq_4_OBUF_GTS_TRI_700 : X_TRI
    port map (
      I => irq_4_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_irq_4_OBUF_GTS_TRI_CTL,
      O => irq(4)
    );
  irq_3_OBUF_GTS_TRI_701 : X_TRI
    port map (
      I => irq_3_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_irq_3_OBUF_GTS_TRI_CTL,
      O => irq(3)
    );
  irq_2_OBUF_GTS_TRI_702 : X_TRI
    port map (
      I => irq_2_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_irq_2_OBUF_GTS_TRI_CTL,
      O => irq(2)
    );
  irq_1_OBUF_GTS_TRI_703 : X_TRI
    port map (
      I => irq_1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_irq_1_OBUF_GTS_TRI_CTL,
      O => irq(1)
    );
  ron_6_OBUF_GTS_TRI_704 : X_TRI
    port map (
      I => ron_6_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_ron_6_OBUF_GTS_TRI_CTL,
      O => ron(6)
    );
  ron_5_OBUF_GTS_TRI_705 : X_TRI
    port map (
      I => ron_5_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_ron_5_OBUF_GTS_TRI_CTL,
      O => ron(5)
    );
  ron_4_OBUF_GTS_TRI_706 : X_TRI
    port map (
      I => ron_4_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_ron_4_OBUF_GTS_TRI_CTL,
      O => ron(4)
    );
  ron_3_OBUF_GTS_TRI_707 : X_TRI
    port map (
      I => ron_3_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_ron_3_OBUF_GTS_TRI_CTL,
      O => ron(3)
    );
  ron_2_OBUF_GTS_TRI_708 : X_TRI
    port map (
      I => ron_2_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_ron_2_OBUF_GTS_TRI_CTL,
      O => ron(2)
    );
  ron_1_OBUF_GTS_TRI_709 : X_TRI
    port map (
      I => ron_1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_ron_1_OBUF_GTS_TRI_CTL,
      O => ron(1)
    );
  ron_0_OBUF_GTS_TRI_710 : X_TRI
    port map (
      I => ron_0_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_ron_0_OBUF_GTS_TRI_CTL,
      O => ron(0)
    );
  pulse_1_OBUF_GTS_TRI_711 : X_TRI
    port map (
      I => pulse_1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_pulse_1_OBUF_GTS_TRI_CTL,
      O => pulse(1)
    );
  pulse_0_OBUF_GTS_TRI_712 : X_TRI
    port map (
      I => pulse_0_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_pulse_0_OBUF_GTS_TRI_CTL,
      O => pulse(0)
    );
  jtadd_3_OBUF_GTS_TRI_713 : X_TRI
    port map (
      I => jtadd_3_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtadd_3_OBUF_GTS_TRI_CTL,
      O => jtadd(3)
    );
  jtadd_2_OBUF_GTS_TRI_714 : X_TRI
    port map (
      I => jtadd_2_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtadd_2_OBUF_GTS_TRI_CTL,
      O => jtadd(2)
    );
  jtadd_1_OBUF_GTS_TRI_715 : X_TRI
    port map (
      I => jtadd_1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtadd_1_OBUF_GTS_TRI_CTL,
      O => jtadd(1)
    );
  jtadd_0_OBUF_GTS_TRI_716 : X_TRI
    port map (
      I => jtadd_0_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_jtadd_0_OBUF_GTS_TRI_CTL,
      O => jtadd(0)
    );
  delay_0_6_OBUF_GTS_TRI_717 : X_TRI
    port map (
      I => delay_0_6_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_0_6_OBUF_GTS_TRI_CTL,
      O => delay_0(6)
    );
  delay_0_5_OBUF_GTS_TRI_718 : X_TRI
    port map (
      I => delay_0_5_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_0_5_OBUF_GTS_TRI_CTL,
      O => delay_0(5)
    );
  delay_0_4_OBUF_GTS_TRI_719 : X_TRI
    port map (
      I => delay_0_4_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_0_4_OBUF_GTS_TRI_CTL,
      O => delay_0(4)
    );
  delay_0_3_OBUF_GTS_TRI_720 : X_TRI
    port map (
      I => delay_0_3_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_0_3_OBUF_GTS_TRI_CTL,
      O => delay_0(3)
    );
  delay_0_2_OBUF_GTS_TRI_721 : X_TRI
    port map (
      I => delay_0_2_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_delay_0_2_OBUF_GTS_TRI_CTL,
      O => delay_0(2)
    );
  U8_GSR_BUF : X_BUF
    port map (
      I => not_sysreset,
      O => GSR
    );
  NlwInverterBlock_I95_0_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_0_T
    );
  NlwBlock_ctrl_x_GND : X_ZERO
    port map (
      O => GND
    );
  NlwInverterBlock_I69_0_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_0_T
    );
  NlwInverterBlock_I70_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I70_0_T
    );
  NlwInverterBlock_I88_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I88_0_T
    );
  NlwInverterBlock_I94_0_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_0_T
    );
  NlwInverterBlock_I87_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I87_0_T
    );
  NlwInverterBlock_I86_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I86_0_T
    );
  NlwInverterBlock_I85_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I85_0_T
    );
  NlwInverterBlock_I93_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I93_0_T
    );
  NlwInverterBlock_I84_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I84_0_T
    );
  NlwInverterBlock_I83_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I83_0_T
    );
  NlwInverterBlock_I82_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I82_0_T
    );
  NlwInverterBlock_I92_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I92_0_T
    );
  NlwInverterBlock_I91_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I91_0_T
    );
  NlwInverterBlock_I90_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I90_0_T
    );
  NlwInverterBlock_I81_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I81_0_T
    );
  NlwInverterBlock_I80_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I80_0_T
    );
  NlwInverterBlock_I79_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I79_0_T
    );
  NlwInverterBlock_I78_0_T : X_INV
    port map (
      I => etr_ivec(1),
      O => NlwInverterSignal_I78_0_T
    );
  NlwInverterBlock_I89_0_T : X_INV
    port map (
      I => etr_ivec(2),
      O => NlwInverterSignal_I89_0_T
    );
  NlwInverterBlock_I77_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I77_0_T
    );
  NlwInverterBlock_I76_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I76_0_T
    );
  NlwInverterBlock_I75_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I75_0_T
    );
  NlwInverterBlock_I74_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I74_0_T
    );
  NlwInverterBlock_I73_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I73_0_T
    );
  NlwInverterBlock_I72_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I72_0_T
    );
  NlwInverterBlock_I71_0_T : X_INV
    port map (
      I => etr_ivec(0),
      O => NlwInverterSignal_I71_0_T
    );
  NlwInverterBlock_add_int_1_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_add_int_1_C
    );
  NlwBlock_ctrl_x_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwInverterBlock_add_int_0_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_add_int_0_C
    );
  NlwInverterBlock_grp_4_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_grp_4_C
    );
  NlwInverterBlock_grp_3_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_grp_3_C
    );
  NlwInverterBlock_grp_2_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_grp_2_C
    );
  NlwInverterBlock_grp_1_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_grp_1_C
    );
  NlwInverterBlock_add_int_2_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_add_int_2_C
    );
  NlwInverterBlock_I51_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I51_0_T
    );
  NlwInverterBlock_I52_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I52_0_T
    );
  NlwInverterBlock_I53_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I53_0_T
    );
  NlwInverterBlock_I54_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I54_0_T
    );
  NlwInverterBlock_I55_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I55_0_T
    );
  NlwInverterBlock_I56_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I56_0_T
    );
  NlwInverterBlock_I57_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I57_0_T
    );
  NlwInverterBlock_I58_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I58_0_T
    );
  NlwInverterBlock_I59_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I59_0_T
    );
  NlwInverterBlock_I60_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I60_0_T
    );
  NlwInverterBlock_I61_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I61_0_T
    );
  NlwInverterBlock_I62_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I62_0_T
    );
  NlwInverterBlock_I63_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I63_0_T
    );
  NlwInverterBlock_I64_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I64_0_T
    );
  NlwInverterBlock_I65_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I65_0_T
    );
  NlwInverterBlock_I66_0_T : X_INV
    port map (
      I => I66_N1191,
      O => NlwInverterSignal_I66_0_T
    );
  NlwInverterBlock_I67_0_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_0_T
    );
  NlwInverterBlock_I68_0_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_0_T
    );
  NlwInverterBlock_I95_15_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_15_T
    );
  NlwInverterBlock_I95_14_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_14_T
    );
  NlwInverterBlock_I95_13_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_13_T
    );
  NlwInverterBlock_I95_12_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_12_T
    );
  NlwInverterBlock_I95_11_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_11_T
    );
  NlwInverterBlock_I95_10_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_10_T
    );
  NlwInverterBlock_I95_9_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_9_T
    );
  NlwInverterBlock_I95_8_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_8_T
    );
  NlwInverterBlock_I95_7_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_7_T
    );
  NlwInverterBlock_I95_6_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_6_T
    );
  NlwInverterBlock_I95_5_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_5_T
    );
  NlwInverterBlock_I95_4_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_4_T
    );
  NlwInverterBlock_I95_3_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_3_T
    );
  NlwInverterBlock_I95_2_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_2_T
    );
  NlwInverterBlock_I95_1_T : X_INV
    port map (
      I => I95_N1141,
      O => NlwInverterSignal_I95_1_T
    );
  NlwInverterBlock_I94_15_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_15_T
    );
  NlwInverterBlock_I94_14_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_14_T
    );
  NlwInverterBlock_I94_13_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_13_T
    );
  NlwInverterBlock_I94_12_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_12_T
    );
  NlwInverterBlock_I94_11_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_11_T
    );
  NlwInverterBlock_I94_10_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_10_T
    );
  NlwInverterBlock_I94_9_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_9_T
    );
  NlwInverterBlock_I94_8_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_8_T
    );
  NlwInverterBlock_I94_7_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_7_T
    );
  NlwInverterBlock_I94_6_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_6_T
    );
  NlwInverterBlock_I94_5_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_5_T
    );
  NlwInverterBlock_I94_4_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_4_T
    );
  NlwInverterBlock_I94_3_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_3_T
    );
  NlwInverterBlock_I94_2_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_2_T
    );
  NlwInverterBlock_I94_1_T : X_INV
    port map (
      I => I94_N1141,
      O => NlwInverterSignal_I94_1_T
    );
  NlwInverterBlock_I69_15_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_15_T
    );
  NlwInverterBlock_I69_14_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_14_T
    );
  NlwInverterBlock_I69_13_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_13_T
    );
  NlwInverterBlock_I69_12_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_12_T
    );
  NlwInverterBlock_I69_11_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_11_T
    );
  NlwInverterBlock_I69_10_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_10_T
    );
  NlwInverterBlock_I69_9_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_9_T
    );
  NlwInverterBlock_I69_8_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_8_T
    );
  NlwInverterBlock_I69_7_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_7_T
    );
  NlwInverterBlock_I69_6_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_6_T
    );
  NlwInverterBlock_I69_5_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_5_T
    );
  NlwInverterBlock_I69_4_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_4_T
    );
  NlwInverterBlock_I69_3_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_3_T
    );
  NlwInverterBlock_I69_2_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_2_T
    );
  NlwInverterBlock_I69_1_T : X_INV
    port map (
      I => I69_N1141,
      O => NlwInverterSignal_I69_1_T
    );
  NlwInverterBlock_I68_15_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_15_T
    );
  NlwInverterBlock_I68_14_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_14_T
    );
  NlwInverterBlock_I68_13_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_13_T
    );
  NlwInverterBlock_I68_12_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_12_T
    );
  NlwInverterBlock_I68_11_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_11_T
    );
  NlwInverterBlock_I68_10_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_10_T
    );
  NlwInverterBlock_I68_9_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_9_T
    );
  NlwInverterBlock_I68_8_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_8_T
    );
  NlwInverterBlock_I68_7_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_7_T
    );
  NlwInverterBlock_I68_6_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_6_T
    );
  NlwInverterBlock_I68_5_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_5_T
    );
  NlwInverterBlock_I68_4_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_4_T
    );
  NlwInverterBlock_I68_3_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_3_T
    );
  NlwInverterBlock_I68_2_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_2_T
    );
  NlwInverterBlock_I68_1_T : X_INV
    port map (
      I => I68_N1141,
      O => NlwInverterSignal_I68_1_T
    );
  NlwInverterBlock_I67_15_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_15_T
    );
  NlwInverterBlock_I67_14_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_14_T
    );
  NlwInverterBlock_I67_13_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_13_T
    );
  NlwInverterBlock_I67_12_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_12_T
    );
  NlwInverterBlock_I67_11_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_11_T
    );
  NlwInverterBlock_I67_10_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_10_T
    );
  NlwInverterBlock_I67_9_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_9_T
    );
  NlwInverterBlock_I67_8_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_8_T
    );
  NlwInverterBlock_I67_7_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_7_T
    );
  NlwInverterBlock_I67_6_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_6_T
    );
  NlwInverterBlock_I67_5_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_5_T
    );
  NlwInverterBlock_I67_4_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_4_T
    );
  NlwInverterBlock_I67_3_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_3_T
    );
  NlwInverterBlock_I67_2_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_2_T
    );
  NlwInverterBlock_I67_1_T : X_INV
    port map (
      I => I67_N1141,
      O => NlwInverterSignal_I67_1_T
    );
  NlwInverterBlock_U7_I12_1_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_1_T
    );
  NlwInverterBlock_U7_I12_2_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_2_T
    );
  NlwInverterBlock_U7_I12_3_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_3_T
    );
  NlwInverterBlock_U7_I12_4_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_4_T
    );
  NlwInverterBlock_U7_I12_5_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_5_T
    );
  NlwInverterBlock_U7_I12_6_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_6_T
    );
  NlwInverterBlock_U7_I12_7_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_7_T
    );
  NlwInverterBlock_grp_0_C : X_INV
    port map (
      I => ds0_clk,
      O => NlwInverterSignal_grp_0_C
    );
  NlwInverterBlock_U7_I12_0_T : X_INV
    port map (
      I => U7_I12_N1423,
      O => NlwInverterSignal_U7_I12_0_T
    );
  NlwInverterBlock_U7_I11_0_T : X_INV
    port map (
      I => U7_I11_N1191,
      O => NlwInverterSignal_U7_I11_0_T
    );
  NlwInverterBlock_U7_I10_0_T : X_INV
    port map (
      I => U7_I10_N1191,
      O => NlwInverterSignal_U7_I10_0_T
    );
  NlwInverterBlock_U5_I11_0_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_0_T
    );
  NlwInverterBlock_U5_I10_0_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_0_T
    );
  NlwInverterBlock_U5_I11_15_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_15_T
    );
  NlwInverterBlock_U5_I11_14_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_14_T
    );
  NlwInverterBlock_U5_I11_13_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_13_T
    );
  NlwInverterBlock_U5_I11_12_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_12_T
    );
  NlwInverterBlock_U5_I11_11_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_11_T
    );
  NlwInverterBlock_U5_I11_10_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_10_T
    );
  NlwInverterBlock_U5_I11_9_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_9_T
    );
  NlwInverterBlock_U5_I11_8_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_8_T
    );
  NlwInverterBlock_U5_I11_7_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_7_T
    );
  NlwInverterBlock_U5_I11_6_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_6_T
    );
  NlwInverterBlock_U5_I11_5_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_5_T
    );
  NlwInverterBlock_U5_I11_4_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_4_T
    );
  NlwInverterBlock_U5_I11_3_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_3_T
    );
  NlwInverterBlock_U5_I11_2_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_2_T
    );
  NlwInverterBlock_U5_I11_1_T : X_INV
    port map (
      I => U5_I11_N1141,
      O => NlwInverterSignal_U5_I11_1_T
    );
  NlwInverterBlock_U5_I10_15_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_15_T
    );
  NlwInverterBlock_U5_I10_14_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_14_T
    );
  NlwInverterBlock_U5_I10_13_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_13_T
    );
  NlwInverterBlock_U5_I10_12_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_12_T
    );
  NlwInverterBlock_U5_I10_11_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_11_T
    );
  NlwInverterBlock_U5_I10_10_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_10_T
    );
  NlwInverterBlock_U5_I10_9_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_9_T
    );
  NlwInverterBlock_U5_I10_8_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_8_T
    );
  NlwInverterBlock_U5_I10_7_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_7_T
    );
  NlwInverterBlock_U5_I10_6_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_6_T
    );
  NlwInverterBlock_U5_I10_5_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_5_T
    );
  NlwInverterBlock_U5_I10_4_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_4_T
    );
  NlwInverterBlock_U5_I10_3_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_3_T
    );
  NlwInverterBlock_U5_I10_2_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_2_T
    );
  NlwInverterBlock_U5_I10_1_T : X_INV
    port map (
      I => U5_I10_N1141,
      O => NlwInverterSignal_U5_I10_1_T
    );
  NlwInverterBlock_U6_I73_2_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_2_T
    );
  NlwInverterBlock_U6_I73_3_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_3_T
    );
  NlwInverterBlock_U6_I73_4_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_4_T
    );
  NlwInverterBlock_U6_I73_5_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_5_T
    );
  NlwInverterBlock_U6_I73_6_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_6_T
    );
  NlwInverterBlock_U6_I73_8_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_8_T
    );
  NlwInverterBlock_U6_I73_7_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_7_T
    );
  NlwInverterBlock_U6_I73_1_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_1_T
    );
  NlwInverterBlock_U6_I78_0_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_0_T
    );
  NlwInverterBlock_U6_I77_0_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_0_T
    );
  NlwInverterBlock_U6_I76_0_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_0_T
    );
  NlwInverterBlock_U6_I75_0_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_0_T
    );
  NlwInverterBlock_U6_I74_0_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_0_T
    );
  NlwInverterBlock_U6_I73_0_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_0_T
    );
  NlwInverterBlock_U6_S2_I1_5_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_5_T
    );
  NlwInverterBlock_U6_I78_15_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_15_T
    );
  NlwInverterBlock_U6_I78_14_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_14_T
    );
  NlwInverterBlock_U6_I78_13_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_13_T
    );
  NlwInverterBlock_U6_I78_12_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_12_T
    );
  NlwInverterBlock_U6_I78_11_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_11_T
    );
  NlwInverterBlock_U6_I78_10_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_10_T
    );
  NlwInverterBlock_U6_I78_9_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_9_T
    );
  NlwInverterBlock_U6_I78_8_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_8_T
    );
  NlwInverterBlock_U6_I78_7_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_7_T
    );
  NlwInverterBlock_U6_I78_6_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_6_T
    );
  NlwInverterBlock_U6_I78_5_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_5_T
    );
  NlwInverterBlock_U6_I78_4_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_4_T
    );
  NlwInverterBlock_U6_I78_3_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_3_T
    );
  NlwInverterBlock_U6_I78_2_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_2_T
    );
  NlwInverterBlock_U6_I78_1_T : X_INV
    port map (
      I => U6_I78_N1141,
      O => NlwInverterSignal_U6_I78_1_T
    );
  NlwInverterBlock_U6_I77_15_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_15_T
    );
  NlwInverterBlock_U6_I77_14_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_14_T
    );
  NlwInverterBlock_U6_I77_13_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_13_T
    );
  NlwInverterBlock_U6_I77_12_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_12_T
    );
  NlwInverterBlock_U6_I77_11_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_11_T
    );
  NlwInverterBlock_U6_I77_10_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_10_T
    );
  NlwInverterBlock_U6_I77_9_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_9_T
    );
  NlwInverterBlock_U6_I77_8_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_8_T
    );
  NlwInverterBlock_U6_I77_7_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_7_T
    );
  NlwInverterBlock_U6_I77_6_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_6_T
    );
  NlwInverterBlock_U6_I77_5_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_5_T
    );
  NlwInverterBlock_U6_I77_4_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_4_T
    );
  NlwInverterBlock_U6_I77_3_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_3_T
    );
  NlwInverterBlock_U6_I77_2_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_2_T
    );
  NlwInverterBlock_U6_I77_1_T : X_INV
    port map (
      I => U6_I77_N1141,
      O => NlwInverterSignal_U6_I77_1_T
    );
  NlwInverterBlock_U6_I76_15_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_15_T
    );
  NlwInverterBlock_U6_I76_14_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_14_T
    );
  NlwInverterBlock_U6_I76_13_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_13_T
    );
  NlwInverterBlock_U6_I76_12_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_12_T
    );
  NlwInverterBlock_U6_I76_11_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_11_T
    );
  NlwInverterBlock_U6_I76_10_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_10_T
    );
  NlwInverterBlock_U6_I76_9_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_9_T
    );
  NlwInverterBlock_U6_I76_8_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_8_T
    );
  NlwInverterBlock_U6_I76_7_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_7_T
    );
  NlwInverterBlock_U6_I76_6_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_6_T
    );
  NlwInverterBlock_U6_I76_5_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_5_T
    );
  NlwInverterBlock_U6_I76_4_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_4_T
    );
  NlwInverterBlock_U6_I76_3_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_3_T
    );
  NlwInverterBlock_U6_I76_2_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_2_T
    );
  NlwInverterBlock_U6_I76_1_T : X_INV
    port map (
      I => U6_I76_N1141,
      O => NlwInverterSignal_U6_I76_1_T
    );
  NlwInverterBlock_U6_I75_15_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_15_T
    );
  NlwInverterBlock_U6_I75_14_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_14_T
    );
  NlwInverterBlock_U6_I75_13_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_13_T
    );
  NlwInverterBlock_U6_I75_12_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_12_T
    );
  NlwInverterBlock_U6_I75_11_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_11_T
    );
  NlwInverterBlock_U6_I75_10_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_10_T
    );
  NlwInverterBlock_U6_I75_9_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_9_T
    );
  NlwInverterBlock_U6_I75_8_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_8_T
    );
  NlwInverterBlock_U6_I75_7_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_7_T
    );
  NlwInverterBlock_U6_I75_6_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_6_T
    );
  NlwInverterBlock_U6_I75_5_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_5_T
    );
  NlwInverterBlock_U6_I75_4_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_4_T
    );
  NlwInverterBlock_U6_I75_3_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_3_T
    );
  NlwInverterBlock_U6_I75_2_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_2_T
    );
  NlwInverterBlock_U6_I75_1_T : X_INV
    port map (
      I => U6_I75_N1141,
      O => NlwInverterSignal_U6_I75_1_T
    );
  NlwInverterBlock_U6_I74_15_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_15_T
    );
  NlwInverterBlock_U6_I74_14_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_14_T
    );
  NlwInverterBlock_U6_I74_13_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_13_T
    );
  NlwInverterBlock_U6_I74_12_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_12_T
    );
  NlwInverterBlock_U6_I74_11_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_11_T
    );
  NlwInverterBlock_U6_I74_10_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_10_T
    );
  NlwInverterBlock_U6_I74_9_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_9_T
    );
  NlwInverterBlock_U6_I74_8_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_8_T
    );
  NlwInverterBlock_U6_I74_7_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_7_T
    );
  NlwInverterBlock_U6_I74_6_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_6_T
    );
  NlwInverterBlock_U6_I74_5_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_5_T
    );
  NlwInverterBlock_U6_I74_4_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_4_T
    );
  NlwInverterBlock_U6_I74_3_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_3_T
    );
  NlwInverterBlock_U6_I74_2_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_2_T
    );
  NlwInverterBlock_U6_I74_1_T : X_INV
    port map (
      I => U6_I74_N1141,
      O => NlwInverterSignal_U6_I74_1_T
    );
  NlwInverterBlock_U6_I73_15_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_15_T
    );
  NlwInverterBlock_U6_I73_14_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_14_T
    );
  NlwInverterBlock_U6_I73_13_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_13_T
    );
  NlwInverterBlock_U6_I73_12_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_12_T
    );
  NlwInverterBlock_U6_I73_11_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_11_T
    );
  NlwInverterBlock_U6_I73_10_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_10_T
    );
  NlwInverterBlock_U6_I73_9_T : X_INV
    port map (
      I => U6_I73_N1141,
      O => NlwInverterSignal_U6_I73_9_T
    );
  NlwInverterBlock_U6_S2_I1_1_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_1_T
    );
  NlwInverterBlock_U6_S2_I1_4_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_4_T
    );
  NlwInverterBlock_U6_S2_I1_2_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_2_T
    );
  NlwInverterBlock_U6_S2_I1_3_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_3_T
    );
  NlwInverterBlock_U6_S2_I1_0_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_0_T
    );
  NlwInverterBlock_U6_S2_I1_15_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_15_T
    );
  NlwInverterBlock_U6_S2_I1_14_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_14_T
    );
  NlwInverterBlock_U6_S2_I1_13_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_13_T
    );
  NlwInverterBlock_U6_S2_I1_12_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_12_T
    );
  NlwInverterBlock_U6_S2_I1_11_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_11_T
    );
  NlwInverterBlock_U6_S2_I1_10_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_10_T
    );
  NlwInverterBlock_U6_S2_I1_9_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_9_T
    );
  NlwInverterBlock_U6_S2_I1_8_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_8_T
    );
  NlwInverterBlock_U6_S2_I1_7_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_7_T
    );
  NlwInverterBlock_U6_S2_I1_6_T : X_INV
    port map (
      I => U6_S2_I1_N1141,
      O => NlwInverterSignal_U6_S2_I1_6_T
    );
  NlwInverterBlock_db_0_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_0_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_0_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_0_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_1_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_1_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_1_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_1_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_2_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_2_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_2_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_2_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_3_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_3_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_3_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_3_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_4_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_4_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_4_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_4_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_5_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_5_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_5_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_5_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_6_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_6_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_6_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_6_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_7_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => I50_N1191,
      O => NlwInverterSignal_db_7_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_7_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_7_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_8_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_8_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_8_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_8_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_tdio_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => U7_I9_N1191,
      O => NlwInverterSignal_tdio_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_tdio_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tdio_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_9_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_9_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_9_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_9_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_10_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_10_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_10_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_10_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_11_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_11_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_11_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_11_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_12_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_12_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_12_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_12_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_13_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_13_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_13_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_13_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_14_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_14_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_14_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_14_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_db_15_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
    port map (
      I => tp1_OBUF,
      O => NlwInverterSignal_db_15_IOBUF_OBUFT_GTS_AND_IN0
    );
  NlwInverterBlock_db_15_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_db_15_IOBUF_OBUFT_GTS_AND_IN1
    );
  NlwInverterBlock_delay_1_2_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_1_2_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_1_1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_1_1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_1_3_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_1_3_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_1_4_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_1_4_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_1_5_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_1_5_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_1_6_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_1_6_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_0_0_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_0_0_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_0_1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_0_1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_1_0_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_1_0_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_mcevrst_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_mcevrst_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_trgttc_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_trgttc_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_trg_dly_p_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_trg_dly_p_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_g245_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_g245_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_mctrg_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_mctrg_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_diftrg_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_diftrg_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_dtack_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dtack_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_tp1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tp1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_tp2_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tp2_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_tp3_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_tp3_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtms_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtms_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtrkrst_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtrkrst_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_difevr_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_difevr_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_done_out_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_done_out_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_trganal_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_trganal_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_difbcr_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_difbcr_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtrktm_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtrktm_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_trgled_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_trgled_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_locked_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_locked_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_trgros_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_trgros_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtrkadv_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtrkadv_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_iackout_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_iackout_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtck_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtck_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtdi_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtdi_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_intled_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_intled_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_difrst_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_difrst_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_mcbcrst_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_mcbcrst_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_irq_7_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_irq_7_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_irq_6_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_irq_6_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_irq_5_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_irq_5_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_irq_4_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_irq_4_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_irq_3_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_irq_3_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_irq_2_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_irq_2_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_irq_1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_irq_1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_ron_6_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_ron_6_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_ron_5_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_ron_5_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_ron_4_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_ron_4_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_ron_3_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_ron_3_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_ron_2_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_ron_2_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_ron_1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_ron_1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_ron_0_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_ron_0_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_pulse_1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_pulse_1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_pulse_0_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_pulse_0_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtadd_3_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtadd_3_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtadd_2_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtadd_2_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtadd_1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtadd_1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_jtadd_0_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_jtadd_0_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_0_6_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_0_6_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_0_5_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_0_5_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_0_4_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_0_4_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_0_3_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_0_3_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_delay_0_2_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_delay_0_2_OBUF_GTS_TRI_CTL
    );
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

