# Xilinx CORE Generator 6.3i
SELECT RAM-based_Shift_Register Spartan2 Xilinx,_Inc. 7.0
CSET data_width = 16
CSET default_data = 0
CSET register_final_bit = false
CSET default_data_radix = 16
CSET depth = 8
CSET asynchronous_init_value = 0
CSET clock_enable = false
CSET create_rpm = true
CSET shift_type = Fixed_Length
CSET synchronous_init_value = 0
CSET component_name = shft16x8
GENERATE
