Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D122TC4J::  Wed Aug 15 10:24:16 2012


C:/Xilinx6/bin/nt/par.exe -w -intstyle ise -ol std -t 1 ctrl_x_map.ncd
ctrl_x.ncd ctrl_x.pcf 


Constraints file: ctrl_x.pcf

Loading device database for application Par from file "ctrl_x_map.ncd".
   "ctrl_x" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx6.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolved that IOB <trgled> must be placed at site P4.
Resolved that IOB <trgnim> must be placed at site P87.
Resolved that IOB <pulse<0>> must be placed at site P43.
Resolved that IOB <pulse<1>> must be placed at site P193.
Resolved that IOB <trgros> must be placed at site P205.
Resolved that IOB <trgttc> must be placed at site P5.
Resolved that IOB <trgttl> must be placed at site P95.
Resolved that IOB <done_in> must be placed at site P102.
Resolved that IOB <trganal> must be placed at site P88.
Resolved that IOB <robrsttl> must be placed at site P164.
Resolved that IOB <g245> must be placed at site P71.
Resolved that IOB <plsttl<0>> must be placed at site P22.
Resolved that IOB <plsttl<1>> must be placed at site P191.
Resolved that IOB <mcbcrst> must be placed at site P3.
Resolved that IOB <dtack> must be placed at site P181.
Resolved that IOB <sysreset> must be placed at site P206.
Resolved that IOB <mctrg> must be placed at site P204.
Resolved that IOB <as> must be placed at site P188.
Resolved that IOB <delay_0<0>> must be placed at site P23.
Resolved that IOB <difbcr> must be placed at site P166.
Resolved that IOB <delay_0<1>> must be placed at site P27.
Resolved that IOB <delay_0<2>> must be placed at site P37.
Resolved that IOB <delay_0<3>> must be placed at site P33.
Resolved that IOB <delay_0<4>> must be placed at site P30.
Resolved that IOB <delay_1<0>> must be placed at site P121.
Resolved that IOB <delay_0<5>> must be placed at site P31.
Resolved that IOB <int_ext<0>> must be placed at site P189.
Resolved that IOB <delay_1<1>> must be placed at site P200.
Resolved that IOB <delay_0<6>> must be placed at site P60.
Resolved that IOB <int_ext<1>> must be placed at site P187.
Resolved that IOB <delay_1<2>> must be placed at site P86.
Resolved that IOB <delay_1<3>> must be placed at site P96.
Resolved that IOB <done_out> must be placed at site P101.
Resolved that IOB <delay_1<4>> must be placed at site P112.
Resolved that IOB <delay_1<5>> must be placed at site P90.
Resolved that IOB <delay_1<6>> must be placed at site P89.
Resolved that IOB <mcevrst> must be placed at site P49.
Resolved that IOB <difevr> must be placed at site P48.
Resolved that IOB <iackin> must be placed at site P74.
Resolved that IOB <lword> must be placed at site P68.
Resolved that IOB <irq<1>> must be placed at site P176.
Resolved that IOB <irq<2>> must be placed at site P175.
Resolved that IOB <diftrg> must be placed at site P199.
Resolved that IOB <irq<3>> must be placed at site P173.
Resolved that IOB <irq<4>> must be placed at site P174.
Resolved that IOB <irq<5>> must be placed at site P167.
Resolved that IOB <irq<6>> must be placed at site P172.
Resolved that IOB <difrst> must be placed at site P136.
Resolved that IOB <irq<7>> must be placed at site P147.
Resolved that IOB <iack> must be placed at site P179.
Resolved that IOB <write> must be placed at site P58.
Resolved that IOB <db<10>> must be placed at site P141.
Resolved that IOB <db<11>> must be placed at site P8.
Resolved that IOB <db<12>> must be placed at site P14.
Resolved that IOB <db<13>> must be placed at site P17.
Resolved that IOB <db<14>> must be placed at site P10.
Resolved that IOB <db<15>> must be placed at site P9.
Resolved that IOB <fltb> must be placed at site P127.
Resolved that IOB <add_in<0>> must be placed at site P94.
Resolved that IOB <add_in<1>> must be placed at site P84.
Resolved that IOB <add_in<2>> must be placed at site P195.
Resolved that IOB <add_in<3>> must be placed at site P203.
Resolved that IOB <add_in<4>> must be placed at site P201.
Resolved that IOB <add_in<5>> must be placed at site P16.
Resolved that IOB <add_in<6>> must be placed at site P194.
Resolved that IOB <jtdi> must be placed at site P61.
Resolved that IOB <jtck> must be placed at site P69.
Resolved that IOB <jtdo> must be placed at site P75.
Resolved that IOB <jroberr> must be placed at site P114.
Resolved that IOB <jtms> must be placed at site P29.
Resolved that IOB <tdio> must be placed at site P202.
Resolved that IOB <ron<0>> must be placed at site P113.
Resolved that IOB <ron<1>> must be placed at site P70.
Resolved that IOB <ron<2>> must be placed at site P120.
Resolved that IOB <ron<3>> must be placed at site P123.
Resolved that IOB <am0> must be placed at site P42.
Resolved that IOB <am1> must be placed at site P57.
Resolved that IOB <ron<4>> must be placed at site P133.
Resolved that IOB <am3> must be placed at site P67.
Resolved that IOB <ron<5>> must be placed at site P134.
Resolved that IOB <am4> must be placed at site P36.
Resolved that IOB <am5> must be placed at site P62.
Resolved that IOB <jtadd<0>> must be placed at site P34.
Resolved that IOB <ron<6>> must be placed at site P82.
Resolved that IOB <jtadd<1>> must be placed at site P35.
Resolved that IOB <jtadd<2>> must be placed at site P20.
Resolved that IOB <jtadd<3>> must be placed at site P63.
Resolved that IOB <trg_dly_p> must be placed at site P192.
Resolved that IOB <evrsttl> must be placed at site P111.
Resolved that IOB <ds0> must be placed at site P83.
Resolved that IOB <ds1> must be placed at site P73.
Resolved that IOB <veto> must be placed at site P138.
Resolved that IOB <locked> must be placed at site P81.
Resolved that IOB <intled> must be placed at site P180.
Resolved that IOB <tp1> must be placed at site P7.
Resolved that IOB <tp2> must be placed at site P151.
Resolved that IOB <tp3> must be placed at site P163.
Resolved that IOB <db<0>> must be placed at site P41.
Resolved that IOB <jtrkadv> must be placed at site P139.
Resolved that IOB <db<1>> must be placed at site P21.
Resolved that IOB <db<2>> must be placed at site P47.
Resolved that IOB <db<3>> must be placed at site P46.
Resolved that IOB <db<4>> must be placed at site P44.
Resolved that IOB <db<5>> must be placed at site P45.
Resolved that IOB <db<6>> must be placed at site P18.
Resolved that IOB <db<7>> must be placed at site P15.
Resolved that IOB <db<8>> must be placed at site P148.
Resolved that IOB <db<9>> must be placed at site P140.
Resolved that IOB <jtrkrst> must be placed at site P125.
Resolved that IOB <jtrktm> must be placed at site P122.
Resolved that IOB <bcrsttl> must be placed at site P6.
Resolved that IOB <brd_sel> must be placed at site P59.
Resolved that IOB <iackout> must be placed at site P178.
Resolved that GCLKIOB <clkin_p> must be placed at site P77.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           113 out of 140    80%
      Number of LOCed External IOBs  113 out of 113   100%

   Number of SLICEs                  299 out of 768    38%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     2 out of 4      50%
   Number of STARTUPs                  1 out of 1     100%
   Number of TBUFs                   274 out of 832    32%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98c176) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.......
....
.....
Phase 5.8 (Checksum:a30af6) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file ctrl_x.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 2938 unrouted;       REAL time: 0 secs 

Phase 2: 2288 unrouted;       REAL time: 2 secs 

Phase 3: 499 unrouted;       REAL time: 2 secs 

Phase 4: 499 unrouted; (0)      REAL time: 2 secs 

Phase 5: 499 unrouted; (0)      REAL time: 2 secs 

Phase 6: 499 unrouted; (0)      REAL time: 2 secs 

Phase 7: 0 unrouted; (0)      REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|               CLK          |  Global  |  230   |  0.122     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|        U7_ck_slow          |  Global  |   35   |  0.092     |  0.465      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 228


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.502
   The MAXIMUM PIN DELAY IS:                               5.439
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.880

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
         887        1088         587          92          26           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "CLKIN" PERIOD =  20 nS   HIGH 50.000 | N/A        | N/A        | N/A  
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  PERIOD analysis for net "CLK0" derived fr | 20.000ns   | 13.095ns   | 4    
  om  NET "CLKIN" PERIOD =  20 nS   HIGH 50 |            |            |      
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  60 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file ctrl_x.ncd.


PAR done.
