library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mono is
generic(time: integer:= 40; tim_bits: integer:=6);	--tim_bits = (log(time)/log(2)) +1
port(
clk, enable: in std_logic;
end_count: out std_logic
);
end mono;

architecture arch of mono is
signal count: std_logic_vector(tim_bits downto 0);
signal time_out: std_logic;
begin

--end_count <= time_out;

process(clk, enable)
begin

	if enable='0' then
	  count <= conv_std_logic_vector(time-1, tim_bits+1);
	elsif (clk'event and clk='1') then
	  if count(count'high)='0' then
	    count <= count - 1;
	  end if;
	end if;
end process;

process (clk)
begin
	if clk'event and clk='1' then
	  end_count <= count(count'high);
	end if;
end process;

end arch;
