-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- synopsys translate_off
configuration cfg_shift of shift is	
	for all : shft16x8 use entity XilinxCoreLib.C_SHIFT_RAM_V1_0(behavioral)
		generic map(
			c_sinit_val => "0000000000000000",
			c_sync_enable => 0,
			c_has_ainit => 0,
			c_sync_priority => 0,
			c_reg_last_bit => 0,
			c_has_sinit => 0,
			c_shift_type => 0,
			c_ainit_val => "0000000000000000",
			c_has_sset => 0,
			c_width => 16,
			c_addr_width => 3,
			c_has_aset => 0,
			c_has_a => 0,
			c_has_sclr => 0,
			c_depth => 8,
			c_has_ce => 0,
			c_has_aclr => 0,
			c_enable_rlocs => 1);
	end for;

 end cfg_shift;
-- synopsys translate_on

entity shift is port (
	clk, trigger: in std_logic;
	trg_shift: out std_logic_vector(15 downto 0)
	);
end shift ;


architecture arch of shift is
signal trsh_in, trsh_out: std_logic_vector(15 downto 0);

component shft16x8
	port (
	CLK: IN std_logic;
	D: IN std_logic_VECTOR(15 downto 0);
	Q: OUT std_logic_VECTOR(15 downto 0));
end component;


begin

trg_shift <= trsh_out;
trsh_in <= trsh_out(14 downto 0) & trigger;

F0: shft16x8 port map (
	CLK=>clk, --: IN std_logic;
	D=> trsh_in,--: IN std_logic_VECTOR(15 downto 0);
	Q=> trsh_out); --: OUT std_logic_VECTOR(15 downto 0));

           
end arch;

	
