library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--tim_bits = (log(time)/log(2)) +1

entity owwrite is
          generic (time_10: integer:=10;  tim_bits_10: integer:=4;
                   time_60: integer:=60;  tim_bits_60: integer:=6);
	  port (
	  clk, ck_slow, start, w_reg: in std_logic;
	  write: out std_logic);
end owwrite ;

architecture arch of owwrite is

signal w0, w0_reset: std_logic;
signal w1, w1_reset: std_logic;

component mono  
	generic(time, tim_bits: integer);
	port (clk, enable: in std_logic;
	end_count: out std_logic);
end component;

begin

write <= w0 when w_reg='0' else
         w1 when w_reg='1' else '0';

-- retardo 10 us (w->1)
M1: mono generic map(time_10, tim_bits_10) 
	 port map(ck_slow, w1, w1_reset);

process (clk, w1_reset)
begin
	if w1_reset='1' then
	  w1 <= '0';
	elsif clk'event and clk='1' then
	  if start='1' then
	    w1 <= '1';
	  end if;
	end if;
end process;

--retardo 60 us (w->0)
M2: mono generic map(time_60, tim_bits_60)
	 port map(ck_slow, w0, w0_reset);

process (clk, w0_reset)
begin
	if w0_reset='1' then
	  w0 <= '0';
	elsif clk'event and clk='1' then
	  if start='1' then
	    w0 <= '1';
	  end if;
	end if;
end process;

end arch;
	
