library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--tim_bits = (log(time)/log(2)) +1

entity owinit is 
	generic(time_600:   integer:= 6; tim_bits_600:   integer:= 3;  --600us
		time_90:   integer:= 3; tim_bits_90:   integer:= 2);  --90us
	port (
	clk, ck_slow, start: in std_logic;
	init_p, read: out std_logic
	);
end owinit ;

architecture arch of owinit is

signal init, init_reset: std_logic;
signal init_read, init_read_reset: std_logic;

component mono  
	generic(time, tim_bits: integer);
	port (clk, enable: in std_logic;
	end_count: out std_logic);
end component;

begin

init_p <= init;
read <= init_read_reset;

-- retardo 600 us
M1: mono generic map(time_600, tim_bits_600) 
	 port map(ck_slow, init, init_reset);

process (clk, init_reset)
begin
	if init_reset='1' then
	  init <= '0';
	elsif clk'event and clk='1' then
	  if start='1' then
	    init <= '1';
	  end if;
	end if;
end process;

--retardo 60 us
M2: mono generic map(time_90, tim_bits_90)
	 port map(ck_slow, init_read, init_read_reset);

process (clk, init_read_reset)
begin
	if init_read_reset='1' then
	  init_read <= '0';
	elsif clk'event and clk='1' then
	  if init_reset='1' then
	    init_read <= '1';
	  end if;
	end if;
end process;

end arch;
	
