library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--tim_bits = (log(time)/log(2)) +1

entity owwrite is
          generic (time_10: integer:=10;  tim_bits_10: integer:=4;
                   time_80: integer:=100; tim_bits_80: integer:=7;
                   time_85: integer:=85;  tim_bits_85: integer:=7);
	  port (
	  clk, ck_slow, start_1, start_8: in std_logic; --byte
	  w_reg: in std_logic_vector(7 downto 0); --byte
	  write: out std_logic);
end owwrite ;

architecture arch of owwrite is

signal w0, w0_reset: std_logic;
signal w1, w1_reset: std_logic;
signal w_reg_i: std_logic_vector(7 downto 0); --byte
signal count_8: std_logic_vector (3 downto 0); --byte
signal start, rst_8, start_bit, w3, w3_pulse, w3_reset, w3_reset_dly, shift_w_reg: std_logic; --byte

component mono  
	generic(time, tim_bits: integer);
	port (clk, enable: in std_logic;
	end_count: out std_logic);
end component;

begin

----byte section----
--local data write register with shift
process (clk)
begin
	if clk'event and clk='1' then
	  if start_1='1' or start_8='1' then
	    w_reg_i <= w_reg; 
	  elsif shift_w_reg='1' then
	    w_reg_i <= '0' & w_reg_i (7 downto 1);
	  end if;
	end if;
end process;
--start
process(clk)
begin
	if clk'event and clk='1' then
	  if start_1='1' or start_bit='1' then
	    start <= '1';
	  else
	    start <= '0';
	  end if;
	end if;
end process;
--one byte = eight bits
process(clk)
begin
	if clk'event and clk='1' then
	  rst_8 <= count_8(3);
	end if;
end process;

process (clk, rst_8)
begin
	if rst_8='1' then
	  count_8 <= (others => '0');
	elsif clk'event and clk='1' then
	  if start_8='1' then
	    count_8 <= count_8 + '1';
	    start_bit <= '1';
	  elsif w3_pulse='1' and count_8 /= "0000" then
	    count_8 <= count_8 + '1';
	    start_bit <= '1';
	    shift_w_reg <= '1';
	  else 
	    start_bit <= '0';
	    shift_w_reg <= '0';
	  end if;
	end if;
end process;

--timer 60 us (8 bits)
M3: mono generic map(time_85, tim_bits_85)
	 port map(ck_slow, w3, w3_reset);
w3_pulse <= not w3_reset and w3_reset_dly;
process (clk)
begin
	if clk'event and clk='1' then
	  w3_reset_dly <= w3_reset;
	end if;
end process;

process (clk, w3_reset)
begin
	if w3_reset='1' then
	  w3 <= '0';
	elsif clk'event and clk='1' then
	  if start_bit='1' then
	    w3 <= '1';
	  end if;
	end if;
end process;

----end byte section ----

write <= w0 when w_reg_i(0)='0' else --byte
         w1 when w_reg_i(0)='1' else '0'; --byte

-- retardo 10 us (w->1)
M1: mono generic map(time_10, tim_bits_10) 
	 port map(ck_slow, w1, w1_reset);

process (clk, w1_reset)
begin
	if w1_reset='1' then
	  w1 <= '0';
	elsif clk'event and clk='1' then
	  if start='1' then
	    w1 <= '1';
	  end if;
	end if;
end process;

--retardo 80 us (w->0)
M2: mono generic map(time_80, tim_bits_80)
	 port map(ck_slow, w0, w0_reset);

process (clk, w0_reset)
begin
	if w0_reset='1' then
	  w0 <= '0';
	elsif clk'event and clk='1' then
	  if start='1' then
	    w0 <= '1';
	  end if;
	end if;
end process;

end arch;
	
