library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity tb_autotrigger is
end tb_autotrigger;
 
architecture behavior of tb_autotrigger is 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    component autotrigger
    port(
         clk : in  std_logic;
         reset : in  std_logic;
         triggerFreq : IN  std_logic_vector(3 downto 0);
         triggerOut : OUT  std_logic
        );
    end component;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal triggerFreq : std_logic_vector(3 downto 0) := "1111";

 	--Outputs
   signal triggerOut : std_logic;

   -- Clock period definitions
   constant clk_period : time := 25ns;
 
begin
 
  -- instantiate the unit under test (uut)
   uut: autotrigger port map (
          clk => clk,
          reset => reset,
          triggerFreq => triggerFreq,
          triggerOut => triggerOut
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      reset <= '1';
      wait for 100ns;	
      reset <= '0';

      wait for clk_period*10000;

      -- insert stimulus here 

      wait;
   end process;

end;
