library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--tim_bits = (log(time)/log(2)) +1

entity owcrc is
	  port (
	  clk, input, shift, reset, enw: in std_logic;
	  db_in: in std_logic_vector (7 downto 0);
	  add: in std_logic_vector (1 downto 0);
	  grp: in std_logic_vector(5 downto 0);
	  crc_p: out std_logic_vector (7 downto 0) );
end owcrc ;

architecture arch of owcrc is
signal crc_in: std_logic;
signal crc_reg: std_logic_vector (7 downto 0);

begin

crc_p <= crc_reg;
crc_in <= input xor crc_reg(0);

process (clk, reset)
begin
	if reset='1' then
	  crc_reg <= (others => '0');
	elsif clk'event and clk='1' then
	  if enw='1' and grp(4)='1' and add=3 then --19
	    crc_reg <= db_in;
	  elsif shift='1' then
	    crc_reg(7) <= crc_in;
	    crc_reg(6) <= crc_reg(7);
	    crc_reg(5) <= crc_reg(6);
	    crc_reg(4) <= crc_reg(5);
	    crc_reg(3) <= crc_in xor crc_reg(4);
	    crc_reg(2) <= crc_in xor crc_reg(3);
	    crc_reg(1) <= crc_reg(2);
	    crc_reg(0) <= crc_reg(1);
	  end if;
	end if;
end process;

end arch;
	
