library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity inthand is port (
	clk, reset: in std_logic;
	int_ext: in std_logic_vector (1 downto 0);
	sel, inv, pulse: in std_logic;
	int_int: out std_logic
	);
end inthand ;

architecture arch of inthand is

signal imed0, imed1, imed2, qi0, qi1, qi2: std_logic;

begin

int_int <= imed1 when pulse='0' else imed2;
imed2   <= qi1 and not qi2;
imed1   <= (imed0 and inv) or (imed0 nor inv);
imed0   <= int_ext(0) when sel='0' else int_ext(1);

process (clk, reset)
begin
	if reset='1' then
	  qi0 <= '0';
	  qi1 <= '0';
	  qi2 <= '0';
	elsif clk'event and clk='1' then
	  qi0 <= imed1;
	  qi1 <= qi0;
	  qi2 <= qi1;
	end if;
end process;

end arch;
	
