library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--
use work.vlib_commonfunc_pkg.all;

----**********************************************************************
---- Cabecera
----**********************************************************************
package control_x_pkg is
  --
  --******* COMPONENTES *******
  --
  component autotrigger is
    port (
      clk         : in  std_logic;        -- 40 MHz
      reset       : in  std_logic;
      triggerFreq : in  std_logic_vector(3 downto 0);
      triggerOut  : out std_logic
    );
  end component;

  component shift is
    generic (MEMBLOCKS : integer := 8); -- Potencias de 2
    port (
      clk         : in  std_logic; 
      trigger     : in  std_logic;
      trgDelaySel : in  std_logic_vector(getBusLines(16*MEMBLOCKS)-1 downto 0);
      trg_dly     : out std_logic
    );
  end component;

  component shft16x8
    port (
    CLK : IN  std_logic;
    D   : IN  std_logic_VECTOR(15 downto 0);
    Q   : OUT std_logic_VECTOR(15 downto 0));
  end component;

  component cuenta is 
    port (
      clk, reset, etr, set_trgin, trigger, enable: in std_logic;
      add         : in std_logic_vector(1 downto 0);
      grp         : in std_logic_vector(5 downto 0);
      trg_maxcnt  : in std_logic_vector(15 downto 0);
      db_out      : out std_logic_vector(15 downto 0);
      end_count   : out std_logic
    );
  end component;

end package;
