##############################################################
#
# Xilinx Core Generator version K.31
# Date: Fri Apr 26 08:15:33 2013
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc2s50
SET devicefamily = spartan2
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -6
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT RAM-based_Shift_Register family Xilinx,_Inc. 9.0
# END Select
# BEGIN Parameters
CSET aclr=false
CSET ainit=false
CSET aset=false
CSET asyncinitradix=2
CSET asyncinitval=0000000000000000
CSET ce=false
CSET cepriority=Sync_Overrides_CE
CSET component_name=shft16x8
CSET defaultdata=0000000000000000
CSET defaultdataradix=2
CSET depth=8
CSET meminitfile=no_coe_file_loaded
CSET optgoal=Resources
CSET readmiffile=false
CSET reglastbit=true
CSET sclr=false
CSET shiftregtype=Fixed_Length
CSET sinit=false
CSET sset=false
CSET syncctrlpriority=Reset_Overrides_Set
CSET syncinitradix=2
CSET syncinitval=0000000000000000
CSET width=16
# END Parameters
GENERATE
# CRC: 9fde9e1a

