library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--tim_bits = (log(time)/log(2)) +1

entity owread is
          generic (time_5:  integer:=5;  tim_bits_5:  integer:=3;
                   time_7:  integer:=7;  tim_bits_7:  integer:=3);
	  port (
	  clk, ck_slow, start: in std_logic;
	  read, read_read: out std_logic);
end owread ;

architecture arch of owread is

signal rdpls, rdpls_reset: std_logic;
signal rd, rd_reset: std_logic;

component mono  
	generic(time, tim_bits: integer);
	port (clk, enable: in std_logic;
	end_count: out std_logic);
end component;

begin

read <= rdpls;
read_read <= rd_reset;

-- retardo 5 us (read pulse)
M1: mono generic map(time_5, tim_bits_5) 
	 port map(ck_slow, rdpls, rdpls_reset);

process (clk, rdpls_reset)
begin
	if rdpls_reset='1' then
	  rdpls <= '0';
	elsif clk'event and clk='1' then
	  if start='1' then
	    rdpls <= '1';
	  end if;
	end if;
end process;

--retardo 7 us (read read)
M2: mono generic map(time_7, tim_bits_7)
	 port map(ck_slow, rd, rd_reset);

process (clk, rd_reset)
begin
	if rd_reset='1' then
	  rd <= '0';
	elsif clk'event and clk='1' then
	  if rdpls_reset='1' then
	    rd <= '1';
	  end if;
	end if;
end process;

end arch;
	
