library ieee;
use ieee.std_logic_1164.all;

entity vmeifc is
	port (
	clk: in std_logic;
	iack, ack_int, dtack_int, ds0, ds1: in std_logic;
	write, brd_sel, lword: in std_logic;
	am0, am1, am3, am4, am5: in std_logic;
	etr, enw, dtack, g245: out std_logic 
	);
end vmeifc;

architecture arch of vmeifc is
component ffrp port (
	d, clk, ce, cr, pr: in std_logic;
	q: out std_logic);
end component;

signal ds_rst, q1, q2, q4, q5, q8: std_logic;
signal md, m_2d_29, acc, d_lec, d_esc, ena_d: std_logic;
signal one, zero, not_ds0, dssync: std_logic;
begin
ds_rst <= ds0 or ds1;
one <= '1';
zero <= '0';
-- interface (A16)
m_2d_29 <= am0 and not am1 and am3 and not am4 and am5; --10 1x01
md <= m_2d_29;
acc <= not brd_sel and lword and iack and md;
d_lec <= acc and     write and dssync; --ds_lec;
d_esc <= acc and not write and dssync; --ds_esc;
ena_d <= q2 or q5;

g245 <= not (ack_int or q1 or q5);
etr <= not q5;
enw <= q2 and not q4;
dtack <= q4 or dtack_int;
not_ds0 <= not ds0;

fq1:  ffrp port map (clk => clk, d => one,     ce => d_esc, cr => ds_rst, pr => zero, q => q1);
fq2:  ffrp port map (clk => clk, d => q1,      ce => one,   cr => ds_rst, pr => zero, q => q2);
fq4:  ffrp port map (clk => clk, d => ena_d,   ce => one,   cr => zero,   pr => zero, q => q4);
fq5:  ffrp port map (clk => clk, d => one,     ce => d_lec, cr => ds_rst, pr => zero, q => q5);
fq8:  ffrp port map (clk => clk, d => not_ds0, ce => one,   cr => zero,   pr => zero, q => q8);
fds:  ffrp port map (clk => clk, d => q8,      ce => one,   cr => ds0,    pr => zero, q => dssync);
  
end arch;
	
