ofcu_ros Project Status (01/14/2014 - 08:36:02)
Project File: ofcu_ros.xise Parser Errors: No Errors
Module Name: ofcu_ros Implementation State: Translated (Stopped)
Target Device: xc6slx4-2tqg144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
 
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 511 4800 10%
Number of Slice LUTs 973 2400 40%
Number of fully used LUT-FF pairs 331 1153 28%
Number of bonded IOBs 436 102 427%
Number of Block RAM/FIFO 5 12 41%
Number of BUFG/BUFGCTRLs 2 16 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue 14. Jan 08:26:25 2014   
Translation ReportCurrentTue 14. Jan 08:26:34 2014   
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateTue 14. Jan 08:06:00 2014
WebTalk ReportOut of DateMon 13. Jan 12:15:10 2014
WebTalk Log FileOut of DateMon 13. Jan 12:15:17 2014

Date Generated: 01/14/2014 - 08:36:02