ofcu_ros Project Status (01/14/2014 - 08:36:02) | |||
Project File: | ofcu_ros.xise | Parser Errors: | No Errors |
Module Name: | ofcu_ros | Implementation State: | Translated (Stopped) |
Target Device: | xc6slx4-2tqg144 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 511 | 4800 | 10% | |
Number of Slice LUTs | 973 | 2400 | 40% | |
Number of fully used LUT-FF pairs | 331 | 1153 | 28% | |
Number of bonded IOBs | 436 | 102 | 427% | |
Number of Block RAM/FIFO | 5 | 12 | 41% | |
Number of BUFG/BUFGCTRLs | 2 | 16 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue 14. Jan 08:26:25 2014 | ||||
Translation Report | Current | Tue 14. Jan 08:26:34 2014 | ||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Tue 14. Jan 08:06:00 2014 | |
WebTalk Report | Out of Date | Mon 13. Jan 12:15:10 2014 | |
WebTalk Log File | Out of Date | Mon 13. Jan 12:15:17 2014 |