----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:04:26 07/06/2012 
-- Design Name: 
-- Module Name:    ofcu_ros - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library WORK;
use WORK.common.ALL;

entity ofcu_ros is
	Port (
		sc_bsel_n		: in std_logic;
		sc_wr_n 		: in std_logic;
		sc_data 		: inout std_logic_vector(7 downto 0);
		sc_add	 	: in std_logic_vector(3 downto 0);
		         	
		sd_tsc		: in std_logic;
		sd_ch24		: in std_logic;
		sd				: in  std_logic_vector(2 downto 1);
		rx_en		 	: out std_logic_vector(2 downto 1);
		sq_en			: out std_logic_vector(2 downto 1);
		en_sd			: out std_logic_vector(2 downto 1);
		
		trg_data		: in	std_logic_vector(15 downto 0);
      trg_strobe	: in std_logic;
      ros_ready	: in std_logic;
		evcntres		: in std_logic;
		l1a			: in std_logic;
      serialin_p 	: in std_logic;
      serialin_n	: in std_logic;
		
		leds			: out std_logic_vector(5 downto 0);
		
		onewire1		: inout std_logic;
		onewire3		: inout std_logic;
		
		Dir_spare	: out	std_logic;
		BSpare		: in std_logic_vector(4 downto 0);
		B_SP_indiv	: in std_logic;
		
		ixo_on		: in STD_LOGIC;
		clk40pad 		: in  STD_LOGIC;
		reset 		: in  STD_LOGIC
		);
end ofcu_ros;

architecture Behavioral of ofcu_ros is




	signal to_registers : t_registers_i;
	signal from_registers : t_registers_o;

	signal to_onewire : t_onewire_i;
	signal from_onewire : t_onewire_o;

	signal to_receivers : t_receivers_i;
	signal from_receivers : t_receivers_o;

	signal to_deser : t_deser_i;
	signal from_deser : t_deser_o;

	signal to_serialpatternrx : t_serialpatternrx_i;
	signal from_serialpatternrx : t_serialpatternrx_o;



	signal clk40 : std_logic;


begin

--   STARTUP_SPARTAN6_inst : STARTUP_SPARTAN6
--   port map (
--      CFGCLK => open,       -- 1-bit output: Configuration logic main clock output.
--      CFGMCLK => open,     -- 1-bit output: Configuration internal oscillator clock output.
--      EOS => open,             -- 1-bit output: Active high output signal indicates the End Of Configuration.
--      CLK => '0',             -- 1-bit input: User startup-clock input
--      GSR => reset,             -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
--      GTS => '0',             -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
--      KEYCLEARB => '0'  -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
--   );

--********************************************************************************
--	<REGISTERS>
--********************************************************************************
	inst_registers : registers
	port map(
		i => to_registers,
		o => from_registers,
		sc_data => sc_data,
		clk40 => clk40
	);
	
	to_registers.sc_add		<= sc_add	;
	to_registers.sc_bsel		<= not sc_bsel_n	;
	to_registers.sc_wr 		<= not sc_wr_n		;
--********************************************************************************
--	</REGISTERS>
--********************************************************************************
	
	
	
--********************************************************************************
--	<ONE WIRE>
--********************************************************************************
	
--	inst_onewire1 : onewire
--	generic map(
--		ctrl_reg => ow1_ctrl_reg,
--	   read_reg => ow1_read_reg,
--	   crc_reg 	=> ow1_crc_reg,
--	   write_reg => ow1_write_reg)
--	port map(
--		i => to_onewire,
--		o => from_onewire,
--		wire => onewire1,
--		clk40 => clk40	);
--		
--	inst_onewire3 : onewire
--	generic map(
--		ctrl_reg => ow3_ctrl_reg,
--	   read_reg => ow3_read_reg,
--	   crc_reg 	=> ow3_crc_reg,
--	   write_reg => ow3_write_reg)
--	port map(
--		i => to_onewire,
--		o => from_onewire,
--		wire => onewire3,
--		clk40 => clk40	);
--		
--	to_onewire.reg <= from_registers.reg;
--	to_onewire.ext_wr <= from_registers.ext_wr;
--	to_onewire.reg_ch_int <= from_registers.reg_ch_int;
--	
--	to_registers.reg_int <= from_onewire.reg_int;
--	to_registers.reg_ch_int <= from_onewire.reg_ch_int;

	onewire1 <= 'Z';
	onewire3 <= 'Z';
	
--********************************************************************************
--	</ONE WIRE>
--********************************************************************************

--********************************************************************************
--	<RECEIVERS>
--********************************************************************************
	inst_receivers : receivers
	port map(
		i => to_receivers,
		o => from_receivers,
		clk40 => clk40	);
	
	to_receivers.reg 			<= from_registers.reg;
	to_receivers.ext_wr 		<= from_registers.ext_wr;
	to_receivers.reg_ch_int <= from_registers.reg_ch_int;
	to_receivers.sd_tsc 		<= sd_tsc;
	to_receivers.sd_ch24 	<= sd_ch24;
	to_receivers.sd 			<= sd;
	
	to_registers.reg_int 	<= from_receivers.reg_int;
	to_registers.reg_ch_int <= from_receivers.reg_ch_int;
	rx_en 						<= from_receivers.rx_en;
	sq_en 						<= from_receivers.sq_en;
	en_sd 						<= from_receivers.en_sd;
--********************************************************************************
--	</RECEIVERS>
--********************************************************************************


--********************************************************************************
--	<DESER>
--********************************************************************************
	inst_deser : deser
	port map(
		i => to_deser,
		o => from_deser,
		reset => reset,
		clk40 => clk40	);
	
	to_deser.serialin_p <= serialin_p;
	to_deser.serialin_n <= serialin_n;
	
	
--********************************************************************************
--	</DESER>
--********************************************************************************

--********************************************************************************
--	<SERIALPATTERNrx>
--********************************************************************************
	inst_serialpatternrx : serialpatternrx
	port map(
		i => to_serialpatternrx,
		o => from_serialpatternrx,
		clk40 => clk40	);
	
	to_serialpatternrx.word <= from_deser.word;
	to_serialpatternrx.deser_lock <= from_deser.lock;

	
	
	
--********************************************************************************
--	</SERIALPATTERNrx>
--********************************************************************************






	
	clkin1_buf : IBUFG
	generic map(IOSTANDARD => "LVCMOS33")
	port map
		(O => clk40, 
		I => clk40pad); -- should be : clk40pad
	
	Dir_spare <= '0';

--leds <= (others => '0');

--leds(5) <= '0';

process (clk40)
	constant bits : integer := 28;
	variable contador : unsigned(bits-1 downto 0) := to_unsigned(2**bits-1,bits);
begin
	if rising_edge(clk40) then
		if contador = 0 then contador := to_unsigned(2**bits-1,bits);
		else contador := contador -1;
		end if;
		leds(0 downto 0) <= std_logic_vector(contador(23 downto 23));
--		leds(5) <= contador(27);

	end if;
end process;

--leds(3) <= '1';
--leds(2) <= from_deser.pll_locked; 
--leds(2) <= from_deser.bufpll_locked; 
--leds(3) <= from_deser.lock; 
--leds(4) <= from_serialpatternrx.realign_flag; 
--leds(5) <= from_serialpatternrx.error_flag; 

leds(1) <= from_registers.leds(1);
leds(2) <= from_registers.leds(2);
leds(3) <=from_registers.leds(3);
leds(4) <=from_registers.leds(4);
leds(5) <=from_registers.leds(5);




end Behavioral;

