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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:10:47 07/12/2012 
-- Design Name: 
-- Module Name:    receivers - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library WORK;
use WORK.common.ALL;

entity receivers is
    Port (
		i 		: in t_receivers_i;
		o 		: out t_receivers_o;
		clk40 : in std_logic
	 );

end receivers;

architecture Behavioral of receivers is

begin

-- avago_ctrl_reg => avago control outputs.
	o.rx_en <= i.reg(avago_ctrl_reg)(5 downto 4);
	o.sq_en <= i.reg(avago_ctrl_reg)(3 downto 2);
	o.en_sd <= i.reg(avago_ctrl_reg)(1 downto 0);
	

-- Signal detects => sd_status_reg
-- el registro se escribe internamente de manera continua. El reg_int con el que se actualiza se fabrica cada ciclo:
-- 	- En estado normal (reg_ed_ext = '0'): el latch se mantiene o baja si SD = '0'.
--		- Si se ha dado evento de escritura en este mismo registro, todos los latches se actualizan con el valor actual de SD.
process (clk40)
	variable status_reg_v : std_logic_vector(7 downto 0);
	variable tmp : std_logic_vector(7 downto 4);
begin
	if rising_edge(clk40) then
		o.reg_int <= (others => (others => 'Z'));
		o.reg_ch_int <= (others => 'Z');
	
		status_reg_v(3 downto 0) := i.sd_tsc & i.sd_ch24 & i.sd(2) & i.sd(1);
		if i.ext_wr(sd_status_reg) = '0' then 
			status_reg_v(7 downto 4) := status_reg_v(7 downto 4) and status_reg_v(3 downto 0);
		else
			status_reg_v(7 downto 4) := status_reg_v(3 downto 0);
		end if;
		
		o.reg_int(sd_status_reg) <= status_reg_v;
		o.reg_ch_int(sd_status_reg) <= not i.reg_ch_int(sd_status_reg);
	end if;
end process;



end Behavioral;

