--
--	Package File Template
--
--	Purpose: This package defines supplemental types, subtypes, 
--		 constants, and functions 
--
--   To use any of the example code shown below, uncomment the lines and modify as necessary
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package common is

--********************************************************************************
--	<REGISTERS>
--********************************************************************************

	type reg_t is array(natural range <>) of std_logic_vector(7 downto 0);

	constant num_of_regs : integer := 16;

	constant test_reg			: integer := 0;	-- (check communication)
	constant test_reg_ro		: integer := 1;	-- (check communication)
	constant sd_status_reg 	: integer := 2;	-- (sd_tsc_l, sd_ch24_l, sd2_l, sd1_l, sd_tsc, sd_ch24, sd2, sd1); wr resets latches
	constant avago_ctrl_reg : integer := 3;	-- (--, --, rx_en2, rx_en1, sq_en2, sq_en1, en_sd2, en_sd2)
	constant ow1_ctrl_reg 	: integer := 4;	-- One wire - 1.2 commands: (--,--,--,byte read, byte write, bit read, bit write, init)
	constant ow1_write_reg 	: integer := 5;	-- One wire - 1.2 write data
	constant ow1_read_reg 	: integer := 6;	-- One wire - 1.2 read data
	constant ow1_crc_reg 	: integer := 7;	-- One wire - 1.2 CRC
	constant ow3_ctrl_reg 	: integer := 8;	-- One wire - 3.3 commands: (--,--,--,byte read, byte write, bit read, bit write, init)
	constant ow3_write_reg 	: integer := 9;	-- One wire - 3.3 write data
	constant ow3_read_reg 	: integer := 10;	-- One wire - 3.3 read data
	constant ow3_crc_reg 	: integer := 11;	-- One wire - 3.3 CRC

	constant reg_init : reg_t(num_of_regs-1 downto 0) := (
		test_reg 		=> "10011010",
		test_reg_ro		=> "10011010",
		sd_status_reg 	=> (others => '1'),
		avago_ctrl_reg	=> (others => '1'),
		ow1_ctrl_reg	=> (others => '0'),
		ow1_write_reg 	=> (others => '0'),
		ow1_read_reg 	=> (others => '0'),
		ow1_crc_reg 	=> (others => '0'),
		ow3_ctrl_reg 	=> (others => '0'),
		ow3_write_reg 	=> (others => '0'),
		ow3_read_reg 	=> (others => '0'),
		ow3_crc_reg 	=> (others => '0'),

		others => "10101010");

	-- 1: user write/read, 0: read only
	constant reg_mode : std_logic_vector(num_of_regs-1 downto 0) := (
		test_reg 		=> '1',
		test_reg_ro		=> '0',
		sd_status_reg 	=> '0',
		avago_ctrl_reg	=> '1',
		ow1_ctrl_reg	=> '1',
		ow1_write_reg 	=> '1',
		ow1_read_reg 	=> '0',
		ow1_crc_reg 	=> '0',
		ow3_ctrl_reg 	=> '1',
		ow3_write_reg 	=> '1',
		ow3_read_reg 	=> '0',
		ow3_crc_reg 	=> '0',
		
		others =>'0');

	type t_registers_i is
	record
		sc_add		: std_logic_vector(3 downto 0);
		sc_bsel		: std_logic;
		sc_wr			: std_logic;
		
		reg_int		: reg_t(num_of_regs-1 downto 0);
		reg_ch_int	: std_logic_vector(num_of_regs-1 downto 0);
	end record;
	
	type t_registers_o is
	record
		reg			: reg_t(num_of_regs-1 downto 0);
		ext_wr		: std_logic_vector(num_of_regs-1 downto 0);
		reg_ch_int	: std_logic_vector(num_of_regs-1 downto 0);
		leds			: std_logic_vector(5 downto 0);
	end record;


	component registers
	Port (
		i 		: in t_registers_i;
		o 		: out t_registers_o;
		sc_data 	: inout std_logic_vector(7 downto 0);
		clk40 	: in std_logic
		);
	end component;

--********************************************************************************
--	</REGISTERS>
--********************************************************************************



--********************************************************************************
--	<ONE WIRE>
--********************************************************************************
	type t_onewire_i is
	record
		reg			: reg_t(num_of_regs-1 downto 0);
		ext_wr		: std_logic_vector(num_of_regs-1 downto 0);
		reg_ch_int	: std_logic_vector(num_of_regs-1 downto 0);
	end record;
	
	type t_onewire_o is
	record
		reg_int		: reg_t(num_of_regs-1 downto 0);
		reg_ch_int	: std_logic_vector(num_of_regs-1 downto 0);
	end record;
	
	
	component onewire
	Generic (
		ctrl_reg		: integer;
		read_reg		: integer;
		write_reg	: integer;
	   crc_reg		: integer
	);
	Port (
		i 		: in t_onewire_i;
		o 		: out t_onewire_o;
		wire		: inout std_logic;
		clk40 	: in std_logic
		);
	end component;
--********************************************************************************
--	</ONE WIRE>
--********************************************************************************




--********************************************************************************
--	<RECEIVERS>
--********************************************************************************
	type t_receivers_i is
	record
		reg			: reg_t(num_of_regs-1 downto 0);
		ext_wr		: std_logic_vector(num_of_regs-1 downto 0);
		reg_ch_int	: std_logic_vector(num_of_regs-1 downto 0);
		
		sd_tsc		: std_logic;
		sd_ch24		: std_logic;
		sd				: std_logic_vector(2 downto 1);
	end record;
	
	type t_receivers_o is
	record
		reg_int		: reg_t(num_of_regs-1 downto 0);
		reg_ch_int	: std_logic_vector(num_of_regs-1 downto 0);
		
		rx_en			: std_logic_vector(2 downto 1);
		sq_en			: std_logic_vector(2 downto 1);
		en_sd			: std_logic_vector(2 downto 1);
	end record;
	
	component receivers
	Port (
		i 		: in t_receivers_i;
		o 		: out t_receivers_o;
		clk40 	: in std_logic
		);
	end component;
--********************************************************************************
--	</RECEIVERS>
--********************************************************************************

--********************************************************************************
--	<DESER>
--********************************************************************************
	type t_deser_i is
	record
		serialin_p		: std_logic;
		serialin_n		: std_logic;
	end record;

	type t_deser_o is
	record
		lock : STD_LOGIC;
		bufpll_locked : std_logic;
		pll_locked : std_logic;
		word : std_logic_vector(19 downto 0);
	end record;
	
	component deser
	Port (
		i 		: in t_deser_i;
		o 		: out t_deser_o;
		reset		: in std_logic;
		clk40 	: in std_logic
		);
	end component;
--********************************************************************************
--	</DESER>
--********************************************************************************


--********************************************************************************
--	<SERIALPATTERNrx>
--********************************************************************************
	type t_serialpatternrx_i is
	record
		deser_lock 	: STD_LOGIC;
		word			: std_logic_vector(19 downto 0);
	end record;
	
	type t_serialpatternrx_o is
	record
		error_flag : std_logic;
		realign_flag : std_logic;
	end record;

	component serialpatternrx
	Port (
		i 		: in t_serialpatternrx_i;
		o 		: out t_serialpatternrx_o;
		clk40 	: in std_logic
		);
	end component;
--********************************************************************************
--	</SERIALPATTERNrx>
--********************************************************************************


--
-- Declare constants
--
-- constant <constant_name>		: time := <time_unit> ns;
-- constant <constant_name>		: integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name>  (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name>	: in <type_declaration>);
--

end common;

package body common is

---- Example 1
--  function <function_name>  (signal <signal_name> : in <type_declaration>  ) return <type_declaration> is
--    variable <variable_name>     : <type_declaration>;
--  begin
--    <variable_name> := <signal_name> xor <signal_name>;
--    return <variable_name>; 
--  end <function_name>;

---- Example 2
--  function <function_name>  (signal <signal_name> : in <type_declaration>;
--                         signal <signal_name>   : in <type_declaration>  ) return <type_declaration> is
--  begin
--    if (<signal_name> = '1') then
--      return <signal_name>;
--    else
--      return 'Z';
--    end if;
--  end <function_name>;

---- Procedure Example
--  procedure <procedure_name>  (<type_declaration> <constant_name>  : in <type_declaration>) is
--    
--  begin
--    
--  end <procedure_name>;
 
end common;
