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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:33:26 08/13/2012 
-- Design Name: 
-- Module Name:    leds_clock - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.pack.all;

entity leds_clock is port(
-- general
	clk, local_reset: in std_logic;
	OUTclk_slow: out std_logic
 	);
end leds_clock;

architecture Behavioral of leds_clock is

signal count1: std_logic_vector(21 downto 0);
signal clk_slow: std_logic;

begin

OUTclk_slow <= clk_slow;

process(clk, local_reset)
begin
   if local_reset='1' then
		count1 <= (others=>'0');
   elsif clk'event and clk='1' then
		count1 <= count1+1;
	end if;
end process;

clk_slow <= '1' when count1(21)='1' else '0'; 

end Behavioral;

