library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.pack.all;

entity registros_vme is port(
-- general
	clk, sysreset, etr, enw, cs: in std_logic;
	sda, scl: out std_logic; --abril12  CUOF
	soft_reset: out std_logic;
	sel_tim: in std_logic;
	add: in std_logic_vector(5 downto 0);
	db_in: in std_logic_vector(15 downto 0);
	db_out: out std_logic_vector(15 downto 0);
-- ROS general
	prs, mrs, reset: out std_logic;
	ldpreg: out std_logic;
--dec10	spaf, sff, fpga_done: in std_logic_vector (4 downto 0);
	fpga_done: in std_logic_vector (4 downto 0);
   hardresetin: in std_logic; --dec10 de rosctrl por el pin de sff4
	spaf, sff: in std_logic_vector (3 downto 0);
-- ROS control
	ros_waiting: in std_logic;
-- ROSMEM control
	mem_done: in std_logic;
-- TIM
	evcnt_res: in std_logic;
   sel_tim_clk_p: out std_logic_vector (1 downto 0);
-- FPGA, flash XC18V01 y CPLD
	cclk, fpga_init_p: out std_logic_vector(4 downto 0);
	prgm_fpga_p: out std_logic_vector(4 downto 0);
	flash_tck_p: out std_logic_vector (5 downto 0);
	flash_tdo: in std_logic_vector (5 downto 0);
	flash_tdi_p, flash_tms_p, ena_evres_prgm_p: out std_logic;
	fl_vme_p: out std_logic_vector(2 downto 0);
	flash_ena_5_rosmem: out std_logic;
-- GOL Y QPLL
	gol_ready: in std_logic;	
	qpll_error, qpll_locked: in std_logic;
	gol_off_p: out std_logic;
-- I2C bus (para GOL y 1-wire)
	i2c_ce, i2c_rd, i2c_wr: out std_logic; -- i2c_intrpt
	i2c_ce_gol_p, i2c_ce_1wire_p: out std_logic;
-- interrupciones
	int_rst, etr_ivec: in std_logic;
	interrupt: out std_logic;  
	int_lev_p: out std_logic_vector(2 downto 0)
 	);
end registros_vme ;

architecture arch of registros_vme is

-- direcciones
constant ctrl_add: std_logic_vector (5 downto 0):=     "000000"; -- $00 status y control
constant pafff_add: std_logic_vector (5 downto 0):=    "000010"; -- $04 SPAF y SFF
constant int_add: std_logic_vector (5 downto 0):=	     "000011"; -- $06 interrupciones
constant fpctrl_add: std_logic_vector (5 downto 0):=   "000100"; -- $08 FPGA control
constant jtagctrl_add: std_logic_vector (5 downto 0):=   "000101"; -- $0A JTAG control
constant jtagr1_add: std_logic_vector (5 downto 0):=   "000110"; -- $0C JTAG registro 1
constant jtag_tdi_add: std_logic_vector (5 downto 0):=   "000111"; -- $0E JTAG TDI registro
constant jtag_tdo_add: std_logic_vector (5 downto 0):=   "001000"; -- $10 JTAG TDO registro
constant i2c_add: std_logic_vector (5 downto 0):=	     "001001"; -- $12 I2C
constant PCA9564_add: std_logic_vector (3 downto 0):=  "0100";    -- $20-26 ZONA RESERVADA para los I2C $20, $22, $24, $26

constant i2c_cuof_scl: std_logic_vector (5 downto 0):=	     "001010"; -- $14 SCL I2C_CUOF		 --abril12  CUOF
constant i2c_cuof_sda: std_logic_vector (5 downto 0):=	     "001011"; -- $16 SDA I2C_CUOF	  --abril12  CUOF


-- señales
signal i2c_ce_gol, i2c_ce_1wire, gol_off, vme_reset, local_reset: std_logic;
signal int_lev: std_logic_vector(2 downto 0);
signal int_vect: std_logic_vector(7 downto 0);
signal fpga_init: std_logic_vector(4 downto 0);
signal flash_tck, flash_tms, flash_tdi: std_logic;
signal flash_enable: std_logic_vector(5 downto 0);
signal cclk_freq: std_logic_vector(2 downto 0);
signal cclk_int: std_logic;
signal cclk_counter: std_logic_vector(4 downto 0);
signal tck_sum: std_logic;
signal int_ena_spaf, int_ena_sff, int_ena_mdone, int_ena_rosw: std_logic;  
signal db_mux: std_logic_vector (15 downto 0);
signal ena_evres: std_logic;
signal ros_w0, ros_waiting_reg, mem_d0, mem_done_reg: std_logic;
signal ena_rst_prgm, ena_evres_prgm: std_logic;
signal add_high: std_logic_vector (3 downto 0);
signal sel_tim_clk: std_logic_vector (1 downto 0);
signal qpll_error_reg: std_logic;
signal fl_vme: std_logic_vector (2 downto 0);
signal gol_notready_reg,qpll_hasunlock_reg: std_logic;
signal activa_pr:std_logic_vector(4 downto 0);
signal cuenta_prgm:std_logic_vector(4 downto 0);
signal not_sel_tim,not_sel_tim_reg: std_logic;
signal reset_1,reset_2: std_logic;
signal s_reset_1,s_reset_2,reset_i: std_logic;

signal prs_vme, mrs_vme: std_logic;

signal tdo_reg,tdo_aux,jtag_shift, jtag_clk,jtag_start,jtag_end: std_logic;
signal tdi_bits, tdo_bits: std_logic_vector(7 downto 0);
signal bits_to_send,jtag_num_bits: std_logic_vector(3 downto 0);
signal flash_tdi_reg,flash_tms_reg,flash_tck_reg: std_logic;

signal ena_HR_prgm: std_logic; --dec10

signal gol_off_reg: std_logic; --dec10
signal pwgolcount: std_logic_vector(15 downto 0); --dec10

signal HR1, HR2, HR_prg,hardresetin_p: std_logic; --dec10 hago un pulso con hardreset negado

signal sda_r,scl_r: std_logic;


----------------
-- FSM JTAG
type state_type is (wait_start, 
	wait_phase0, wait_phase1, 
	send_clock, next_bit,
	 jtag_exit);
signal state: state_type;


begin

add_high <= add (5 downto 2);

-- puertos
i2c_ce_gol_p <= i2c_ce_gol;
i2c_ce_1wire_p <= i2c_ce_1wire;
gol_off_p <= gol_off;
int_lev_p <= int_lev;
fpga_init_p <= fpga_init;
ena_evres_prgm_p <= ena_evres_prgm;
sel_tim_clk_p <= sel_tim_clk;


sda<= sda_r;
scl<= scl_r;




-- tck de vmeflash o del registro vme
-- tdi del shift-register o del registro vme
-- flash_tck debe estar a cero !!
tck_sum <=  flash_tck or flash_tck_reg;
flash_tck_p <= multi_and (flash_enable, tck_sum);
flash_tdi_p <= flash_tdi or flash_tdi_reg;
flash_tms_p <= flash_tms or flash_tms_reg;


-----------------------------------------------
-- cs y etr están puestos en el 3-estados
db_out <=   X"00" & int_vect when etr_ivec='0' else  -- interrupt vector
         db_mux;

process (add,
	fpga_init,fl_vme,not_sel_tim,not_sel_tim_reg,
	gol_notready_reg,qpll_hasunlock_reg,qpll_error_reg,
   int_vect, qpll_locked, qpll_error, gol_ready, gol_off, i2c_ce_1wire, i2c_ce_gol, 
 	sff, spaf, fpga_done, mem_done, ros_waiting, int_lev, int_rst, 
   int_ena_rosw, int_ena_mdone, int_ena_sff, int_ena_spaf,
   cclk_freq, flash_tdo, flash_tdi, flash_tms, flash_tck, flash_enable, 
	jtag_num_bits,tdi_bits,tdo_bits,jtag_end,
	flash_tdi_reg, flash_tck_reg,flash_tms_reg,
	ena_evres, ena_evres_prgm, ena_rst_prgm, sel_tim_clk,ena_HR_prgm)
begin

     case add is

	-- status y control
     when ctrl_add =>
	  db_mux <= "00000" & sel_tim_clk & ena_evres & '0' & not(fpga_done) 
                    & mem_done & ros_waiting;
 
	-- SPAF y SFF
     when pafff_add =>
--dec10	  db_mux <= "000000" & sff & spaf;
	  db_mux <= "0000000" & sff & '0' & spaf;

	--interrupciones
     when int_add =>
	  db_mux <= int_vect & int_lev & int_rst & int_ena_rosw & int_ena_mdone 
               & int_ena_sff & int_ena_spaf;

	-- FPGA control
     when fpctrl_add =>
--dec10  	  db_mux <= '0' & ena_rst_prgm & ena_evres_prgm & cclk_freq & "00000" & fpga_init;
  	  db_mux <= ena_HR_prgm & ena_rst_prgm & ena_evres_prgm & cclk_freq & "00000" & fpga_init;

	-- JTAG control
     when jtagctrl_add =>
	  db_mux <= "0000000000000" & fl_vme;

	-- JTAG register 1
     when jtagr1_add =>
	  db_mux <= '0' & flash_tdo & flash_tdi_reg & flash_tms_reg & flash_tck_reg & flash_enable;

	-- JTAG TDI register
     when jtag_tdi_add =>
	  db_mux <= "000" & jtag_num_bits & flash_tms & tdi_bits;

	-- JTAG TDO register
     when jtag_tdo_add =>
	  db_mux <= "0000000" & jtag_end & tdo_bits;


	-- I2C, GOL, QPLL, etc
     when  i2c_add =>
       db_mux <=  "00000" & not_sel_tim_reg & not_sel_tim & '0' & gol_notready_reg & qpll_hasunlock_reg & qpll_locked & qpll_error_reg & gol_ready & gol_off  
                & i2c_ce_1wire & i2c_ce_gol;

     when i2c_cuof_scl =>
       db_mux <= "000000000000000" & scl_r;

     when i2c_cuof_sda =>
       db_mux <= "000000000000000" & sda_r;
		     
	when others => 
       db_mux <= (others => '0');

     end case;
end process;

not_sel_tim <= not(sel_tim);

process(local_reset, clk)
begin
	if local_reset='1' then
			not_sel_tim_reg <= '0';
	elsif clk'event and clk='1' then
		if add=i2c_add and cs='1' and enw='1' then
			not_sel_tim_reg <= db_in(10);
		elsif not_sel_tim='1' then
			not_sel_tim_reg <= '1'; --error viene del cristal
		end if;
	end if;
end process;

process(local_reset, clk)
begin
	if local_reset='1' then
			qpll_error_reg <= '0';
	elsif clk'event and clk='1' then
		if add=i2c_add and cs='1' and enw='1' then
			qpll_error_reg <= db_in(4);
		elsif qpll_error='1' then
			qpll_error_reg <= '1';
		end if;
	end if;
end process;

process(local_reset, clk)
begin
	if local_reset='1' then
			qpll_hasunlock_reg <='0';
	elsif clk'event and clk='1' then
		if add=i2c_add and cs='1' and enw='1' then
			qpll_hasunlock_reg <=db_in(6);
		elsif qpll_locked='0' then
			qpll_hasunlock_reg <='1';
		end if;
	end if;
end process;

process(local_reset, clk)
begin
	if local_reset='1' then
			gol_notready_reg <='0';
	elsif clk'event and clk='1' then
		if add=i2c_add and cs='1' and enw='1' then
			gol_notready_reg <=db_in(7);
		elsif gol_ready='0' then
			gol_notready_reg <='1';
		end if;
	end if;
end process;
			
-- registro de status y control
--bits  description	acc	signal
--0     ros_waiting (puede producir interr)     R ros_waiting
--1     mem_done (puede producir interr)        R mem_done
--2-6   FPGA's programadas                      R fpga_done
--7     Registros de las FPGA's cargados        R      
--8     Enable EVCNT_RES  board reset           R/W ena_evres
--9-10  Select TIM clock: clk40 or clkdes2      R/W sel_tim_clk   		
--11    transf. de VME FLASH a registros FPGA   W load_fpga_reg
--12    Partial reset de las CEROS FIFOS        W prs
--13    Master reset de las CEROS FIFOS         W mrs
--14    Reset de RosVME                         W local_reset
--15    Reset de la placa (pero no de RosVME)   W reset
	
ldpreg <=        db_in (11) when add=ctrl_add and cs='1' and enw='1'  else '0'; -- aquí activo alto    

--RESETS
prs_vme <=           db_in (12) when add=ctrl_add and cs='1' and enw='1'  else '0';
prs <= prs_vme or reset_i; -- aquí activo alto   
 
mrs_vme <=           db_in (13) when add=ctrl_add and cs='1' and enw='1'  else '0'; -- aquí activo alto
mrs <= mrs_vme or local_reset; -- aquí activo alto   

local_reset <= '1' when sysreset='1'
                   or (db_in (14)='1' and add=ctrl_add and cs='1' and enw='1')  
                   else '0';
--HARD RESET resetea ROSVME y todo lo demás. Apaga GOL. Obliga a reprogramar
process(clk)
begin
	if clk'event and clk='1' then
		reset_1 <= local_reset;
		reset_2 <= reset_1;
	end if;
end process;

reset <= reset_1 or reset_2; --dura 50 ns

--SOFT RESET Lo genera también un HARD reset. Resetea algunos registros, pero no obliga a reprogramar.
--reset <= '1' when sysreset='1' or vme_reset='1' or (evcnt_res='1' and ena_evres='1') else '0';
reset_i <= '1' when local_reset='1' or vme_reset='1' or (evcnt_res='1' and ena_evres='1') else '0';
vme_reset <=     db_in (15) when add=ctrl_add and cs='1' and enw='1'  else '0';

process(clk)
begin
	if clk'event and clk='1' then
		s_reset_1 <= reset_i;
		s_reset_2 <= s_reset_1;
	end if;
end process;

soft_reset <= s_reset_1 or s_reset_2; --dura 50 ns

process (clk, local_reset)
begin
	if local_reset='1' then
	  ena_evres <= '0';
       sel_tim_clk <=(others => '0');  -- por defecto reloj tim
	elsif clk'event and clk='1' then
	  if add=ctrl_add and cs='1' and enw='1' then		
         ena_evres <= db_in (8);
         sel_tim_clk <= db_in (10 downto 9);
	  end if;
	end if;
end process;

		
-- interrupciones
 interrupt <= '1' when 
          (or_reduce(spaf)='1' and int_ena_spaf='1') or	  -- alguna esta a 1
          (or_reduce(sff)='1'   and int_ena_sff='1') or	  -- alguna esta a 1
          (mem_done_reg='1'         and int_ena_mdone='1') or
          (ros_waiting_reg='1'  and int_ena_rosw='1') else '0';

process (clk, local_reset)
begin
	if local_reset='1' then 	
	  int_ena_spaf <= '0';  
	  int_ena_sff <= '0';  
	  int_ena_mdone <= '0';  
	  int_ena_rosw <= '0';  
	  int_lev <= "001";
	  int_vect <= (others => '0');
	elsif clk'event and clk='1' then
	  if int_rst='1' then
	    int_ena_spaf <= '0';  
	    int_ena_sff <= '0';  
	    int_ena_mdone <= '0';  
	    int_ena_rosw <= '0';  
	  elsif add=int_add and cs='1' and enw='1' then  
	    int_ena_spaf <= db_in (0);  
	    int_ena_sff <= db_in (1);  
	    int_ena_mdone <= db_in (2);  
	    int_ena_rosw <= db_in (3);  
	    int_lev <= db_in (7 downto 5);
	    int_vect <= db_in (15 downto 8);
	  end if;
	end if;
end process;

     -- ros waiting: interrupción por flanco de subida
process (clk, local_reset)
begin
	if local_reset='1' then
	  ros_w0 <= '0'; 	
	  ros_waiting_reg <= '0'; 	
	elsif clk'event and clk='1' then
       ros_w0 <= ros_waiting;
       if ros_waiting='1' and ros_w0='0' then 
         ros_waiting_reg <= '1';
       elsif ros_waiting='0' or int_rst='1' then
         ros_waiting_reg <= '0';
       end if;
	end if;
end process;

     -- memory done: interrupción por flanco de subida
process (clk, local_reset)
begin
	if local_reset='1' then
	  mem_d0 <= '0'; 	
	  mem_done_reg <= '0'; 	
	elsif clk'event and clk='1' then
       mem_d0 <= mem_done;
       if mem_done='1' and mem_d0='0' then 
         mem_done_reg <= '1';
       elsif mem_done='0' or int_rst='1' then
         mem_done_reg <= '0';
      end if;
	end if;
end process;

-- FPGA y flash XC18V01
process (clk, local_reset)
begin
	if local_reset='1' then
	    fpga_init <= (others => '0'); 	-- invertido en la placa, aquí activo alto
	    cclk_freq <= "100";              -- inicialmente 20 MHz
       ena_rst_prgm <= '0';	
       ena_evres_prgm <= '0';	
       ena_HR_prgm <=  '1';	--dec10 hardreset
	elsif clk'event and clk='1' then
	  if add=fpctrl_add and cs='1' and enw='1' then  
	    fpga_init <= db_in (4 downto 0); 	
	    cclk_freq <= db_in (12 downto 10); 	
       ena_evres_prgm <= db_in (13);
       ena_rst_prgm <= db_in (14);	
       ena_HR_prgm <=  db_in (15);	--dec10 hardreset
	  end if;
	end if;
end process;

prgm_fpga_p <= activa_pr;

process(clk,vme_reset,evcnt_res,ena_rst_prgm,ena_evres_prgm,ena_HR_prgm,HR_prg)
begin
	if  (vme_reset='1' and ena_rst_prgm='1') or 
        (evcnt_res='1' and ena_evres_prgm='1') or
		  (HR_prg='1' and ena_HR_prgm='1') then  --dec10
			cuenta_prgm <= (others=>'0'); 
			activa_pr<=(others=>'1');
	elsif clk'event and clk='1' then
		if add=fpctrl_add and cs='1' and enw='1' then
			activa_pr <= db_in(9 downto 5);
			cuenta_prgm <= (others=>'0'); 
		elsif cuenta_prgm="11111" then
			activa_pr<= (others=>'0');
		else
			cuenta_prgm<= cuenta_prgm+1;
		end if;
	end if;
end process;


process(clk,hardresetin,local_reset) --dec10 todo este registro
begin
	if (local_reset='1') then
			HR1 <='0';
			HR2 <='0';
	elsif clk'event and clk='1' then
			HR1 <= hardresetin_p;
			HR2 <= HR1;
	end if;
end process;
hardresetin_p <= not(hardresetin);
HR_prg <= HR1 and not (HR2);  --dec10
		

-- JTAG CONTROL sirve de switch para conectar J1 con lo que quieras 
-- 0 configuras la XC18V01 de ceros0
-- 1 ceros 1
-- 2 ceros 2
-- 3 ceros 3
-- 4 rosctrl
-- 5 rosmem
-- 6 carga desde el vme
-- 7 manda el switch bcd

process (clk, local_reset)
begin
	if local_reset='1' then
	  fl_vme <= (others => '1'); 	
	elsif clk'event and clk='1' then
	  if add=jtagctrl_add and cs='1' and enw='1' then  
	    fl_vme <= db_in (2 downto 0); 	
	  end if;
	end if;
end process;

fl_vme_p <= fl_vme;

-- CCLK                                                                
cclk_int <= 
		cclk_counter(0) when cclk_freq="100" else  -- 20 MHz valor por defecto
		cclk_counter(1) when cclk_freq="011" else  -- 10 MHz
		cclk_counter(2) when cclk_freq="010" else  -- 5 MHz
		cclk_counter(3) when cclk_freq="001" else  -- 2.5 MHz
		cclk_counter(4) when cclk_freq="000" else  -- 1.25 MHz
		cclk_counter(4);   ---Si alguien escribe algo raro aún así se programan a 1.25MHz

process(clk)
begin
	if clk'event and clk='1' then
		if fpga_done(0)='0' then 
				cclk(0) <= '0';
		else cclk(0) <= cclk_int; 
		end if;
		if fpga_done(1)='0' then 
				cclk(1) <= '0';
		else cclk(1) <= cclk_int; 
		end if;
		if fpga_done(2)='0' then 
				cclk(2) <= '0';
		else cclk(2) <= cclk_int; 
		end if;
		if fpga_done(3)='0' then 
				cclk(3) <= '0';
		else cclk(3) <= cclk_int; 
		end if;
		if fpga_done(4)='0' then 
				cclk(4) <= '0';
		else cclk(4) <= cclk_int; 
		end if;
	end if;
end process;

		  
process (clk, local_reset)
begin
	if local_reset='1' then
	  cclk_counter <= (others => '0');
	elsif clk'event and clk='1' then
	  cclk_counter <= cclk_counter +1;
	end if;
end process;

-- JTAG register 1
-- flash_tck_p y flash_tdi_p se definen en puertos
     -- flash_enable de 0 a 3 -> flash de las CEROS
     -- flash_enable 4        -> flash de las RosCTRL
     -- flash_enable 5        -> CPLD de RosMEM
process (clk, local_reset)                                                   
begin
	if local_reset='1' then
	  flash_enable <= (others => '0');
	  flash_tck_reg <= '0';
	  flash_tms_reg <= '0';
	  flash_tdi_reg <= '0';
	elsif clk'event and clk='1' then
	  if add=jtagr1_add and cs='1' and enw='1' then  
	    flash_enable (3 downto 0) <= db_in(3 downto 0);  -- CEROS
	    flash_enable (4) <= db_in(4) and not db_in (5) and not db_in(3) and not db_in(2) and not db_in(1) and not db_in(0);  -- RosCTRL
	    flash_enable (5) <= db_in(5) and not db_in (4) and not db_in(3) and not db_in(2) and not db_in(1) and not db_in(0);  -- RosVME
	    flash_tck_reg <= db_in (6);
	    flash_tms_reg <= db_in (7);
	    flash_tdi_reg <= db_in (8);
       elsif flash_enable (4)='1' or flash_enable (5)='1' then
         flash_enable (3 downto 0) <= (others => '0');
	  end if;
	end if;
end process;

flash_ena_5_rosmem <= flash_enable (5);

process (clk, local_reset)
begin
	if local_reset='1' then
	  jtag_start <= '0';
	elsif clk'event and clk='1' then
	  if add=jtag_tdi_add and cs='1' and enw='1' then  
	    jtag_start <= '1';
	  elsif jtag_end='1' then 
	    jtag_start <= '0';
	  end if;
	end if;
end process;

process (clk, local_reset)
begin
	if local_reset='1' then
	  jtag_num_bits <= (others=>'0');
	  flash_tms <= '0';
	elsif clk'event and clk='1' then
	  if add=jtag_tdi_add and cs='1' and enw='1' then  
		jtag_num_bits <= db_in(12 downto 9);
	    flash_tms <= db_in(8);
	  end if;
	end if;
end process;
--TDI
process (clk, local_reset)
begin
	if local_reset='1' then
	  tdi_bits <= (others=>'0');
	elsif clk'event and clk='1' then
	  if add=jtag_tdi_add and cs='1' and enw='1' then  
	    tdi_bits <= db_in(7 downto 0);
	  elsif jtag_shift='1' then 
		tdi_bits <= '0' & tdi_bits(7 downto 1);
	  end if;
	end if;
end process;
--TDO
process (clk, local_reset)
begin
	if local_reset='1' then
	  tdo_bits <= (others=>'0');
	elsif clk'event and clk='1' then
	  if jtag_start='1' then 
		  tdo_bits <= (others=>'0');
	  elsif jtag_shift='1' then 
		  tdo_bits <=  tdo_reg & tdo_bits(7 downto 1);
	  end if;
	end if;
end process;

flash_tdi <= tdi_bits(0);

jtag_clk <=  cclk_counter(4);

tdo_aux <= (flash_enable(5) and flash_tdo(5)) or 
	(flash_enable(4) and flash_tdo(4)) or (flash_enable(3) and flash_tdo(3)) or
	(flash_enable(2) and flash_tdo(2)) or (flash_enable(1) and flash_tdo(1)) or
	(flash_enable(0) and flash_tdo(0));


--MAQUINA DE ESTADOS JTAG

process (clk, local_reset)
begin
	if local_reset='1' then  
	  jtag_shift <= '0';
	  bits_to_send <= (others => '0');
	  jtag_end <= '0';
	  flash_tck <='0';
	  tdo_reg <= '0';
	  state <= wait_start;
	  

	elsif clk'event and clk='1' then
	  
	  case state is

	  when wait_start =>
 	    flash_tck <='0';
	    bits_to_send <= jtag_num_bits;
	    if jtag_start='1' then
	      state <= wait_phase0;
	      jtag_end <= '0';
	    end if;

	  when wait_phase0 =>
	    flash_tck <='0';
	    if jtag_clk='0' then
	      state <= wait_phase1;
	    end if;
  
	  when wait_phase1 =>
	    flash_tck <='0';
	    jtag_shift <= '0';
	    if jtag_clk='1' then	      
	      state <= send_clock;
	    end if;
  
	  when send_clock =>
	    flash_tck <='1';
	    if jtag_clk='0' then
		   bits_to_send <= bits_to_send -1;
	      state <= next_bit;
	      tdo_reg <= tdo_aux;
	    end if;

	  when next_bit =>
 	    flash_tck <='0';
	    jtag_shift <= '1';
	    if bits_to_send/="0000" then
		   state <= wait_phase1;
	    else
	      state <= jtag_exit;
	    end if;
  
	  when jtag_exit =>
	    jtag_shift <= '0';
	    jtag_end <= '1';
	    state <= wait_start;
  
	  end case;
	end if;
end process;
 
-- I2C, 1-wire, GOL y QPLL, PCA9564
--bits	description         acc	signal
--0	Enable I2C GOL lines     R/W	i2c_ce_gol
--1	Enable 1-Wire lines		R/W	i2c_ce_1wire
--2	GOL power off            R/W	gol_off
--3 	GOL ready                R	gol_ready
--4	QPLL error               R	qpll_error
--5	QPLL locked              R	qpll_locked

i2c_ce <= '0'     when add_high=PCA9564_add and cs='1' else '1';
i2c_rd <= etr     when add_high=PCA9564_add and cs='1' else '1'; 
i2c_wr <= not enw when add_high=PCA9564_add and cs='1' else '1';

process (clk, local_reset)
begin
	if local_reset='1' then 	
	  i2c_ce_gol <= '0';
	  i2c_ce_1wire <= '0';
	  gol_off_reg <= '0';  --dec10 COMIENZA ENCENDIDO!!!!! lo pongo a '0' en vez de '1' 
	elsif clk'event and clk='1' then
	  if add=i2c_add and cs='1' and enw='1' then 
	    i2c_ce_gol <= db_in (0) and not(db_in(1));
	    i2c_ce_1wire <= db_in(1);			  --en caso de duda habilita acceso para sensor
	    gol_off_reg <= db_in (2);       -- activo alto
	  end if;
	end if;
end process;


---DECEMBER 2010
gol_off <= gol_off_reg or not(pwgolcount(15));

process (clk, sysreset)
begin
	if sysreset='1' then 	
	   pwgolcount <= (others =>'0');
	elsif clk'event and clk='1' then
		if pwgolcount(15)='0' then
			pwgolcount <= pwgolcount + 1;
	   end if;
	end if;
end process;


--abril12  CUOF
process (clk, local_reset)
begin
	if local_reset='1' then 	
	  scl_r <= '1';
	elsif clk'event and clk='1' then
	  if add=i2c_cuof_scl and cs='1' and enw='1' then 	  --0x394 (14)
  	    scl_r <= db_in (0);
	  end if;
	end if;
end process;

--abril12  CUOF
process (clk, local_reset)
begin
	if local_reset='1' then 	
	  sda_r <= '1';
	elsif clk'event and clk='1' then				   --0x396 (16)
	  if add=i2c_cuof_sda and cs='1' and enw='1' then 
  	    sda_r <= db_in (0);
	  end if;
	end if;
end process;


end arch;
	
