vme_patch Project Status (11/01/2013 - 08:59:25)
Project File: | vme_patch.xise | Parser Errors: | No Errors
Module Name: | vme_patch | Implementation State: | Programming File Generated
Target Device: | xc6slx4-2tqg144 |

- Errors:

No Errors
Product Version: | ISE 13.3 |

- Warnings:

3 Warnings (0 new)
Design Goal: | Balanced |

- Routing Results:

All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

X 1 Failing Constraint
Environment: | System Settings |

- Final Timing Score:

200 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 180 | 4,800 | 3% |
Number used as Flip Flops | 180 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 238 | 2,400 | 9% |
Number used as logic | 236 | 2,400 | 9% |
Number using O6 output only | 156 |  |  |
Number using O5 output only | 20 |  |  |
Number using O5 and O6 | 60 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 0 | 1,200 | 0% |
Number used exclusively as route-thrus | 2 |  |  |
Number with same-slice register load | 1 |  |  |
Number with same-slice carry load | 1 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 117 | 600 | 19% |
Nummber of MUXCYs used | 24 | 1,200 | 2% |
Number of LUT Flip Flop pairs used | 266 |  |  |
Number with an unused Flip Flop | 107 | 266 | 40% |
Number with an unused LUT | 28 | 266 | 10% |
Number of fully used LUT-FF pairs | 131 | 266 | 49% |
Number of unique control sets | 23 |  |  |
Number of slice register sites lost to control set restrictions | 84 | 4,800 | 1% |
Number of bonded IOBs | 101 | 102 | 99% |
Number of LOCed IOBs | 101 | 101 | 100% |
IOB Flip Flops | 2 |  |  |
Number of RAMB16BWERs | 0 | 12 | 0% |
Number of RAMB8BWERs | 0 | 24 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 1 | 16 | 6% |
Number used as BUFGs | 1 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 2 | 200 | 1% |
Number used as ILOGIC2s | 2 |  |  |
Number used as ISERDES2s | 0 |  |  |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 8 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.58 |  |  |

Performance Summary | [-]
Final Timing Score: | 200 (Setup: 200, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | X 1 Failing Constraint |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | mié 30. oct 12:54:21 2013 | 0 | 3 Warnings (0 new) | 3 Infos (0 new)
Translation Report | Current | vie 1. nov 08:58:40 2013 | 0 | 0 | 0
Map Report | Current | vie 1. nov 08:58:51 2013 | 0 | 0 | 7 Infos (0 new)
Place and Route Report | Current | vie 1. nov 08:59:01 2013 | 0 | 0 | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | vie 1. nov 08:59:06 2013 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | vie 1. nov 08:59:15 2013 | 0 | 0 | 0

Secondary Reports | [-]
Report Name | Status | Generated
Locked Pin Constraints | Out of Date | vie 27. abr 12:55:50 2012
WebTalk Report | Current | vie 1. nov 08:59:16 2013
WebTalk Log File | Current | vie 1. nov 08:59:24 2013

Date Generated: 11/01/2013 - 08:59:25