Release 13.3 Map O.76xd (nt)
Xilinx Mapping Report File for Design 'vme_patch'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx4-tqg144-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o vme_patch_map.ncd vme_patch.ngd vme_patch.pcf 
Target Device  : xc6slx4
Target Package : tqg144
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Fri Nov 01 08:58:42 2013

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                   180 out of   4,800    3%
    Number used as Flip Flops:                 180
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        238 out of   2,400    9%
    Number used as logic:                      236 out of   2,400    9%
      Number using O6 output only:             156
      Number using O5 output only:              20
      Number using O5 and O6:                   60
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   1,200    0%
    Number used exclusively as route-thrus:      2
      Number with same-slice register load:      1
      Number with same-slice carry load:         1
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   117 out of     600   19%
  Nummber of MUXCYs used:                       24 out of   1,200    2%
  Number of LUT Flip Flop pairs used:          266
    Number with an unused Flip Flop:           107 out of     266   40%
    Number with an unused LUT:                  28 out of     266   10%
    Number of fully used LUT-FF pairs:         131 out of     266   49%
    Number of unique control sets:              23
    Number of slice register sites lost
      to control set restrictions:              84 out of   4,800    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       101 out of     102   99%
    Number of LOCed IOBs:                      101 out of     101  100%
    IOB Flip Flops:                              2

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      12    0%
  Number of RAMB8BWERs:                          0 out of      24    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
    Number used as BUFGs:                        1
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   2 out of     200    1%
    Number used as ILOGIC2s:                     2
    Number used as ISERDES2s:                    0
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of       8    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.58

Peak Memory Usage:  206 MB
Total REAL time to MAP completion:  9 secs 
Total CPU time to MAP completion:   8 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.

Section 3 - Informational
-------------------------
INFO:Security:54 - 'xc6slx4' is a WebPack part.
INFO:MapLib:564 - The following environment variables are currently set:
INFO:MapLib:591 - XIL_MAP_LOCWARN 	Value: 1
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| BRDSEL_J2<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<2>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<3>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<4>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<5>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<6>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<7>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<8>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<9>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<10>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| BRDSEL_J2<11>                      | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<0>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<1>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<2>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<3>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<4>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<5>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<6>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DOUT_J2<7>                         | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DoutDir                            | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| DoutOE                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| I2C_Add_p<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| I2C_Add_p<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| LEDS<0>                            | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| LEDS<1>                            | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| Read_J2                            | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| Reset_J2                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| SCL                                | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW | IFF          | PULLUP   |          |
| SDA                                | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW | IFF          | PULLUP   |          |
| SignalDetect_10<0>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_10<1>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_10<2>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_11<0>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_11<1>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_11<2>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_12<0>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_12<1>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_12<2>                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_1<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_1<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_1<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_2<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_2<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_2<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_3<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_3<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_3<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_4<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_4<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_4<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_5<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_5<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_5<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_6<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_6<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_6<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_7<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_7<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_7<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_8<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_8<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_8<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_9<0>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_9<1>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| SignalDetect_9<2>                  | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| Spare_J2                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| TP<0>                              | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| TP<1>                              | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| Vwrite                             | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| Write_J2                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| add_hold                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| add_mod_ok                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_1<0>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_1<1>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_1<2>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_1<3>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_2<5>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_2<6>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_2<7>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| add_p_2<8>                         | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| as                                 | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| brd_sel_16_p                       | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| clk                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| db<0>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| db<1>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| db<2>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| db<3>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| db<4>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| db<5>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| db<6>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| db<7>                              | IOB              | BIDIR     | LVCMOS25             |       | 12       | SLOW |              |          |          |
| ds0                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| ds1                                | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| dtack_p                            | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| g245_p                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| iack                               | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| iackin                             | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| iackout                            | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| irq<7>                             | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| lword                              | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.

For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
