library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;

entity rv_memadd is port(
     inc_add, acc_blk, as: in std_logic;
     add: in std_logic_vector(8 downto 0);
     madd: out std_logic_vector(8 downto 0)
     );
end rv_memadd;

architecture arch of rv_memadd is
signal add_aux: std_logic_vector (8 downto 0);
signal va_cnt: std_logic_vector (8 downto 0);

begin

--madd <= mem_pointer when acc_fifo='1' else
  --     add_aux + va_aux when acc_blk='1' else add;
madd <=  add_aux + va_cnt when acc_blk='1' else add;

process (inc_add, acc_blk,as)
begin
   if as='1' then
    va_cnt <= (others => '0');
    elsif inc_add'event and inc_add='1' then
       va_cnt <= va_cnt + 1;
     end if;
end process;

process(as)
begin
	if as'event and as='0' then
		add_aux <= add;
	else add_aux <= add_aux;
	end if;
end process;


end arch;
	
