library ieee;
use ieee.std_logic_1164.all;

entity rv_vmeblk is
     port (
	  clk: in std_logic;
     ds0, ds1, iack: in std_logic;
     write, brdsel24, lword: in std_logic;
     am: in std_logic_vector (5 downto 0);
     we, dtack, g245, oe, inc_add, acc_blk: out std_logic 
     );
end rv_vmeblk;

----------------------------------------------
-- ver esquema INTERFACE A24:D16 BLT ASYNCH --
----------------------------------------------

architecture arch of rv_vmeblk is
component ffrp port (
     d, clk, ce, cr, pr: in std_logic;
     q: out std_logic);
end component;

signal b1, b2: std_logic;
--signal b3, b4, b5: std_logic;
signal acc, accw, accr, blt: std_logic;
signal ds, one, zero, aux_dtack, dtack_aux: std_logic;
--signal not_ds: std_logic;
signal dsdly0, dsdly1: std_logic;

begin
one <= '1';
zero <= '0';
ds <= ds0 or ds1;
--not_ds <= not(ds);

-- A24, standard non-prileged block transfer, mod= $3B
blt <= '1' when am="111011" else '0';
acc <= not brdsel24 and lword and iack and blt;  -- D16
accr <= acc and write;
accw <= acc and not write;
--
--we <= not (not ds and accw and not b4 and b1); -- activo bajo
--dtack <= b3 or b4;            -- activo alto
--g245 <= not acc;              -- activo bajo
--oe <= not accr;               -- activo bajo
--inc_add <= b2 and (b3 nor b4); --> b2 and not dtack, activo alto
--
--fb1:  ffrp port map (clk => not_dsdly, d => accw, ce => one, cr => as, pr => zero, q => b1);
--fb2:  ffrp port map (clk => ds,    d => b5,   ce => one, cr => as, pr => zero, q => b2);
--fb3:  ffrp port map (clk => dsdly, d => accr, ce => one, cr => ds, pr => zero, q => b3);
--fb4:  ffrp port map (clk => dsdly, d => accw, ce => one, cr => ds, pr => zero, q => b4);
--fb5:  ffrp port map (clk => ds,    d => acc,  ce => one, cr => as, pr => zero, q => b5);
 
fc1:  ffrp port map (clk => clk,    d => ds0,  ce => one, cr => dsdly1, pr => zero, q => dsdly0);
fc2:  ffrp port map (clk => clk,    d => ds1,  ce => one, cr => dsdly1, pr => zero, q => dsdly1);
  
aux_dtack <= dsdly1 and acc;
--
we    <= not(b2); --active low
g245  <= ds or not(acc); --active low
oe    <= not(b1);      --active low

fq1:  ffrp port map (clk => dsdly0, d => accr, ce => one, cr => dsdly1, pr => zero, q => b1);
fq2:  ffrp port map (clk => dsdly0, d => accw, ce => one, cr => dsdly1, pr => zero, q => b2);
fq3:  ffrp port map (clk => aux_dtack, d => one, ce => one, cr => not(dsdly1), pr => zero, q => dtack_aux);

inc_add <= dsdly1 and not(dsdly0); 
   
dtack <= dtack_aux;
acc_blk <= acc;

end arch;
	
