library ieee;
use ieee.std_logic_1164.all;

entity stretch is port (
	clk_1, clk_2, din, reset: in std_logic;
	dout: out std_logic
	);		
end stretch;

architecture arch of stretch is
signal q1, q2, q3: std_logic;

begin

dout <= not q2;

process (clk_1, q3)
begin
	if q3='1' then
	  q1 <= '0';
	elsif clk_1'event and clk_1='1' then
	  if din='1' then 
	    q1 <= '1';
	  end if;
	end if;
end process;

process (clk_2, reset)
begin
	if reset='1' then
	  q2 <= '0';
	  q3 <= '0';
	elsif clk_2'event and clk_2='1' then
	  q2 <= q1;
	  q3 <= q2;
	end if;
end process;

end arch;



	
