# Xilinx CORE Generator 6.3i
# User = Cristina Fernandez
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in C:\CRIS\CMS\VHDL\PARA_FINAL\ceros_agosto\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=C:\CRIS\CMS\VHDL\PARA_FINAL\ceros_agosto
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=C:\CRIS\CMS\VHDL\PARA_FINAL\ceros_agosto
SETPROJECT .
Set current Project to C:\CRIS\CMS\VHDL\PARA_FINAL\ceros_agosto
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1164
XIPCPJSENDCORES spartan2e
