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FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_registros_1.vhd 2006/12/16.13:02:00
EN work/CR_REGISTROS \
      FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_registros_1.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_MISC \
      PB work/PACK
AR work/CR_REGISTROS/ARCH \
      FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_registros_1.vhd \
      EN work/CR_REGISTROS
FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/stretch.vhd 2005/03/03.17:46:02
EN work/STRETCH         FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/stretch.vhd \
      PB ieee/STD_LOGIC_1164
AR work/STRETCH/ARCH    FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/stretch.vhd \
      EN work/STRETCH
FL C:/DATOSLAB/VHDL/ROS_FINAL_AGOSTO/ceros_agosto/milib.vhd 2005/02/04.20:33:24
FL C:/DATOSLAB/VHDL/ROS_FINAL_AGOSTO/ceros_agosto/stretch.vhd 2005/03/02.23:46:02
FL c:/datoslab/vhdl/ceros_feb/cr_fifos.vhd 2005/02/08.12:35:18
FL C:/DATOSLAB/VHDL/PARA_FINAL/ceros_agosto/ceros_1.vhd 2006/12/28.09:56:14
FL C:/DATOSLAB/VHDL/ROS_madrid_abril/ceros_feb_abril/cr_ros_1.vhd 2006/04/28.11:43:54
FL C:/DATOSLAB/VHDL/ROS_madrid_abril/ceros_feb_abril/milib.vhd 2005/02/04.05:33:24
FL C:/DATOSLAB/VHDL/PARA_FINAL/ceros_agosto/cr_ros_cris.vhd 2006/12/16.13:56:54
FL C:/DATOSLAB/VHDL/ceros_feb/cr_fifos.vhd 2005/02/08.16:35:18
FL c:/datoslab/vhdl/ceros_feb/milib.vhd 2005/02/01.16:33:24
FL C:/DATOSLAB/VHDL/ceros_feb/ceros_1.vhd 2006/03/15.02:13:00
FL c:/datoslab/vhdl/ceros_feb/stretch.vhd 2005/02/27.19:46:02
FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/ceros_1.vhd 2006/12/28.10:56:14
EN work/CEROS           FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/ceros_1.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_MISC \
      PB work/PACK
AR work/CEROS/ARCH      FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/ceros_1.vhd \
      EN work/CEROS     CP STRETCH        CP IBUFG          CP CLKDLLE        CP BUFG \
      CP OBUF           CP CR_REGISTROS   CP CR_FIFOS       CP CR_ROS
FL C:/DATOSLAB/VHDL/ROS_FINAL_AGOSTO/ceros_agosto/ceros_1.vhd 2006/08/08.18:24:00
FL C:/DATOSLAB/VHDL/ROS_madrid_abril/ceros_feb_abril/stretch.vhd 2005/03/02.08:46:02
FL C:/DATOSLAB/VHDL/ceros_feb/milib.vhd 2005/02/01.20:33:24
FL C:/DATOSLAB/VHDL/ceros_feb/stretch.vhd 2005/02/27.23:46:02
FL C:/DATOSLAB/VHDL/ROS_FINAL_AGOSTO/ceros_agosto/cr_ros_cris.vhd 2006/08/08.19:43:22
FL c:/datoslab/vhdl/ceros_feb/cr_ros_1.vhd 2006/01/05.19:18:52
FL C:/DATOSLAB/VHDL/ROS_madrid_abril/ceros_feb_abril/cr_fifos.vhd 2006/04/26.11:31:54
FL C:/DATOSLAB/VHDL/ROS_madrid_abril/ceros_feb_abril/cr_registros_1.vhd 2006/05/15.11:19:14
FL C:/DATOSLAB/VHDL/ROS_FINAL_AGOSTO/ceros_agosto/cr_registros_1.vhd 2006/08/08.18:24:00
FL C:/DATOSLAB/VHDL/PARA_FINAL/ceros_agosto/cr_registros_1.vhd 2006/12/16.12:02:00
FL C:/DATOSLAB/VHDL/PARA_FINAL/ceros_agosto/cr_fifos.vhd 2006/04/26.11:31:54
FL C:/DATOSLAB/VHDL/PARA_FINAL/ceros_agosto/stretch.vhd 2005/03/03.16:46:02
FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_ros_cris.vhd 2006/12/16.14:56:54
EN work/CR_ROS          FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_ros_cris.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_MISC \
      PB ieee/STD_LOGIC_ARITH PB work/PACK
AR work/CR_ROS/ARCH     FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_ros_cris.vhd \
      EN work/CR_ROS
FL C:/DATOSLAB/VHDL/ceros_feb/cr_ros_1.vhd 2006/01/05.23:18:52
FL c:/datoslab/vhdl/ceros_feb/cr_registros.vhd 2005/12/10.18:28:44
FL c:/datoslab/vhdl/ceros_feb/ceros_1.vhd 2005/12/29.10:54:14
FL C:/DATOSLAB/VHDL/ceros_feb/cr_registros.vhd 2006/03/15.02:28:18
FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_fifos.vhd 2006/04/26.11:31:54
EN work/CR_FIFOS        FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_fifos.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_MISC \
      PB work/PACK
AR work/CR_FIFOS/ARCH   FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/cr_fifos.vhd \
      EN work/CR_FIFOS
FL C:/DATOSLAB/VHDL/ROS_madrid_abril/ceros_feb_abril/cr_ros_cris.vhd 2006/05/17.09:41:32
FL C:/DATOSLAB/VHDL/ROS_madrid_abril/ceros_feb_abril/ceros_1.vhd 2006/05/15.11:16:30
FL C:/DATOSLAB/VHDL/ROS_FINAL_AGOSTO/ceros_agosto/cr_fifos.vhd 2006/04/26.11:31:54
FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/milib.vhd 2005/02/05.14:33:24
PH work/PACK            FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/milib.vhd \
      PB ieee/STD_LOGIC_1164
PB work/PACK            FL C:/CRIS/CMS/VHDL/PARA_FINAL/ceros_agosto/milib.vhd \
      PH work/PACK
FL C:/DATOSLAB/VHDL/PARA_FINAL/ceros_agosto/milib.vhd 2005/02/05.13:33:24
