JDF G
// Created by Project Navigator ver 1.0
PROJECT ceros_feb
DESIGN ceros_feb
DEVFAM spartan2e
DEVFAMTIME 1140627359
DEVICE xc2s50e
DEVICETIME 1140627359
DEVPKG ft256
DEVPKGTIME 1140627359
DEVSPEED -7
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE stretch.vhd
SOURCE milib.vhd
SOURCE ceros_1.vhd
SOURCE cr_fifos.vhd
SOURCE cr_registros_1.vhd
SOURCE cr_ros_cris.vhd
DEPASSOC ceros ceros.ucf
[Normal]
xilxBitgCfg_GenOpt_LogicAllocFile=xstvhd, spartan2e, VHDL.t_bitFile, 1160161539, True
xilxBitgCfg_GenOpt_MaskFile=xstvhd, spartan2e, VHDL.t_bitFile, 1160161539, True
xilxBitgCfg_GenOpt_ReadBack=xstvhd, spartan2e, VHDL.t_bitFile, 1160161539, True
xilxBitgReadBk_GenBitStr=xstvhd, spartan2e, VHDL.t_bitFile, 1160161539, True
xilxBitgStart_Clk=xstvhd, spartan2e, VHDL.t_bitFile, 1171132302, JTAG Clock
xilxBitgStart_Clk_Done=xstvhd, spartan2e, VHDL.t_bitFile, 1141381865, 4
xilxBitgStart_Clk_EnOut=xstvhd, spartan2e, VHDL.t_bitFile, 1141381865, Done
xilxBitgStart_Clk_RelSet=xstvhd, spartan2e, VHDL.t_bitFile, 1141381865, Done
xilxBitgStart_Clk_WrtEn=xstvhd, spartan2e, VHDL.t_bitFile, 1141381865, Done
[STATUS-ALL]
ceros.ncdFile=WARNINGS,1202760519
ceros.ngcFile=WARNINGS,1202760499
ceros.ngdFile=WARNINGS,1202760514
[STRATEGY-LIST]
Normal=True
