-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 7 -pcf ceros.pcf -ngm ceros.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim ceros_map.ncd ceros_map.vhd 
-- Input file    : ceros_map.ncd
-- Output file   : ceros_map.vhd
-- Design name   : ceros
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2s50eft256-7 (PRODUCTION 1.17 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity ceros is
  port (
    sff : out STD_LOGIC; 
    fmrs : out STD_LOGIC; 
    lives_p : out STD_LOGIC; 
    txena_p : out STD_LOGIC; 
    fsi : out STD_LOGIC; 
    doneout : out STD_LOGIC; 
    wclkena_p : out STD_LOGIC; 
    fld : out STD_LOGIC; 
    fsen : out STD_LOGIC; 
    clk20_p : out STD_LOGIC; 
    recoff_p : out STD_LOGIC; 
    locked_p : out STD_LOGIC; 
    spaf_p : out STD_LOGIC; 
    ceros_done_p : out STD_LOGIC; 
    clkin_p : in STD_LOGIC := 'X'; 
    valen : in STD_LOGIC := 'X'; 
    donein : in STD_LOGIC := 'X'; 
    mrs : in STD_LOGIC := 'X'; 
    enw : in STD_LOGIC := 'X'; 
    etr_x : in STD_LOGIC := 'X'; 
    vspare_1 : in STD_LOGIC := 'X'; 
    vspare_0 : in STD_LOGIC := 'X'; 
    load_paepaf : in STD_LOGIC := 'X'; 
    cspare_1 : in STD_LOGIC := 'X'; 
    cspare_0 : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    cs : in STD_LOGIC := 'X'; 
    token : in STD_LOGIC := 'X'; 
    clk_slow : in STD_LOGIC := 'X'; 
    led : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    ren : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    hasul : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    tp : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    oe : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    db : inout STD_LOGIC_VECTOR ( 15 downto 0 ); 
    lock : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    add : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    par : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    paf : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    fout : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    ff : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    ef : in STD_LOGIC_VECTOR ( 5 downto 0 ); 
    ceros_id : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    evid : in STD_LOGIC_VECTOR ( 11 downto 0 ) 
  );
end ceros;

architecture Structure of ceros is
  signal CLK : STD_LOGIC; 
  signal enw1 : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal U1_n0010 : STD_LOGIC; 
  signal N44072 : STD_LOGIC; 
  signal reset_largo : STD_LOGIC; 
  signal I18_N1762 : STD_LOGIC; 
  signal N44074 : STD_LOGIC; 
  signal N44076 : STD_LOGIC; 
  signal N44078 : STD_LOGIC; 
  signal U1_n0009 : STD_LOGIC; 
  signal N44080 : STD_LOGIC; 
  signal N44082 : STD_LOGIC; 
  signal N44084 : STD_LOGIC; 
  signal N44086 : STD_LOGIC; 
  signal mrs_IBUF : STD_LOGIC; 
  signal N44088 : STD_LOGIC; 
  signal N44090 : STD_LOGIC; 
  signal ef_0_IBUF : STD_LOGIC; 
  signal ef_1_IBUF : STD_LOGIC; 
  signal ef_2_IBUF : STD_LOGIC; 
  signal ef_3_IBUF : STD_LOGIC; 
  signal ef_4_IBUF : STD_LOGIC; 
  signal ef_5_IBUF : STD_LOGIC; 
  signal ff_0_IBUF : STD_LOGIC; 
  signal ff_1_IBUF : STD_LOGIC; 
  signal ff_2_IBUF : STD_LOGIC; 
  signal ff_3_IBUF : STD_LOGIC; 
  signal ff_4_IBUF : STD_LOGIC; 
  signal ff_5_IBUF : STD_LOGIC; 
  signal add_0_IBUF : STD_LOGIC; 
  signal add_1_IBUF : STD_LOGIC; 
  signal add_2_IBUF : STD_LOGIC; 
  signal add_3_IBUF : STD_LOGIC; 
  signal add_4_IBUF : STD_LOGIC; 
  signal add_5_IBUF : STD_LOGIC; 
  signal load_paepaf_IBUF : STD_LOGIC; 
  signal ceros_id_0_IBUF : STD_LOGIC; 
  signal ceros_id_1_IBUF : STD_LOGIC; 
  signal vspare_0_IBUF : STD_LOGIC; 
  signal vspare_1_IBUF : STD_LOGIC; 
  signal spaf_p_OBUF : STD_LOGIC; 
  signal oe_0_OBUF : STD_LOGIC; 
  signal oe_1_OBUF : STD_LOGIC; 
  signal oe_2_OBUF : STD_LOGIC; 
  signal oe_3_OBUF : STD_LOGIC; 
  signal oe_4_OBUF : STD_LOGIC; 
  signal oe_5_OBUF : STD_LOGIC; 
  signal CLKIN : STD_LOGIC; 
  signal clk_slow_BUFGP_IBUFG : STD_LOGIC; 
  signal CLK0 : STD_LOGIC; 
  signal CLK20 : STD_LOGIC; 
  signal LOCKED : STD_LOGIC; 
  signal clk_slow_BUFGP : STD_LOGIC; 
  signal U1_I50_N1762 : STD_LOGIC; 
  signal U1_I43_N1762 : STD_LOGIC; 
  signal lock_5_IBUF : STD_LOGIC; 
  signal U1_I51_N1762 : STD_LOGIC; 
  signal lock_4_IBUF : STD_LOGIC; 
  signal lock_3_IBUF : STD_LOGIC; 
  signal lock_2_IBUF : STD_LOGIC; 
  signal lock_1_IBUF : STD_LOGIC; 
  signal lock_0_IBUF : STD_LOGIC; 
  signal U1_I44_N1762 : STD_LOGIC; 
  signal U1_dis_evid_wrong : STD_LOGIC; 
  signal U1_I52_N1762 : STD_LOGIC; 
  signal U1_I60_N1762 : STD_LOGIC; 
  signal U1_dis_paf_warn : STD_LOGIC; 
  signal U1_dis_ffreg_mask : STD_LOGIC; 
  signal U1_dis_timo_mask : STD_LOGIC; 
  signal U1_dis_hul_mask : STD_LOGIC; 
  signal U1_dis_maxw_mask : STD_LOGIC; 
  signal U1_I45_N1762 : STD_LOGIC; 
  signal U1_I53_N1762 : STD_LOGIC; 
  signal U1_I61_N1762 : STD_LOGIC; 
  signal U1_I46_N1762 : STD_LOGIC; 
  signal paf_5_IBUF : STD_LOGIC; 
  signal U1_I54_N1762 : STD_LOGIC; 
  signal U1_I62_N1762 : STD_LOGIC; 
  signal paf_4_IBUF : STD_LOGIC; 
  signal paf_3_IBUF : STD_LOGIC; 
  signal paf_2_IBUF : STD_LOGIC; 
  signal paf_1_IBUF : STD_LOGIC; 
  signal paf_0_IBUF : STD_LOGIC; 
  signal U1_I47_N1762 : STD_LOGIC; 
  signal U1_I55_N1762 : STD_LOGIC; 
  signal U1_I63_N1762 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal U1_I48_N1762 : STD_LOGIC; 
  signal U1_I56_N1762 : STD_LOGIC; 
  signal U1_I64_N1762 : STD_LOGIC; 
  signal U1_resynch_maxw : STD_LOGIC; 
  signal U1_resynch_FF : STD_LOGIC; 
  signal U1_warn_PAF : STD_LOGIC; 
  signal U1_resynch_evidmis : STD_LOGIC; 
  signal U1_resynch_to : STD_LOGIC; 
  signal U1_I49_N1762 : STD_LOGIC; 
  signal U1_I57_N1762 : STD_LOGIC; 
  signal U1_I65_N1762 : STD_LOGIC; 
  signal U1_dis_errorw : STD_LOGIC; 
  signal U1_dis_evid_bloq : STD_LOGIC; 
  signal U1_dis_head_trail : STD_LOGIC; 
  signal U1_I58_N1762 : STD_LOGIC; 
  signal U1_I66_N1762 : STD_LOGIC; 
  signal U1_I59_N1762 : STD_LOGIC; 
  signal U1_I67_N1762 : STD_LOGIC; 
  signal U1_recoff : STD_LOGIC; 
  signal U3_n0216 : STD_LOGIC; 
  signal U3_sel_read_5_1 : STD_LOGIC; 
  signal U3_state_FFd31 : STD_LOGIC; 
  signal CHOICE1026 : STD_LOGIC; 
  signal CHOICE996 : STD_LOGIC; 
  signal CHOICE1011 : STD_LOGIC; 
  signal CHOICE981 : STD_LOGIC; 
  signal U3_cr_ros_n0151_1_cyo : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal U3_cr_ros_n0151_3_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0151_5_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0151_7_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0151_9_cyo : STD_LOGIC; 
  signal U2_n0131 : STD_LOGIC; 
  signal U2_disparity_inst_cy_1 : STD_LOGIC; 
  signal enw_dispar : STD_LOGIC; 
  signal U2_disparity_inst_lut3_0 : STD_LOGIC; 
  signal reset_IBUF_1 : STD_LOGIC; 
  signal U2_disparity_inst_cy_3 : STD_LOGIC; 
  signal enw2 : STD_LOGIC; 
  signal N44542 : STD_LOGIC; 
  signal U2_disparity_inst_cy_5 : STD_LOGIC; 
  signal U2_disparity_inst_cy_7 : STD_LOGIC; 
  signal U2_disparity_inst_cy_9 : STD_LOGIC; 
  signal U2_disparity_inst_cy_11 : STD_LOGIC; 
  signal N44092 : STD_LOGIC; 
  signal U2_disparity_inst_cy_13 : STD_LOGIC; 
  signal N44094 : STD_LOGIC; 
  signal N44096 : STD_LOGIC; 
  signal U2_disparity_inst_cy_15 : STD_LOGIC; 
  signal N44098 : STD_LOGIC; 
  signal N44100 : STD_LOGIC; 
  signal N44102 : STD_LOGIC; 
  signal parcheck : STD_LOGIC; 
  signal CHOICE200 : STD_LOGIC; 
  signal U3_Neq_stage_cyo1 : STD_LOGIC; 
  signal U3_n0050 : STD_LOGIC; 
  signal U3_cr_ros_n0251_1_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0251_3_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0251_5_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0251_7_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0251_9_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0251_11_cyo : STD_LOGIC; 
  signal U3_n0242 : STD_LOGIC; 
  signal U3_time_start : STD_LOGIC; 
  signal U3_fmt_error_ff_2_1_Q : STD_LOGIC; 
  signal soft_reset1_1 : STD_LOGIC; 
  signal U3_time_out : STD_LOGIC; 
  signal U3_Eq_stage_cyo1 : STD_LOGIC; 
  signal evid_0_IBUF : STD_LOGIC; 
  signal evid_1_IBUF : STD_LOGIC; 
  signal evid_2_IBUF : STD_LOGIC; 
  signal evid_3_IBUF : STD_LOGIC; 
  signal U3_Eq_stage_cyo3 : STD_LOGIC; 
  signal evid_4_IBUF : STD_LOGIC; 
  signal evid_5_IBUF : STD_LOGIC; 
  signal evid_6_IBUF : STD_LOGIC; 
  signal evid_7_IBUF : STD_LOGIC; 
  signal U3_n0150 : STD_LOGIC; 
  signal evid_8_IBUF : STD_LOGIC; 
  signal evid_9_IBUF : STD_LOGIC; 
  signal evid_10_IBUF : STD_LOGIC; 
  signal evid_11_IBUF : STD_LOGIC; 
  signal U2_loadcnt_LPM_COUNTER_2_n0002_1_cyo : STD_LOGIC; 
  signal U2_loadcnt_LPM_COUNTER_2_n0002_3_cyo : STD_LOGIC; 
  signal U1_n0177 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_1 : STD_LOGIC; 
  signal U1_enw_paf_counter1_3 : STD_LOGIC; 
  signal U1_enw_paf_counter : STD_LOGIC; 
  signal soft_reset : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_3 : STD_LOGIC; 
  signal U1_enw_paf_counter1_2 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_5 : STD_LOGIC; 
  signal U1_enw_paf_counter1_1 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_7 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_9 : STD_LOGIC; 
  signal U1_enw_paf_counter1_4 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_11 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_13 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_15 : STD_LOGIC; 
  signal U1_n0183 : STD_LOGIC; 
  signal U1_n0178 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_1 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_3 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_5 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_7 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_9 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_11 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_13 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_15 : STD_LOGIC; 
  signal U1_n0185 : STD_LOGIC; 
  signal U1_n0179 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_1 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_3 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_5 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_7 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_9 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_11 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_13 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_15 : STD_LOGIC; 
  signal U1_n0187 : STD_LOGIC; 
  signal U1_n0180 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_1 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_3 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_5 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_7 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_9 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_11 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_9 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_13 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_15 : STD_LOGIC; 
  signal U1_n0189 : STD_LOGIC; 
  signal U1_n0181 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_1 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_3 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_5 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_7 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_9 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_11 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_13 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_15 : STD_LOGIC; 
  signal U1_n0191 : STD_LOGIC; 
  signal U1_n0182 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_1 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_3 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_5 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_7 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_9 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_11 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_13 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_15 : STD_LOGIC; 
  signal U3_cr_ros_n0121_1_cyo : STD_LOGIC; 
  signal U3_cr_ros_n0121_3_cyo : STD_LOGIC; 
  signal U3_state_FFd14 : STD_LOGIC; 
  signal U3_trailer_reg_6_Q : STD_LOGIC; 
  signal U3_state_FFd36_In : STD_LOGIC; 
  signal CHOICE808 : STD_LOGIC; 
  signal U3_state_FFd13_In : STD_LOGIC; 
  signal CHOICE814 : STD_LOGIC; 
  signal N44320 : STD_LOGIC; 
  signal U3_n0102_6_44_SW0_O : STD_LOGIC; 
  signal CHOICE818 : STD_LOGIC; 
  signal CHOICE489 : STD_LOGIC; 
  signal CHOICE493 : STD_LOGIC; 
  signal U3_read_fifo_dir : STD_LOGIC; 
  signal U3_n009899_O : STD_LOGIC; 
  signal U3_this_ef23_1 : STD_LOGIC; 
  signal CHOICE482 : STD_LOGIC; 
  signal U3_N31621 : STD_LOGIC; 
  signal valen_IBUF : STD_LOGIC; 
  signal CHOICE683 : STD_LOGIC; 
  signal CHOICE686 : STD_LOGIC; 
  signal CHOICE689 : STD_LOGIC; 
  signal read : STD_LOGIC; 
  signal U1_per_fifo : STD_LOGIC; 
  signal U3_state_FFd10 : STD_LOGIC; 
  signal U3_N31683 : STD_LOGIC; 
  signal fout_6_IBUF : STD_LOGIC; 
  signal U3_N31172 : STD_LOGIC; 
  signal U3_n0102_6_1_O : STD_LOGIC; 
  signal U3_state_FFd13 : STD_LOGIC; 
  signal N39317 : STD_LOGIC; 
  signal U3_fmt_error_ff_2_3_Q : STD_LOGIC; 
  signal fout_8_IBUF : STD_LOGIC; 
  signal U3_N31677 : STD_LOGIC; 
  signal CHOICE709 : STD_LOGIC; 
  signal CHOICE712 : STD_LOGIC; 
  signal CHOICE715 : STD_LOGIC; 
  signal fout_7_IBUF : STD_LOGIC; 
  signal U3_N31183 : STD_LOGIC; 
  signal U3_n0102_7_1_O : STD_LOGIC; 
  signal CHOICE703 : STD_LOGIC; 
  signal CHOICE679 : STD_LOGIC; 
  signal CHOICE676 : STD_LOGIC; 
  signal N39520 : STD_LOGIC; 
  signal N44314 : STD_LOGIC; 
  signal U3_N31661 : STD_LOGIC; 
  signal N44350 : STD_LOGIC; 
  signal N44348 : STD_LOGIC; 
  signal CHOICE651 : STD_LOGIC; 
  signal fout_5_IBUF : STD_LOGIC; 
  signal U3_N31709 : STD_LOGIC; 
  signal U3_trailer_reg_5_Q : STD_LOGIC; 
  signal CHOICE625 : STD_LOGIC; 
  signal U3_n0102_5_124_SW0_O : STD_LOGIC; 
  signal fout_9_IBUF : STD_LOGIC; 
  signal CHOICE723 : STD_LOGIC; 
  signal CHOICE726 : STD_LOGIC; 
  signal U3_n0102_9_21_O : STD_LOGIC; 
  signal N44356 : STD_LOGIC; 
  signal N44354 : STD_LOGIC; 
  signal U3_this_ef23_2 : STD_LOGIC; 
  signal U3_n009971_O : STD_LOGIC; 
  signal CHOICE463 : STD_LOGIC; 
  signal N44490 : STD_LOGIC; 
  signal U3_txena_dir : STD_LOGIC; 
  signal CHOICE919 : STD_LOGIC; 
  signal CHOICE948 : STD_LOGIC; 
  signal fout_1_IBUF : STD_LOGIC; 
  signal U3_n0102_1_1_O : STD_LOGIC; 
  signal CHOICE861 : STD_LOGIC; 
  signal fout_2_IBUF : STD_LOGIC; 
  signal U3_n0102_2_1_O : STD_LOGIC; 
  signal CHOICE915 : STD_LOGIC; 
  signal fout_3_IBUF : STD_LOGIC; 
  signal U3_n0102_3_1_O : STD_LOGIC; 
  signal CHOICE783 : STD_LOGIC; 
  signal fout_4_IBUF : STD_LOGIC; 
  signal U3_n0102_4_1_O : STD_LOGIC; 
  signal CHOICE801 : STD_LOGIC; 
  signal U3_n0240 : STD_LOGIC; 
  signal enw_maxw : STD_LOGIC; 
  signal U1_N29954 : STD_LOGIC; 
  signal U1_N30021 : STD_LOGIC; 
  signal enw_timed_out : STD_LOGIC; 
  signal U1_N29930 : STD_LOGIC; 
  signal enw_evid_mis : STD_LOGIC; 
  signal U3_state_FFd23 : STD_LOGIC; 
  signal U3_state_FFd22 : STD_LOGIC; 
  signal U3_error_evid : STD_LOGIC; 
  signal U3_n0241 : STD_LOGIC; 
  signal U2_n0096 : STD_LOGIC; 
  signal enw_word_par : STD_LOGIC; 
  signal U3_n0252 : STD_LOGIC; 
  signal U3_n0239 : STD_LOGIC; 
  signal U3_state_FFd9 : STD_LOGIC; 
  signal U3_state_FFd4 : STD_LOGIC; 
  signal U3_state_FFd5 : STD_LOGIC; 
  signal U3_state_FFd3 : STD_LOGIC; 
  signal U3_N31130 : STD_LOGIC; 
  signal U3_trailer_reg_13_Q : STD_LOGIC; 
  signal fout_13_IBUF : STD_LOGIC; 
  signal U3_N31845 : STD_LOGIC; 
  signal U3_trailer_reg_12_Q : STD_LOGIC; 
  signal fout_12_IBUF : STD_LOGIC; 
  signal U3_state_FFd8 : STD_LOGIC; 
  signal U3_n0049 : STD_LOGIC; 
  signal U3_state_FFd6 : STD_LOGIC; 
  signal U3_trailer_reg_1_Q : STD_LOGIC; 
  signal U3_trailer_reg_14_Q : STD_LOGIC; 
  signal fout_14_IBUF : STD_LOGIC; 
  signal U3_N31919 : STD_LOGIC; 
  signal CHOICE335 : STD_LOGIC; 
  signal N44456 : STD_LOGIC; 
  signal CHOICE741 : STD_LOGIC; 
  signal CHOICE748 : STD_LOGIC; 
  signal U3_N31548 : STD_LOGIC; 
  signal U3_n0102_10_49_SW0_O : STD_LOGIC; 
  signal CHOICE758 : STD_LOGIC; 
  signal CHOICE765 : STD_LOGIC; 
  signal U3_n0102_11_46_SW0_O : STD_LOGIC; 
  signal U3_state_FFd16 : STD_LOGIC; 
  signal U3_N31671 : STD_LOGIC; 
  signal U3_n0102_12_5_O : STD_LOGIC; 
  signal N44362 : STD_LOGIC; 
  signal N44360 : STD_LOGIC; 
  signal CHOICE837 : STD_LOGIC; 
  signal CHOICE618 : STD_LOGIC; 
  signal U3_n0102_13_51_O : STD_LOGIC; 
  signal N44486 : STD_LOGIC; 
  signal U3_N31479 : STD_LOGIC; 
  signal CHOICE881 : STD_LOGIC; 
  signal U3_n0102_14_85_O : STD_LOGIC; 
  signal U3_state_FFd33 : STD_LOGIC; 
  signal fout_15_IBUF : STD_LOGIC; 
  signal N44586 : STD_LOGIC; 
  signal U3_n0102_15_68_O : STD_LOGIC; 
  signal U3_N31146 : STD_LOGIC; 
  signal U3_N31862 : STD_LOGIC; 
  signal U1_N29937 : STD_LOGIC; 
  signal U1_n0088 : STD_LOGIC; 
  signal U3_n0253 : STD_LOGIC; 
  signal CHOICE661 : STD_LOGIC; 
  signal U3_state_FFd40 : STD_LOGIC; 
  signal CHOICE659 : STD_LOGIC; 
  signal U3_n011015_O : STD_LOGIC; 
  signal U3_N31536 : STD_LOGIC; 
  signal N44328 : STD_LOGIC; 
  signal CHOICE520 : STD_LOGIC; 
  signal U3_this_hasunlock9_O : STD_LOGIC; 
  signal CHOICE526 : STD_LOGIC; 
  signal U3_state_FFd25 : STD_LOGIC; 
  signal U3_n010417_O : STD_LOGIC; 
  signal U3_N31790 : STD_LOGIC; 
  signal N44470 : STD_LOGIC; 
  signal U3_trail : STD_LOGIC; 
  signal N39701 : STD_LOGIC; 
  signal U3_state_FFd29 : STD_LOGIC; 
  signal N44282 : STD_LOGIC; 
  signal CHOICE601 : STD_LOGIC; 
  signal U3_N31572 : STD_LOGIC; 
  signal CHOICE590 : STD_LOGIC; 
  signal U3_n0218 : STD_LOGIC; 
  signal CHOICE596 : STD_LOGIC; 
  signal U3_n010527_O : STD_LOGIC; 
  signal U3_N31192 : STD_LOGIC; 
  signal U3_n010634_O : STD_LOGIC; 
  signal U3_n010734_O : STD_LOGIC; 
  signal U3_n010834_O : STD_LOGIC; 
  signal U3_N31564 : STD_LOGIC; 
  signal N39571 : STD_LOGIC; 
  signal N44430 : STD_LOGIC; 
  signal U3_N31808 : STD_LOGIC; 
  signal N44340 : STD_LOGIC; 
  signal CHOICE986 : STD_LOGIC; 
  signal U2_n0132 : STD_LOGIC; 
  signal enw_paf_value : STD_LOGIC; 
  signal U1_n0090 : STD_LOGIC; 
  signal U3_state_FFd27 : STD_LOGIC; 
  signal U3_state_FFd28 : STD_LOGIC; 
  signal CHOICE556 : STD_LOGIC; 
  signal U3_state_FFd34 : STD_LOGIC; 
  signal tp_2_OBUF : STD_LOGIC; 
  signal U3_state_FFd18 : STD_LOGIC; 
  signal U3_state_FFd11 : STD_LOGIC; 
  signal U3_state_FFd7 : STD_LOGIC; 
  signal U3_Ker31546_SW0_O : STD_LOGIC; 
  signal U3_state_FFd15 : STD_LOGIC; 
  signal U3_Ker31554_SW1_O : STD_LOGIC; 
  signal U3_state_FFd19 : STD_LOGIC; 
  signal U3_N31556 : STD_LOGIC; 
  signal U3_n009536_O : STD_LOGIC; 
  signal CHOICE580 : STD_LOGIC; 
  signal U3_n024317_O : STD_LOGIC; 
  signal CHOICE428 : STD_LOGIC; 
  signal U3_n0243 : STD_LOGIC; 
  signal cs_IBUF : STD_LOGIC; 
  signal N39677 : STD_LOGIC; 
  signal N44255 : STD_LOGIC; 
  signal CHOICE574 : STD_LOGIC; 
  signal CHOICE570 : STD_LOGIC; 
  signal U3_ros_done : STD_LOGIC; 
  signal U1_n0092 : STD_LOGIC; 
  signal U3_N31504 : STD_LOGIC; 
  signal N44366 : STD_LOGIC; 
  signal CHOICE554 : STD_LOGIC; 
  signal U3_Ker3114418_SW0_O : STD_LOGIC; 
  signal fout_0_IBUF : STD_LOGIC; 
  signal U3_N31636 : STD_LOGIC; 
  signal CHOICE771 : STD_LOGIC; 
  signal U3_Ker3112814_O : STD_LOGIC; 
  signal N44324 : STD_LOGIC; 
  signal N44434 : STD_LOGIC; 
  signal U3_N31161 : STD_LOGIC; 
  signal U3_N31900 : STD_LOGIC; 
  signal U3_Ker31659_SW3_O : STD_LOGIC; 
  signal N39486 : STD_LOGIC; 
  signal N44422 : STD_LOGIC; 
  signal U3_state_FFd27_1 : STD_LOGIC; 
  signal U3_N31111 : STD_LOGIC; 
  signal U3_state_FFd38 : STD_LOGIC; 
  signal U3_state_FFd35 : STD_LOGIC; 
  signal U3_N31761 : STD_LOGIC; 
  signal CHOICE561 : STD_LOGIC; 
  signal CHOICE564 : STD_LOGIC; 
  signal U3_state_FFd12 : STD_LOGIC; 
  signal N38705 : STD_LOGIC; 
  signal U3_state_FFd24 : STD_LOGIC; 
  signal U3_state_FFd20 : STD_LOGIC; 
  signal U3_state_FFd21 : STD_LOGIC; 
  signal U3_state_FFd17 : STD_LOGIC; 
  signal N44590 : STD_LOGIC; 
  signal U3_trailer_reg_0_Q : STD_LOGIC; 
  signal U3_state_FFd32 : STD_LOGIC; 
  signal N44662 : STD_LOGIC; 
  signal U3_this_dontread : STD_LOGIC; 
  signal CHOICE440 : STD_LOGIC; 
  signal U3_state_FFd39 : STD_LOGIC; 
  signal U3_state_FFd32_In30_SW0_O : STD_LOGIC; 
  signal U3_state_FFd26 : STD_LOGIC; 
  signal U3_state_FFd27_In : STD_LOGIC; 
  signal U3_N31694 : STD_LOGIC; 
  signal CHOICE277 : STD_LOGIC; 
  signal CHOICE273 : STD_LOGIC; 
  signal U3_state_FFd30 : STD_LOGIC; 
  signal U3_N31940 : STD_LOGIC; 
  signal U3_N31235 : STD_LOGIC; 
  signal U3_N31911 : STD_LOGIC; 
  signal CHOICE970 : STD_LOGIC; 
  signal U3_n0096_2_20_O : STD_LOGIC; 
  signal U3_N31219 : STD_LOGIC; 
  signal N44215 : STD_LOGIC; 
  signal CHOICE954 : STD_LOGIC; 
  signal U3_n0096_3_9_O : STD_LOGIC; 
  signal U2_n0114 : STD_LOGIC; 
  signal enw_byte_par0 : STD_LOGIC; 
  signal U2_n0097 : STD_LOGIC; 
  signal enw_byte_par1 : STD_LOGIC; 
  signal fout_11_IBUF : STD_LOGIC; 
  signal fout_10_IBUF : STD_LOGIC; 
  signal U3_trailer_reg_3_Q : STD_LOGIC; 
  signal U3_trailer_reg_2_Q : STD_LOGIC; 
  signal U3_trailer_reg_4_Q : STD_LOGIC; 
  signal U3_trailer_reg_7_Q : STD_LOGIC; 
  signal U3_trailer_reg_9_Q : STD_LOGIC; 
  signal U3_trailer_reg_8_Q : STD_LOGIC; 
  signal U3_N31749 : STD_LOGIC; 
  signal U3_N31256 : STD_LOGIC; 
  signal CHOICE1036 : STD_LOGIC; 
  signal N44666 : STD_LOGIC; 
  signal N41351 : STD_LOGIC; 
  signal U3_N31407 : STD_LOGIC; 
  signal U3_n0102_8_30_SW1_O : STD_LOGIC; 
  signal U3_n0102_8_30_SW0_O : STD_LOGIC; 
  signal U3_n0102_9_30_SW1_O : STD_LOGIC; 
  signal U3_n0102_9_30_SW0_O : STD_LOGIC; 
  signal U3_n0102_12_8_SW1_O : STD_LOGIC; 
  signal U3_n0102_12_8_SW0_O : STD_LOGIC; 
  signal N44426 : STD_LOGIC; 
  signal U3_state_FFd37 : STD_LOGIC; 
  signal U3_Ker317234_O : STD_LOGIC; 
  signal N44290 : STD_LOGIC; 
  signal N44302 : STD_LOGIC; 
  signal CHOICE960 : STD_LOGIC; 
  signal CHOICE962 : STD_LOGIC; 
  signal N39609 : STD_LOGIC; 
  signal U3_state_FFd2 : STD_LOGIC; 
  signal U3_state_FFd1 : STD_LOGIC; 
  signal U3_n0096_1_SW0_O : STD_LOGIC; 
  signal U1_N30014 : STD_LOGIC; 
  signal CHOICE934 : STD_LOGIC; 
  signal U3_this_paf : STD_LOGIC; 
  signal N44380 : STD_LOGIC; 
  signal U3_Ker311284_O : STD_LOGIC; 
  signal U3_Ker316491_SW0_O : STD_LOGIC; 
  signal U3_n0102_11_11_O : STD_LOGIC; 
  signal U3_Ker31405_SW1_O : STD_LOGIC; 
  signal U3_state_FFd36 : STD_LOGIC; 
  signal CHOICE394 : STD_LOGIC; 
  signal CHOICE922 : STD_LOGIC; 
  signal CHOICE925 : STD_LOGIC; 
  signal U3_n0102_0_22_O : STD_LOGIC; 
  signal CHOICE945 : STD_LOGIC; 
  signal CHOICE846 : STD_LOGIC; 
  signal CHOICE849 : STD_LOGIC; 
  signal U3_n0102_1_22_O : STD_LOGIC; 
  signal CHOICE858 : STD_LOGIC; 
  signal CHOICE774 : STD_LOGIC; 
  signal CHOICE777 : STD_LOGIC; 
  signal U3_n0102_3_23_O : STD_LOGIC; 
  signal CHOICE906 : STD_LOGIC; 
  signal CHOICE909 : STD_LOGIC; 
  signal CHOICE903 : STD_LOGIC; 
  signal U3_n0102_2_66_O : STD_LOGIC; 
  signal CHOICE792 : STD_LOGIC; 
  signal CHOICE795 : STD_LOGIC; 
  signal CHOICE789 : STD_LOGIC; 
  signal U3_n0102_4_25_O : STD_LOGIC; 
  signal U2_q1a : STD_LOGIC; 
  signal U2_q4 : STD_LOGIC; 
  signal U2_q1 : STD_LOGIC; 
  signal U2_q2 : STD_LOGIC; 
  signal U2_q3 : STD_LOGIC; 
  signal U2_n0133 : STD_LOGIC; 
  signal U2_fwrg1 : STD_LOGIC; 
  signal U1_etr_paepaf_reg_1 : STD_LOGIC; 
  signal U1_etr_paepaf_reg_2 : STD_LOGIC; 
  signal fld_OBUF : STD_LOGIC; 
  signal per_paepaf : STD_LOGIC; 
  signal U1_per_paepaf_reg : STD_LOGIC; 
  signal U1_N29944 : STD_LOGIC; 
  signal etr_x_IBUF : STD_LOGIC; 
  signal U1_etr_fifo_reg : STD_LOGIC; 
  signal U1_etr_paf_counter : STD_LOGIC; 
  signal U1_per_fifo_aux_2 : STD_LOGIC; 
  signal N44538 : STD_LOGIC; 
  signal CHOICE383 : STD_LOGIC; 
  signal CHOICE386 : STD_LOGIC; 
  signal CHOICE389 : STD_LOGIC; 
  signal CHOICE268 : STD_LOGIC; 
  signal U3_lives_in : STD_LOGIC; 
  signal U3_N31509 : STD_LOGIC; 
  signal U3_dontread_1_n0001 : STD_LOGIC; 
  signal U3_dontread_1_n0000 : STD_LOGIC; 
  signal U3_dontread_2_n0001 : STD_LOGIC; 
  signal U3_dontread_2_n0000 : STD_LOGIC; 
  signal U3_dontread_3_n0001 : STD_LOGIC; 
  signal U3_dontread_3_n0000 : STD_LOGIC; 
  signal U3_dontread_4_n0001 : STD_LOGIC; 
  signal U3_dontread_4_n0000 : STD_LOGIC; 
  signal U3_dontread_5_n0001 : STD_LOGIC; 
  signal U3_dontread_5_n0000 : STD_LOGIC; 
  signal recoff_p_OBUF : STD_LOGIC; 
  signal U1_n0077 : STD_LOGIC; 
  signal CHOICE509 : STD_LOGIC; 
  signal fsi_OBUF : STD_LOGIC; 
  signal N44344 : STD_LOGIC; 
  signal CHOICE872 : STD_LOGIC; 
  signal N38242 : STD_LOGIC; 
  signal ULED1_q2 : STD_LOGIC; 
  signal led_0_OBUF : STD_LOGIC; 
  signal U3_N31827 : STD_LOGIC; 
  signal N44502 : STD_LOGIC; 
  signal U1_N29992 : STD_LOGIC; 
  signal N44656 : STD_LOGIC; 
  signal N44644 : STD_LOGIC; 
  signal N38423 : STD_LOGIC; 
  signal N44652 : STD_LOGIC; 
  signal CHOICE260 : STD_LOGIC; 
  signal reset2 : STD_LOGIC; 
  signal reset1 : STD_LOGIC; 
  signal U3_dontread_0_n0000 : STD_LOGIC; 
  signal N44648 : STD_LOGIC; 
  signal N44631 : STD_LOGIC; 
  signal CHOICE301 : STD_LOGIC; 
  signal CHOICE284 : STD_LOGIC; 
  signal CHOICE91 : STD_LOGIC; 
  signal CHOICE293 : STD_LOGIC; 
  signal CHOICE294 : STD_LOGIC; 
  signal N38375 : STD_LOGIC; 
  signal U1_n0016 : STD_LOGIC; 
  signal Q_n0051 : STD_LOGIC; 
  signal hasul_0_OBUF : STD_LOGIC; 
  signal CHOICE106 : STD_LOGIC; 
  signal CHOICE696 : STD_LOGIC; 
  signal CHOICE99 : STD_LOGIC; 
  signal CHOICE310 : STD_LOGIC; 
  signal CHOICE311 : STD_LOGIC; 
  signal hasul_1_OBUF : STD_LOGIC; 
  signal CHOICE369 : STD_LOGIC; 
  signal CHOICE318 : STD_LOGIC; 
  signal U1_N29983 : STD_LOGIC; 
  signal U1_N29974 : STD_LOGIC; 
  signal U3_dontread_0_n0001 : STD_LOGIC; 
  signal CHOICE327 : STD_LOGIC; 
  signal CHOICE328 : STD_LOGIC; 
  signal hasul_2_OBUF : STD_LOGIC; 
  signal CHOICE352 : STD_LOGIC; 
  signal CHOICE512 : STD_LOGIC; 
  signal CHOICE397 : STD_LOGIC; 
  signal CHOICE265 : STD_LOGIC; 
  signal N44336 : STD_LOGIC; 
  signal CHOICE530 : STD_LOGIC; 
  signal CHOICE361 : STD_LOGIC; 
  signal CHOICE362 : STD_LOGIC; 
  signal hasul_3_OBUF : STD_LOGIC; 
  signal U1_N30000 : STD_LOGIC; 
  signal CHOICE344 : STD_LOGIC; 
  signal CHOICE345 : STD_LOGIC; 
  signal hasul_4_OBUF : STD_LOGIC; 
  signal cspare_0_IBUF : STD_LOGIC; 
  signal cspare_1_IBUF : STD_LOGIC; 
  signal N44514 : STD_LOGIC; 
  signal tp_3_OBUF : STD_LOGIC; 
  signal CHOICE378 : STD_LOGIC; 
  signal CHOICE379 : STD_LOGIC; 
  signal hasul_5_OBUF : STD_LOGIC; 
  signal N44622 : STD_LOGIC; 
  signal N44640 : STD_LOGIC; 
  signal N38588 : STD_LOGIC; 
  signal CHOICE578 : STD_LOGIC; 
  signal U1_n0012 : STD_LOGIC; 
  signal N38533 : STD_LOGIC; 
  signal CHOICE475 : STD_LOGIC; 
  signal CHOICE478 : STD_LOGIC; 
  signal CHOICE480 : STD_LOGIC; 
  signal N44510 : STD_LOGIC; 
  signal N38478 : STD_LOGIC; 
  signal U2_n0044 : STD_LOGIC; 
  signal U2_n0045 : STD_LOGIC; 
  signal U2_fwrg2 : STD_LOGIC; 
  signal U2_fwrg3 : STD_LOGIC; 
  signal U2_fwrg4 : STD_LOGIC; 
  signal U2_fwrg5 : STD_LOGIC; 
  signal N37571 : STD_LOGIC; 
  signal etr_paepaf : STD_LOGIC; 
  signal CHOICE400 : STD_LOGIC; 
  signal U3_this_ff : STD_LOGIC; 
  signal CHOICE894 : STD_LOGIC; 
  signal CHOICE931 : STD_LOGIC; 
  signal N44332 : STD_LOGIC; 
  signal CHOICE856 : STD_LOGIC; 
  signal U1_n0008 : STD_LOGIC; 
  signal CHOICE457 : STD_LOGIC; 
  signal CHOICE460 : STD_LOGIC; 
  signal CHOICE824 : STD_LOGIC; 
  signal N44482 : STD_LOGIC; 
  signal N39166 : STD_LOGIC; 
  signal U1_n0193 : STD_LOGIC; 
  signal etr_fifo : STD_LOGIC; 
  signal ren_5_OBUF : STD_LOGIC; 
  signal ren_4_OBUF : STD_LOGIC; 
  signal ren_3_OBUF : STD_LOGIC; 
  signal ren_2_OBUF : STD_LOGIC; 
  signal ren_1_OBUF : STD_LOGIC; 
  signal ren_0_OBUF : STD_LOGIC; 
  signal N37993 : STD_LOGIC; 
  signal sff_OBUF : STD_LOGIC; 
  signal CHOICE515 : STD_LOGIC; 
  signal CHOICE759 : STD_LOGIC; 
  signal N44306 : STD_LOGIC; 
  signal N44494 : STD_LOGIC; 
  signal CHOICE615 : STD_LOGIC; 
  signal CHOICE613 : STD_LOGIC; 
  signal CHOICE829 : STD_LOGIC; 
  signal CHOICE831 : STD_LOGIC; 
  signal N44518 : STD_LOGIC; 
  signal N44534 : STD_LOGIC; 
  signal CHOICE643 : STD_LOGIC; 
  signal CHOICE944 : STD_LOGIC; 
  signal U1_n0126 : STD_LOGIC; 
  signal N44294 : STD_LOGIC; 
  signal N44594 : STD_LOGIC; 
  signal N37936 : STD_LOGIC; 
  signal CHOICE629 : STD_LOGIC; 
  signal N40761 : STD_LOGIC; 
  signal N44375 : STD_LOGIC; 
  signal N40608 : STD_LOGIC; 
  signal U1_N29949 : STD_LOGIC; 
  signal N38020 : STD_LOGIC; 
  signal CHOICE742 : STD_LOGIC; 
  signal N38770 : STD_LOGIC; 
  signal CHOICE635 : STD_LOGIC; 
  signal N44614 : STD_LOGIC; 
  signal CHOICE745 : STD_LOGIC; 
  signal CHOICE762 : STD_LOGIC; 
  signal ULED1_q3 : STD_LOGIC; 
  signal ULED1_q1 : STD_LOGIC; 
  signal ULED2_q3 : STD_LOGIC; 
  signal ULED2_q1 : STD_LOGIC; 
  signal par_1_IBUF : STD_LOGIC; 
  signal par_0_IBUF : STD_LOGIC; 
  signal ULED2_q2 : STD_LOGIC; 
  signal CHOICE875 : STD_LOGIC; 
  signal N44506 : STD_LOGIC; 
  signal CHOICE879 : STD_LOGIC; 
  signal CHOICE827 : STD_LOGIC; 
  signal CHOICE868 : STD_LOGIC; 
  signal CHOICE937 : STD_LOGIC; 
  signal CHOICE897 : STD_LOGIC; 
  signal CHOICE900 : STD_LOGIC; 
  signal N44598 : STD_LOGIC; 
  signal CHOICE632 : STD_LOGIC; 
  signal N44390 : STD_LOGIC; 
  signal N44384 : STD_LOGIC; 
  signal CHOICE637 : STD_LOGIC; 
  signal CHOICE813 : STD_LOGIC; 
  signal CHOICE640 : STD_LOGIC; 
  signal CHOICE646 : STD_LOGIC; 
  signal donein_IBUF : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal enw_IFF_RST : STD_LOGIC; 
  signal enw_IBUF : STD_LOGIC; 
  signal db_0_IFF_SET : STD_LOGIC; 
  signal db_0_ENABLE : STD_LOGIC; 
  signal db_0_TORGTS : STD_LOGIC; 
  signal db_0_OUTMUX : STD_LOGIC; 
  signal db_0_IBUF : STD_LOGIC; 
  signal db_1_IFF_SET : STD_LOGIC; 
  signal db_1_ENABLE : STD_LOGIC; 
  signal db_1_TORGTS : STD_LOGIC; 
  signal db_1_OUTMUX : STD_LOGIC; 
  signal db_1_IBUF : STD_LOGIC; 
  signal db_2_IFF_SET : STD_LOGIC; 
  signal db_2_ENABLE : STD_LOGIC; 
  signal db_2_TORGTS : STD_LOGIC; 
  signal db_2_OUTMUX : STD_LOGIC; 
  signal db_2_IBUF : STD_LOGIC; 
  signal db_3_ENABLE : STD_LOGIC; 
  signal db_3_TORGTS : STD_LOGIC; 
  signal db_3_OUTMUX : STD_LOGIC; 
  signal db_3_IBUF : STD_LOGIC; 
  signal db_4_ENABLE : STD_LOGIC; 
  signal db_4_TORGTS : STD_LOGIC; 
  signal db_4_OUTMUX : STD_LOGIC; 
  signal db_4_IBUF : STD_LOGIC; 
  signal db_5_ENABLE : STD_LOGIC; 
  signal db_5_TORGTS : STD_LOGIC; 
  signal db_5_OUTMUX : STD_LOGIC; 
  signal db_5_IBUF : STD_LOGIC; 
  signal db_6_ENABLE : STD_LOGIC; 
  signal db_6_TORGTS : STD_LOGIC; 
  signal db_6_OUTMUX : STD_LOGIC; 
  signal db_6_IBUF : STD_LOGIC; 
  signal db_3_IFF_SET : STD_LOGIC; 
  signal db_7_ENABLE : STD_LOGIC; 
  signal db_7_TORGTS : STD_LOGIC; 
  signal db_7_OUTMUX : STD_LOGIC; 
  signal db_7_IBUF : STD_LOGIC; 
  signal mrs_IBUF_0 : STD_LOGIC; 
  signal db_8_ENABLE : STD_LOGIC; 
  signal db_8_TORGTS : STD_LOGIC; 
  signal db_8_OUTMUX : STD_LOGIC; 
  signal db_8_IBUF : STD_LOGIC; 
  signal db_9_ENABLE : STD_LOGIC; 
  signal db_9_TORGTS : STD_LOGIC; 
  signal db_9_OUTMUX : STD_LOGIC; 
  signal db_9_IBUF : STD_LOGIC; 
  signal ef_0_IBUF_1 : STD_LOGIC; 
  signal ef_1_IBUF_2 : STD_LOGIC; 
  signal ef_2_IBUF_3 : STD_LOGIC; 
  signal ef_3_IBUF_4 : STD_LOGIC; 
  signal ef_4_IBUF_5 : STD_LOGIC; 
  signal ef_5_IBUF_6 : STD_LOGIC; 
  signal ff_0_IBUF_7 : STD_LOGIC; 
  signal ff_1_IBUF_8 : STD_LOGIC; 
  signal ff_2_IBUF_9 : STD_LOGIC; 
  signal ff_3_IBUF_10 : STD_LOGIC; 
  signal ff_4_IBUF_11 : STD_LOGIC; 
  signal ff_5_IBUF_12 : STD_LOGIC; 
  signal add_0_IBUF_13 : STD_LOGIC; 
  signal db_5_IFF_SET : STD_LOGIC; 
  signal add_1_IBUF_14 : STD_LOGIC; 
  signal add_2_IBUF_15 : STD_LOGIC; 
  signal db_4_IFF_SET : STD_LOGIC; 
  signal add_3_IBUF_16 : STD_LOGIC; 
  signal add_4_IBUF_17 : STD_LOGIC; 
  signal add_5_IBUF_18 : STD_LOGIC; 
  signal load_paepaf_IBUF_19 : STD_LOGIC; 
  signal ceros_id_0_IBUF_20 : STD_LOGIC; 
  signal ceros_id_1_IBUF_21 : STD_LOGIC; 
  signal vspare_0_IBUF_22 : STD_LOGIC; 
  signal vspare_1_IBUF_23 : STD_LOGIC; 
  signal spaf_p_ENABLE : STD_LOGIC; 
  signal spaf_p_TORGTS : STD_LOGIC; 
  signal spaf_p_OUTMUX : STD_LOGIC; 
  signal oe_0_ENABLE : STD_LOGIC; 
  signal oe_0_TORGTS : STD_LOGIC; 
  signal oe_0_OUTMUX : STD_LOGIC; 
  signal oe_1_ENABLE : STD_LOGIC; 
  signal oe_1_TORGTS : STD_LOGIC; 
  signal oe_1_OUTMUX : STD_LOGIC; 
  signal oe_2_ENABLE : STD_LOGIC; 
  signal oe_2_TORGTS : STD_LOGIC; 
  signal oe_2_OUTMUX : STD_LOGIC; 
  signal oe_3_ENABLE : STD_LOGIC; 
  signal oe_3_TORGTS : STD_LOGIC; 
  signal oe_3_OUTMUX : STD_LOGIC; 
  signal oe_4_ENABLE : STD_LOGIC; 
  signal oe_4_TORGTS : STD_LOGIC; 
  signal oe_4_OUTMUX : STD_LOGIC; 
  signal oe_5_ENABLE : STD_LOGIC; 
  signal oe_5_TORGTS : STD_LOGIC; 
  signal oe_5_OUTMUX : STD_LOGIC; 
  signal UDLL2_CLK2X180 : STD_LOGIC; 
  signal UDLL2_CLK2X : STD_LOGIC; 
  signal UDLL2_CLK270 : STD_LOGIC; 
  signal UDLL2_CLK180 : STD_LOGIC; 
  signal UDLL2_CLK90 : STD_LOGIC; 
  signal UDLL2_LOGIC_ZERO : STD_LOGIC; 
  signal U1_I50_10_TINV : STD_LOGIC; 
  signal U1_I50_11_TINV : STD_LOGIC; 
  signal U1_I50_12_TINV : STD_LOGIC; 
  signal U1_I50_13_TINV : STD_LOGIC; 
  signal U1_I50_14_TINV : STD_LOGIC; 
  signal U1_I50_15_TINV : STD_LOGIC; 
  signal U1_I43_10_TINV : STD_LOGIC; 
  signal U1_I51_10_TINV : STD_LOGIC; 
  signal U1_I43_11_TINV : STD_LOGIC; 
  signal U1_I51_11_TINV : STD_LOGIC; 
  signal U1_I43_12_TINV : STD_LOGIC; 
  signal U1_I51_12_TINV : STD_LOGIC; 
  signal U1_I46_0_TINV : STD_LOGIC; 
  signal U1_I54_0_TINV : STD_LOGIC; 
  signal U1_I62_0_TINV : STD_LOGIC; 
  signal U1_I44_9_TINV : STD_LOGIC; 
  signal U1_I45_5_TINV : STD_LOGIC; 
  signal U1_I46_1_TINV : STD_LOGIC; 
  signal U1_I49_14_TINV : STD_LOGIC; 
  signal U1_I52_9_TINV : STD_LOGIC; 
  signal U1_I53_5_TINV : STD_LOGIC; 
  signal U1_I54_1_TINV : STD_LOGIC; 
  signal U1_I57_14_TINV : STD_LOGIC; 
  signal U1_I60_9_TINV : STD_LOGIC; 
  signal U1_I61_5_TINV : STD_LOGIC; 
  signal U1_I62_1_TINV : STD_LOGIC; 
  signal U1_I65_14_TINV : STD_LOGIC; 
  signal U1_I45_6_TINV : STD_LOGIC; 
  signal U1_I46_2_TINV : STD_LOGIC; 
  signal U1_I49_15_TINV : STD_LOGIC; 
  signal U1_I53_6_TINV : STD_LOGIC; 
  signal U1_I54_2_TINV : STD_LOGIC; 
  signal U1_I57_15_TINV : STD_LOGIC; 
  signal U1_I61_6_TINV : STD_LOGIC; 
  signal U1_I62_2_TINV : STD_LOGIC; 
  signal U1_I65_15_TINV : STD_LOGIC; 
  signal U1_I45_7_TINV : STD_LOGIC; 
  signal U1_I46_3_TINV : STD_LOGIC; 
  signal U1_I53_7_TINV : STD_LOGIC; 
  signal U1_I54_3_TINV : STD_LOGIC; 
  signal U1_I61_7_TINV : STD_LOGIC; 
  signal U1_I62_3_TINV : STD_LOGIC; 
  signal U1_I45_8_TINV : STD_LOGIC; 
  signal U1_I46_4_TINV : STD_LOGIC; 
  signal U1_I53_8_TINV : STD_LOGIC; 
  signal U1_I54_4_TINV : STD_LOGIC; 
  signal U1_I61_8_TINV : STD_LOGIC; 
  signal U1_I62_4_TINV : STD_LOGIC; 
  signal U1_I47_0_TINV : STD_LOGIC; 
  signal U1_I55_0_TINV : STD_LOGIC; 
  signal U1_I63_0_TINV : STD_LOGIC; 
  signal U1_I45_9_TINV : STD_LOGIC; 
  signal U1_I46_5_TINV : STD_LOGIC; 
  signal U1_I47_1_TINV : STD_LOGIC; 
  signal U1_I53_9_TINV : STD_LOGIC; 
  signal U1_I54_5_TINV : STD_LOGIC; 
  signal U1_I55_1_TINV : STD_LOGIC; 
  signal U1_I43_13_TINV : STD_LOGIC; 
  signal U1_I51_13_TINV : STD_LOGIC; 
  signal U1_I43_14_TINV : STD_LOGIC; 
  signal db_7_IFF_SET : STD_LOGIC; 
  signal U1_I51_14_TINV : STD_LOGIC; 
  signal U1_I43_15_TINV : STD_LOGIC; 
  signal db_6_IFF_SET : STD_LOGIC; 
  signal U1_I51_15_TINV : STD_LOGIC; 
  signal U1_I44_10_TINV : STD_LOGIC; 
  signal U1_I52_10_TINV : STD_LOGIC; 
  signal U1_I60_10_TINV : STD_LOGIC; 
  signal U1_I44_11_TINV : STD_LOGIC; 
  signal U1_I52_11_TINV : STD_LOGIC; 
  signal U1_I60_11_TINV : STD_LOGIC; 
  signal U1_I44_12_TINV : STD_LOGIC; 
  signal U1_I52_12_TINV : STD_LOGIC; 
  signal U1_I60_12_TINV : STD_LOGIC; 
  signal U1_I44_13_TINV : STD_LOGIC; 
  signal U1_I52_13_TINV : STD_LOGIC; 
  signal U1_I60_13_TINV : STD_LOGIC; 
  signal U1_I44_14_TINV : STD_LOGIC; 
  signal U1_I52_14_TINV : STD_LOGIC; 
  signal U1_I60_14_TINV : STD_LOGIC; 
  signal U1_I44_15_TINV : STD_LOGIC; 
  signal U1_I52_15_TINV : STD_LOGIC; 
  signal U1_I60_15_TINV : STD_LOGIC; 
  signal U1_I45_10_TINV : STD_LOGIC; 
  signal U1_I53_10_TINV : STD_LOGIC; 
  signal U1_I61_10_TINV : STD_LOGIC; 
  signal U1_I45_11_TINV : STD_LOGIC; 
  signal U1_I53_11_TINV : STD_LOGIC; 
  signal U1_I61_11_TINV : STD_LOGIC; 
  signal U1_I45_12_TINV : STD_LOGIC; 
  signal U1_I53_12_TINV : STD_LOGIC; 
  signal U1_I61_12_TINV : STD_LOGIC; 
  signal U1_I45_13_TINV : STD_LOGIC; 
  signal U1_I53_13_TINV : STD_LOGIC; 
  signal U1_I61_13_TINV : STD_LOGIC; 
  signal U1_I45_14_TINV : STD_LOGIC; 
  signal U1_I53_14_TINV : STD_LOGIC; 
  signal U1_I61_14_TINV : STD_LOGIC; 
  signal U1_I45_15_TINV : STD_LOGIC; 
  signal U1_I53_15_TINV : STD_LOGIC; 
  signal U1_I61_15_TINV : STD_LOGIC; 
  signal U1_I46_10_TINV : STD_LOGIC; 
  signal U1_I46_10_IMUXNOT : STD_LOGIC; 
  signal U1_I54_10_TINV : STD_LOGIC; 
  signal U1_I62_10_TINV : STD_LOGIC; 
  signal U1_I46_11_TINV : STD_LOGIC; 
  signal U1_I46_11_IMUXNOT : STD_LOGIC; 
  signal U1_I54_11_TINV : STD_LOGIC; 
  signal U1_I62_11_TINV : STD_LOGIC; 
  signal U1_I46_12_TINV : STD_LOGIC; 
  signal U1_I46_12_IMUXNOT : STD_LOGIC; 
  signal U1_I54_12_TINV : STD_LOGIC; 
  signal U1_I62_12_TINV : STD_LOGIC; 
  signal U1_I46_13_TINV : STD_LOGIC; 
  signal U1_I46_13_IMUXNOT : STD_LOGIC; 
  signal U1_I54_13_TINV : STD_LOGIC; 
  signal U1_I62_13_TINV : STD_LOGIC; 
  signal U1_I46_14_TINV : STD_LOGIC; 
  signal U1_I46_14_IMUXNOT : STD_LOGIC; 
  signal db_9_IFF_SET : STD_LOGIC; 
  signal U1_I54_14_TINV : STD_LOGIC; 
  signal db_8_IFF_SET : STD_LOGIC; 
  signal U1_I62_14_TINV : STD_LOGIC; 
  signal U1_I46_15_TINV : STD_LOGIC; 
  signal U1_I46_15_IMUXNOT : STD_LOGIC; 
  signal U1_I54_15_TINV : STD_LOGIC; 
  signal U1_I62_15_TINV : STD_LOGIC; 
  signal U1_I47_10_TINV : STD_LOGIC; 
  signal U1_I55_10_TINV : STD_LOGIC; 
  signal U1_I63_10_TINV : STD_LOGIC; 
  signal U1_I47_11_TINV : STD_LOGIC; 
  signal U1_I55_11_TINV : STD_LOGIC; 
  signal U1_I63_11_TINV : STD_LOGIC; 
  signal U1_I47_12_TINV : STD_LOGIC; 
  signal U1_I55_12_TINV : STD_LOGIC; 
  signal U1_I63_12_TINV : STD_LOGIC; 
  signal U1_I47_13_TINV : STD_LOGIC; 
  signal U1_I55_13_TINV : STD_LOGIC; 
  signal U1_I63_13_TINV : STD_LOGIC; 
  signal U1_I50_0_TINV : STD_LOGIC; 
  signal U1_I47_14_TINV : STD_LOGIC; 
  signal U1_I50_1_TINV : STD_LOGIC; 
  signal U1_I55_14_TINV : STD_LOGIC; 
  signal U1_I63_14_TINV : STD_LOGIC; 
  signal U1_I47_15_TINV : STD_LOGIC; 
  signal U1_I50_2_TINV : STD_LOGIC; 
  signal U1_I55_15_TINV : STD_LOGIC; 
  signal U1_I63_15_TINV : STD_LOGIC; 
  signal U1_I50_3_TINV : STD_LOGIC; 
  signal U1_I50_4_TINV : STD_LOGIC; 
  signal U1_I43_0_TINV : STD_LOGIC; 
  signal U1_I51_0_TINV : STD_LOGIC; 
  signal U1_I43_1_TINV : STD_LOGIC; 
  signal U1_I48_10_TINV : STD_LOGIC; 
  signal U1_I50_5_TINV : STD_LOGIC; 
  signal U1_I51_1_TINV : STD_LOGIC; 
  signal U1_I56_10_TINV : STD_LOGIC; 
  signal U1_I64_10_TINV : STD_LOGIC; 
  signal U1_I43_2_TINV : STD_LOGIC; 
  signal U1_I48_11_TINV : STD_LOGIC; 
  signal U1_I50_6_TINV : STD_LOGIC; 
  signal U1_I51_2_TINV : STD_LOGIC; 
  signal U1_I56_11_TINV : STD_LOGIC; 
  signal U1_I64_11_TINV : STD_LOGIC; 
  signal U1_I43_3_TINV : STD_LOGIC; 
  signal U1_I48_12_TINV : STD_LOGIC; 
  signal U1_I50_7_TINV : STD_LOGIC; 
  signal U1_I51_3_TINV : STD_LOGIC; 
  signal U1_I56_12_TINV : STD_LOGIC; 
  signal U1_I64_12_TINV : STD_LOGIC; 
  signal U1_I43_4_TINV : STD_LOGIC; 
  signal U1_I48_13_TINV : STD_LOGIC; 
  signal U1_I50_8_TINV : STD_LOGIC; 
  signal U1_I51_4_TINV : STD_LOGIC; 
  signal U1_I56_13_TINV : STD_LOGIC; 
  signal U1_I64_13_TINV : STD_LOGIC; 
  signal U1_I44_0_TINV : STD_LOGIC; 
  signal U1_I52_0_TINV : STD_LOGIC; 
  signal U1_I60_0_TINV : STD_LOGIC; 
  signal U1_I43_5_TINV : STD_LOGIC; 
  signal U1_I44_1_TINV : STD_LOGIC; 
  signal U1_I48_14_TINV : STD_LOGIC; 
  signal U1_I50_9_TINV : STD_LOGIC; 
  signal U1_I51_5_TINV : STD_LOGIC; 
  signal U1_I52_1_TINV : STD_LOGIC; 
  signal U1_I56_14_TINV : STD_LOGIC; 
  signal U1_I60_1_TINV : STD_LOGIC; 
  signal U1_I64_14_TINV : STD_LOGIC; 
  signal U1_I43_6_TINV : STD_LOGIC; 
  signal U1_I44_2_TINV : STD_LOGIC; 
  signal U1_I48_15_TINV : STD_LOGIC; 
  signal U1_I51_6_TINV : STD_LOGIC; 
  signal U1_I52_2_TINV : STD_LOGIC; 
  signal U1_I56_15_TINV : STD_LOGIC; 
  signal U1_I60_2_TINV : STD_LOGIC; 
  signal U1_I64_15_TINV : STD_LOGIC; 
  signal U1_I43_7_TINV : STD_LOGIC; 
  signal U1_I44_3_TINV : STD_LOGIC; 
  signal U1_I51_7_TINV : STD_LOGIC; 
  signal U1_I52_3_TINV : STD_LOGIC; 
  signal U1_I60_3_TINV : STD_LOGIC; 
  signal U1_I43_8_TINV : STD_LOGIC; 
  signal U1_I44_4_TINV : STD_LOGIC; 
  signal U1_I51_8_TINV : STD_LOGIC; 
  signal U1_I52_4_TINV : STD_LOGIC; 
  signal U1_I60_4_TINV : STD_LOGIC; 
  signal U1_I45_0_TINV : STD_LOGIC; 
  signal U1_I53_0_TINV : STD_LOGIC; 
  signal U1_I61_0_TINV : STD_LOGIC; 
  signal U1_I43_9_TINV : STD_LOGIC; 
  signal U1_I44_5_TINV : STD_LOGIC; 
  signal U1_I45_1_TINV : STD_LOGIC; 
  signal U1_I49_10_TINV : STD_LOGIC; 
  signal U1_I51_9_TINV : STD_LOGIC; 
  signal U1_I52_5_TINV : STD_LOGIC; 
  signal U1_I53_1_TINV : STD_LOGIC; 
  signal U1_I57_10_TINV : STD_LOGIC; 
  signal U1_I60_5_TINV : STD_LOGIC; 
  signal U1_I61_1_TINV : STD_LOGIC; 
  signal U1_I65_10_TINV : STD_LOGIC; 
  signal U1_I44_6_TINV : STD_LOGIC; 
  signal U1_I45_2_TINV : STD_LOGIC; 
  signal U1_I49_11_TINV : STD_LOGIC; 
  signal U1_I52_6_TINV : STD_LOGIC; 
  signal U1_I53_2_TINV : STD_LOGIC; 
  signal U1_I57_11_TINV : STD_LOGIC; 
  signal U1_I60_6_TINV : STD_LOGIC; 
  signal U1_I61_2_TINV : STD_LOGIC; 
  signal U1_I65_11_TINV : STD_LOGIC; 
  signal U1_I44_7_TINV : STD_LOGIC; 
  signal U1_I45_3_TINV : STD_LOGIC; 
  signal U1_I49_12_TINV : STD_LOGIC; 
  signal U1_I52_7_TINV : STD_LOGIC; 
  signal U1_I53_3_TINV : STD_LOGIC; 
  signal U1_I57_12_TINV : STD_LOGIC; 
  signal U1_I60_7_TINV : STD_LOGIC; 
  signal U1_I61_3_TINV : STD_LOGIC; 
  signal U1_I65_12_TINV : STD_LOGIC; 
  signal U1_I44_8_TINV : STD_LOGIC; 
  signal U1_I45_4_TINV : STD_LOGIC; 
  signal U1_I49_13_TINV : STD_LOGIC; 
  signal U1_I52_8_TINV : STD_LOGIC; 
  signal U1_I53_4_TINV : STD_LOGIC; 
  signal U1_I57_13_TINV : STD_LOGIC; 
  signal U1_I60_8_TINV : STD_LOGIC; 
  signal U1_I61_4_TINV : STD_LOGIC; 
  signal U1_I65_13_TINV : STD_LOGIC; 
  signal U3_dontread_0_FROM : STD_LOGIC; 
  signal CHOICE858_FROM : STD_LOGIC; 
  signal CHOICE858_GROM : STD_LOGIC; 
  signal CHOICE564_FROM : STD_LOGIC; 
  signal CHOICE564_GROM : STD_LOGIC; 
  signal CHOICE906_FROM : STD_LOGIC; 
  signal CHOICE906_GROM : STD_LOGIC; 
  signal CHOICE759_FROM : STD_LOGIC; 
  signal CHOICE759_GROM : STD_LOGIC; 
  signal U3_state_FFd17_FROM : STD_LOGIC; 
  signal U3_state_FFd17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd18_In : STD_LOGIC; 
  signal N44494_FROM : STD_LOGIC; 
  signal N44494_GROM : STD_LOGIC; 
  signal CHOICE618_FROM : STD_LOGIC; 
  signal CHOICE618_GROM : STD_LOGIC; 
  signal U3_state_FFd23_FROM : STD_LOGIC; 
  signal U3_state_FFd23_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd23_In : STD_LOGIC; 
  signal CHOICE960_FROM : STD_LOGIC; 
  signal CHOICE960_GROM : STD_LOGIC; 
  signal I18_N1762_FROM : STD_LOGIC; 
  signal I18_N1762_GROM : STD_LOGIC; 
  signal U1_I45_N1762_FROM : STD_LOGIC; 
  signal U1_I45_N1762_GROM : STD_LOGIC; 
  signal N44534_FROM : STD_LOGIC; 
  signal N44534_GROM : STD_LOGIC; 
  signal U1_n0009_FROM : STD_LOGIC; 
  signal U1_n0009_GROM : STD_LOGIC; 
  signal CHOICE643_FROM : STD_LOGIC; 
  signal CHOICE643_GROM : STD_LOGIC; 
  signal N41351_FROM : STD_LOGIC; 
  signal N41351_GROM : STD_LOGIC; 
  signal U1_n0126_GROM : STD_LOGIC; 
  signal U1_N30014_FROM : STD_LOGIC; 
  signal U1_N30014_GROM : STD_LOGIC; 
  signal N39317_FROM : STD_LOGIC; 
  signal N39317_GROM : STD_LOGIC; 
  signal N44294_FROM : STD_LOGIC; 
  signal N44294_GROM : STD_LOGIC; 
  signal U1_I66_N1762_FROM : STD_LOGIC; 
  signal U1_I66_N1762_GROM : STD_LOGIC; 
  signal U1_paf_reg_5_FROM : STD_LOGIC; 
  signal U1_N30021_FROM : STD_LOGIC; 
  signal U1_N30021_GROM : STD_LOGIC; 
  signal N44594_FROM : STD_LOGIC; 
  signal N44594_GROM : STD_LOGIC; 
  signal N37936_FROM : STD_LOGIC; 
  signal N37936_GROM : STD_LOGIC; 
  signal CHOICE629_FROM : STD_LOGIC; 
  signal CHOICE629_GROM : STD_LOGIC; 
  signal N40761_FROM : STD_LOGIC; 
  signal N40761_GROM : STD_LOGIC; 
  signal U3_N31636_FROM : STD_LOGIC; 
  signal U3_N31636_GROM : STD_LOGIC; 
  signal CHOICE837_FROM : STD_LOGIC; 
  signal CHOICE837_GROM : STD_LOGIC; 
  signal N44282_FROM : STD_LOGIC; 
  signal N44282_GROM : STD_LOGIC; 
  signal U3_N31749_FROM : STD_LOGIC; 
  signal U3_N31749_GROM : STD_LOGIC; 
  signal U3_N31694_FROM : STD_LOGIC; 
  signal U3_N31694_GROM : STD_LOGIC; 
  signal U3_state_FFd33_FROM : STD_LOGIC; 
  signal U3_state_FFd33_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd33_In : STD_LOGIC; 
  signal U3_N31940_FROM : STD_LOGIC; 
  signal U3_N31940_GROM : STD_LOGIC; 
  signal U3_N31900_GROM : STD_LOGIC; 
  signal U1_I58_10_TINV : STD_LOGIC; 
  signal U1_I61_9_TINV : STD_LOGIC; 
  signal U1_I62_5_TINV : STD_LOGIC; 
  signal U1_I63_1_TINV : STD_LOGIC; 
  signal U1_I66_10_TINV : STD_LOGIC; 
  signal U1_I46_6_TINV : STD_LOGIC; 
  signal U1_I47_2_TINV : STD_LOGIC; 
  signal U1_I54_6_TINV : STD_LOGIC; 
  signal U1_I55_2_TINV : STD_LOGIC; 
  signal U1_I58_11_TINV : STD_LOGIC; 
  signal U1_I62_6_TINV : STD_LOGIC; 
  signal U1_I63_2_TINV : STD_LOGIC; 
  signal U1_I66_11_TINV : STD_LOGIC; 
  signal U1_I46_7_TINV : STD_LOGIC; 
  signal U1_I47_3_TINV : STD_LOGIC; 
  signal U1_I54_7_TINV : STD_LOGIC; 
  signal U1_I55_3_TINV : STD_LOGIC; 
  signal U1_I58_12_TINV : STD_LOGIC; 
  signal U1_I62_7_TINV : STD_LOGIC; 
  signal U1_I63_3_TINV : STD_LOGIC; 
  signal U1_I66_12_TINV : STD_LOGIC; 
  signal U1_I46_8_TINV : STD_LOGIC; 
  signal U1_I47_4_TINV : STD_LOGIC; 
  signal U1_I54_8_TINV : STD_LOGIC; 
  signal U1_I55_4_TINV : STD_LOGIC; 
  signal U1_I58_13_TINV : STD_LOGIC; 
  signal U1_I62_8_TINV : STD_LOGIC; 
  signal U1_I63_4_TINV : STD_LOGIC; 
  signal U1_I66_13_TINV : STD_LOGIC; 
  signal U1_I48_0_TINV : STD_LOGIC; 
  signal U1_I56_0_TINV : STD_LOGIC; 
  signal U1_I64_0_TINV : STD_LOGIC; 
  signal U1_I46_9_TINV : STD_LOGIC; 
  signal U1_I47_5_TINV : STD_LOGIC; 
  signal U1_I48_1_TINV : STD_LOGIC; 
  signal U1_I54_9_TINV : STD_LOGIC; 
  signal U1_I55_5_TINV : STD_LOGIC; 
  signal U1_I56_1_TINV : STD_LOGIC; 
  signal U1_I58_14_TINV : STD_LOGIC; 
  signal U1_I62_9_TINV : STD_LOGIC; 
  signal U1_I63_5_TINV : STD_LOGIC; 
  signal U1_I64_1_TINV : STD_LOGIC; 
  signal U1_I66_14_TINV : STD_LOGIC; 
  signal U1_I47_6_TINV : STD_LOGIC; 
  signal U1_I48_2_TINV : STD_LOGIC; 
  signal U1_I55_6_TINV : STD_LOGIC; 
  signal U1_I56_2_TINV : STD_LOGIC; 
  signal U1_I58_15_TINV : STD_LOGIC; 
  signal U1_I63_6_TINV : STD_LOGIC; 
  signal U1_I64_2_TINV : STD_LOGIC; 
  signal U1_I66_15_TINV : STD_LOGIC; 
  signal U1_I47_7_TINV : STD_LOGIC; 
  signal U1_I48_3_TINV : STD_LOGIC; 
  signal U1_I55_7_TINV : STD_LOGIC; 
  signal U1_I56_3_TINV : STD_LOGIC; 
  signal U1_I63_7_TINV : STD_LOGIC; 
  signal U1_I64_3_TINV : STD_LOGIC; 
  signal U1_I47_8_TINV : STD_LOGIC; 
  signal U1_I48_4_TINV : STD_LOGIC; 
  signal U1_I55_8_TINV : STD_LOGIC; 
  signal U1_I56_4_TINV : STD_LOGIC; 
  signal U1_I63_8_TINV : STD_LOGIC; 
  signal U1_I64_4_TINV : STD_LOGIC; 
  signal U1_I49_0_TINV : STD_LOGIC; 
  signal U1_I57_0_TINV : STD_LOGIC; 
  signal U1_I65_0_TINV : STD_LOGIC; 
  signal U1_I47_9_TINV : STD_LOGIC; 
  signal U1_I48_5_TINV : STD_LOGIC; 
  signal U1_I49_1_TINV : STD_LOGIC; 
  signal U1_I55_9_TINV : STD_LOGIC; 
  signal U1_I56_5_TINV : STD_LOGIC; 
  signal U1_I57_1_TINV : STD_LOGIC; 
  signal U1_I59_10_TINV : STD_LOGIC; 
  signal U1_I63_9_TINV : STD_LOGIC; 
  signal U1_I64_5_TINV : STD_LOGIC; 
  signal U1_I65_1_TINV : STD_LOGIC; 
  signal U1_I67_10_TINV : STD_LOGIC; 
  signal U1_I48_6_TINV : STD_LOGIC; 
  signal U1_I49_2_TINV : STD_LOGIC; 
  signal U1_I56_6_TINV : STD_LOGIC; 
  signal U1_I57_2_TINV : STD_LOGIC; 
  signal U1_I59_11_TINV : STD_LOGIC; 
  signal U1_I64_6_TINV : STD_LOGIC; 
  signal U1_I65_2_TINV : STD_LOGIC; 
  signal U1_I67_11_TINV : STD_LOGIC; 
  signal U1_I48_7_TINV : STD_LOGIC; 
  signal U1_I49_3_TINV : STD_LOGIC; 
  signal U1_I56_7_TINV : STD_LOGIC; 
  signal U1_I57_3_TINV : STD_LOGIC; 
  signal U1_I59_12_TINV : STD_LOGIC; 
  signal U1_I64_7_TINV : STD_LOGIC; 
  signal U1_I65_3_TINV : STD_LOGIC; 
  signal U1_I67_12_TINV : STD_LOGIC; 
  signal U1_I48_8_TINV : STD_LOGIC; 
  signal U1_I49_4_TINV : STD_LOGIC; 
  signal U1_I56_8_TINV : STD_LOGIC; 
  signal U1_I57_4_TINV : STD_LOGIC; 
  signal U1_I59_13_TINV : STD_LOGIC; 
  signal U1_I64_8_TINV : STD_LOGIC; 
  signal U1_I65_4_TINV : STD_LOGIC; 
  signal U1_I67_13_TINV : STD_LOGIC; 
  signal U1_I58_0_TINV : STD_LOGIC; 
  signal U1_I66_0_TINV : STD_LOGIC; 
  signal U1_I48_9_TINV : STD_LOGIC; 
  signal U1_I49_5_TINV : STD_LOGIC; 
  signal U1_I56_9_TINV : STD_LOGIC; 
  signal U1_I57_5_TINV : STD_LOGIC; 
  signal U1_I58_1_TINV : STD_LOGIC; 
  signal U1_I59_14_TINV : STD_LOGIC; 
  signal U1_I64_9_TINV : STD_LOGIC; 
  signal U1_I65_5_TINV : STD_LOGIC; 
  signal U1_I66_1_TINV : STD_LOGIC; 
  signal U1_I67_14_TINV : STD_LOGIC; 
  signal U1_I49_6_TINV : STD_LOGIC; 
  signal U1_I57_6_TINV : STD_LOGIC; 
  signal U1_I58_2_TINV : STD_LOGIC; 
  signal U1_I59_15_TINV : STD_LOGIC; 
  signal U1_I65_6_TINV : STD_LOGIC; 
  signal U1_I66_2_TINV : STD_LOGIC; 
  signal U1_I67_15_TINV : STD_LOGIC; 
  signal U1_I49_7_TINV : STD_LOGIC; 
  signal U1_I57_7_TINV : STD_LOGIC; 
  signal U1_I58_3_TINV : STD_LOGIC; 
  signal U1_I65_7_TINV : STD_LOGIC; 
  signal U1_I66_3_TINV : STD_LOGIC; 
  signal U1_I49_8_TINV : STD_LOGIC; 
  signal U1_I57_8_TINV : STD_LOGIC; 
  signal U1_I58_4_TINV : STD_LOGIC; 
  signal U1_I65_8_TINV : STD_LOGIC; 
  signal U1_I66_4_TINV : STD_LOGIC; 
  signal U1_I59_0_TINV : STD_LOGIC; 
  signal U1_I67_0_TINV : STD_LOGIC; 
  signal U1_I49_9_TINV : STD_LOGIC; 
  signal U1_I57_9_TINV : STD_LOGIC; 
  signal U1_I58_5_TINV : STD_LOGIC; 
  signal U1_I59_1_TINV : STD_LOGIC; 
  signal U1_I65_9_TINV : STD_LOGIC; 
  signal U1_I66_5_TINV : STD_LOGIC; 
  signal U1_I67_1_TINV : STD_LOGIC; 
  signal U1_I58_6_TINV : STD_LOGIC; 
  signal U1_I59_2_TINV : STD_LOGIC; 
  signal U1_I66_6_TINV : STD_LOGIC; 
  signal U1_I67_2_TINV : STD_LOGIC; 
  signal U1_I58_7_TINV : STD_LOGIC; 
  signal U1_I59_3_TINV : STD_LOGIC; 
  signal U1_I66_7_TINV : STD_LOGIC; 
  signal U1_I67_3_TINV : STD_LOGIC; 
  signal U1_I58_8_TINV : STD_LOGIC; 
  signal U1_I59_4_TINV : STD_LOGIC; 
  signal U1_I66_8_TINV : STD_LOGIC; 
  signal U1_I67_4_TINV : STD_LOGIC; 
  signal U1_I58_9_TINV : STD_LOGIC; 
  signal U1_I59_5_TINV : STD_LOGIC; 
  signal U1_I66_9_TINV : STD_LOGIC; 
  signal U1_I67_5_TINV : STD_LOGIC; 
  signal U1_I59_6_TINV : STD_LOGIC; 
  signal U1_I67_6_TINV : STD_LOGIC; 
  signal U1_I59_7_TINV : STD_LOGIC; 
  signal U1_I67_7_TINV : STD_LOGIC; 
  signal U1_I59_8_TINV : STD_LOGIC; 
  signal U1_I67_8_TINV : STD_LOGIC; 
  signal U1_I59_9_TINV : STD_LOGIC; 
  signal U1_I67_9_TINV : STD_LOGIC; 
  signal N44692 : STD_LOGIC; 
  signal N44690 : STD_LOGIC; 
  signal CHOICE1026_F5MUX : STD_LOGIC; 
  signal N44707 : STD_LOGIC; 
  signal N44705 : STD_LOGIC; 
  signal CHOICE996_F5MUX : STD_LOGIC; 
  signal N44702 : STD_LOGIC; 
  signal N44700 : STD_LOGIC; 
  signal CHOICE1011_F5MUX : STD_LOGIC; 
  signal N44697 : STD_LOGIC; 
  signal N44695 : STD_LOGIC; 
  signal CHOICE981_F5MUX : STD_LOGIC; 
  signal U3_N21487 : STD_LOGIC; 
  signal U3_n0151_1_CYMUXG : STD_LOGIC; 
  signal U3_n0151_1_XORG : STD_LOGIC; 
  signal U3_n0151_1_GROM : STD_LOGIC; 
  signal U3_cr_ros_n0151_0_cyo : STD_LOGIC; 
  signal U3_n0151_1_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0151_2_FROM : STD_LOGIC; 
  signal U3_n0151_2_XORF : STD_LOGIC; 
  signal U3_n0151_2_CYMUXG : STD_LOGIC; 
  signal U3_n0151_2_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0151_2_XORG : STD_LOGIC; 
  signal U3_n0151_2_GROM : STD_LOGIC; 
  signal U3_cr_ros_n0151_2_cyo : STD_LOGIC; 
  signal U3_n0151_2_CYINIT : STD_LOGIC; 
  signal U3_n0151_4_FROM : STD_LOGIC; 
  signal U3_n0151_4_XORF : STD_LOGIC; 
  signal U3_n0151_4_CYMUXG : STD_LOGIC; 
  signal U3_n0151_4_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0151_4_XORG : STD_LOGIC; 
  signal U3_n0151_4_GROM : STD_LOGIC; 
  signal U3_cr_ros_n0151_4_cyo : STD_LOGIC; 
  signal U3_n0151_4_CYINIT : STD_LOGIC; 
  signal U3_n0151_6_FROM : STD_LOGIC; 
  signal U3_n0151_6_XORF : STD_LOGIC; 
  signal U3_n0151_6_CYMUXG : STD_LOGIC; 
  signal U3_n0151_6_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0151_6_XORG : STD_LOGIC; 
  signal U3_n0151_6_GROM : STD_LOGIC; 
  signal U3_cr_ros_n0151_6_cyo : STD_LOGIC; 
  signal U3_n0151_6_CYINIT : STD_LOGIC; 
  signal U3_n0151_8_FROM : STD_LOGIC; 
  signal U3_n0151_8_XORF : STD_LOGIC; 
  signal U3_n0151_8_CYMUXG : STD_LOGIC; 
  signal U3_n0151_8_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0151_8_XORG : STD_LOGIC; 
  signal U3_n0151_8_GROM : STD_LOGIC; 
  signal U3_cr_ros_n0151_8_cyo : STD_LOGIC; 
  signal U3_n0151_8_CYINIT : STD_LOGIC; 
  signal U3_n0151_10_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0151_10_FROM : STD_LOGIC; 
  signal U3_n0151_10_XORF : STD_LOGIC; 
  signal U3_n0151_10_XORG : STD_LOGIC; 
  signal U3_word_count_11_rt : STD_LOGIC; 
  signal U3_cr_ros_n0151_10_cyo : STD_LOGIC; 
  signal U3_n0151_10_CYINIT : STD_LOGIC; 
  signal U2_disparity_0_FFY_RST : STD_LOGIC; 
  signal enw_dispar_rt : STD_LOGIC; 
  signal U2_disparity_0_CYMUXG : STD_LOGIC; 
  signal U2_disparity_0_GROM : STD_LOGIC; 
  signal U2_disparity_inst_cy_0 : STD_LOGIC; 
  signal U2_disparity_0_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_sum_0 : STD_LOGIC; 
  signal U2_disparity_1_FFY_RST : STD_LOGIC; 
  signal U2_disparity_inst_lut3_1 : STD_LOGIC; 
  signal U2_disparity_inst_sum_1 : STD_LOGIC; 
  signal U2_disparity_1_CYMUXG : STD_LOGIC; 
  signal U2_disparity_1_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_lut3_2 : STD_LOGIC; 
  signal U2_disparity_inst_cy_2 : STD_LOGIC; 
  signal U2_disparity_1_CYINIT : STD_LOGIC; 
  signal U2_disparity_inst_sum_2 : STD_LOGIC; 
  signal U2_disparity_inst_lut3_3 : STD_LOGIC; 
  signal U2_disparity_inst_sum_3 : STD_LOGIC; 
  signal U2_disparity_3_CYMUXG : STD_LOGIC; 
  signal U2_disparity_3_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_lut3_4 : STD_LOGIC; 
  signal U2_disparity_inst_cy_4 : STD_LOGIC; 
  signal U2_disparity_3_CYINIT : STD_LOGIC; 
  signal U2_disparity_inst_sum_4 : STD_LOGIC; 
  signal U2_disparity_5_FFX_RST : STD_LOGIC; 
  signal U2_disparity_inst_lut3_5 : STD_LOGIC; 
  signal U2_disparity_inst_sum_5 : STD_LOGIC; 
  signal U2_disparity_5_CYMUXG : STD_LOGIC; 
  signal U2_disparity_5_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_lut3_6 : STD_LOGIC; 
  signal U2_disparity_inst_cy_6 : STD_LOGIC; 
  signal U2_disparity_5_CYINIT : STD_LOGIC; 
  signal U2_disparity_inst_sum_6 : STD_LOGIC; 
  signal U2_disparity_7_FFX_RST : STD_LOGIC; 
  signal U2_disparity_inst_lut3_7 : STD_LOGIC; 
  signal U2_disparity_inst_sum_7 : STD_LOGIC; 
  signal U2_disparity_7_CYMUXG : STD_LOGIC; 
  signal U2_disparity_7_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_lut3_8 : STD_LOGIC; 
  signal U2_disparity_inst_cy_8 : STD_LOGIC; 
  signal U2_disparity_7_CYINIT : STD_LOGIC; 
  signal U2_disparity_inst_sum_8 : STD_LOGIC; 
  signal U2_disparity_9_FFX_RST : STD_LOGIC; 
  signal U2_disparity_9_FFY_RST : STD_LOGIC; 
  signal U2_disparity_inst_lut3_9 : STD_LOGIC; 
  signal U2_disparity_inst_sum_9 : STD_LOGIC; 
  signal U2_disparity_9_CYMUXG : STD_LOGIC; 
  signal U2_disparity_9_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_lut3_10 : STD_LOGIC; 
  signal U2_disparity_inst_cy_10 : STD_LOGIC; 
  signal U2_disparity_9_CYINIT : STD_LOGIC; 
  signal U2_disparity_inst_sum_10 : STD_LOGIC; 
  signal U2_disparity_11_FFY_RST : STD_LOGIC; 
  signal U2_disparity_inst_lut3_11 : STD_LOGIC; 
  signal U2_disparity_inst_sum_11 : STD_LOGIC; 
  signal U2_disparity_11_CYMUXG : STD_LOGIC; 
  signal U2_disparity_11_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_lut3_12 : STD_LOGIC; 
  signal U2_disparity_inst_cy_12 : STD_LOGIC; 
  signal U2_disparity_11_CYINIT : STD_LOGIC; 
  signal U2_disparity_inst_sum_12 : STD_LOGIC; 
  signal U2_disparity_13_FFY_RST : STD_LOGIC; 
  signal U2_disparity_inst_lut3_13 : STD_LOGIC; 
  signal U2_disparity_inst_sum_13 : STD_LOGIC; 
  signal U2_disparity_13_CYMUXG : STD_LOGIC; 
  signal U2_disparity_13_LOGIC_ZERO : STD_LOGIC; 
  signal U2_disparity_inst_lut3_14 : STD_LOGIC; 
  signal U2_disparity_inst_cy_14 : STD_LOGIC; 
  signal U2_disparity_13_CYINIT : STD_LOGIC; 
  signal U2_disparity_inst_sum_14 : STD_LOGIC; 
  signal U2_disparity_inst_lut3_15 : STD_LOGIC; 
  signal U2_disparity_inst_sum_15 : STD_LOGIC; 
  signal U2_disparity_15_GROM : STD_LOGIC; 
  signal U2_disparity_15_CYINIT : STD_LOGIC; 
  signal U3_N21575 : STD_LOGIC; 
  signal U3_Neq_stage_cyo1_CYMUXG : STD_LOGIC; 
  signal U3_N21578 : STD_LOGIC; 
  signal U3_Neq_stage_cyo : STD_LOGIC; 
  signal U3_Neq_stage_cyo1_LOGIC_ONE : STD_LOGIC; 
  signal U3_Neq_stage_cyo1_LOGIC_ZERO : STD_LOGIC; 
  signal U3_N21581 : STD_LOGIC; 
  signal U3_n0050_CYMUXG : STD_LOGIC; 
  signal U3_N21584 : STD_LOGIC; 
  signal U3_Neq_stage_cyo2 : STD_LOGIC; 
  signal U3_n0050_LOGIC_ONE : STD_LOGIC; 
  signal U3_n0050_CYINIT : STD_LOGIC; 
  signal U3_n0251_0_FROM : STD_LOGIC; 
  signal U3_n0251_0_XORF : STD_LOGIC; 
  signal U3_n0251_0_CYMUXG : STD_LOGIC; 
  signal U3_n0251_0_XORG : STD_LOGIC; 
  signal U3_N21515 : STD_LOGIC; 
  signal U3_cr_ros_n0251_0_cyo : STD_LOGIC; 
  signal U3_n0251_0_CYINIT : STD_LOGIC; 
  signal U3_n0251_0_LOGIC_ONE : STD_LOGIC; 
  signal U3_N21519 : STD_LOGIC; 
  signal U3_n0251_2_XORF : STD_LOGIC; 
  signal U3_n0251_2_CYMUXG : STD_LOGIC; 
  signal U3_n0251_2_LOGIC_ONE : STD_LOGIC; 
  signal U3_n0251_2_XORG : STD_LOGIC; 
  signal U3_N21523 : STD_LOGIC; 
  signal U3_cr_ros_n0251_2_cyo : STD_LOGIC; 
  signal U3_n0251_2_CYINIT : STD_LOGIC; 
  signal U3_N21527 : STD_LOGIC; 
  signal U3_n0251_4_XORF : STD_LOGIC; 
  signal U3_n0251_4_CYMUXG : STD_LOGIC; 
  signal U3_n0251_4_LOGIC_ONE : STD_LOGIC; 
  signal U3_n0251_4_XORG : STD_LOGIC; 
  signal U3_N21531 : STD_LOGIC; 
  signal U3_cr_ros_n0251_4_cyo : STD_LOGIC; 
  signal U3_n0251_4_CYINIT : STD_LOGIC; 
  signal U3_N21535 : STD_LOGIC; 
  signal U3_n0251_6_XORF : STD_LOGIC; 
  signal U3_n0251_6_CYMUXG : STD_LOGIC; 
  signal U3_n0251_6_LOGIC_ONE : STD_LOGIC; 
  signal U3_n0251_6_XORG : STD_LOGIC; 
  signal U3_N21539 : STD_LOGIC; 
  signal U3_cr_ros_n0251_6_cyo : STD_LOGIC; 
  signal U3_n0251_6_CYINIT : STD_LOGIC; 
  signal U3_N21543 : STD_LOGIC; 
  signal U3_n0251_8_XORF : STD_LOGIC; 
  signal U3_n0251_8_CYMUXG : STD_LOGIC; 
  signal U3_n0251_8_LOGIC_ONE : STD_LOGIC; 
  signal U3_n0251_8_XORG : STD_LOGIC; 
  signal U3_N21547 : STD_LOGIC; 
  signal U3_cr_ros_n0251_8_cyo : STD_LOGIC; 
  signal U3_n0251_8_CYINIT : STD_LOGIC; 
  signal U3_N21551 : STD_LOGIC; 
  signal U3_n0251_10_XORF : STD_LOGIC; 
  signal U3_n0251_10_CYMUXG : STD_LOGIC; 
  signal U3_n0251_10_LOGIC_ONE : STD_LOGIC; 
  signal U3_n0251_10_XORG : STD_LOGIC; 
  signal U3_N21555 : STD_LOGIC; 
  signal U3_cr_ros_n0251_10_cyo : STD_LOGIC; 
  signal U3_n0251_10_CYINIT : STD_LOGIC; 
  signal U3_N21559 : STD_LOGIC; 
  signal U3_time_out_XORF : STD_LOGIC; 
  signal U3_time_out_CYINIT : STD_LOGIC; 
  signal U3_n0118 : STD_LOGIC; 
  signal U3_N21469 : STD_LOGIC; 
  signal U3_Eq_stage_cyo1_CYMUXG : STD_LOGIC; 
  signal U3_N21472 : STD_LOGIC; 
  signal U3_Eq_stage_cyo : STD_LOGIC; 
  signal U3_Eq_stage_cyo1_LOGIC_ZERO : STD_LOGIC; 
  signal U3_Eq_stage_cyo1_LOGIC_ONE : STD_LOGIC; 
  signal U3_N21475 : STD_LOGIC; 
  signal U3_Eq_stage_cyo3_CYMUXG : STD_LOGIC; 
  signal U3_N21478 : STD_LOGIC; 
  signal U3_Eq_stage_cyo2 : STD_LOGIC; 
  signal U3_Eq_stage_cyo3_LOGIC_ZERO : STD_LOGIC; 
  signal U3_Eq_stage_cyo3_CYINIT : STD_LOGIC; 
  signal U3_N21481 : STD_LOGIC; 
  signal U3_n0150_CYMUXG : STD_LOGIC; 
  signal U3_N21484 : STD_LOGIC; 
  signal U3_Eq_stage_cyo4 : STD_LOGIC; 
  signal U3_n0150_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0150_CYINIT : STD_LOGIC; 
  signal U2_loadcnt_N21450 : STD_LOGIC; 
  signal U2_loadcnt_n0002_1_CYMUXG : STD_LOGIC; 
  signal U2_loadcnt_n0002_1_XORG : STD_LOGIC; 
  signal U2_loadcnt_n0002_1_GROM : STD_LOGIC; 
  signal U2_loadcnt_LPM_COUNTER_2_n0002_0_cyo : STD_LOGIC; 
  signal U2_loadcnt_n0002_1_LOGIC_ZERO : STD_LOGIC; 
  signal U2_loadcnt_n0002_2_FROM : STD_LOGIC; 
  signal U2_loadcnt_n0002_2_XORF : STD_LOGIC; 
  signal U2_loadcnt_n0002_2_CYMUXG : STD_LOGIC; 
  signal U2_loadcnt_n0002_2_LOGIC_ZERO : STD_LOGIC; 
  signal U2_loadcnt_n0002_2_XORG : STD_LOGIC; 
  signal U2_loadcnt_n0002_2_GROM : STD_LOGIC; 
  signal U2_loadcnt_LPM_COUNTER_2_n0002_2_cyo : STD_LOGIC; 
  signal U2_loadcnt_n0002_2_CYINIT : STD_LOGIC; 
  signal U2_loadcnt_n0002_4_LOGIC_ZERO : STD_LOGIC; 
  signal U2_loadcnt_n0002_4_FROM : STD_LOGIC; 
  signal U2_loadcnt_n0002_4_XORF : STD_LOGIC; 
  signal U2_loadcnt_n0002_4_XORG : STD_LOGIC; 
  signal U2_loadcnt_5_rt : STD_LOGIC; 
  signal U2_loadcnt_LPM_COUNTER_2_n0002_4_cyo : STD_LOGIC; 
  signal U2_loadcnt_n0002_4_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_0_FFY_RST : STD_LOGIC; 
  signal U1_enw_paf_counter1_3_rt : STD_LOGIC; 
  signal U1_paf_counter_0_0_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_0 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_0 : STD_LOGIC; 
  signal U1_paf_counter_0_0_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_0 : STD_LOGIC; 
  signal U1_paf_counter_0_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_0_1_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_1 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_1 : STD_LOGIC; 
  signal U1_paf_counter_0_1_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_1_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_2 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_2 : STD_LOGIC; 
  signal U1_paf_counter_0_1_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_2 : STD_LOGIC; 
  signal U1_paf_counter_0_3_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_3 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_3 : STD_LOGIC; 
  signal U1_paf_counter_0_3_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_3_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_4 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_4 : STD_LOGIC; 
  signal U1_paf_counter_0_3_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_4 : STD_LOGIC; 
  signal U1_paf_counter_0_5_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_5 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_5 : STD_LOGIC; 
  signal U1_paf_counter_0_5_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_5_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_6 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_6 : STD_LOGIC; 
  signal U1_paf_counter_0_5_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_6 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_7 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_7 : STD_LOGIC; 
  signal U1_paf_counter_0_7_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_7_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_8 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_8 : STD_LOGIC; 
  signal U1_paf_counter_0_7_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_8 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_9 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_9 : STD_LOGIC; 
  signal U1_paf_counter_0_9_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_9_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_10 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_10 : STD_LOGIC; 
  signal U1_paf_counter_0_9_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_10 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_11 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_11 : STD_LOGIC; 
  signal U1_paf_counter_0_11_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_11_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_12 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_12 : STD_LOGIC; 
  signal U1_paf_counter_0_11_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_12 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_13 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_13 : STD_LOGIC; 
  signal U1_paf_counter_0_13_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_0_13_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_14 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_cy_14 : STD_LOGIC; 
  signal U1_paf_counter_0_13_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_14 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_lut3_15 : STD_LOGIC; 
  signal U1_paf_counter_0_inst_sum_15 : STD_LOGIC; 
  signal U1_paf_counter_0_15_GROM : STD_LOGIC; 
  signal U1_paf_counter_0_15_CYINIT : STD_LOGIC; 
  signal Q_SIG_0 : STD_LOGIC; 
  signal U1_paf_counter_1_0_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_0 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_0 : STD_LOGIC; 
  signal U1_paf_counter_1_0_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_0 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_1 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_1 : STD_LOGIC; 
  signal U1_paf_counter_1_1_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_1_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_2 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_2 : STD_LOGIC; 
  signal U1_paf_counter_1_1_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_2 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_3 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_3 : STD_LOGIC; 
  signal U1_paf_counter_1_3_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_3_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_4 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_4 : STD_LOGIC; 
  signal U1_paf_counter_1_3_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_4 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_5 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_5 : STD_LOGIC; 
  signal U1_paf_counter_1_5_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_5_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_6 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_6 : STD_LOGIC; 
  signal U1_paf_counter_1_5_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_6 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_7 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_7 : STD_LOGIC; 
  signal U1_paf_counter_1_7_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_7_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_8 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_8 : STD_LOGIC; 
  signal U1_paf_counter_1_7_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_8 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_9 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_9 : STD_LOGIC; 
  signal U1_paf_counter_1_9_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_9_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_10 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_10 : STD_LOGIC; 
  signal U1_paf_counter_1_9_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_10 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_11 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_11 : STD_LOGIC; 
  signal U1_paf_counter_1_11_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_11_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_12 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_12 : STD_LOGIC; 
  signal U1_paf_counter_1_11_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_12 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_13 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_13 : STD_LOGIC; 
  signal U1_paf_counter_1_13_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_1_13_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_14 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_cy_14 : STD_LOGIC; 
  signal U1_paf_counter_1_13_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_14 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_lut3_15 : STD_LOGIC; 
  signal U1_paf_counter_1_inst_sum_15 : STD_LOGIC; 
  signal U1_paf_counter_1_15_GROM : STD_LOGIC; 
  signal U1_paf_counter_1_15_CYINIT : STD_LOGIC; 
  signal Q_SIG_1 : STD_LOGIC; 
  signal U1_paf_counter_2_0_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_0 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_0 : STD_LOGIC; 
  signal U1_paf_counter_2_0_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_0 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_1 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_1 : STD_LOGIC; 
  signal U1_paf_counter_2_1_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_1_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_2 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_2 : STD_LOGIC; 
  signal U1_paf_counter_2_1_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_2 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_3 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_3 : STD_LOGIC; 
  signal U1_paf_counter_2_3_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_3_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_4 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_4 : STD_LOGIC; 
  signal U1_paf_counter_2_3_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_4 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_5 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_5 : STD_LOGIC; 
  signal U1_paf_counter_2_5_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_5_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_6 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_6 : STD_LOGIC; 
  signal U1_paf_counter_2_5_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_6 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_7 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_7 : STD_LOGIC; 
  signal U1_paf_counter_2_7_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_7_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_8 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_8 : STD_LOGIC; 
  signal U1_paf_counter_2_7_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_8 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_9 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_9 : STD_LOGIC; 
  signal U1_paf_counter_2_9_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_9_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_10 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_10 : STD_LOGIC; 
  signal U1_paf_counter_2_9_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_10 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_11 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_11 : STD_LOGIC; 
  signal U1_paf_counter_2_11_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_11_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_12 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_12 : STD_LOGIC; 
  signal U1_paf_counter_2_11_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_12 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_13 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_13 : STD_LOGIC; 
  signal U1_paf_counter_2_13_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_2_13_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_14 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_cy_14 : STD_LOGIC; 
  signal U1_paf_counter_2_13_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_14 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_lut3_15 : STD_LOGIC; 
  signal U1_paf_counter_2_inst_sum_15 : STD_LOGIC; 
  signal U1_paf_counter_2_15_GROM : STD_LOGIC; 
  signal U1_paf_counter_2_15_CYINIT : STD_LOGIC; 
  signal Q_SIG_2 : STD_LOGIC; 
  signal U1_paf_counter_3_0_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_0 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_0 : STD_LOGIC; 
  signal U1_paf_counter_3_0_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_0 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_1 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_1 : STD_LOGIC; 
  signal U1_paf_counter_3_1_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_1_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_2 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_2 : STD_LOGIC; 
  signal U1_paf_counter_3_1_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_2 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_3 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_3 : STD_LOGIC; 
  signal U1_paf_counter_3_3_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_3_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_4 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_4 : STD_LOGIC; 
  signal U1_paf_counter_3_3_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_4 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_5 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_5 : STD_LOGIC; 
  signal U1_paf_counter_3_5_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_5_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_6 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_6 : STD_LOGIC; 
  signal U1_paf_counter_3_5_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_6 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_7 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_7 : STD_LOGIC; 
  signal U1_paf_counter_3_7_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_7_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_8 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_8 : STD_LOGIC; 
  signal U1_paf_counter_3_7_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_8 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_9 : STD_LOGIC; 
  signal U1_paf_counter_3_10_XORF : STD_LOGIC; 
  signal U1_paf_counter_3_10_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_10_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_10 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_10 : STD_LOGIC; 
  signal U1_paf_counter_3_10_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_10 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_11 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_11 : STD_LOGIC; 
  signal U1_paf_counter_3_11_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_11_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_12 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_12 : STD_LOGIC; 
  signal U1_paf_counter_3_11_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_12 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_13 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_13 : STD_LOGIC; 
  signal U1_paf_counter_3_13_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_3_13_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_14 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_cy_14 : STD_LOGIC; 
  signal U1_paf_counter_3_13_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_14 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_lut3_15 : STD_LOGIC; 
  signal U1_paf_counter_3_inst_sum_15 : STD_LOGIC; 
  signal U1_paf_counter_3_15_GROM : STD_LOGIC; 
  signal U1_paf_counter_3_15_CYINIT : STD_LOGIC; 
  signal Q_SIG_3 : STD_LOGIC; 
  signal U1_paf_counter_4_0_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_0 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_0 : STD_LOGIC; 
  signal U1_paf_counter_4_0_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_0 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_1 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_1 : STD_LOGIC; 
  signal U1_paf_counter_4_1_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_1_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_2 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_2 : STD_LOGIC; 
  signal U1_paf_counter_4_1_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_2 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_3 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_3 : STD_LOGIC; 
  signal U1_paf_counter_4_3_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_3_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_4 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_4 : STD_LOGIC; 
  signal U1_paf_counter_4_3_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_4 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_5 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_5 : STD_LOGIC; 
  signal U1_paf_counter_4_5_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_5_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_6 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_6 : STD_LOGIC; 
  signal U1_paf_counter_4_5_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_6 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_7 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_7 : STD_LOGIC; 
  signal U1_paf_counter_4_7_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_7_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_8 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_8 : STD_LOGIC; 
  signal U1_paf_counter_4_7_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_8 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_9 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_9 : STD_LOGIC; 
  signal U1_paf_counter_4_9_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_9_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_10 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_10 : STD_LOGIC; 
  signal U1_paf_counter_4_9_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_10 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_11 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_11 : STD_LOGIC; 
  signal U1_paf_counter_4_11_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_11_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_12 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_12 : STD_LOGIC; 
  signal U1_paf_counter_4_11_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_12 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_13 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_13 : STD_LOGIC; 
  signal U1_paf_counter_4_13_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_4_13_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_14 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_cy_14 : STD_LOGIC; 
  signal U1_paf_counter_4_13_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_14 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_lut3_15 : STD_LOGIC; 
  signal U1_paf_counter_4_inst_sum_15 : STD_LOGIC; 
  signal U1_paf_counter_4_15_GROM : STD_LOGIC; 
  signal U1_paf_counter_4_15_CYINIT : STD_LOGIC; 
  signal Q_SIG_4 : STD_LOGIC; 
  signal U1_paf_counter_5_0_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_0 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_0 : STD_LOGIC; 
  signal U1_paf_counter_5_0_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_0 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_1 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_1 : STD_LOGIC; 
  signal U1_paf_counter_5_1_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_1_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_2 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_2 : STD_LOGIC; 
  signal U1_paf_counter_5_1_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_2 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_3 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_3 : STD_LOGIC; 
  signal U1_paf_counter_5_3_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_3_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_4 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_4 : STD_LOGIC; 
  signal U1_paf_counter_5_3_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_4 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_5 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_5 : STD_LOGIC; 
  signal U1_paf_counter_5_5_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_5_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_6 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_6 : STD_LOGIC; 
  signal U1_paf_counter_5_5_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_6 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_7 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_7 : STD_LOGIC; 
  signal U1_paf_counter_5_7_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_7_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_8 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_8 : STD_LOGIC; 
  signal U1_paf_counter_5_7_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_8 : STD_LOGIC; 
  signal U1_paf_counter_5_9_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_9 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_9 : STD_LOGIC; 
  signal U1_paf_counter_5_9_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_9_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_10 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_10 : STD_LOGIC; 
  signal U1_paf_counter_5_9_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_10 : STD_LOGIC; 
  signal U1_paf_counter_5_11_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_11 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_11 : STD_LOGIC; 
  signal U1_paf_counter_5_11_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_11_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_12 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_12 : STD_LOGIC; 
  signal U1_paf_counter_5_11_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_12 : STD_LOGIC; 
  signal U1_paf_counter_5_13_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_13 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_13 : STD_LOGIC; 
  signal U1_paf_counter_5_13_CYMUXG : STD_LOGIC; 
  signal U1_paf_counter_5_13_LOGIC_ZERO : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_14 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_cy_14 : STD_LOGIC; 
  signal U1_paf_counter_5_13_CYINIT : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_14 : STD_LOGIC; 
  signal U1_paf_counter_5_15_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_inst_lut3_15 : STD_LOGIC; 
  signal U1_paf_counter_5_inst_sum_15 : STD_LOGIC; 
  signal U1_paf_counter_5_15_CYINIT : STD_LOGIC; 
  signal U3_N21563 : STD_LOGIC; 
  signal U3_n0121_1_CYMUXG : STD_LOGIC; 
  signal U3_n0121_1_XORG : STD_LOGIC; 
  signal U3_n0121_1_GROM : STD_LOGIC; 
  signal U3_cr_ros_n0121_0_cyo : STD_LOGIC; 
  signal U3_n0121_1_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0121_2_FROM : STD_LOGIC; 
  signal U3_n0121_2_XORF : STD_LOGIC; 
  signal U3_n0121_2_CYMUXG : STD_LOGIC; 
  signal U3_n0121_2_LOGIC_ZERO : STD_LOGIC; 
  signal U3_n0121_2_XORG : STD_LOGIC; 
  signal U3_n0121_2_GROM : STD_LOGIC; 
  signal U3_cr_ros_n0121_2_cyo : STD_LOGIC; 
  signal U3_n0121_2_CYINIT : STD_LOGIC; 
  signal U3_rob_id_4_rt : STD_LOGIC; 
  signal U3_n0121_4_XORF : STD_LOGIC; 
  signal U3_n0121_4_CYINIT : STD_LOGIC; 
  signal U3_n0102_6_44_SW0_O_FROM : STD_LOGIC; 
  signal U3_n0102_6_44_SW0_O_GROM : STD_LOGIC; 
  signal U3_read_fifo_dir_FROM : STD_LOGIC; 
  signal U3_read_fifo_dir_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0098111_O : STD_LOGIC; 
  signal read_FROM : STD_LOGIC; 
  signal read_GROM : STD_LOGIC; 
  signal U3_s_data_6_FROM : STD_LOGIC; 
  signal U3_s_data_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_6_67_O : STD_LOGIC; 
  signal U3_N31677_FROM : STD_LOGIC; 
  signal U3_N31677_GROM : STD_LOGIC; 
  signal U3_s_data_7_FROM : STD_LOGIC; 
  signal U3_s_data_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_7_47_O : STD_LOGIC; 
  signal U3_s_data_8_FROM : STD_LOGIC; 
  signal U3_s_data_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_8_44_O : STD_LOGIC; 
  signal U3_s_data_5_FROM : STD_LOGIC; 
  signal U3_s_data_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_5_133_O : STD_LOGIC; 
  signal U3_s_data_9_FROM : STD_LOGIC; 
  signal U3_s_data_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_9_44_O : STD_LOGIC; 
  signal U3_txena_dir_FROM : STD_LOGIC; 
  signal U3_txena_dir_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n009986_O : STD_LOGIC; 
  signal U3_s_data_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_0_129_O : STD_LOGIC; 
  signal U3_s_data_1_FROM : STD_LOGIC; 
  signal U3_s_data_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_1_83_O : STD_LOGIC; 
  signal U3_s_data_2_FROM : STD_LOGIC; 
  signal U3_s_data_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_2_109_O : STD_LOGIC; 
  signal U3_s_data_3_FROM : STD_LOGIC; 
  signal U3_s_data_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_3_66_O : STD_LOGIC; 
  signal U3_s_data_4_FROM : STD_LOGIC; 
  signal U3_s_data_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_4_71_O : STD_LOGIC; 
  signal U3_Mmux_n0115_Result_1_1_O : STD_LOGIC; 
  signal U3_Mmux_n0115_Result_0_1_O : STD_LOGIC; 
  signal U3_Mmux_n0115_Result_3_1_O : STD_LOGIC; 
  signal U3_Mmux_n0115_Result_2_1_O : STD_LOGIC; 
  signal U3_Mmux_n0115_Result_5_1_O : STD_LOGIC; 
  signal U3_Mmux_n0115_Result_4_1_O : STD_LOGIC; 
  signal U1_hasunlock_5_FROM : STD_LOGIC; 
  signal U1_Mmux_n0013_Result_5_1_O : STD_LOGIC; 
  signal enw_evid_mis_FROM : STD_LOGIC; 
  signal enw_evid_mis_GROM : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_11_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_10_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_13_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_12_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_15_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_14_1_O : STD_LOGIC; 
  signal U3_time_counter_0_FROM : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_0_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_1_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_3_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_2_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_5_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_4_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_7_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_6_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_9_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_8_1_O : STD_LOGIC; 
  signal U3_Mmux_n0114_Result_1_1_O : STD_LOGIC; 
  signal U3_Mmux_n0114_Result_0_1_O : STD_LOGIC; 
  signal U3_Mmux_n0114_Result_3_1_O : STD_LOGIC; 
  signal U3_Mmux_n0114_Result_2_1_O : STD_LOGIC; 
  signal U3_Mmux_n0114_Result_5_1_O : STD_LOGIC; 
  signal U3_Mmux_n0114_Result_4_1_O : STD_LOGIC; 
  signal U1_ff_reg_5_FROM : STD_LOGIC; 
  signal U1_Mmux_n0015_Result_5_1_O : STD_LOGIC; 
  signal U3_state_FFd4_In1_O : STD_LOGIC; 
  signal U3_state_FFd4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd3_In1_O : STD_LOGIC; 
  signal U3_n0113_13_1_O : STD_LOGIC; 
  signal U3_n0113_12_1_O : STD_LOGIC; 
  signal U3_state_FFd6_In1_O : STD_LOGIC; 
  signal U3_state_FFd6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd5_In1_O : STD_LOGIC; 
  signal U3_n0113_1_1_O : STD_LOGIC; 
  signal U3_n0113_14_1_O : STD_LOGIC; 
  signal U3_state_FFd10_In1_O : STD_LOGIC; 
  signal U3_state_FFd10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd9_In1_O : STD_LOGIC; 
  signal U1_Mmux_n0013_Result_1_1_O : STD_LOGIC; 
  signal U1_Mmux_n0013_Result_0_1_O : STD_LOGIC; 
  signal U1_Mmux_n0013_Result_3_1_O : STD_LOGIC; 
  signal U1_Mmux_n0013_Result_2_1_O : STD_LOGIC; 
  signal U1_hasunlock_4_FROM : STD_LOGIC; 
  signal U1_Mmux_n0013_Result_4_1_O : STD_LOGIC; 
  signal U3_s_data_10_FROM : STD_LOGIC; 
  signal U3_s_data_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_10_62_O : STD_LOGIC; 
  signal U3_s_data_11_FROM : STD_LOGIC; 
  signal U3_s_data_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_11_58_O : STD_LOGIC; 
  signal U3_s_data_12_FFY_RST : STD_LOGIC; 
  signal U3_s_data_12_FROM : STD_LOGIC; 
  signal U3_s_data_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_12_17_O : STD_LOGIC; 
  signal U3_s_data_13_FFY_RST : STD_LOGIC; 
  signal U3_s_data_13_FROM : STD_LOGIC; 
  signal U3_s_data_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_13_64_O : STD_LOGIC; 
  signal U3_s_data_14_FFY_RST : STD_LOGIC; 
  signal U3_s_data_14_FROM : STD_LOGIC; 
  signal U3_s_data_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_14_97_O : STD_LOGIC; 
  signal U3_s_data_15_FFY_RST : STD_LOGIC; 
  signal U3_s_data_15_FROM : STD_LOGIC; 
  signal U3_s_data_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0102_15_80_O : STD_LOGIC; 
  signal U3_word_count_11_FFX_RST : STD_LOGIC; 
  signal U3_word_count_11_FFY_RST : STD_LOGIC; 
  signal U3_n0100_11_1_O : STD_LOGIC; 
  signal U3_word_count_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0100_10_1_O : STD_LOGIC; 
  signal U1_db_error1_11_FFY_RST : STD_LOGIC; 
  signal U1_db_error1_11_FROM : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_11_1_O : STD_LOGIC; 
  signal CHOICE689_FROM : STD_LOGIC; 
  signal CHOICE689_GROM : STD_LOGIC; 
  signal U3_sel_read_0_FROM : STD_LOGIC; 
  signal U3_sel_read_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0110 : STD_LOGIC; 
  signal U3_this_hasunlock9_O_FROM : STD_LOGIC; 
  signal U3_this_hasunlock9_O_GROM : STD_LOGIC; 
  signal U3_trail_FROM : STD_LOGIC; 
  signal U3_trail_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n010420_O : STD_LOGIC; 
  signal U3_sel_read_5_FROM : STD_LOGIC; 
  signal U3_sel_read_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n010539_O : STD_LOGIC; 
  signal U3_n010527_O_FROM : STD_LOGIC; 
  signal U3_n010527_O_GROM : STD_LOGIC; 
  signal U3_sel_read_4_FROM : STD_LOGIC; 
  signal U3_sel_read_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0106 : STD_LOGIC; 
  signal U3_sel_read_3_FROM : STD_LOGIC; 
  signal U3_sel_read_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0107 : STD_LOGIC; 
  signal U3_sel_read_2_FROM : STD_LOGIC; 
  signal U3_sel_read_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0108 : STD_LOGIC; 
  signal CHOICE679_FROM : STD_LOGIC; 
  signal CHOICE679_GROM : STD_LOGIC; 
  signal U3_sel_read_1_FROM : STD_LOGIC; 
  signal U3_sel_read_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0109 : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_1_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_0_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_3_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_2_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_5_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_4_1_O : STD_LOGIC; 
  signal U1_db_error2_11_FROM : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_11_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_7_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_6_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_9_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_8_1_O : STD_LOGIC; 
  signal CHOICE556_FROM : STD_LOGIC; 
  signal CHOICE556_GROM : STD_LOGIC; 
  signal U3_Ker31546_SW0_O_FROM : STD_LOGIC; 
  signal U3_Ker31546_SW0_O_GROM : STD_LOGIC; 
  signal U3_Ker31554_SW1_O_FROM : STD_LOGIC; 
  signal U3_Ker31554_SW1_O_GROM : STD_LOGIC; 
  signal U3_error_evid_FROM : STD_LOGIC; 
  signal U3_error_evid_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n009539_O : STD_LOGIC; 
  signal U3_n024317_O_FROM : STD_LOGIC; 
  signal U3_n024317_O_GROM : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_11_1_O : STD_LOGIC; 
  signal U3_Mmux_n0117_Result_10_1_O : STD_LOGIC; 
  signal U1_N29954_FROM : STD_LOGIC; 
  signal U1_N29954_GROM : STD_LOGIC; 
  signal CHOICE683_FROM : STD_LOGIC; 
  signal CHOICE683_GROM : STD_LOGIC; 
  signal U3_ros_done_FROM : STD_LOGIC; 
  signal U3_ros_done_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n009724_O : STD_LOGIC; 
  signal U1_db_error3_11_FROM : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_11_1_O : STD_LOGIC; 
  signal U3_word_count_0_FROM : STD_LOGIC; 
  signal U3_word_count_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0100_0_1_O : STD_LOGIC; 
  signal U3_word_count_1_FROM : STD_LOGIC; 
  signal U3_word_count_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0100_1_1_O : STD_LOGIC; 
  signal U3_N31683_FROM : STD_LOGIC; 
  signal U3_N31683_GROM : STD_LOGIC; 
  signal CHOICE686_FROM : STD_LOGIC; 
  signal CHOICE686_GROM : STD_LOGIC; 
  signal U3_Ker3112814_O_FROM : STD_LOGIC; 
  signal U3_Ker3112814_O_GROM : STD_LOGIC; 
  signal CHOICE554_FROM : STD_LOGIC; 
  signal CHOICE554_GROM : STD_LOGIC; 
  signal U3_header1_reg_1_FROM : STD_LOGIC; 
  signal U3_n0111_1_1_O : STD_LOGIC; 
  signal U3_Ker31659_SW3_O_FROM : STD_LOGIC; 
  signal U3_Ker31659_SW3_O_GROM : STD_LOGIC; 
  signal U3_header2_reg_1_FROM : STD_LOGIC; 
  signal U3_n0112_1_1_O : STD_LOGIC; 
  signal U3_N31808_FROM : STD_LOGIC; 
  signal U3_N31808_GROM : STD_LOGIC; 
  signal U3_state_FFd12_In1_O : STD_LOGIC; 
  signal U3_state_FFd12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd11_In_O : STD_LOGIC; 
  signal U3_state_FFd24_In1_O : STD_LOGIC; 
  signal U3_state_FFd24_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd20_In1_O : STD_LOGIC; 
  signal U3_state_FFd22_In1_O : STD_LOGIC; 
  signal U3_state_FFd22_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd21_In1_O : STD_LOGIC; 
  signal U3_state_FFd16_FROM : STD_LOGIC; 
  signal U3_state_FFd16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd15_In1_O : STD_LOGIC; 
  signal U3_trailer_reg_0_FROM : STD_LOGIC; 
  signal U3_n0113_0_1_O : STD_LOGIC; 
  signal U3_state_FFd32_FROM : STD_LOGIC; 
  signal U3_state_FFd32_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd32_In30_O : STD_LOGIC; 
  signal U3_state_FFd26_In1_O : STD_LOGIC; 
  signal U3_state_FFd26_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd25_In1_O : STD_LOGIC; 
  signal U3_state_FFd27_1_FROM : STD_LOGIC; 
  signal U3_state_FFd27_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd27_1_GROM : STD_LOGIC; 
  signal U3_state_FFd28_FROM : STD_LOGIC; 
  signal U3_state_FFd28_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd28_In20_O : STD_LOGIC; 
  signal U3_state_FFd30_In : STD_LOGIC; 
  signal U3_state_FFd30_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd29_In1_O : STD_LOGIC; 
  signal U3_state_FFd40_LOGIC_ZERO : STD_LOGIC; 
  signal U3_state_FFd40_FROM : STD_LOGIC; 
  signal U3_state_FFd40_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd39_In1_O : STD_LOGIC; 
  signal U3_rob_id_2_FROM : STD_LOGIC; 
  signal U3_rob_id_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0096_2_28_O : STD_LOGIC; 
  signal U3_rob_id_3_FROM : STD_LOGIC; 
  signal U3_rob_id_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0096_3_14_O : STD_LOGIC; 
  signal U2_Mmux_n0025_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0026_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0023_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0024_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0014_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0015_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_1_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_0_1_O : STD_LOGIC; 
  signal U2_Mmux_n0004_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0005_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0021_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0022_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0012_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0013_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_3_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_2_1_O : STD_LOGIC; 
  signal U2_Mmux_n0010_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0011_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0018_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0019_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_5_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_4_1_O : STD_LOGIC; 
  signal U2_Mmux_n0008_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0009_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0016_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0017_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_7_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_6_1_O : STD_LOGIC; 
  signal U2_Mmux_n0006_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0007_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_9_1_O : STD_LOGIC; 
  signal U2_Mmux_n0002_Result_8_1_O : STD_LOGIC; 
  signal U3_n0112_11_1_O : STD_LOGIC; 
  signal U3_n0112_10_1_O : STD_LOGIC; 
  signal U3_n0112_13_1_O : STD_LOGIC; 
  signal U3_n0112_12_1_O : STD_LOGIC; 
  signal U3_n0112_15_1_O : STD_LOGIC; 
  signal U3_n0112_14_1_O : STD_LOGIC; 
  signal U3_n0113_3_1_O : STD_LOGIC; 
  signal U3_n0113_2_1_O : STD_LOGIC; 
  signal U3_n0113_5_1_O : STD_LOGIC; 
  signal U3_n0113_4_1_O : STD_LOGIC; 
  signal U3_n0113_7_1_O : STD_LOGIC; 
  signal U3_n0113_6_1_O : STD_LOGIC; 
  signal U3_n0113_9_1_O : STD_LOGIC; 
  signal U3_n0113_8_1_O : STD_LOGIC; 
  signal U3_N31256_FROM : STD_LOGIC; 
  signal U3_N31256_GROM : STD_LOGIC; 
  signal U3_n0100_3_1_O : STD_LOGIC; 
  signal U3_word_count_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0100_2_1_O : STD_LOGIC; 
  signal U3_n0100_5_1_O : STD_LOGIC; 
  signal U3_word_count_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0100_4_1_O : STD_LOGIC; 
  signal U3_n0100_7_1_O : STD_LOGIC; 
  signal U3_word_count_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0100_6_1_O : STD_LOGIC; 
  signal U3_n0100_9_1_O : STD_LOGIC; 
  signal U3_word_count_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0100_8_1_O : STD_LOGIC; 
  signal U3_N31407_FROM : STD_LOGIC; 
  signal U3_N31407_GROM : STD_LOGIC; 
  signal U3_n0102_8_30_SW1_O_FROM : STD_LOGIC; 
  signal U3_n0102_8_30_SW1_O_GROM : STD_LOGIC; 
  signal U3_n0102_8_30_SW0_O_FROM : STD_LOGIC; 
  signal U3_n0102_8_30_SW0_O_GROM : STD_LOGIC; 
  signal U3_n0102_9_30_SW1_O_FROM : STD_LOGIC; 
  signal U3_n0102_9_30_SW1_O_GROM : STD_LOGIC; 
  signal U3_n0102_9_30_SW0_O_FROM : STD_LOGIC; 
  signal U3_n0102_9_30_SW0_O_GROM : STD_LOGIC; 
  signal U3_n0102_12_8_SW1_O_FROM : STD_LOGIC; 
  signal U3_n0102_12_8_SW1_O_GROM : STD_LOGIC; 
  signal U3_n0102_12_8_SW0_O_FROM : STD_LOGIC; 
  signal U3_n0102_12_8_SW0_O_GROM : STD_LOGIC; 
  signal U3_n0112_0_1_O : STD_LOGIC; 
  signal U3_n0111_0_1_O : STD_LOGIC; 
  signal U3_n0111_3_1_O : STD_LOGIC; 
  signal U3_n0111_2_1_O : STD_LOGIC; 
  signal U3_n0111_5_1_O : STD_LOGIC; 
  signal U3_n0111_4_1_O : STD_LOGIC; 
  signal U3_n0111_7_1_O : STD_LOGIC; 
  signal U3_n0111_6_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_11_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_10_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_13_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_12_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_21_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_20_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_15_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_14_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_17_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_16_1_O : STD_LOGIC; 
  signal U2_pae_paf_reg_18_FROM : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_18_1_O : STD_LOGIC; 
  signal U2_Mmux_n0038_Result_19_1_O : STD_LOGIC; 
  signal U3_rob_id_0_FROM : STD_LOGIC; 
  signal U3_rob_id_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0096_0_1_O : STD_LOGIC; 
  signal U3_state_FFd13_FROM : STD_LOGIC; 
  signal U3_state_FFd13_GROM : STD_LOGIC; 
  signal U3_state_FFd13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_Ker317234_O_FROM : STD_LOGIC; 
  signal U3_Ker317234_O_GROM : STD_LOGIC; 
  signal U2_Mmux_n0035_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0036_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0033_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0034_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0031_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0032_Result1_O : STD_LOGIC; 
  signal U3_N31911_FROM : STD_LOGIC; 
  signal U3_N31911_GROM : STD_LOGIC; 
  signal U2_Mmux_n0029_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0030_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0027_Result1_O : STD_LOGIC; 
  signal U2_Mmux_n0028_Result1_O : STD_LOGIC; 
  signal U3_n0253_FROM : STD_LOGIC; 
  signal U3_n0253_GROM : STD_LOGIC; 
  signal U3_n0112_3_1_O : STD_LOGIC; 
  signal U3_n0112_2_1_O : STD_LOGIC; 
  signal U3_n0112_5_1_O : STD_LOGIC; 
  signal U3_n0112_4_1_O : STD_LOGIC; 
  signal U3_n0112_7_1_O : STD_LOGIC; 
  signal U3_n0112_6_1_O : STD_LOGIC; 
  signal U3_n0112_9_1_O : STD_LOGIC; 
  signal U3_n0112_8_1_O : STD_LOGIC; 
  signal U3_n0216_FROM : STD_LOGIC; 
  signal U3_n0216_GROM : STD_LOGIC; 
  signal U3_rob_id_1_FROM : STD_LOGIC; 
  signal U3_rob_id_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0096_1_O : STD_LOGIC; 
  signal U3_rob_id_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0096_4_10_O : STD_LOGIC; 
  signal enw_byte_par0_FROM : STD_LOGIC; 
  signal enw_byte_par0_GROM : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_10_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_10_1_O : STD_LOGIC; 
  signal U1_db_error2_10_FROM : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_10_1_O : STD_LOGIC; 
  signal U3_N31671_FROM : STD_LOGIC; 
  signal U3_N31671_GROM : STD_LOGIC; 
  signal U3_N31761_FROM : STD_LOGIC; 
  signal U3_N31761_GROM : STD_LOGIC; 
  signal U3_Ker311284_O_FROM : STD_LOGIC; 
  signal U3_Ker311284_O_GROM : STD_LOGIC; 
  signal N39486_FROM : STD_LOGIC; 
  signal N39486_GROM : STD_LOGIC; 
  signal U3_Ker316491_SW0_O_FROM : STD_LOGIC; 
  signal U3_Ker316491_SW0_O_GROM : STD_LOGIC; 
  signal U3_n0102_11_11_O_FROM : STD_LOGIC; 
  signal U3_n0102_11_11_O_GROM : STD_LOGIC; 
  signal U3_state_FFd36_FROM : STD_LOGIC; 
  signal U3_state_FFd36_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd36_GROM : STD_LOGIC; 
  signal U1_Mmux_n0015_Result_1_1_O : STD_LOGIC; 
  signal U1_Mmux_n0015_Result_0_1_O : STD_LOGIC; 
  signal U1_Mmux_n0015_Result_3_1_O : STD_LOGIC; 
  signal U1_Mmux_n0015_Result_2_1_O : STD_LOGIC; 
  signal enw_byte_par1_FROM : STD_LOGIC; 
  signal enw_byte_par1_GROM : STD_LOGIC; 
  signal U1_ff_reg_4_FROM : STD_LOGIC; 
  signal U1_Mmux_n0015_Result_4_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_1_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_0_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_3_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_2_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_1_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_0_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_5_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_4_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_3_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_2_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_7_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_6_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_5_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_4_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_9_1_O : STD_LOGIC; 
  signal U1_Mmux_n0036_Result_8_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_1_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_0_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_7_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_6_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_3_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_2_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_5_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_4_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_9_1_O : STD_LOGIC; 
  signal U1_Mmux_n0037_Result_8_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_7_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_6_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_9_1_O : STD_LOGIC; 
  signal U1_Mmux_n0038_Result_8_1_O : STD_LOGIC; 
  signal U3_n0102_0_22_O_FROM : STD_LOGIC; 
  signal U3_n0102_0_22_O_GROM : STD_LOGIC; 
  signal U3_n0102_1_22_O_FROM : STD_LOGIC; 
  signal U3_n0102_1_22_O_GROM : STD_LOGIC; 
  signal U3_n0102_3_23_O_FROM : STD_LOGIC; 
  signal U3_n0102_3_23_O_GROM : STD_LOGIC; 
  signal U3_n0102_2_66_O_FROM : STD_LOGIC; 
  signal U3_n0102_2_66_O_GROM : STD_LOGIC; 
  signal N44314_FROM : STD_LOGIC; 
  signal N44314_GROM : STD_LOGIC; 
  signal U3_header2_reg_11_FFX_RST : STD_LOGIC; 
  signal U3_header2_reg_13_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_13_FFX_RST : STD_LOGIC; 
  signal U3_header2_reg_15_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_15_FFX_RST : STD_LOGIC; 
  signal U3_trailer_reg_3_FFY_RST : STD_LOGIC; 
  signal U3_trailer_reg_3_FFX_RST : STD_LOGIC; 
  signal U3_trailer_reg_5_FFY_RST : STD_LOGIC; 
  signal U3_trailer_reg_5_FFX_RST : STD_LOGIC; 
  signal U3_trailer_reg_7_FFY_RST : STD_LOGIC; 
  signal U3_trailer_reg_9_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_3_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_3_FFX_RST : STD_LOGIC; 
  signal U3_header2_reg_5_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_5_FFX_RST : STD_LOGIC; 
  signal U3_header2_reg_7_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_7_FFX_RST : STD_LOGIC; 
  signal U3_header2_reg_9_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_9_FFX_RST : STD_LOGIC; 
  signal U3_rob_id_1_FFY_RST : STD_LOGIC; 
  signal U3_rob_id_4_FFY_RST : STD_LOGIC; 
  signal U1_ff_reg_1_FFY_RST : STD_LOGIC; 
  signal U1_ff_reg_1_FFX_RST : STD_LOGIC; 
  signal U1_ff_reg_3_FFY_RST : STD_LOGIC; 
  signal U1_ff_reg_3_FFX_RST : STD_LOGIC; 
  signal U1_ff_reg_4_FFY_RST : STD_LOGIC; 
  signal U1_db_error1_1_FFY_RST : STD_LOGIC; 
  signal U1_db_error1_1_FFX_RST : STD_LOGIC; 
  signal U1_db_error1_3_FFY_RST : STD_LOGIC; 
  signal U1_db_error2_1_FFY_RST : STD_LOGIC; 
  signal U1_db_error1_3_FFX_RST : STD_LOGIC; 
  signal U3_word_count_9_FFX_RST : STD_LOGIC; 
  signal U3_header2_reg_0_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_0_FFX_RST : STD_LOGIC; 
  signal U3_header1_reg_3_FFX_RST : STD_LOGIC; 
  signal U3_header1_reg_3_FFY_RST : STD_LOGIC; 
  signal U3_header1_reg_5_FFY_RST : STD_LOGIC; 
  signal U1_etr_fifo_reg_FROM : STD_LOGIC; 
  signal U1_etr_fifo_reg_GROM : STD_LOGIC; 
  signal U1_N29937_FROM : STD_LOGIC; 
  signal U1_N29937_GROM : STD_LOGIC; 
  signal U1_I50_N1762_FROM : STD_LOGIC; 
  signal U1_I50_N1762_GROM : STD_LOGIC; 
  signal U1_N29930_FROM : STD_LOGIC; 
  signal U1_N29930_GROM : STD_LOGIC; 
  signal U1_N29949_FROM : STD_LOGIC; 
  signal U1_N29949_GROM : STD_LOGIC; 
  signal U1_N29974_FROM : STD_LOGIC; 
  signal U1_N29974_GROM : STD_LOGIC; 
  signal U1_N29983_FROM : STD_LOGIC; 
  signal U1_N29983_GROM : STD_LOGIC; 
  signal U1_N29992_FROM : STD_LOGIC; 
  signal U1_N29992_GROM : STD_LOGIC; 
  signal CHOICE440_GROM : STD_LOGIC; 
  signal U1_N30000_FROM : STD_LOGIC; 
  signal U1_N30000_GROM : STD_LOGIC; 
  signal N38020_FROM : STD_LOGIC; 
  signal N38020_GROM : STD_LOGIC; 
  signal U3_dontread_4_n0001_FROM : STD_LOGIC; 
  signal U3_dontread_4_n0001_GROM : STD_LOGIC; 
  signal U2_n0045_FROM : STD_LOGIC; 
  signal U2_n0045_GROM : STD_LOGIC; 
  signal U1_enw_paf_counter1_1_GROM : STD_LOGIC; 
  signal U1_enw_paf_counter1_3_FROM : STD_LOGIC; 
  signal U1_enw_paf_counter1_3_GROM : STD_LOGIC; 
  signal CHOICE925_FROM : STD_LOGIC; 
  signal CHOICE925_GROM : STD_LOGIC; 
  signal U3_time_start_FROM : STD_LOGIC; 
  signal U3_time_start_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0101 : STD_LOGIC; 
  signal CHOICE635_FROM : STD_LOGIC; 
  signal CHOICE635_GROM : STD_LOGIC; 
  signal U3_state_FFd34_FROM : STD_LOGIC; 
  signal U3_state_FFd34_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd34_In : STD_LOGIC; 
  signal CHOICE745_FROM : STD_LOGIC; 
  signal CHOICE745_GROM : STD_LOGIC; 
  signal N44255_FROM : STD_LOGIC; 
  signal N44255_GROM : STD_LOGIC; 
  signal N44470_FROM : STD_LOGIC; 
  signal N44470_GROM : STD_LOGIC; 
  signal CHOICE762_FROM : STD_LOGIC; 
  signal CHOICE762_GROM : STD_LOGIC; 
  signal U2_n0096_GROM : STD_LOGIC; 
  signal ULED1_q1_LOGIC_ONE : STD_LOGIC; 
  signal U2_Mxor_cpar_0_Xo_4_GROM : STD_LOGIC; 
  signal U2_Mxor_cpar_0_Xo_5_GROM : STD_LOGIC; 
  signal ULED2_q1_LOGIC_ONE : STD_LOGIC; 
  signal U2_cpar_0_FROM : STD_LOGIC; 
  signal U2_cpar_0_GROM : STD_LOGIC; 
  signal CHOICE909_FROM : STD_LOGIC; 
  signal CHOICE909_GROM : STD_LOGIC; 
  signal CHOICE831_FROM : STD_LOGIC; 
  signal CHOICE831_GROM : STD_LOGIC; 
  signal CHOICE875_FROM : STD_LOGIC; 
  signal CHOICE875_GROM : STD_LOGIC; 
  signal CHOICE879_GROM : STD_LOGIC; 
  signal CHOICE827_FROM : STD_LOGIC; 
  signal CHOICE827_GROM : STD_LOGIC; 
  signal CHOICE868_FROM : STD_LOGIC; 
  signal CHOICE868_GROM : STD_LOGIC; 
  signal CHOICE777_FROM : STD_LOGIC; 
  signal CHOICE777_GROM : STD_LOGIC; 
  signal CHOICE937_FROM : STD_LOGIC; 
  signal CHOICE937_GROM : STD_LOGIC; 
  signal CHOICE515_FROM : STD_LOGIC; 
  signal CHOICE515_GROM : STD_LOGIC; 
  signal U3_n0102_4_25_O_FROM : STD_LOGIC; 
  signal U3_n0102_4_25_O_GROM : STD_LOGIC; 
  signal U3_state_FFd8_In1_O : STD_LOGIC; 
  signal U3_state_FFd8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd7_In : STD_LOGIC; 
  signal U3_time_counter_12_FROM : STD_LOGIC; 
  signal U2_n0042 : STD_LOGIC; 
  signal U2_n0040 : STD_LOGIC; 
  signal U2_q4_FROM : STD_LOGIC; 
  signal U2_n0043 : STD_LOGIC; 
  signal U1_per_paepaf_reg_FROM : STD_LOGIC; 
  signal U1_per_paepaf_reg_GROM : STD_LOGIC; 
  signal U1_per_fifo_aux_2_FROM : STD_LOGIC; 
  signal U1_per_fifo_aux : STD_LOGIC; 
  signal U3_state_FFd14_FROM : STD_LOGIC; 
  signal U3_state_FFd14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd14_In : STD_LOGIC; 
  signal U3_state_FFd31_FROM : STD_LOGIC; 
  signal U3_state_FFd31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd31_In : STD_LOGIC; 
  signal U3_state_FFd35_FROM : STD_LOGIC; 
  signal U3_state_FFd35_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd35_In : STD_LOGIC; 
  signal U3_state_FFd37_FROM : STD_LOGIC; 
  signal U3_state_FFd37_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd37_In : STD_LOGIC; 
  signal U3_lives_in_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n0103 : STD_LOGIC; 
  signal U3_dontread_1_FROM : STD_LOGIC; 
  signal U3_dontread_2_FFY_RST : STD_LOGIC; 
  signal U3_dontread_2_FFY_SET : STD_LOGIC; 
  signal U3_dontread_2_FROM : STD_LOGIC; 
  signal U3_dontread_3_FFY_RST : STD_LOGIC; 
  signal U3_dontread_3_FFY_SET : STD_LOGIC; 
  signal U3_dontread_3_FROM : STD_LOGIC; 
  signal U3_dontread_4_FROM : STD_LOGIC; 
  signal U3_dontread_5_FFY_RST : STD_LOGIC; 
  signal U3_dontread_5_FFY_SET : STD_LOGIC; 
  signal U3_dontread_5_FROM : STD_LOGIC; 
  signal U2_q1a_FFY_RST : STD_LOGIC; 
  signal U2_q1a_FROM : STD_LOGIC; 
  signal U2_n0041 : STD_LOGIC; 
  signal U1_paf_reg_4_FROM : STD_LOGIC; 
  signal fsi_OBUF_GROM : STD_LOGIC; 
  signal CHOICE1036_FROM : STD_LOGIC; 
  signal CHOICE1036_GROM : STD_LOGIC; 
  signal CHOICE872_FROM : STD_LOGIC; 
  signal CHOICE872_GROM : STD_LOGIC; 
  signal CHOICE277_FROM : STD_LOGIC; 
  signal CHOICE277_GROM : STD_LOGIC; 
  signal U3_state_FFd19_FROM : STD_LOGIC; 
  signal U3_state_FFd19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd19_In : STD_LOGIC; 
  signal led_0_OBUF_GROM : STD_LOGIC; 
  signal U3_N31827_FROM : STD_LOGIC; 
  signal U3_N31827_GROM : STD_LOGIC; 
  signal N44502_FROM : STD_LOGIC; 
  signal N44502_GROM : STD_LOGIC; 
  signal U1_I46_N1762_FROM : STD_LOGIC; 
  signal U1_I46_N1762_GROM : STD_LOGIC; 
  signal N44656_FROM : STD_LOGIC; 
  signal N44656_GROM : STD_LOGIC; 
  signal N38423_FROM : STD_LOGIC; 
  signal N38423_GROM : STD_LOGIC; 
  signal N44652_FROM : STD_LOGIC; 
  signal N44652_GROM : STD_LOGIC; 
  signal soft_reset1_1_FROM : STD_LOGIC; 
  signal soft_reset1_1_GROM : STD_LOGIC; 
  signal N44648_FROM : STD_LOGIC; 
  signal N44648_GROM : STD_LOGIC; 
  signal CHOICE301_FROM : STD_LOGIC; 
  signal CHOICE301_GROM : STD_LOGIC; 
  signal CHOICE774_FROM : STD_LOGIC; 
  signal CHOICE774_GROM : STD_LOGIC; 
  signal CHOICE293_FROM : STD_LOGIC; 
  signal CHOICE293_GROM : STD_LOGIC; 
  signal N38375_FROM : STD_LOGIC; 
  signal N38375_GROM : STD_LOGIC; 
  signal blocked_0_FROM : STD_LOGIC; 
  signal CHOICE723_FROM : STD_LOGIC; 
  signal CHOICE723_GROM : STD_LOGIC; 
  signal CHOICE696_FROM : STD_LOGIC; 
  signal CHOICE696_GROM : STD_LOGIC; 
  signal CHOICE310_FROM : STD_LOGIC; 
  signal CHOICE310_GROM : STD_LOGIC; 
  signal blocked_1_FROM : STD_LOGIC; 
  signal CHOICE369_FROM : STD_LOGIC; 
  signal CHOICE369_GROM : STD_LOGIC; 
  signal U1_I43_N1762_FROM : STD_LOGIC; 
  signal U1_I43_N1762_GROM : STD_LOGIC; 
  signal U1_I60_N1762_FROM : STD_LOGIC; 
  signal U1_I60_N1762_GROM : STD_LOGIC; 
  signal U3_dontread_0_n0001_FROM : STD_LOGIC; 
  signal U3_dontread_0_n0001_GROM : STD_LOGIC; 
  signal CHOICE327_FROM : STD_LOGIC; 
  signal CHOICE327_GROM : STD_LOGIC; 
  signal blocked_2_FROM : STD_LOGIC; 
  signal CHOICE352_GROM : STD_LOGIC; 
  signal CHOICE512_FROM : STD_LOGIC; 
  signal CHOICE512_GROM : STD_LOGIC; 
  signal CHOICE265_FROM : STD_LOGIC; 
  signal CHOICE265_GROM : STD_LOGIC; 
  signal N44336_FROM : STD_LOGIC; 
  signal N44336_GROM : STD_LOGIC; 
  signal CHOICE361_FROM : STD_LOGIC; 
  signal CHOICE361_GROM : STD_LOGIC; 
  signal U3_sel_read_5_1_FROM : STD_LOGIC; 
  signal U3_sel_read_5_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_n010539_1_O : STD_LOGIC; 
  signal blocked_3_FROM : STD_LOGIC; 
  signal N44542_FROM : STD_LOGIC; 
  signal N44542_GROM : STD_LOGIC; 
  signal U3_dontread_2_n0000_FROM : STD_LOGIC; 
  signal U3_dontread_2_n0000_GROM : STD_LOGIC; 
  signal CHOICE344_FROM : STD_LOGIC; 
  signal CHOICE344_GROM : STD_LOGIC; 
  signal blocked_4_FROM : STD_LOGIC; 
  signal N44514_FROM : STD_LOGIC; 
  signal N44514_GROM : STD_LOGIC; 
  signal CHOICE378_FROM : STD_LOGIC; 
  signal CHOICE378_GROM : STD_LOGIC; 
  signal U3_n0049_FROM : STD_LOGIC; 
  signal U3_n0049_GROM : STD_LOGIC; 
  signal blocked_5_FROM : STD_LOGIC; 
  signal CHOICE661_FROM : STD_LOGIC; 
  signal CHOICE661_GROM : STD_LOGIC; 
  signal N44622_FROM : STD_LOGIC; 
  signal N44622_GROM : STD_LOGIC; 
  signal N38588_FROM : STD_LOGIC; 
  signal N38588_GROM : STD_LOGIC; 
  signal reset_IBUF_1_FROM : STD_LOGIC; 
  signal reset_IBUF_1_GROM : STD_LOGIC; 
  signal U2_n0132_FROM : STD_LOGIC; 
  signal U2_n0132_GROM : STD_LOGIC; 
  signal CHOICE578_FROM : STD_LOGIC; 
  signal CHOICE578_GROM : STD_LOGIC; 
  signal U2_Mxor_cpar_1_Xo_4_GROM : STD_LOGIC; 
  signal U2_Mxor_cpar_1_Xo_5_FROM : STD_LOGIC; 
  signal U2_Mxor_cpar_1_Xo_5_GROM : STD_LOGIC; 
  signal U1_I52_N1762_FROM : STD_LOGIC; 
  signal U1_I52_N1762_GROM : STD_LOGIC; 
  signal N38533_FROM : STD_LOGIC; 
  signal N38533_GROM : STD_LOGIC; 
  signal CHOICE475_FROM : STD_LOGIC; 
  signal CHOICE475_GROM : STD_LOGIC; 
  signal N44510_FROM : STD_LOGIC; 
  signal N44510_GROM : STD_LOGIC; 
  signal N38478_FROM : STD_LOGIC; 
  signal N38478_GROM : STD_LOGIC; 
  signal U3_state_FFd2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U2_fwrg1_LOGIC_ONE : STD_LOGIC; 
  signal U2_fwrg2_LOGIC_ONE : STD_LOGIC; 
  signal U2_fwrg3_FFY_RST : STD_LOGIC; 
  signal CHOICE389_FROM : STD_LOGIC; 
  signal CHOICE389_GROM : STD_LOGIC; 
  signal U1_etr_paepaf_reg_2_FROM : STD_LOGIC; 
  signal U1_etr_paepaf_reg_2_GROM : STD_LOGIC; 
  signal U1_enw_paf_counter1_4_FROM : STD_LOGIC; 
  signal U1_enw_paf_counter1_4_GROM : STD_LOGIC; 
  signal CHOICE400_FROM : STD_LOGIC; 
  signal CHOICE400_GROM : STD_LOGIC; 
  signal CHOICE894_FROM : STD_LOGIC; 
  signal CHOICE894_GROM : STD_LOGIC; 
  signal N39609_FROM : STD_LOGIC; 
  signal N39609_GROM : STD_LOGIC; 
  signal U3_N31479_FROM : STD_LOGIC; 
  signal U3_N31479_GROM : STD_LOGIC; 
  signal CHOICE931_FROM : STD_LOGIC; 
  signal CHOICE931_GROM : STD_LOGIC; 
  signal CHOICE856_FROM : STD_LOGIC; 
  signal CHOICE856_GROM : STD_LOGIC; 
  signal N39520_FROM : STD_LOGIC; 
  signal N39520_GROM : STD_LOGIC; 
  signal U1_I44_N1762_FROM : STD_LOGIC; 
  signal U1_I44_N1762_GROM : STD_LOGIC; 
  signal U1_I65_N1762_FROM : STD_LOGIC; 
  signal U1_I65_N1762_GROM : STD_LOGIC; 
  signal U3_dontread_3_n0001_FROM : STD_LOGIC; 
  signal U3_dontread_3_n0001_GROM : STD_LOGIC; 
  signal N44290_FROM : STD_LOGIC; 
  signal N44290_GROM : STD_LOGIC; 
  signal N44328_FROM : STD_LOGIC; 
  signal N44328_GROM : STD_LOGIC; 
  signal CHOICE460_FROM : STD_LOGIC; 
  signal CHOICE460_GROM : STD_LOGIC; 
  signal CHOICE824_FROM : STD_LOGIC; 
  signal CHOICE824_GROM : STD_LOGIC; 
  signal N44482_FROM : STD_LOGIC; 
  signal N44482_GROM : STD_LOGIC; 
  signal U3_state_FFd38_FROM : STD_LOGIC; 
  signal U3_state_FFd38_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal U3_state_FFd38_In_O : STD_LOGIC; 
  signal U1_enw_paf_counter1_2_FROM : STD_LOGIC; 
  signal U1_enw_paf_counter1_2_GROM : STD_LOGIC; 
  signal U1_paf_cnt_set_0_BYMUXNOT : STD_LOGIC; 
  signal U1_paf_cnt_set_1_BYMUXNOT : STD_LOGIC; 
  signal U1_paf_cnt_set_2_BYMUXNOT : STD_LOGIC; 
  signal U1_paf_cnt_set_3_BYMUXNOT : STD_LOGIC; 
  signal oe_5_OBUF_FROM : STD_LOGIC; 
  signal oe_5_OBUF_GROM : STD_LOGIC; 
  signal U1_paf_cnt_set_4_BYMUXNOT : STD_LOGIC; 
  signal oe_4_OBUF_FROM : STD_LOGIC; 
  signal oe_4_OBUF_GROM : STD_LOGIC; 
  signal U1_paf_cnt_set_5_BYMUXNOT : STD_LOGIC; 
  signal oe_3_OBUF_FROM : STD_LOGIC; 
  signal oe_3_OBUF_GROM : STD_LOGIC; 
  signal oe_2_OBUF_FROM : STD_LOGIC; 
  signal oe_2_OBUF_GROM : STD_LOGIC; 
  signal oe_1_OBUF_FROM : STD_LOGIC; 
  signal oe_1_OBUF_GROM : STD_LOGIC; 
  signal oe_0_OBUF_FROM : STD_LOGIC; 
  signal oe_0_OBUF_GROM : STD_LOGIC; 
  signal N37993_FROM : STD_LOGIC; 
  signal N37993_GROM : STD_LOGIC; 
  signal CHOICE846_FROM : STD_LOGIC; 
  signal CHOICE846_GROM : STD_LOGIC; 
  signal CHOICE897_GROM : STD_LOGIC; 
  signal CHOICE900_FROM : STD_LOGIC; 
  signal CHOICE900_GROM : STD_LOGIC; 
  signal N44598_FROM : STD_LOGIC; 
  signal N44598_GROM : STD_LOGIC; 
  signal CHOICE632_FROM : STD_LOGIC; 
  signal CHOICE632_GROM : STD_LOGIC; 
  signal N44390_FROM : STD_LOGIC; 
  signal N44390_GROM : STD_LOGIC; 
  signal CHOICE637_FROM : STD_LOGIC; 
  signal CHOICE637_GROM : STD_LOGIC; 
  signal CHOICE813_FROM : STD_LOGIC; 
  signal CHOICE813_GROM : STD_LOGIC; 
  signal CHOICE640_GROM : STD_LOGIC; 
  signal CHOICE646_FROM : STD_LOGIC; 
  signal CHOICE646_GROM : STD_LOGIC; 
  signal evid_0_IBUF_24 : STD_LOGIC; 
  signal doneout_ENABLE : STD_LOGIC; 
  signal doneout_TORGTS : STD_LOGIC; 
  signal doneout_OUTMUX : STD_LOGIC; 
  signal doneout_OBUF : STD_LOGIC; 
  signal doneout_LOGIC_ONE : STD_LOGIC; 
  signal evid_1_IBUF_25 : STD_LOGIC; 
  signal evid_2_IBUF_26 : STD_LOGIC; 
  signal evid_3_IBUF_27 : STD_LOGIC; 
  signal evid_4_IBUF_28 : STD_LOGIC; 
  signal evid_5_IBUF_29 : STD_LOGIC; 
  signal evid_6_IBUF_30 : STD_LOGIC; 
  signal evid_7_IBUF_31 : STD_LOGIC; 
  signal evid_8_IBUF_32 : STD_LOGIC; 
  signal evid_9_IBUF_33 : STD_LOGIC; 
  signal sff_ENABLE : STD_LOGIC; 
  signal sff_TORGTS : STD_LOGIC; 
  signal sff_OUTMUX : STD_LOGIC; 
  signal dout_0_ENABLE : STD_LOGIC; 
  signal dout_0_TORGTS : STD_LOGIC; 
  signal dout_0_OUTMUX : STD_LOGIC; 
  signal dout_0_TDATANOT : STD_LOGIC; 
  signal dout_0_OD : STD_LOGIC; 
  signal dout_1_ENABLE : STD_LOGIC; 
  signal dout_1_TORGTS : STD_LOGIC; 
  signal dout_1_OUTMUX : STD_LOGIC; 
  signal dout_1_TDATANOT : STD_LOGIC; 
  signal dout_1_OD : STD_LOGIC; 
  signal dout_2_ENABLE : STD_LOGIC; 
  signal dout_2_TORGTS : STD_LOGIC; 
  signal dout_2_OUTMUX : STD_LOGIC; 
  signal dout_2_TDATANOT : STD_LOGIC; 
  signal dout_2_OD : STD_LOGIC; 
  signal dout_3_ENABLE : STD_LOGIC; 
  signal dout_3_TORGTS : STD_LOGIC; 
  signal dout_3_OUTMUX : STD_LOGIC; 
  signal dout_3_TDATANOT : STD_LOGIC; 
  signal dout_3_OD : STD_LOGIC; 
  signal evid_10_IBUF_34 : STD_LOGIC; 
  signal dout_4_ENABLE : STD_LOGIC; 
  signal dout_4_TORGTS : STD_LOGIC; 
  signal dout_4_OUTMUX : STD_LOGIC; 
  signal dout_4_TDATANOT : STD_LOGIC; 
  signal dout_4_OD : STD_LOGIC; 
  signal evid_11_IBUF_35 : STD_LOGIC; 
  signal dout_5_ENABLE : STD_LOGIC; 
  signal dout_5_TORGTS : STD_LOGIC; 
  signal dout_5_OUTMUX : STD_LOGIC; 
  signal dout_5_TDATANOT : STD_LOGIC; 
  signal dout_5_OD : STD_LOGIC; 
  signal dout_6_ENABLE : STD_LOGIC; 
  signal dout_6_TORGTS : STD_LOGIC; 
  signal dout_6_OUTMUX : STD_LOGIC; 
  signal dout_6_TDATANOT : STD_LOGIC; 
  signal dout_6_OD : STD_LOGIC; 
  signal dout_7_ENABLE : STD_LOGIC; 
  signal dout_7_TORGTS : STD_LOGIC; 
  signal dout_7_OUTMUX : STD_LOGIC; 
  signal dout_7_TDATANOT : STD_LOGIC; 
  signal dout_7_OD : STD_LOGIC; 
  signal dout_8_ENABLE : STD_LOGIC; 
  signal dout_8_TORGTS : STD_LOGIC; 
  signal dout_8_OUTMUX : STD_LOGIC; 
  signal dout_8_TDATANOT : STD_LOGIC; 
  signal dout_8_OD : STD_LOGIC; 
  signal dout_9_ENABLE : STD_LOGIC; 
  signal dout_9_TORGTS : STD_LOGIC; 
  signal dout_9_OUTMUX : STD_LOGIC; 
  signal dout_9_TDATANOT : STD_LOGIC; 
  signal dout_9_OD : STD_LOGIC; 
  signal locked_p_ENABLE : STD_LOGIC; 
  signal locked_p_TORGTS : STD_LOGIC; 
  signal locked_p_OUTMUX : STD_LOGIC; 
  signal hasul_0_ENABLE : STD_LOGIC; 
  signal hasul_0_TORGTS : STD_LOGIC; 
  signal hasul_0_OUTMUX : STD_LOGIC; 
  signal hasul_1_ENABLE : STD_LOGIC; 
  signal hasul_1_TORGTS : STD_LOGIC; 
  signal hasul_1_OUTMUX : STD_LOGIC; 
  signal hasul_2_ENABLE : STD_LOGIC; 
  signal hasul_2_TORGTS : STD_LOGIC; 
  signal hasul_2_OUTMUX : STD_LOGIC; 
  signal dout_10_ENABLE : STD_LOGIC; 
  signal dout_10_TORGTS : STD_LOGIC; 
  signal dout_10_OUTMUX : STD_LOGIC; 
  signal dout_10_TDATANOT : STD_LOGIC; 
  signal dout_10_OD : STD_LOGIC; 
  signal hasul_3_ENABLE : STD_LOGIC; 
  signal hasul_3_TORGTS : STD_LOGIC; 
  signal hasul_3_OUTMUX : STD_LOGIC; 
  signal dout_11_ENABLE : STD_LOGIC; 
  signal dout_11_TORGTS : STD_LOGIC; 
  signal dout_11_OUTMUX : STD_LOGIC; 
  signal dout_11_TDATANOT : STD_LOGIC; 
  signal dout_11_OD : STD_LOGIC; 
  signal hasul_4_ENABLE : STD_LOGIC; 
  signal hasul_4_TORGTS : STD_LOGIC; 
  signal hasul_4_OUTMUX : STD_LOGIC; 
  signal dout_12_ENABLE : STD_LOGIC; 
  signal dout_12_TORGTS : STD_LOGIC; 
  signal dout_12_OUTMUX : STD_LOGIC; 
  signal dout_12_TDATANOT : STD_LOGIC; 
  signal dout_12_OD : STD_LOGIC; 
  signal hasul_5_ENABLE : STD_LOGIC; 
  signal hasul_5_TORGTS : STD_LOGIC; 
  signal hasul_5_OUTMUX : STD_LOGIC; 
  signal dout_13_ENABLE : STD_LOGIC; 
  signal dout_13_TORGTS : STD_LOGIC; 
  signal dout_13_OUTMUX : STD_LOGIC; 
  signal dout_13_TDATANOT : STD_LOGIC; 
  signal dout_13_OD : STD_LOGIC; 
  signal dout_14_ENABLE : STD_LOGIC; 
  signal dout_14_TORGTS : STD_LOGIC; 
  signal dout_14_OUTMUX : STD_LOGIC; 
  signal dout_14_TDATANOT : STD_LOGIC; 
  signal dout_14_OD : STD_LOGIC; 
  signal dout_15_ENABLE : STD_LOGIC; 
  signal dout_15_TORGTS : STD_LOGIC; 
  signal dout_15_OUTMUX : STD_LOGIC; 
  signal dout_15_TDATANOT : STD_LOGIC; 
  signal dout_15_OD : STD_LOGIC; 
  signal tp_0_ENABLE : STD_LOGIC; 
  signal tp_0_TORGTS : STD_LOGIC; 
  signal tp_0_OUTMUX : STD_LOGIC; 
  signal tp_1_ENABLE : STD_LOGIC; 
  signal tp_1_TORGTS : STD_LOGIC; 
  signal tp_1_OUTMUX : STD_LOGIC; 
  signal tp_2_ENABLE : STD_LOGIC; 
  signal tp_2_TORGTS : STD_LOGIC; 
  signal tp_2_OUTMUX : STD_LOGIC; 
  signal tp_3_ENABLE : STD_LOGIC; 
  signal tp_3_TORGTS : STD_LOGIC; 
  signal tp_3_OUTMUX : STD_LOGIC; 
  signal wclkena_p_ENABLE : STD_LOGIC; 
  signal wclkena_p_TORGTS : STD_LOGIC; 
  signal wclkena_p_OUTMUX : STD_LOGIC; 
  signal fout_0_IBUF_36 : STD_LOGIC; 
  signal fout_1_IBUF_37 : STD_LOGIC; 
  signal fout_2_IBUF_38 : STD_LOGIC; 
  signal fout_3_IBUF_39 : STD_LOGIC; 
  signal fout_4_IBUF_40 : STD_LOGIC; 
  signal fout_5_IBUF_41 : STD_LOGIC; 
  signal fout_6_IBUF_42 : STD_LOGIC; 
  signal fout_7_IBUF_43 : STD_LOGIC; 
  signal fout_8_IBUF_44 : STD_LOGIC; 
  signal fout_9_IBUF_45 : STD_LOGIC; 
  signal lock_0_IBUF_46 : STD_LOGIC; 
  signal lock_1_IBUF_47 : STD_LOGIC; 
  signal lock_2_IBUF_48 : STD_LOGIC; 
  signal lock_3_IBUF_49 : STD_LOGIC; 
  signal lock_4_IBUF_50 : STD_LOGIC; 
  signal lock_5_IBUF_51 : STD_LOGIC; 
  signal led_0_ENABLE : STD_LOGIC; 
  signal led_0_TORGTS : STD_LOGIC; 
  signal led_0_OUTMUX : STD_LOGIC; 
  signal led_1_ENABLE : STD_LOGIC; 
  signal led_1_TORGTS : STD_LOGIC; 
  signal led_1_OUTMUX : STD_LOGIC; 
  signal led_1_ODNOT : STD_LOGIC; 
  signal recoff_p_ENABLE : STD_LOGIC; 
  signal recoff_p_TORGTS : STD_LOGIC; 
  signal recoff_p_OUTMUX : STD_LOGIC; 
  signal etr_x_IBUF_52 : STD_LOGIC; 
  signal clk20_p_ENABLE : STD_LOGIC; 
  signal clk20_p_TORGTS : STD_LOGIC; 
  signal clk20_p_OUTMUX : STD_LOGIC; 
  signal paf_0_IBUF_53 : STD_LOGIC; 
  signal paf_1_IBUF_54 : STD_LOGIC; 
  signal paf_2_IBUF_55 : STD_LOGIC; 
  signal paf_3_IBUF_56 : STD_LOGIC; 
  signal paf_4_IBUF_57 : STD_LOGIC; 
  signal paf_5_IBUF_58 : STD_LOGIC; 
  signal cs_IBUF_59 : STD_LOGIC; 
  signal txena_p_ENABLE : STD_LOGIC; 
  signal txena_p_TORGTS : STD_LOGIC; 
  signal txena_p_OUTMUX : STD_LOGIC; 
  signal txena_p_TDATANOT : STD_LOGIC; 
  signal txena_reg : STD_LOGIC; 
  signal txena_p_OD : STD_LOGIC; 
  signal fout_10_IBUF_60 : STD_LOGIC; 
  signal fout_11_IBUF_61 : STD_LOGIC; 
  signal fout_12_IBUF_62 : STD_LOGIC; 
  signal fout_13_IBUF_63 : STD_LOGIC; 
  signal fout_14_IBUF_64 : STD_LOGIC; 
  signal fout_15_IBUF_65 : STD_LOGIC; 
  signal valen_IBUF_66 : STD_LOGIC; 
  signal reset_IBUF_67 : STD_LOGIC; 
  signal par_0_IBUF_68 : STD_LOGIC; 
  signal par_1_IBUF_69 : STD_LOGIC; 
  signal token_IBUF : STD_LOGIC; 
  signal cspare_0_IBUF_70 : STD_LOGIC; 
  signal ren_0_ENABLE : STD_LOGIC; 
  signal ren_0_TORGTS : STD_LOGIC; 
  signal ren_0_OUTMUX : STD_LOGIC; 
  signal cspare_1_IBUF_71 : STD_LOGIC; 
  signal ren_1_ENABLE : STD_LOGIC; 
  signal ren_1_TORGTS : STD_LOGIC; 
  signal ren_1_OUTMUX : STD_LOGIC; 
  signal ren_2_ENABLE : STD_LOGIC; 
  signal ren_2_TORGTS : STD_LOGIC; 
  signal ren_2_OUTMUX : STD_LOGIC; 
  signal ren_3_ENABLE : STD_LOGIC; 
  signal ren_3_TORGTS : STD_LOGIC; 
  signal ren_3_OUTMUX : STD_LOGIC; 
  signal ren_4_ENABLE : STD_LOGIC; 
  signal ren_4_TORGTS : STD_LOGIC; 
  signal ren_4_OUTMUX : STD_LOGIC; 
  signal ren_5_ENABLE : STD_LOGIC; 
  signal ren_5_TORGTS : STD_LOGIC; 
  signal ren_5_OUTMUX : STD_LOGIC; 
  signal donein_IBUF_72 : STD_LOGIC; 
  signal db_10_ENABLE : STD_LOGIC; 
  signal db_10_TORGTS : STD_LOGIC; 
  signal db_10_OUTMUX : STD_LOGIC; 
  signal db_10_IBUF : STD_LOGIC; 
  signal db_11_ENABLE : STD_LOGIC; 
  signal db_11_TORGTS : STD_LOGIC; 
  signal db_11_OUTMUX : STD_LOGIC; 
  signal db_11_IBUF : STD_LOGIC; 
  signal db_12_ENABLE : STD_LOGIC; 
  signal db_12_TORGTS : STD_LOGIC; 
  signal db_12_OUTMUX : STD_LOGIC; 
  signal db_12_IBUF : STD_LOGIC; 
  signal db_13_ENABLE : STD_LOGIC; 
  signal db_13_TORGTS : STD_LOGIC; 
  signal db_13_OUTMUX : STD_LOGIC; 
  signal db_13_IBUF : STD_LOGIC; 
  signal db_14_ENABLE : STD_LOGIC; 
  signal db_14_TORGTS : STD_LOGIC; 
  signal db_14_OUTMUX : STD_LOGIC; 
  signal db_14_IBUF : STD_LOGIC; 
  signal db_15_ENABLE : STD_LOGIC; 
  signal db_15_TORGTS : STD_LOGIC; 
  signal db_15_OUTMUX : STD_LOGIC; 
  signal db_15_IBUF : STD_LOGIC; 
  signal ceros_done_p_ENABLE : STD_LOGIC; 
  signal ceros_done_p_TORGTS : STD_LOGIC; 
  signal ceros_done_p_OUTMUX : STD_LOGIC; 
  signal fsen_ENABLE : STD_LOGIC; 
  signal fsen_TORGTS : STD_LOGIC; 
  signal fsen_OUTMUX : STD_LOGIC; 
  signal fmrs_ENABLE : STD_LOGIC; 
  signal fmrs_TORGTS : STD_LOGIC; 
  signal fmrs_OUTMUX : STD_LOGIC; 
  signal fmrs_ODNOT : STD_LOGIC; 
  signal lives_p_ENABLE : STD_LOGIC; 
  signal lives_p_TORGTS : STD_LOGIC; 
  signal lives_p_OUTMUX : STD_LOGIC; 
  signal fld_ENABLE : STD_LOGIC; 
  signal fld_TORGTS : STD_LOGIC; 
  signal fld_OUTMUX : STD_LOGIC; 
  signal fsi_ENABLE : STD_LOGIC; 
  signal fsi_TORGTS : STD_LOGIC; 
  signal fsi_OUTMUX : STD_LOGIC; 
  signal U1_paf_counter_3_13_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_0_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_15_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_4_5_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_4_1_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_3_FFY_RST : STD_LOGIC; 
  signal U3_header1_reg_1_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_1_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd12_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd22_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd12_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd24_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd24_FFX_RST : STD_LOGIC; 
  signal U1_timeout_value_11_FFY_SET : STD_LOGIC; 
  signal U3_time_out_FFY_RST : STD_LOGIC; 
  signal fout_10_IFF_RST : STD_LOGIC; 
  signal fout_11_IFF_RST : STD_LOGIC; 
  signal fout_12_IFF_RST : STD_LOGIC; 
  signal fout_13_IFF_RST : STD_LOGIC; 
  signal fout_14_IFF_RST : STD_LOGIC; 
  signal fout_15_IFF_RST : STD_LOGIC; 
  signal reset_IFF_RST : STD_LOGIC; 
  signal U2_byte_par_5_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_1_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_3_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_3_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_5_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_7_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_7_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_9_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_9_FFY_RST : STD_LOGIC; 
  signal blocked_0_FFY_RST : STD_LOGIC; 
  signal U1_warn_PAF_FFY_SET : STD_LOGIC; 
  signal blocked_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_11_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_0_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_13_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_1_15_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_0_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_0_9_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_11_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_13_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_0_15_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_13_FFX_RST : STD_LOGIC; 
  signal U2_disparity_7_FFY_RST : STD_LOGIC; 
  signal U2_disparity_1_FFX_RST : STD_LOGIC; 
  signal U2_disparity_3_FFY_RST : STD_LOGIC; 
  signal U2_disparity_5_FFY_RST : STD_LOGIC; 
  signal U2_disparity_3_FFX_RST : STD_LOGIC; 
  signal U2_disparity_11_FFX_RST : STD_LOGIC; 
  signal U2_disparity_13_FFX_RST : STD_LOGIC; 
  signal U2_disparity_15_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_1_13_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_5_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_1_7_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_1_9_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_11_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_9_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_1_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_7_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_1_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_1_3_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_5_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_1_3_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_3_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_5_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_7_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_0_7_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_0_9_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_0_11_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_9_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_1_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_3_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_3_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_5_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_7_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_5_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_7_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_9_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_11_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_13_FFY_RST : STD_LOGIC; 
  signal U2_word_par_5_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_27_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_19_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_19_FFY_RST : STD_LOGIC; 
  signal U2_word_par_7_FFX_RST : STD_LOGIC; 
  signal U2_word_par_7_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_29_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_29_FFY_RST : STD_LOGIC; 
  signal U2_word_par_9_FFX_RST : STD_LOGIC; 
  signal U2_word_par_9_FFY_RST : STD_LOGIC; 
  signal U3_header2_reg_11_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_7_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_3_11_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_11_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_3_13_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_11_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_3_0_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_2_13_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_2_15_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_3_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_3_FFY_RST : STD_LOGIC; 
  signal U3_read_fifo_dir_FFY_RST : STD_LOGIC; 
  signal U3_s_data_6_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd27_1_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd30_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd40_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd30_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd40_FFX_SET : STD_LOGIC; 
  signal U3_rob_id_2_FFY_RST : STD_LOGIC; 
  signal U3_rob_id_3_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_11_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_1_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_3_3_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_3_5_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_5_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_3_7_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_10_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_4_3_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_5_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_7_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_4_11_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_4_7_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_9_FFY_RST : STD_LOGIC; 
  signal U3_sel_read_1_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_1_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_3_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_1_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_3_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_5_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_5_FFY_RST : STD_LOGIC; 
  signal U1_db_error2_11_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_7_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_5_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_5_7_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_5_1_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_3_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_5_5_FFY_RST : STD_LOGIC; 
  signal U3_maxw_reached_1_FFX_RST : STD_LOGIC; 
  signal U3_s_data_2_FFY_RST : STD_LOGIC; 
  signal U3_s_data_3_FFY_RST : STD_LOGIC; 
  signal U3_s_data_4_FFY_RST : STD_LOGIC; 
  signal U3_maxw_reached_1_FFY_RST : STD_LOGIC; 
  signal U3_maxw_reached_3_FFY_RST : STD_LOGIC; 
  signal U3_maxw_reached_3_FFX_RST : STD_LOGIC; 
  signal U3_maxw_reached_5_FFY_RST : STD_LOGIC; 
  signal U1_hasunlock_5_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_4_15_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_9_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_11_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_4_13_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_5_0_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_4_13_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_3_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_13_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_5_5_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_7_FFX_RST : STD_LOGIC; 
  signal U1_paf_counter_5_9_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_5_11_FFY_RST : STD_LOGIC; 
  signal U3_s_data_7_FFY_RST : STD_LOGIC; 
  signal U3_s_data_8_FFY_RST : STD_LOGIC; 
  signal U3_s_data_5_FFY_RST : STD_LOGIC; 
  signal U3_s_data_9_FFY_RST : STD_LOGIC; 
  signal U3_txena_dir_FFY_RST : STD_LOGIC; 
  signal U3_s_data_1_FFY_RST : STD_LOGIC; 
  signal U3_s_data_0_FFY_RST : STD_LOGIC; 
  signal U3_evid_mis_5_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd8_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd8_FFX_RST : STD_LOGIC; 
  signal U3_time_counter_12_FFY_RST : STD_LOGIC; 
  signal U2_q2_FFY_RST : STD_LOGIC; 
  signal U2_q4_FFY_RST : STD_LOGIC; 
  signal U2_q2_FFX_RST : STD_LOGIC; 
  signal U2_q4_FFX_RST : STD_LOGIC; 
  signal U2_loadcnt_1_FFY_RST : STD_LOGIC; 
  signal U2_loadcnt_3_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_9_FFX_SET : STD_LOGIC; 
  signal U2_pae_paf_reg_7_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_9_FFY_RST : STD_LOGIC; 
  signal U3_error_evid_FFY_RST : STD_LOGIC; 
  signal U3_time_counter_11_FFY_RST : STD_LOGIC; 
  signal U3_maxw_reached_5_FFX_RST : STD_LOGIC; 
  signal U2_word_par_11_FFY_RST : STD_LOGIC; 
  signal U2_word_par_13_FFY_RST : STD_LOGIC; 
  signal U2_word_par_13_FFX_RST : STD_LOGIC; 
  signal U2_word_par_11_FFX_RST : STD_LOGIC; 
  signal U2_word_par_15_FFX_RST : STD_LOGIC; 
  signal U2_word_par_15_FFY_RST : STD_LOGIC; 
  signal U3_time_counter_0_FFY_RST : STD_LOGIC; 
  signal U3_time_counter_3_FFY_RST : STD_LOGIC; 
  signal U3_time_counter_1_FFY_RST : STD_LOGIC; 
  signal U3_sel_read_0_FFY_RST : STD_LOGIC; 
  signal U3_trail_FFY_RST : STD_LOGIC; 
  signal U3_sel_read_5_FFY_RST : STD_LOGIC; 
  signal U3_sel_read_4_FFY_RST : STD_LOGIC; 
  signal U3_sel_read_2_FFY_RST : STD_LOGIC; 
  signal U3_sel_read_3_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd4_FFY_RST : STD_LOGIC; 
  signal U3_timed_out_3_FFX_RST : STD_LOGIC; 
  signal U3_timed_out_5_FFY_RST : STD_LOGIC; 
  signal U3_timed_out_5_FFX_RST : STD_LOGIC; 
  signal U1_ff_reg_5_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd4_FFX_RST : STD_LOGIC; 
  signal U3_trailer_reg_13_FFY_RST : STD_LOGIC; 
  signal U3_trailer_reg_13_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd6_FFY_RST : STD_LOGIC; 
  signal U3_trailer_reg_1_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd6_FFX_RST : STD_LOGIC; 
  signal U3_time_counter_3_FFX_RST : STD_LOGIC; 
  signal U3_time_counter_5_FFX_RST : STD_LOGIC; 
  signal U3_time_counter_5_FFY_RST : STD_LOGIC; 
  signal U3_time_counter_7_FFX_RST : STD_LOGIC; 
  signal U3_time_counter_7_FFY_RST : STD_LOGIC; 
  signal U3_time_counter_9_FFX_RST : STD_LOGIC; 
  signal U3_time_counter_9_FFY_RST : STD_LOGIC; 
  signal U3_timed_out_1_FFX_RST : STD_LOGIC; 
  signal U3_timed_out_1_FFY_RST : STD_LOGIC; 
  signal U3_timed_out_3_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd22_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd16_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd16_FFX_RST : STD_LOGIC; 
  signal U3_trailer_reg_0_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd32_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd26_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd26_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd27_1_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd28_FFY_RST : STD_LOGIC; 
  signal U3_time_counter_11_FFX_RST : STD_LOGIC; 
  signal U3_ros_done_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_11_FFY_RST : STD_LOGIC; 
  signal U3_word_count_0_FFY_RST : STD_LOGIC; 
  signal U3_word_count_1_FFY_RST : STD_LOGIC; 
  signal U3_trailer_reg_1_FFX_RST : STD_LOGIC; 
  signal U3_state_FFd10_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd10_FFX_RST : STD_LOGIC; 
  signal U1_hasunlock_1_FFY_RST : STD_LOGIC; 
  signal U1_hasunlock_1_FFX_RST : STD_LOGIC; 
  signal U1_hasunlock_3_FFY_RST : STD_LOGIC; 
  signal U1_hasunlock_3_FFX_RST : STD_LOGIC; 
  signal U1_hasunlock_4_FFY_RST : STD_LOGIC; 
  signal U3_s_data_10_FFY_RST : STD_LOGIC; 
  signal U3_s_data_11_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_13_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_11_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_13_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_21_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_21_FFY_RST : STD_LOGIC; 
  signal U2_word_par_1_FFY_RST : STD_LOGIC; 
  signal U2_word_par_1_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_31_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_31_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_23_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_15_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_15_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_23_FFX_RST : STD_LOGIC; 
  signal U2_word_par_3_FFX_RST : STD_LOGIC; 
  signal U2_word_par_3_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_25_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_25_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_17_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_17_FFY_RST : STD_LOGIC; 
  signal U2_word_par_5_FFY_RST : STD_LOGIC; 
  signal U2_byte_par_27_FFY_RST : STD_LOGIC; 
  signal U3_trailer_reg_7_FFX_RST : STD_LOGIC; 
  signal U3_trailer_reg_9_FFX_RST : STD_LOGIC; 
  signal U3_word_count_3_FFY_RST : STD_LOGIC; 
  signal U3_word_count_3_FFX_RST : STD_LOGIC; 
  signal U3_word_count_5_FFY_RST : STD_LOGIC; 
  signal U3_word_count_5_FFX_RST : STD_LOGIC; 
  signal U3_word_count_7_FFY_RST : STD_LOGIC; 
  signal U3_word_count_7_FFX_RST : STD_LOGIC; 
  signal U3_word_count_9_FFY_RST : STD_LOGIC; 
  signal U2_loadcnt_1_FFX_SET : STD_LOGIC; 
  signal U2_loadcnt_3_FFX_SET : STD_LOGIC; 
  signal U2_loadcnt_5_FFY_RST : STD_LOGIC; 
  signal U2_loadcnt_5_FFX_SET : STD_LOGIC; 
  signal U1_per_fifo_aux_2_FFY_SET : STD_LOGIC; 
  signal U1_per_paepaf_reg_FFY_SET : STD_LOGIC; 
  signal U3_state_FFd14_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd31_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd35_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_15_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_17_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_18_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_19_FFY_RST : STD_LOGIC; 
  signal U3_rob_id_0_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd13_FFX_RST : STD_LOGIC; 
  signal U2_byte_par_1_FFY_RST : STD_LOGIC; 
  signal U3_header1_reg_5_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_13_FFX_RST : STD_LOGIC; 
  signal U3_header1_reg_7_FFY_RST : STD_LOGIC; 
  signal U3_header1_reg_7_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_11_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_11_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_13_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_17_FFY_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_21_FFY_SET : STD_LOGIC; 
  signal U2_pae_paf_reg_21_FFX_RST : STD_LOGIC; 
  signal U2_pae_paf_reg_15_FFY_RST : STD_LOGIC; 
  signal blocked_2_FFY_RST : STD_LOGIC; 
  signal U1_resynch_FF_FFY_SET : STD_LOGIC; 
  signal U1_paf_reg_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_reg_1_FFX_RST : STD_LOGIC; 
  signal U1_paf_reg_3_FFY_RST : STD_LOGIC; 
  signal U1_paf_reg_3_FFX_RST : STD_LOGIC; 
  signal U1_paf_reg_4_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd19_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_10_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_10_FFX_RST : STD_LOGIC; 
  signal U1_db_error2_10_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd36_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_9_FFX_RST : STD_LOGIC; 
  signal U3_evid_mis_3_FFY_RST : STD_LOGIC; 
  signal U3_evid_mis_1_FFY_RST : STD_LOGIC; 
  signal U3_evid_mis_3_FFX_RST : STD_LOGIC; 
  signal U3_evid_mis_1_FFX_RST : STD_LOGIC; 
  signal U3_evid_mis_5_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_1_FFX_RST : STD_LOGIC; 
  signal U1_db_error2_7_FFY_RST : STD_LOGIC; 
  signal U1_db_error2_7_FFX_RST : STD_LOGIC; 
  signal U1_db_error3_3_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_3_FFX_RST : STD_LOGIC; 
  signal U1_db_error3_5_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_5_FFX_RST : STD_LOGIC; 
  signal U1_db_error2_9_FFY_RST : STD_LOGIC; 
  signal U1_db_error2_9_FFX_RST : STD_LOGIC; 
  signal U1_db_error3_7_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_9_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_7_FFX_RST : STD_LOGIC; 
  signal U1_recoff_FFY_RST : STD_LOGIC; 
  signal U1_dis_errorw_FFY_SET : STD_LOGIC; 
  signal U1_dis_ffreg_mask_FFY_RST : STD_LOGIC; 
  signal U1_paf_counter_3_9_FFY_RST : STD_LOGIC; 
  signal U1_db_error2_1_FFX_RST : STD_LOGIC; 
  signal U1_db_error1_5_FFY_RST : STD_LOGIC; 
  signal U1_db_error1_5_FFX_RST : STD_LOGIC; 
  signal U1_db_error2_3_FFY_RST : STD_LOGIC; 
  signal U1_db_error2_3_FFX_RST : STD_LOGIC; 
  signal U1_db_error1_7_FFY_RST : STD_LOGIC; 
  signal U1_db_error1_7_FFX_RST : STD_LOGIC; 
  signal U1_db_error2_5_FFY_RST : STD_LOGIC; 
  signal U1_db_error2_5_FFX_RST : STD_LOGIC; 
  signal U1_db_error1_9_FFY_RST : STD_LOGIC; 
  signal U1_db_error3_1_FFY_RST : STD_LOGIC; 
  signal U1_db_error1_9_FFX_RST : STD_LOGIC; 
  signal U3_sel_read_5_1_FFY_RST : STD_LOGIC; 
  signal blocked_3_FFY_RST : STD_LOGIC; 
  signal blocked_4_FFY_RST : STD_LOGIC; 
  signal U3_time_start_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd34_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd37_FFY_RST : STD_LOGIC; 
  signal U3_lives_in_FFY_RST : STD_LOGIC; 
  signal U3_dontread_1_FFY_SET : STD_LOGIC; 
  signal U3_dontread_1_FFY_RST : STD_LOGIC; 
  signal U3_dontread_4_FFY_SET : STD_LOGIC; 
  signal U3_dontread_4_FFY_RST : STD_LOGIC; 
  signal blocked_5_FFY_RST : STD_LOGIC; 
  signal U1_dis_evid_wrong_FFY_RST : STD_LOGIC; 
  signal U1_mask_1_FFY_RST : STD_LOGIC; 
  signal U1_mask_3_FFY_RST : STD_LOGIC; 
  signal U1_mask_1_FFX_RST : STD_LOGIC; 
  signal U1_mask_3_FFX_RST : STD_LOGIC; 
  signal U1_mask_4_FFY_RST : STD_LOGIC; 
  signal U1_paf_cnt_set_5_FFY_RST : STD_LOGIC; 
  signal U1_dis_paf_warn_FFY_RST : STD_LOGIC; 
  signal U1_timeout_value_1_FFY_SET : STD_LOGIC; 
  signal U1_timeout_value_1_FFX_SET : STD_LOGIC; 
  signal U1_timeout_value_3_FFY_SET : STD_LOGIC; 
  signal U3_dontread_0_FFY_SET : STD_LOGIC; 
  signal U3_dontread_0_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd2_FFY_RST : STD_LOGIC; 
  signal U2_fwrg2_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd2_FFX_RST : STD_LOGIC; 
  signal U2_fwrg1_FFX_SET : STD_LOGIC; 
  signal U2_fwrg1_FFX_RST : STD_LOGIC; 
  signal U2_fwrg4_FFY_RST : STD_LOGIC; 
  signal U2_fwrg5_FFY_RST : STD_LOGIC; 
  signal U1_dis_evid_bloq_FFY_SET : STD_LOGIC; 
  signal U3_state_FFd38_FFY_RST : STD_LOGIC; 
  signal U1_paf_cnt_set_0_FFY_RST : STD_LOGIC; 
  signal U1_paf_cnt_set_1_FFY_RST : STD_LOGIC; 
  signal U1_paf_cnt_set_2_FFY_RST : STD_LOGIC; 
  signal U1_paf_cnt_set_3_FFY_RST : STD_LOGIC; 
  signal U1_paf_cnt_set_4_FFY_RST : STD_LOGIC; 
  signal fout_5_IFF_RST : STD_LOGIC; 
  signal fout_6_IFF_RST : STD_LOGIC; 
  signal fout_7_IFF_RST : STD_LOGIC; 
  signal fout_8_IFF_RST : STD_LOGIC; 
  signal fout_9_IFF_RST : STD_LOGIC; 
  signal U1_dis_head_trail_FFY_RST : STD_LOGIC; 
  signal U1_resynch_to_FFY_SET : STD_LOGIC; 
  signal U1_etr_paepaf_reg_2_FFY_SET : STD_LOGIC; 
  signal U1_etr_paepaf_reg_2_FFX_SET : STD_LOGIC; 
  signal U1_resynch_maxw_FFY_SET : STD_LOGIC; 
  signal dout_10_OFF_RST : STD_LOGIC; 
  signal dout_11_OFF_RST : STD_LOGIC; 
  signal dout_12_OFF_RST : STD_LOGIC; 
  signal dout_3_OFF_RST : STD_LOGIC; 
  signal dout_4_OFF_RST : STD_LOGIC; 
  signal dout_5_OFF_RST : STD_LOGIC; 
  signal dout_6_OFF_RST : STD_LOGIC; 
  signal dout_7_OFF_RST : STD_LOGIC; 
  signal dout_8_OFF_RST : STD_LOGIC; 
  signal dout_9_OFF_RST : STD_LOGIC; 
  signal U1_timeout_value_3_FFX_SET : STD_LOGIC; 
  signal U3_state_FFd17_FFY_RST : STD_LOGIC; 
  signal U3_state_FFd17_FFX_RST : STD_LOGIC; 
  signal U1_per_fifo_FFY_SET : STD_LOGIC; 
  signal U3_state_FFd23_FFY_RST : STD_LOGIC; 
  signal enw2_FFY_RST : STD_LOGIC; 
  signal U1_paf_reg_5_FFY_RST : STD_LOGIC; 
  signal U1_dis_timo_mask_FFY_RST : STD_LOGIC; 
  signal U1_nmaxwords_5_FFY_SET : STD_LOGIC; 
  signal U1_nmaxwords_5_FFX_SET : STD_LOGIC; 
  signal U1_nmaxwords_7_FFY_SET : STD_LOGIC; 
  signal U1_nmaxwords_7_FFX_SET : STD_LOGIC; 
  signal U3_state_FFd33_FFY_RST : STD_LOGIC; 
  signal U1_dis_maxw_mask_FFY_SET : STD_LOGIC; 
  signal U1_resynch_evidmis_FFY_SET : STD_LOGIC; 
  signal reset2_FFY_RST : STD_LOGIC; 
  signal U1_dis_hul_mask_FFY_RST : STD_LOGIC; 
  signal U1_etr_fifo_reg_FFY_SET : STD_LOGIC; 
  signal ULED1_q1_FFY_RST : STD_LOGIC; 
  signal ULED1_q2_FFY_RST : STD_LOGIC; 
  signal ULED1_q3_FFY_RST : STD_LOGIC; 
  signal ULED2_q1_FFY_RST : STD_LOGIC; 
  signal ULED2_q2_FFY_RST : STD_LOGIC; 
  signal ULED2_q3_FFY_RST : STD_LOGIC; 
  signal db_11_IFF_RST : STD_LOGIC; 
  signal db_10_IFF_SET : STD_LOGIC; 
  signal dout_0_OFF_RST : STD_LOGIC; 
  signal dout_1_OFF_RST : STD_LOGIC; 
  signal dout_2_OFF_RST : STD_LOGIC; 
  signal fout_0_IFF_RST : STD_LOGIC; 
  signal fout_1_IFF_RST : STD_LOGIC; 
  signal fout_2_IFF_RST : STD_LOGIC; 
  signal fout_3_IFF_RST : STD_LOGIC; 
  signal fout_4_IFF_RST : STD_LOGIC; 
  signal dout_13_OFF_RST : STD_LOGIC; 
  signal dout_14_OFF_RST : STD_LOGIC; 
  signal dout_15_OFF_RST : STD_LOGIC; 
  signal txena_p_OFF_RST : STD_LOGIC; 
  signal UDLL3_CE : STD_LOGIC; 
  signal clk_slow_BUFGP_BUFG_CE : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal U1_nmaxwords : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal db_out : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U1_timeout_value : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal U2_word_par : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U2_byte_par : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal U1_paf_counter_1 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U3_timed_out : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U2_disparity : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U1_paf_counter_2 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U1_paf_counter_3 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U1_paf_counter_4 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U3_maxw_reached : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U1_paf_counter_5 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U1_mask : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal blocked : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U2_pae_paf_reg : STD_LOGIC_VECTOR ( 21 downto 0 ); 
  signal U1_fout_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U1_db_error1 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal U1_hasunlock : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U1_paf_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U1_db_error2 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal U3_evid_mis : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U1_ff_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U1_paf_counter_0 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U1_db_error3 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal U3_sel_read : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U3_word_count : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal U3_n0151 : STD_LOGIC_VECTOR ( 11 downto 1 ); 
  signal U3_time_counter : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal U3_n0251 : STD_LOGIC_VECTOR ( 12 downto 0 ); 
  signal U3_header2_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U3_header1_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal U2_loadcnt : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U2_loadcnt_n0002 : STD_LOGIC_VECTOR ( 5 downto 1 ); 
  signal U1_paf_cnt_set : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U3_rob_id : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U3_n0121 : STD_LOGIC_VECTOR ( 4 downto 1 ); 
  signal U3_s_data : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal U3_dontread : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U2_Mxor_cpar_1_Xo : STD_LOGIC_VECTOR ( 5 downto 4 ); 
  signal U2_Mxor_cpar_0_Xo : STD_LOGIC_VECTOR ( 5 downto 4 ); 
  signal U2_cpar : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal U3_n0120 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U1_n0014 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U3_n0116 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U3_n0117 : STD_LOGIC_VECTOR ( 12 downto 12 ); 
  signal U2_loadcnt_n0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal Q_n0048 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal s_data_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  GLOBAL_LOGIC1_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  enw_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => enw_IFF_RST
    );
  enw1_73 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => enw_IBUF,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => enw_IFF_RST,
      O => enw1
    );
  enw_IBUF_74 : X_BUF
    port map (
      I => enw,
      O => enw_IBUF
    );
  db_0_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_0_IFF_SET
    );
  U1_nmaxwords_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_0_IBUF,
      CE => U1_n0010,
      CLK => CLK,
      SET => db_0_IFF_SET,
      RST => GND,
      O => U1_nmaxwords(0)
    );
  db_0_IOBUF_OBUFT : X_TRI
    port map (
      I => db_0_OUTMUX,
      CTL => db_0_ENABLE,
      O => db(0)
    );
  db_0_ENABLEINV : X_INV
    port map (
      I => db_0_TORGTS,
      O => db_0_ENABLE
    );
  db_0_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_0_TORGTS
    );
  db_0_OUTMUX_75 : X_BUF
    port map (
      I => db_out(0),
      O => db_0_OUTMUX
    );
  db_0_IMUX : X_BUF
    port map (
      I => db_0_IBUF,
      O => N44072
    );
  db_0_IOBUF_IBUF : X_BUF
    port map (
      I => db(0),
      O => db_0_IBUF
    );
  db_1_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_1_IFF_SET
    );
  U1_nmaxwords_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_1_IBUF,
      CE => U1_n0010,
      CLK => CLK,
      SET => db_1_IFF_SET,
      RST => GND,
      O => U1_nmaxwords(1)
    );
  db_1_IOBUF_OBUFT : X_TRI
    port map (
      I => db_1_OUTMUX,
      CTL => db_1_ENABLE,
      O => db(1)
    );
  db_1_ENABLEINV : X_INV
    port map (
      I => db_1_TORGTS,
      O => db_1_ENABLE
    );
  db_1_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_1_TORGTS
    );
  db_1_OUTMUX_76 : X_BUF
    port map (
      I => db_out(1),
      O => db_1_OUTMUX
    );
  db_1_IMUX : X_BUF
    port map (
      I => db_1_IBUF,
      O => N44074
    );
  db_1_IOBUF_IBUF : X_BUF
    port map (
      I => db(1),
      O => db_1_IBUF
    );
  db_2_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_2_IFF_SET
    );
  U1_nmaxwords_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_2_IBUF,
      CE => U1_n0010,
      CLK => CLK,
      SET => db_2_IFF_SET,
      RST => GND,
      O => U1_nmaxwords(2)
    );
  db_2_IOBUF_OBUFT : X_TRI
    port map (
      I => db_2_OUTMUX,
      CTL => db_2_ENABLE,
      O => db(2)
    );
  db_2_ENABLEINV : X_INV
    port map (
      I => db_2_TORGTS,
      O => db_2_ENABLE
    );
  db_2_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_2_TORGTS
    );
  db_2_OUTMUX_77 : X_BUF
    port map (
      I => db_out(2),
      O => db_2_OUTMUX
    );
  db_2_IMUX : X_BUF
    port map (
      I => db_2_IBUF,
      O => N44076
    );
  db_2_IOBUF_IBUF : X_BUF
    port map (
      I => db(2),
      O => db_2_IBUF
    );
  db_3_IOBUF_OBUFT : X_TRI
    port map (
      I => db_3_OUTMUX,
      CTL => db_3_ENABLE,
      O => db(3)
    );
  db_3_ENABLEINV : X_INV
    port map (
      I => db_3_TORGTS,
      O => db_3_ENABLE
    );
  db_3_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_3_TORGTS
    );
  db_3_OUTMUX_78 : X_BUF
    port map (
      I => db_out(3),
      O => db_3_OUTMUX
    );
  db_3_IMUX : X_BUF
    port map (
      I => db_3_IBUF,
      O => N44078
    );
  db_3_IOBUF_IBUF : X_BUF
    port map (
      I => db(3),
      O => db_3_IBUF
    );
  db_4_IOBUF_OBUFT : X_TRI
    port map (
      I => db_4_OUTMUX,
      CTL => db_4_ENABLE,
      O => db(4)
    );
  db_4_ENABLEINV : X_INV
    port map (
      I => db_4_TORGTS,
      O => db_4_ENABLE
    );
  db_4_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_4_TORGTS
    );
  db_4_OUTMUX_79 : X_BUF
    port map (
      I => db_out(4),
      O => db_4_OUTMUX
    );
  db_4_IMUX : X_BUF
    port map (
      I => db_4_IBUF,
      O => N44080
    );
  db_4_IOBUF_IBUF : X_BUF
    port map (
      I => db(4),
      O => db_4_IBUF
    );
  db_5_IOBUF_OBUFT : X_TRI
    port map (
      I => db_5_OUTMUX,
      CTL => db_5_ENABLE,
      O => db(5)
    );
  db_5_ENABLEINV : X_INV
    port map (
      I => db_5_TORGTS,
      O => db_5_ENABLE
    );
  db_5_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_5_TORGTS
    );
  db_5_OUTMUX_80 : X_BUF
    port map (
      I => db_out(5),
      O => db_5_OUTMUX
    );
  db_5_IMUX : X_BUF
    port map (
      I => db_5_IBUF,
      O => N44082
    );
  db_5_IOBUF_IBUF : X_BUF
    port map (
      I => db(5),
      O => db_5_IBUF
    );
  db_6_IOBUF_OBUFT : X_TRI
    port map (
      I => db_6_OUTMUX,
      CTL => db_6_ENABLE,
      O => db(6)
    );
  db_6_ENABLEINV : X_INV
    port map (
      I => db_6_TORGTS,
      O => db_6_ENABLE
    );
  db_6_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_6_TORGTS
    );
  db_6_OUTMUX_81 : X_BUF
    port map (
      I => db_out(6),
      O => db_6_OUTMUX
    );
  db_6_IMUX : X_BUF
    port map (
      I => db_6_IBUF,
      O => N44084
    );
  db_6_IOBUF_IBUF : X_BUF
    port map (
      I => db(6),
      O => db_6_IBUF
    );
  U1_nmaxwords_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_3_IBUF,
      CE => U1_n0010,
      CLK => CLK,
      SET => db_3_IFF_SET,
      RST => GND,
      O => U1_nmaxwords(3)
    );
  db_3_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_3_IFF_SET
    );
  db_7_IOBUF_OBUFT : X_TRI
    port map (
      I => db_7_OUTMUX,
      CTL => db_7_ENABLE,
      O => db(7)
    );
  db_7_ENABLEINV : X_INV
    port map (
      I => db_7_TORGTS,
      O => db_7_ENABLE
    );
  db_7_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_7_TORGTS
    );
  db_7_OUTMUX_82 : X_BUF
    port map (
      I => db_out(7),
      O => db_7_OUTMUX
    );
  db_7_IMUX : X_BUF
    port map (
      I => db_7_IBUF,
      O => N44086
    );
  db_7_IOBUF_IBUF : X_BUF
    port map (
      I => db(7),
      O => db_7_IBUF
    );
  mrs_IMUX : X_BUF
    port map (
      I => mrs_IBUF_0,
      O => mrs_IBUF
    );
  mrs_IBUF_83 : X_BUF
    port map (
      I => mrs,
      O => mrs_IBUF_0
    );
  db_8_IOBUF_OBUFT : X_TRI
    port map (
      I => db_8_OUTMUX,
      CTL => db_8_ENABLE,
      O => db(8)
    );
  db_8_ENABLEINV : X_INV
    port map (
      I => db_8_TORGTS,
      O => db_8_ENABLE
    );
  db_8_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_8_TORGTS
    );
  db_8_OUTMUX_84 : X_BUF
    port map (
      I => db_out(8),
      O => db_8_OUTMUX
    );
  db_8_IMUX : X_BUF
    port map (
      I => db_8_IBUF,
      O => N44088
    );
  db_8_IOBUF_IBUF : X_BUF
    port map (
      I => db(8),
      O => db_8_IBUF
    );
  db_9_IOBUF_OBUFT : X_TRI
    port map (
      I => db_9_OUTMUX,
      CTL => db_9_ENABLE,
      O => db(9)
    );
  db_9_ENABLEINV : X_INV
    port map (
      I => db_9_TORGTS,
      O => db_9_ENABLE
    );
  db_9_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_9_TORGTS
    );
  db_9_OUTMUX_85 : X_BUF
    port map (
      I => db_out(9),
      O => db_9_OUTMUX
    );
  db_9_IMUX : X_BUF
    port map (
      I => db_9_IBUF,
      O => N44090
    );
  db_9_IOBUF_IBUF : X_BUF
    port map (
      I => db(9),
      O => db_9_IBUF
    );
  ef_0_IMUX : X_BUF
    port map (
      I => ef_0_IBUF_1,
      O => ef_0_IBUF
    );
  ef_0_IBUF_86 : X_BUF
    port map (
      I => ef(0),
      O => ef_0_IBUF_1
    );
  ef_1_IMUX : X_BUF
    port map (
      I => ef_1_IBUF_2,
      O => ef_1_IBUF
    );
  ef_1_IBUF_87 : X_BUF
    port map (
      I => ef(1),
      O => ef_1_IBUF_2
    );
  ef_2_IMUX : X_BUF
    port map (
      I => ef_2_IBUF_3,
      O => ef_2_IBUF
    );
  ef_2_IBUF_88 : X_BUF
    port map (
      I => ef(2),
      O => ef_2_IBUF_3
    );
  ef_3_IMUX : X_BUF
    port map (
      I => ef_3_IBUF_4,
      O => ef_3_IBUF
    );
  ef_3_IBUF_89 : X_BUF
    port map (
      I => ef(3),
      O => ef_3_IBUF_4
    );
  ef_4_IMUX : X_BUF
    port map (
      I => ef_4_IBUF_5,
      O => ef_4_IBUF
    );
  ef_4_IBUF_90 : X_BUF
    port map (
      I => ef(4),
      O => ef_4_IBUF_5
    );
  ef_5_IMUX : X_BUF
    port map (
      I => ef_5_IBUF_6,
      O => ef_5_IBUF
    );
  ef_5_IBUF_91 : X_BUF
    port map (
      I => ef(5),
      O => ef_5_IBUF_6
    );
  ff_0_IMUX : X_BUF
    port map (
      I => ff_0_IBUF_7,
      O => ff_0_IBUF
    );
  ff_0_IBUF_92 : X_BUF
    port map (
      I => ff(0),
      O => ff_0_IBUF_7
    );
  ff_1_IMUX : X_BUF
    port map (
      I => ff_1_IBUF_8,
      O => ff_1_IBUF
    );
  ff_1_IBUF_93 : X_BUF
    port map (
      I => ff(1),
      O => ff_1_IBUF_8
    );
  ff_2_IMUX : X_BUF
    port map (
      I => ff_2_IBUF_9,
      O => ff_2_IBUF
    );
  ff_2_IBUF_94 : X_BUF
    port map (
      I => ff(2),
      O => ff_2_IBUF_9
    );
  ff_3_IMUX : X_BUF
    port map (
      I => ff_3_IBUF_10,
      O => ff_3_IBUF
    );
  ff_3_IBUF_95 : X_BUF
    port map (
      I => ff(3),
      O => ff_3_IBUF_10
    );
  ff_4_IMUX : X_BUF
    port map (
      I => ff_4_IBUF_11,
      O => ff_4_IBUF
    );
  ff_4_IBUF_96 : X_BUF
    port map (
      I => ff(4),
      O => ff_4_IBUF_11
    );
  ff_5_IMUX : X_BUF
    port map (
      I => ff_5_IBUF_12,
      O => ff_5_IBUF
    );
  ff_5_IBUF_97 : X_BUF
    port map (
      I => ff(5),
      O => ff_5_IBUF_12
    );
  add_0_IMUX : X_BUF
    port map (
      I => add_0_IBUF_13,
      O => add_0_IBUF
    );
  add_0_IBUF_98 : X_BUF
    port map (
      I => add(0),
      O => add_0_IBUF_13
    );
  U1_timeout_value_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_5_IBUF,
      CE => U1_n0009,
      CLK => CLK,
      SET => db_5_IFF_SET,
      RST => GND,
      O => U1_timeout_value(5)
    );
  db_5_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_5_IFF_SET
    );
  add_1_IMUX : X_BUF
    port map (
      I => add_1_IBUF_14,
      O => add_1_IBUF
    );
  add_1_IBUF_99 : X_BUF
    port map (
      I => add(1),
      O => add_1_IBUF_14
    );
  add_2_IMUX : X_BUF
    port map (
      I => add_2_IBUF_15,
      O => add_2_IBUF
    );
  add_2_IBUF_100 : X_BUF
    port map (
      I => add(2),
      O => add_2_IBUF_15
    );
  U1_timeout_value_4 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_4_IBUF,
      CE => U1_n0009,
      CLK => CLK,
      SET => db_4_IFF_SET,
      RST => GND,
      O => U1_timeout_value(4)
    );
  db_4_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_4_IFF_SET
    );
  add_3_IMUX : X_BUF
    port map (
      I => add_3_IBUF_16,
      O => add_3_IBUF
    );
  add_3_IBUF_101 : X_BUF
    port map (
      I => add(3),
      O => add_3_IBUF_16
    );
  add_4_IMUX : X_BUF
    port map (
      I => add_4_IBUF_17,
      O => add_4_IBUF
    );
  add_4_IBUF_102 : X_BUF
    port map (
      I => add(4),
      O => add_4_IBUF_17
    );
  add_5_IMUX : X_BUF
    port map (
      I => add_5_IBUF_18,
      O => add_5_IBUF
    );
  add_5_IBUF_103 : X_BUF
    port map (
      I => add(5),
      O => add_5_IBUF_18
    );
  load_paepaf_IMUX : X_BUF
    port map (
      I => load_paepaf_IBUF_19,
      O => load_paepaf_IBUF
    );
  load_paepaf_IBUF_104 : X_BUF
    port map (
      I => load_paepaf,
      O => load_paepaf_IBUF_19
    );
  ceros_id_0_IMUX : X_BUF
    port map (
      I => ceros_id_0_IBUF_20,
      O => ceros_id_0_IBUF
    );
  ceros_id_0_IBUF_105 : X_BUF
    port map (
      I => ceros_id(0),
      O => ceros_id_0_IBUF_20
    );
  ceros_id_1_IMUX : X_BUF
    port map (
      I => ceros_id_1_IBUF_21,
      O => ceros_id_1_IBUF
    );
  ceros_id_1_IBUF_106 : X_BUF
    port map (
      I => ceros_id(1),
      O => ceros_id_1_IBUF_21
    );
  vspare_0_IMUX : X_BUF
    port map (
      I => vspare_0_IBUF_22,
      O => vspare_0_IBUF
    );
  vspare_0_IBUF_107 : X_BUF
    port map (
      I => vspare_0,
      O => vspare_0_IBUF_22
    );
  vspare_1_IMUX : X_BUF
    port map (
      I => vspare_1_IBUF_23,
      O => vspare_1_IBUF
    );
  vspare_1_IBUF_108 : X_BUF
    port map (
      I => vspare_1,
      O => vspare_1_IBUF_23
    );
  spaf_p_OBUF_109 : X_TRI
    port map (
      I => spaf_p_OUTMUX,
      CTL => spaf_p_ENABLE,
      O => spaf_p
    );
  spaf_p_ENABLEINV : X_INV
    port map (
      I => spaf_p_TORGTS,
      O => spaf_p_ENABLE
    );
  spaf_p_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => spaf_p_TORGTS
    );
  spaf_p_OUTMUX_110 : X_BUF
    port map (
      I => spaf_p_OBUF,
      O => spaf_p_OUTMUX
    );
  oe_0_OBUF_111 : X_TRI
    port map (
      I => oe_0_OUTMUX,
      CTL => oe_0_ENABLE,
      O => oe(0)
    );
  oe_0_ENABLEINV : X_INV
    port map (
      I => oe_0_TORGTS,
      O => oe_0_ENABLE
    );
  oe_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => oe_0_TORGTS
    );
  oe_0_OUTMUX_112 : X_BUF
    port map (
      I => oe_0_OBUF,
      O => oe_0_OUTMUX
    );
  oe_1_OBUF_113 : X_TRI
    port map (
      I => oe_1_OUTMUX,
      CTL => oe_1_ENABLE,
      O => oe(1)
    );
  oe_1_ENABLEINV : X_INV
    port map (
      I => oe_1_TORGTS,
      O => oe_1_ENABLE
    );
  oe_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => oe_1_TORGTS
    );
  oe_1_OUTMUX_114 : X_BUF
    port map (
      I => oe_1_OBUF,
      O => oe_1_OUTMUX
    );
  oe_2_OBUF_115 : X_TRI
    port map (
      I => oe_2_OUTMUX,
      CTL => oe_2_ENABLE,
      O => oe(2)
    );
  oe_2_ENABLEINV : X_INV
    port map (
      I => oe_2_TORGTS,
      O => oe_2_ENABLE
    );
  oe_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => oe_2_TORGTS
    );
  oe_2_OUTMUX_116 : X_BUF
    port map (
      I => oe_2_OBUF,
      O => oe_2_OUTMUX
    );
  oe_3_OBUF_117 : X_TRI
    port map (
      I => oe_3_OUTMUX,
      CTL => oe_3_ENABLE,
      O => oe(3)
    );
  oe_3_ENABLEINV : X_INV
    port map (
      I => oe_3_TORGTS,
      O => oe_3_ENABLE
    );
  oe_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => oe_3_TORGTS
    );
  oe_3_OUTMUX_118 : X_BUF
    port map (
      I => oe_3_OBUF,
      O => oe_3_OUTMUX
    );
  oe_4_OBUF_119 : X_TRI
    port map (
      I => oe_4_OUTMUX,
      CTL => oe_4_ENABLE,
      O => oe(4)
    );
  oe_4_ENABLEINV : X_INV
    port map (
      I => oe_4_TORGTS,
      O => oe_4_ENABLE
    );
  oe_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => oe_4_TORGTS
    );
  oe_4_OUTMUX_120 : X_BUF
    port map (
      I => oe_4_OBUF,
      O => oe_4_OUTMUX
    );
  oe_5_OBUF_121 : X_TRI
    port map (
      I => oe_5_OUTMUX,
      CTL => oe_5_ENABLE,
      O => oe(5)
    );
  oe_5_ENABLEINV : X_INV
    port map (
      I => oe_5_TORGTS,
      O => oe_5_ENABLE
    );
  oe_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => oe_5_TORGTS
    );
  oe_5_OUTMUX_122 : X_BUF
    port map (
      I => oe_5_OBUF,
      O => oe_5_OUTMUX
    );
  UDLL2_LOGIC_ZERO_123 : X_ZERO
    port map (
      O => UDLL2_LOGIC_ZERO
    );
  UDLL2 : X_CLKDLLE
    generic map(
      CLKDV_DIVIDE => 2.0,
      DUTY_CYCLE_CORRECTION => TRUE,
      MAXPERCLKIN => 40000 ps
    )
    port map (
      CLKIN => CLKIN,
      CLKFB => CLK,
      RST => UDLL2_LOGIC_ZERO,
      CLK0 => CLK0,
      CLK90 => UDLL2_CLK90,
      CLK180 => UDLL2_CLK180,
      CLK270 => UDLL2_CLK270,
      CLK2X => UDLL2_CLK2X,
      CLK2X180 => UDLL2_CLK2X180,
      CLKDV => CLK20,
      LOCKED => LOCKED
    );
  U1_I50_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I50_10 : X_TRI
    port map (
      I => U2_word_par(5),
      CTL => U1_I50_10_TINV,
      O => db_out(5)
    );
  U1_I50_10_TINV_124 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_10_TINV
    );
  U1_I50_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I50_11 : X_TRI
    port map (
      I => U2_word_par(4),
      CTL => U1_I50_11_TINV,
      O => db_out(4)
    );
  U1_I50_11_TINV_125 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_11_TINV
    );
  U1_I50_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I50_12 : X_TRI
    port map (
      I => U2_word_par(3),
      CTL => U1_I50_12_TINV,
      O => db_out(3)
    );
  U1_I50_12_TINV_126 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_12_TINV
    );
  U1_I50_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I50_13 : X_TRI
    port map (
      I => U2_word_par(2),
      CTL => U1_I50_13_TINV,
      O => db_out(2)
    );
  U1_I50_13_TINV_127 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_13_TINV
    );
  U1_I50_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I50_14 : X_TRI
    port map (
      I => U2_word_par(1),
      CTL => U1_I50_14_TINV,
      O => db_out(1)
    );
  U1_I50_14_TINV_128 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_14_TINV
    );
  U1_I50_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I50_15 : X_TRI
    port map (
      I => U2_word_par(0),
      CTL => U1_I50_15_TINV,
      O => db_out(0)
    );
  U1_I50_15_TINV_129 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_15_TINV
    );
  U1_I43_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I43_10 : X_TRI
    port map (
      I => lock_5_IBUF,
      CTL => U1_I43_10_TINV,
      O => db_out(5)
    );
  U1_I43_10_TINV_130 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_10_TINV
    );
  U1_I51_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I51_10 : X_TRI
    port map (
      I => U2_byte_par(5),
      CTL => U1_I51_10_TINV,
      O => db_out(5)
    );
  U1_I51_10_TINV_131 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_10_TINV
    );
  U1_I43_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I43_11 : X_TRI
    port map (
      I => lock_4_IBUF,
      CTL => U1_I43_11_TINV,
      O => db_out(4)
    );
  U1_I43_11_TINV_132 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_11_TINV
    );
  U1_I51_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I51_11 : X_TRI
    port map (
      I => U2_byte_par(4),
      CTL => U1_I51_11_TINV,
      O => db_out(4)
    );
  U1_I51_11_TINV_133 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_11_TINV
    );
  U1_I43_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I43_12 : X_TRI
    port map (
      I => lock_3_IBUF,
      CTL => U1_I43_12_TINV,
      O => db_out(3)
    );
  U1_I43_12_TINV_134 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_12_TINV
    );
  U1_I51_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I51_12 : X_TRI
    port map (
      I => U2_byte_par(3),
      CTL => U1_I51_12_TINV,
      O => db_out(3)
    );
  U1_I51_12_TINV_135 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_12_TINV
    );
  U1_I46_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I46_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I46_0_TINV,
      O => db_out(15)
    );
  U1_I46_0_TINV_136 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_0_TINV
    );
  U1_I54_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I54_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I54_0_TINV,
      O => db_out(15)
    );
  U1_I54_0_TINV_137 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_0_TINV
    );
  U1_I62_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I62_0 : X_TRI
    port map (
      I => U1_paf_counter_3(15),
      CTL => U1_I62_0_TINV,
      O => db_out(15)
    );
  U1_I62_0_TINV_138 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_0_TINV
    );
  U1_I44_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I44_9 : X_TRI
    port map (
      I => U1_dis_head_trail,
      CTL => U1_I44_9_TINV,
      O => db_out(6)
    );
  U1_I44_9_TINV_139 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_9_TINV
    );
  U1_I45_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I45_5 : X_TRI
    port map (
      I => U1_hasunlock(4),
      CTL => U1_I45_5_TINV,
      O => db_out(10)
    );
  U1_I45_5_TINV_140 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_5_TINV
    );
  U1_I46_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I46_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I46_1_TINV,
      O => db_out(14)
    );
  U1_I46_1_TINV_141 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_1_TINV
    );
  U1_I49_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I49_14 : X_TRI
    port map (
      I => U2_pae_paf_reg(1),
      CTL => U1_I49_14_TINV,
      O => db_out(1)
    );
  U1_I49_14_TINV_142 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_14_TINV
    );
  U1_I52_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I52_9 : X_TRI
    port map (
      I => U2_byte_par(22),
      CTL => U1_I52_9_TINV,
      O => db_out(6)
    );
  U1_I52_9_TINV_143 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_9_TINV
    );
  U1_I53_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I53_5 : X_TRI
    port map (
      I => U2_disparity(10),
      CTL => U1_I53_5_TINV,
      O => db_out(10)
    );
  U1_I53_5_TINV_144 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_5_TINV
    );
  U1_I54_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I54_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I54_1_TINV,
      O => db_out(14)
    );
  U1_I54_1_TINV_145 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_1_TINV
    );
  U1_I57_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I57_14 : X_TRI
    port map (
      I => U1_fout_reg(1),
      CTL => U1_I57_14_TINV,
      O => db_out(1)
    );
  U1_I57_14_TINV_146 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_14_TINV
    );
  U1_I60_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I60_9 : X_TRI
    port map (
      I => U1_paf_counter_1(6),
      CTL => U1_I60_9_TINV,
      O => db_out(6)
    );
  U1_I60_9_TINV_147 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_9_TINV
    );
  U1_I61_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I61_5 : X_TRI
    port map (
      I => U1_paf_counter_2(10),
      CTL => U1_I61_5_TINV,
      O => db_out(10)
    );
  U1_I61_5_TINV_148 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_5_TINV
    );
  U1_I62_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I62_1 : X_TRI
    port map (
      I => U1_paf_counter_3(14),
      CTL => U1_I62_1_TINV,
      O => db_out(14)
    );
  U1_I62_1_TINV_149 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_1_TINV
    );
  U1_I65_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I65_14 : X_TRI
    port map (
      I => U1_db_error1(1),
      CTL => U1_I65_14_TINV,
      O => db_out(1)
    );
  U1_I65_14_TINV_150 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_14_TINV
    );
  U1_I45_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I45_6 : X_TRI
    port map (
      I => U1_hasunlock(3),
      CTL => U1_I45_6_TINV,
      O => db_out(9)
    );
  U1_I45_6_TINV_151 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_6_TINV
    );
  U1_I46_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I46_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I46_2_TINV,
      O => db_out(13)
    );
  U1_I46_2_TINV_152 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_2_TINV
    );
  U1_I49_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I49_15 : X_TRI
    port map (
      I => U2_pae_paf_reg(0),
      CTL => U1_I49_15_TINV,
      O => db_out(0)
    );
  U1_I49_15_TINV_153 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_15_TINV
    );
  U1_I53_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I53_6 : X_TRI
    port map (
      I => U2_disparity(9),
      CTL => U1_I53_6_TINV,
      O => db_out(9)
    );
  U1_I53_6_TINV_154 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_6_TINV
    );
  U1_I54_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I54_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I54_2_TINV,
      O => db_out(13)
    );
  U1_I54_2_TINV_155 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_2_TINV
    );
  U1_I57_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I57_15 : X_TRI
    port map (
      I => U1_fout_reg(0),
      CTL => U1_I57_15_TINV,
      O => db_out(0)
    );
  U1_I57_15_TINV_156 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_15_TINV
    );
  U1_I61_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I61_6 : X_TRI
    port map (
      I => U1_paf_counter_2(9),
      CTL => U1_I61_6_TINV,
      O => db_out(9)
    );
  U1_I61_6_TINV_157 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_6_TINV
    );
  U1_I62_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I62_2 : X_TRI
    port map (
      I => U1_paf_counter_3(13),
      CTL => U1_I62_2_TINV,
      O => db_out(13)
    );
  U1_I62_2_TINV_158 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_2_TINV
    );
  U1_I65_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I65_15 : X_TRI
    port map (
      I => U1_db_error1(0),
      CTL => U1_I65_15_TINV,
      O => db_out(0)
    );
  U1_I65_15_TINV_159 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_15_TINV
    );
  U1_I45_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I45_7 : X_TRI
    port map (
      I => U1_hasunlock(2),
      CTL => U1_I45_7_TINV,
      O => db_out(8)
    );
  U1_I45_7_TINV_160 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_7_TINV
    );
  U1_I46_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I46_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I46_3_TINV,
      O => db_out(12)
    );
  U1_I46_3_TINV_161 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_3_TINV
    );
  U1_I53_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I53_7 : X_TRI
    port map (
      I => U2_disparity(8),
      CTL => U1_I53_7_TINV,
      O => db_out(8)
    );
  U1_I53_7_TINV_162 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_7_TINV
    );
  U1_I54_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I54_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I54_3_TINV,
      O => db_out(12)
    );
  U1_I54_3_TINV_163 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_3_TINV
    );
  U1_I61_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I61_7 : X_TRI
    port map (
      I => U1_paf_counter_2(8),
      CTL => U1_I61_7_TINV,
      O => db_out(8)
    );
  U1_I61_7_TINV_164 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_7_TINV
    );
  U1_I62_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I62_3 : X_TRI
    port map (
      I => U1_paf_counter_3(12),
      CTL => U1_I62_3_TINV,
      O => db_out(12)
    );
  U1_I62_3_TINV_165 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_3_TINV
    );
  U1_I45_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I45_8 : X_TRI
    port map (
      I => U1_hasunlock(1),
      CTL => U1_I45_8_TINV,
      O => db_out(7)
    );
  U1_I45_8_TINV_166 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_8_TINV
    );
  U1_I46_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I46_4 : X_TRI
    port map (
      I => U1_paf_reg(5),
      CTL => U1_I46_4_TINV,
      O => db_out(11)
    );
  U1_I46_4_TINV_167 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_4_TINV
    );
  U1_I53_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I53_8 : X_TRI
    port map (
      I => U2_disparity(7),
      CTL => U1_I53_8_TINV,
      O => db_out(7)
    );
  U1_I53_8_TINV_168 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_8_TINV
    );
  U1_I54_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I54_4 : X_TRI
    port map (
      I => U1_timeout_value(11),
      CTL => U1_I54_4_TINV,
      O => db_out(11)
    );
  U1_I54_4_TINV_169 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_4_TINV
    );
  U1_I61_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I61_8 : X_TRI
    port map (
      I => U1_paf_counter_2(7),
      CTL => U1_I61_8_TINV,
      O => db_out(7)
    );
  U1_I61_8_TINV_170 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_8_TINV
    );
  U1_I62_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I62_4 : X_TRI
    port map (
      I => U1_paf_counter_3(11),
      CTL => U1_I62_4_TINV,
      O => db_out(11)
    );
  U1_I62_4_TINV_171 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_4_TINV
    );
  U1_I47_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I47_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I47_0_TINV,
      O => db_out(15)
    );
  U1_I47_0_TINV_172 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_0_TINV
    );
  U1_I55_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I55_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_0_TINV,
      O => db_out(15)
    );
  U1_I55_0_TINV_173 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_0_TINV
    );
  U1_I63_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I63_0 : X_TRI
    port map (
      I => U1_paf_counter_4(15),
      CTL => U1_I63_0_TINV,
      O => db_out(15)
    );
  U1_I63_0_TINV_174 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_0_TINV
    );
  U1_I45_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I45_9 : X_TRI
    port map (
      I => U1_hasunlock(0),
      CTL => U1_I45_9_TINV,
      O => db_out(6)
    );
  U1_I45_9_TINV_175 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_9_TINV
    );
  U1_I46_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I46_5 : X_TRI
    port map (
      I => U1_paf_reg(4),
      CTL => U1_I46_5_TINV,
      O => db_out(10)
    );
  U1_I46_5_TINV_176 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_5_TINV
    );
  U1_I47_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I47_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I47_1_TINV,
      O => db_out(14)
    );
  U1_I47_1_TINV_177 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_1_TINV
    );
  U1_I53_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I53_9 : X_TRI
    port map (
      I => U2_disparity(6),
      CTL => U1_I53_9_TINV,
      O => db_out(6)
    );
  U1_I53_9_TINV_178 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_9_TINV
    );
  U1_I54_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I54_5 : X_TRI
    port map (
      I => U1_timeout_value(10),
      CTL => U1_I54_5_TINV,
      O => db_out(10)
    );
  U1_I54_5_TINV_179 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_5_TINV
    );
  U1_I55_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I55_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_1_TINV,
      O => db_out(14)
    );
  U1_I55_1_TINV_180 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_1_TINV
    );
  U1_I43_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I43_13 : X_TRI
    port map (
      I => lock_2_IBUF,
      CTL => U1_I43_13_TINV,
      O => db_out(2)
    );
  U1_I43_13_TINV_181 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_13_TINV
    );
  U1_I51_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I51_13 : X_TRI
    port map (
      I => U2_byte_par(2),
      CTL => U1_I51_13_TINV,
      O => db_out(2)
    );
  U1_I51_13_TINV_182 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_13_TINV
    );
  U1_I43_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I43_14 : X_TRI
    port map (
      I => lock_1_IBUF,
      CTL => U1_I43_14_TINV,
      O => db_out(1)
    );
  U1_I43_14_TINV_183 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_14_TINV
    );
  U1_timeout_value_7 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_7_IBUF,
      CE => U1_n0009,
      CLK => CLK,
      SET => db_7_IFF_SET,
      RST => GND,
      O => U1_timeout_value(7)
    );
  db_7_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_7_IFF_SET
    );
  U1_I51_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I51_14 : X_TRI
    port map (
      I => U2_byte_par(1),
      CTL => U1_I51_14_TINV,
      O => db_out(1)
    );
  U1_I51_14_TINV_184 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_14_TINV
    );
  U1_I43_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I43_15 : X_TRI
    port map (
      I => lock_0_IBUF,
      CTL => U1_I43_15_TINV,
      O => db_out(0)
    );
  U1_I43_15_TINV_185 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_15_TINV
    );
  U1_timeout_value_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_6_IBUF,
      CE => U1_n0009,
      CLK => CLK,
      SET => db_6_IFF_SET,
      RST => GND,
      O => U1_timeout_value(6)
    );
  db_6_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_6_IFF_SET
    );
  U1_I51_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I51_15 : X_TRI
    port map (
      I => U2_byte_par(0),
      CTL => U1_I51_15_TINV,
      O => db_out(0)
    );
  U1_I51_15_TINV_186 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_15_TINV
    );
  U1_I44_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I44_10 : X_TRI
    port map (
      I => U1_dis_evid_wrong,
      CTL => U1_I44_10_TINV,
      O => db_out(5)
    );
  U1_I44_10_TINV_187 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_10_TINV
    );
  U1_I52_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I52_10 : X_TRI
    port map (
      I => U2_byte_par(21),
      CTL => U1_I52_10_TINV,
      O => db_out(5)
    );
  U1_I52_10_TINV_188 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_10_TINV
    );
  U1_I60_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I60_10 : X_TRI
    port map (
      I => U1_paf_counter_1(5),
      CTL => U1_I60_10_TINV,
      O => db_out(5)
    );
  U1_I60_10_TINV_189 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_10_TINV
    );
  U1_I44_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I44_11 : X_TRI
    port map (
      I => U1_dis_paf_warn,
      CTL => U1_I44_11_TINV,
      O => db_out(4)
    );
  U1_I44_11_TINV_190 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_11_TINV
    );
  U1_I52_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I52_11 : X_TRI
    port map (
      I => U2_byte_par(20),
      CTL => U1_I52_11_TINV,
      O => db_out(4)
    );
  U1_I52_11_TINV_191 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_11_TINV
    );
  U1_I60_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I60_11 : X_TRI
    port map (
      I => U1_paf_counter_1(4),
      CTL => U1_I60_11_TINV,
      O => db_out(4)
    );
  U1_I60_11_TINV_192 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_11_TINV
    );
  U1_I44_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I44_12 : X_TRI
    port map (
      I => U1_dis_ffreg_mask,
      CTL => U1_I44_12_TINV,
      O => db_out(3)
    );
  U1_I44_12_TINV_193 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_12_TINV
    );
  U1_I52_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I52_12 : X_TRI
    port map (
      I => U2_byte_par(19),
      CTL => U1_I52_12_TINV,
      O => db_out(3)
    );
  U1_I52_12_TINV_194 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_12_TINV
    );
  U1_I60_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I60_12 : X_TRI
    port map (
      I => U1_paf_counter_1(3),
      CTL => U1_I60_12_TINV,
      O => db_out(3)
    );
  U1_I60_12_TINV_195 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_12_TINV
    );
  U1_I44_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I44_13 : X_TRI
    port map (
      I => U1_dis_timo_mask,
      CTL => U1_I44_13_TINV,
      O => db_out(2)
    );
  U1_I44_13_TINV_196 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_13_TINV
    );
  U1_I52_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I52_13 : X_TRI
    port map (
      I => U2_byte_par(18),
      CTL => U1_I52_13_TINV,
      O => db_out(2)
    );
  U1_I52_13_TINV_197 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_13_TINV
    );
  U1_I60_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I60_13 : X_TRI
    port map (
      I => U1_paf_counter_1(2),
      CTL => U1_I60_13_TINV,
      O => db_out(2)
    );
  U1_I60_13_TINV_198 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_13_TINV
    );
  U1_I44_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I44_14 : X_TRI
    port map (
      I => U1_dis_hul_mask,
      CTL => U1_I44_14_TINV,
      O => db_out(1)
    );
  U1_I44_14_TINV_199 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_14_TINV
    );
  U1_I52_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I52_14 : X_TRI
    port map (
      I => U2_byte_par(17),
      CTL => U1_I52_14_TINV,
      O => db_out(1)
    );
  U1_I52_14_TINV_200 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_14_TINV
    );
  U1_I60_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I60_14 : X_TRI
    port map (
      I => U1_paf_counter_1(1),
      CTL => U1_I60_14_TINV,
      O => db_out(1)
    );
  U1_I60_14_TINV_201 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_14_TINV
    );
  U1_I44_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I44_15 : X_TRI
    port map (
      I => U1_dis_maxw_mask,
      CTL => U1_I44_15_TINV,
      O => db_out(0)
    );
  U1_I44_15_TINV_202 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_15_TINV
    );
  U1_I52_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I52_15 : X_TRI
    port map (
      I => U2_byte_par(16),
      CTL => U1_I52_15_TINV,
      O => db_out(0)
    );
  U1_I52_15_TINV_203 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_15_TINV
    );
  U1_I60_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I60_15 : X_TRI
    port map (
      I => U1_paf_counter_1(0),
      CTL => U1_I60_15_TINV,
      O => db_out(0)
    );
  U1_I60_15_TINV_204 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_15_TINV
    );
  U1_I45_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I45_10 : X_TRI
    port map (
      I => U3_timed_out(5),
      CTL => U1_I45_10_TINV,
      O => db_out(5)
    );
  U1_I45_10_TINV_205 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_10_TINV
    );
  U1_I53_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I53_10 : X_TRI
    port map (
      I => U2_disparity(5),
      CTL => U1_I53_10_TINV,
      O => db_out(5)
    );
  U1_I53_10_TINV_206 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_10_TINV
    );
  U1_I61_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I61_10 : X_TRI
    port map (
      I => U1_paf_counter_2(5),
      CTL => U1_I61_10_TINV,
      O => db_out(5)
    );
  U1_I61_10_TINV_207 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_10_TINV
    );
  U1_I45_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I45_11 : X_TRI
    port map (
      I => U3_timed_out(4),
      CTL => U1_I45_11_TINV,
      O => db_out(4)
    );
  U1_I45_11_TINV_208 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_11_TINV
    );
  U1_I53_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I53_11 : X_TRI
    port map (
      I => U2_disparity(4),
      CTL => U1_I53_11_TINV,
      O => db_out(4)
    );
  U1_I53_11_TINV_209 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_11_TINV
    );
  U1_I61_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I61_11 : X_TRI
    port map (
      I => U1_paf_counter_2(4),
      CTL => U1_I61_11_TINV,
      O => db_out(4)
    );
  U1_I61_11_TINV_210 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_11_TINV
    );
  U1_I45_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I45_12 : X_TRI
    port map (
      I => U3_timed_out(3),
      CTL => U1_I45_12_TINV,
      O => db_out(3)
    );
  U1_I45_12_TINV_211 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_12_TINV
    );
  U1_I53_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I53_12 : X_TRI
    port map (
      I => U2_disparity(3),
      CTL => U1_I53_12_TINV,
      O => db_out(3)
    );
  U1_I53_12_TINV_212 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_12_TINV
    );
  U1_I61_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I61_12 : X_TRI
    port map (
      I => U1_paf_counter_2(3),
      CTL => U1_I61_12_TINV,
      O => db_out(3)
    );
  U1_I61_12_TINV_213 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_12_TINV
    );
  U1_I45_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I45_13 : X_TRI
    port map (
      I => U3_timed_out(2),
      CTL => U1_I45_13_TINV,
      O => db_out(2)
    );
  U1_I45_13_TINV_214 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_13_TINV
    );
  U1_I53_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I53_13 : X_TRI
    port map (
      I => U2_disparity(2),
      CTL => U1_I53_13_TINV,
      O => db_out(2)
    );
  U1_I53_13_TINV_215 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_13_TINV
    );
  U1_I61_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I61_13 : X_TRI
    port map (
      I => U1_paf_counter_2(2),
      CTL => U1_I61_13_TINV,
      O => db_out(2)
    );
  U1_I61_13_TINV_216 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_13_TINV
    );
  U1_I45_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I45_14 : X_TRI
    port map (
      I => U3_timed_out(1),
      CTL => U1_I45_14_TINV,
      O => db_out(1)
    );
  U1_I45_14_TINV_217 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_14_TINV
    );
  U1_I53_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I53_14 : X_TRI
    port map (
      I => U2_disparity(1),
      CTL => U1_I53_14_TINV,
      O => db_out(1)
    );
  U1_I53_14_TINV_218 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_14_TINV
    );
  U1_I61_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I61_14 : X_TRI
    port map (
      I => U1_paf_counter_2(1),
      CTL => U1_I61_14_TINV,
      O => db_out(1)
    );
  U1_I61_14_TINV_219 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_14_TINV
    );
  U1_I45_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I45_15 : X_TRI
    port map (
      I => U3_timed_out(0),
      CTL => U1_I45_15_TINV,
      O => db_out(0)
    );
  U1_I45_15_TINV_220 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_15_TINV
    );
  U1_I53_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I53_15 : X_TRI
    port map (
      I => U2_disparity(0),
      CTL => U1_I53_15_TINV,
      O => db_out(0)
    );
  U1_I53_15_TINV_221 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_15_TINV
    );
  U1_I61_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I61_15 : X_TRI
    port map (
      I => U1_paf_counter_2(0),
      CTL => U1_I61_15_TINV,
      O => db_out(0)
    );
  U1_I61_15_TINV_222 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_15_TINV
    );
  U1_I46_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I46_10 : X_TRI
    port map (
      I => U1_I46_10_IMUXNOT,
      CTL => U1_I46_10_TINV,
      O => db_out(5)
    );
  U1_I46_10_TINV_223 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_10_TINV
    );
  U1_I46_10_IMUX : X_INV
    port map (
      I => paf_5_IBUF,
      O => U1_I46_10_IMUXNOT
    );
  U1_I54_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I54_10 : X_TRI
    port map (
      I => U1_timeout_value(5),
      CTL => U1_I54_10_TINV,
      O => db_out(5)
    );
  U1_I54_10_TINV_224 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_10_TINV
    );
  U1_I62_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I62_10 : X_TRI
    port map (
      I => U1_paf_counter_3(5),
      CTL => U1_I62_10_TINV,
      O => db_out(5)
    );
  U1_I62_10_TINV_225 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_10_TINV
    );
  U1_I46_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I46_11 : X_TRI
    port map (
      I => U1_I46_11_IMUXNOT,
      CTL => U1_I46_11_TINV,
      O => db_out(4)
    );
  U1_I46_11_TINV_226 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_11_TINV
    );
  U1_I46_11_IMUX : X_INV
    port map (
      I => paf_4_IBUF,
      O => U1_I46_11_IMUXNOT
    );
  U1_I54_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I54_11 : X_TRI
    port map (
      I => U1_timeout_value(4),
      CTL => U1_I54_11_TINV,
      O => db_out(4)
    );
  U1_I54_11_TINV_227 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_11_TINV
    );
  U1_I62_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I62_11 : X_TRI
    port map (
      I => U1_paf_counter_3(4),
      CTL => U1_I62_11_TINV,
      O => db_out(4)
    );
  U1_I62_11_TINV_228 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_11_TINV
    );
  U1_I46_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I46_12 : X_TRI
    port map (
      I => U1_I46_12_IMUXNOT,
      CTL => U1_I46_12_TINV,
      O => db_out(3)
    );
  U1_I46_12_TINV_229 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_12_TINV
    );
  U1_I46_12_IMUX : X_INV
    port map (
      I => paf_3_IBUF,
      O => U1_I46_12_IMUXNOT
    );
  U1_I54_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I54_12 : X_TRI
    port map (
      I => U1_timeout_value(3),
      CTL => U1_I54_12_TINV,
      O => db_out(3)
    );
  U1_I54_12_TINV_230 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_12_TINV
    );
  U1_I62_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I62_12 : X_TRI
    port map (
      I => U1_paf_counter_3(3),
      CTL => U1_I62_12_TINV,
      O => db_out(3)
    );
  U1_I62_12_TINV_231 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_12_TINV
    );
  U1_I46_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I46_13 : X_TRI
    port map (
      I => U1_I46_13_IMUXNOT,
      CTL => U1_I46_13_TINV,
      O => db_out(2)
    );
  U1_I46_13_TINV_232 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_13_TINV
    );
  U1_I46_13_IMUX : X_INV
    port map (
      I => paf_2_IBUF,
      O => U1_I46_13_IMUXNOT
    );
  U1_I54_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I54_13 : X_TRI
    port map (
      I => U1_timeout_value(2),
      CTL => U1_I54_13_TINV,
      O => db_out(2)
    );
  U1_I54_13_TINV_233 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_13_TINV
    );
  U1_I62_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I62_13 : X_TRI
    port map (
      I => U1_paf_counter_3(2),
      CTL => U1_I62_13_TINV,
      O => db_out(2)
    );
  U1_I62_13_TINV_234 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_13_TINV
    );
  U1_I46_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I46_14 : X_TRI
    port map (
      I => U1_I46_14_IMUXNOT,
      CTL => U1_I46_14_TINV,
      O => db_out(1)
    );
  U1_I46_14_TINV_235 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_14_TINV
    );
  U1_I46_14_IMUX : X_INV
    port map (
      I => paf_1_IBUF,
      O => U1_I46_14_IMUXNOT
    );
  U1_timeout_value_9 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_9_IBUF,
      CE => U1_n0009,
      CLK => CLK,
      SET => db_9_IFF_SET,
      RST => GND,
      O => U1_timeout_value(9)
    );
  db_9_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_9_IFF_SET
    );
  U1_I54_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I54_14 : X_TRI
    port map (
      I => U1_timeout_value(1),
      CTL => U1_I54_14_TINV,
      O => db_out(1)
    );
  U1_I54_14_TINV_236 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_14_TINV
    );
  U1_timeout_value_8 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_8_IBUF,
      CE => U1_n0009,
      CLK => CLK,
      SET => db_8_IFF_SET,
      RST => GND,
      O => U1_timeout_value(8)
    );
  db_8_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_8_IFF_SET
    );
  U1_I62_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I62_14 : X_TRI
    port map (
      I => U1_paf_counter_3(1),
      CTL => U1_I62_14_TINV,
      O => db_out(1)
    );
  U1_I62_14_TINV_237 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_14_TINV
    );
  U1_I46_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I46_15 : X_TRI
    port map (
      I => U1_I46_15_IMUXNOT,
      CTL => U1_I46_15_TINV,
      O => db_out(0)
    );
  U1_I46_15_TINV_238 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_15_TINV
    );
  U1_I46_15_IMUX : X_INV
    port map (
      I => paf_0_IBUF,
      O => U1_I46_15_IMUXNOT
    );
  U1_I54_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I54_15 : X_TRI
    port map (
      I => U1_timeout_value(0),
      CTL => U1_I54_15_TINV,
      O => db_out(0)
    );
  U1_I54_15_TINV_239 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_15_TINV
    );
  U1_I62_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I62_15 : X_TRI
    port map (
      I => U1_paf_counter_3(0),
      CTL => U1_I62_15_TINV,
      O => db_out(0)
    );
  U1_I62_15_TINV_240 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_15_TINV
    );
  U1_I47_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I47_10 : X_TRI
    port map (
      I => ef_5_IBUF,
      CTL => U1_I47_10_TINV,
      O => db_out(5)
    );
  U1_I47_10_TINV_241 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_10_TINV
    );
  U1_I55_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I55_10 : X_TRI
    port map (
      I => U1_nmaxwords(5),
      CTL => U1_I55_10_TINV,
      O => db_out(5)
    );
  U1_I55_10_TINV_242 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_10_TINV
    );
  U1_I63_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I63_10 : X_TRI
    port map (
      I => U1_paf_counter_4(5),
      CTL => U1_I63_10_TINV,
      O => db_out(5)
    );
  U1_I63_10_TINV_243 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_10_TINV
    );
  U1_I47_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I47_11 : X_TRI
    port map (
      I => ef_4_IBUF,
      CTL => U1_I47_11_TINV,
      O => db_out(4)
    );
  U1_I47_11_TINV_244 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_11_TINV
    );
  U1_I55_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I55_11 : X_TRI
    port map (
      I => U1_nmaxwords(4),
      CTL => U1_I55_11_TINV,
      O => db_out(4)
    );
  U1_I55_11_TINV_245 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_11_TINV
    );
  U1_I63_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I63_11 : X_TRI
    port map (
      I => U1_paf_counter_4(4),
      CTL => U1_I63_11_TINV,
      O => db_out(4)
    );
  U1_I63_11_TINV_246 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_11_TINV
    );
  U1_I47_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I47_12 : X_TRI
    port map (
      I => ef_3_IBUF,
      CTL => U1_I47_12_TINV,
      O => db_out(3)
    );
  U1_I47_12_TINV_247 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_12_TINV
    );
  U1_I55_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I55_12 : X_TRI
    port map (
      I => U1_nmaxwords(3),
      CTL => U1_I55_12_TINV,
      O => db_out(3)
    );
  U1_I55_12_TINV_248 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_12_TINV
    );
  U1_I63_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I63_12 : X_TRI
    port map (
      I => U1_paf_counter_4(3),
      CTL => U1_I63_12_TINV,
      O => db_out(3)
    );
  U1_I63_12_TINV_249 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_12_TINV
    );
  U1_I47_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I47_13 : X_TRI
    port map (
      I => ef_2_IBUF,
      CTL => U1_I47_13_TINV,
      O => db_out(2)
    );
  U1_I47_13_TINV_250 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_13_TINV
    );
  U1_I55_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I55_13 : X_TRI
    port map (
      I => U1_nmaxwords(2),
      CTL => U1_I55_13_TINV,
      O => db_out(2)
    );
  U1_I55_13_TINV_251 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_13_TINV
    );
  U1_I63_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I63_13 : X_TRI
    port map (
      I => U1_paf_counter_4(2),
      CTL => U1_I63_13_TINV,
      O => db_out(2)
    );
  U1_I63_13_TINV_252 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_13_TINV
    );
  U1_I50_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I50_0 : X_TRI
    port map (
      I => U2_word_par(15),
      CTL => U1_I50_0_TINV,
      O => db_out(15)
    );
  U1_I50_0_TINV_253 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_0_TINV
    );
  U1_I47_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I47_14 : X_TRI
    port map (
      I => ef_1_IBUF,
      CTL => U1_I47_14_TINV,
      O => db_out(1)
    );
  U1_I47_14_TINV_254 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_14_TINV
    );
  U1_I50_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I50_1 : X_TRI
    port map (
      I => U2_word_par(14),
      CTL => U1_I50_1_TINV,
      O => db_out(14)
    );
  U1_I50_1_TINV_255 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_1_TINV
    );
  U1_I55_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I55_14 : X_TRI
    port map (
      I => U1_nmaxwords(1),
      CTL => U1_I55_14_TINV,
      O => db_out(1)
    );
  U1_I55_14_TINV_256 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_14_TINV
    );
  U1_I63_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I63_14 : X_TRI
    port map (
      I => U1_paf_counter_4(1),
      CTL => U1_I63_14_TINV,
      O => db_out(1)
    );
  U1_I63_14_TINV_257 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_14_TINV
    );
  U1_I47_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I47_15 : X_TRI
    port map (
      I => ef_0_IBUF,
      CTL => U1_I47_15_TINV,
      O => db_out(0)
    );
  U1_I47_15_TINV_258 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_15_TINV
    );
  U1_I50_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I50_2 : X_TRI
    port map (
      I => U2_word_par(13),
      CTL => U1_I50_2_TINV,
      O => db_out(13)
    );
  U1_I50_2_TINV_259 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_2_TINV
    );
  U1_I55_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I55_15 : X_TRI
    port map (
      I => U1_nmaxwords(0),
      CTL => U1_I55_15_TINV,
      O => db_out(0)
    );
  U1_I55_15_TINV_260 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_15_TINV
    );
  U1_I63_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I63_15 : X_TRI
    port map (
      I => U1_paf_counter_4(0),
      CTL => U1_I63_15_TINV,
      O => db_out(0)
    );
  U1_I63_15_TINV_261 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_15_TINV
    );
  U1_I50_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I50_3 : X_TRI
    port map (
      I => U2_word_par(12),
      CTL => U1_I50_3_TINV,
      O => db_out(12)
    );
  U1_I50_3_TINV_262 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_3_TINV
    );
  U1_I50_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I50_4 : X_TRI
    port map (
      I => U2_word_par(11),
      CTL => U1_I50_4_TINV,
      O => db_out(11)
    );
  U1_I50_4_TINV_263 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_4_TINV
    );
  U1_I43_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I43_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I43_0_TINV,
      O => db_out(15)
    );
  U1_I43_0_TINV_264 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_0_TINV
    );
  U1_I51_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I51_0 : X_TRI
    port map (
      I => U2_byte_par(15),
      CTL => U1_I51_0_TINV,
      O => db_out(15)
    );
  U1_I51_0_TINV_265 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_0_TINV
    );
  U1_I43_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I43_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I43_1_TINV,
      O => db_out(14)
    );
  U1_I43_1_TINV_266 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_1_TINV
    );
  U1_I48_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I48_10 : X_TRI
    port map (
      I => U3_maxw_reached(5),
      CTL => U1_I48_10_TINV,
      O => db_out(5)
    );
  U1_I48_10_TINV_267 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_10_TINV
    );
  U1_I50_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I50_5 : X_TRI
    port map (
      I => U2_word_par(10),
      CTL => U1_I50_5_TINV,
      O => db_out(10)
    );
  U1_I50_5_TINV_268 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_5_TINV
    );
  U1_I51_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I51_1 : X_TRI
    port map (
      I => U2_byte_par(14),
      CTL => U1_I51_1_TINV,
      O => db_out(14)
    );
  U1_I51_1_TINV_269 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_1_TINV
    );
  U1_I56_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I56_10 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_10_TINV,
      O => db_out(5)
    );
  U1_I56_10_TINV_270 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_10_TINV
    );
  U1_I64_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I64_10 : X_TRI
    port map (
      I => U1_paf_counter_5(5),
      CTL => U1_I64_10_TINV,
      O => db_out(5)
    );
  U1_I64_10_TINV_271 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_10_TINV
    );
  U1_I43_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I43_2 : X_TRI
    port map (
      I => ceros_id_1_IBUF,
      CTL => U1_I43_2_TINV,
      O => db_out(13)
    );
  U1_I43_2_TINV_272 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_2_TINV
    );
  U1_I48_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I48_11 : X_TRI
    port map (
      I => U3_maxw_reached(4),
      CTL => U1_I48_11_TINV,
      O => db_out(4)
    );
  U1_I48_11_TINV_273 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_11_TINV
    );
  U1_I50_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I50_6 : X_TRI
    port map (
      I => U2_word_par(9),
      CTL => U1_I50_6_TINV,
      O => db_out(9)
    );
  U1_I50_6_TINV_274 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_6_TINV
    );
  U1_I51_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I51_2 : X_TRI
    port map (
      I => U2_byte_par(13),
      CTL => U1_I51_2_TINV,
      O => db_out(13)
    );
  U1_I51_2_TINV_275 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_2_TINV
    );
  U1_I56_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I56_11 : X_TRI
    port map (
      I => U1_resynch_maxw,
      CTL => U1_I56_11_TINV,
      O => db_out(4)
    );
  U1_I56_11_TINV_276 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_11_TINV
    );
  U1_I64_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I64_11 : X_TRI
    port map (
      I => U1_paf_counter_5(4),
      CTL => U1_I64_11_TINV,
      O => db_out(4)
    );
  U1_I64_11_TINV_277 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_11_TINV
    );
  U1_I43_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I43_3 : X_TRI
    port map (
      I => ceros_id_0_IBUF,
      CTL => U1_I43_3_TINV,
      O => db_out(12)
    );
  U1_I43_3_TINV_278 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_3_TINV
    );
  U1_I48_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I48_12 : X_TRI
    port map (
      I => U3_maxw_reached(3),
      CTL => U1_I48_12_TINV,
      O => db_out(3)
    );
  U1_I48_12_TINV_279 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_12_TINV
    );
  U1_I50_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I50_7 : X_TRI
    port map (
      I => U2_word_par(8),
      CTL => U1_I50_7_TINV,
      O => db_out(8)
    );
  U1_I50_7_TINV_280 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_7_TINV
    );
  U1_I51_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I51_3 : X_TRI
    port map (
      I => U2_byte_par(12),
      CTL => U1_I51_3_TINV,
      O => db_out(12)
    );
  U1_I51_3_TINV_281 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_3_TINV
    );
  U1_I56_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I56_12 : X_TRI
    port map (
      I => U1_resynch_FF,
      CTL => U1_I56_12_TINV,
      O => db_out(3)
    );
  U1_I56_12_TINV_282 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_12_TINV
    );
  U1_I64_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I64_12 : X_TRI
    port map (
      I => U1_paf_counter_5(3),
      CTL => U1_I64_12_TINV,
      O => db_out(3)
    );
  U1_I64_12_TINV_283 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_12_TINV
    );
  U1_I43_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I43_4 : X_TRI
    port map (
      I => U1_mask(5),
      CTL => U1_I43_4_TINV,
      O => db_out(11)
    );
  U1_I43_4_TINV_284 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_4_TINV
    );
  U1_I48_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I48_13 : X_TRI
    port map (
      I => U3_maxw_reached(2),
      CTL => U1_I48_13_TINV,
      O => db_out(2)
    );
  U1_I48_13_TINV_285 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_13_TINV
    );
  U1_I50_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I50_8 : X_TRI
    port map (
      I => U2_word_par(7),
      CTL => U1_I50_8_TINV,
      O => db_out(7)
    );
  U1_I50_8_TINV_286 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_8_TINV
    );
  U1_I51_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I51_4 : X_TRI
    port map (
      I => U2_byte_par(11),
      CTL => U1_I51_4_TINV,
      O => db_out(11)
    );
  U1_I51_4_TINV_287 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_4_TINV
    );
  U1_I56_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I56_13 : X_TRI
    port map (
      I => U1_warn_PAF,
      CTL => U1_I56_13_TINV,
      O => db_out(2)
    );
  U1_I56_13_TINV_288 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_13_TINV
    );
  U1_I64_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I64_13 : X_TRI
    port map (
      I => U1_paf_counter_5(2),
      CTL => U1_I64_13_TINV,
      O => db_out(2)
    );
  U1_I64_13_TINV_289 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_13_TINV
    );
  U1_I44_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I44_0 : X_TRI
    port map (
      I => blocked(5),
      CTL => U1_I44_0_TINV,
      O => db_out(15)
    );
  U1_I44_0_TINV_290 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_0_TINV
    );
  U1_I52_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I52_0 : X_TRI
    port map (
      I => U2_byte_par(31),
      CTL => U1_I52_0_TINV,
      O => db_out(15)
    );
  U1_I52_0_TINV_291 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_0_TINV
    );
  U1_I60_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I60_0 : X_TRI
    port map (
      I => U1_paf_counter_1(15),
      CTL => U1_I60_0_TINV,
      O => db_out(15)
    );
  U1_I60_0_TINV_292 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_0_TINV
    );
  U1_I43_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I43_5 : X_TRI
    port map (
      I => U1_mask(4),
      CTL => U1_I43_5_TINV,
      O => db_out(10)
    );
  U1_I43_5_TINV_293 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_5_TINV
    );
  U1_I44_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I44_1 : X_TRI
    port map (
      I => blocked(4),
      CTL => U1_I44_1_TINV,
      O => db_out(14)
    );
  U1_I44_1_TINV_294 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_1_TINV
    );
  U1_I48_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I48_14 : X_TRI
    port map (
      I => U3_maxw_reached(1),
      CTL => U1_I48_14_TINV,
      O => db_out(1)
    );
  U1_I48_14_TINV_295 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_14_TINV
    );
  U1_I50_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I50_9 : X_TRI
    port map (
      I => U2_word_par(6),
      CTL => U1_I50_9_TINV,
      O => db_out(6)
    );
  U1_I50_9_TINV_296 : X_INV
    port map (
      I => U1_I50_N1762,
      O => U1_I50_9_TINV
    );
  U1_I51_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I51_5 : X_TRI
    port map (
      I => U2_byte_par(10),
      CTL => U1_I51_5_TINV,
      O => db_out(10)
    );
  U1_I51_5_TINV_297 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_5_TINV
    );
  U1_I52_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I52_1 : X_TRI
    port map (
      I => U2_byte_par(30),
      CTL => U1_I52_1_TINV,
      O => db_out(14)
    );
  U1_I52_1_TINV_298 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_1_TINV
    );
  U1_I56_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I56_14 : X_TRI
    port map (
      I => U1_resynch_evidmis,
      CTL => U1_I56_14_TINV,
      O => db_out(1)
    );
  U1_I56_14_TINV_299 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_14_TINV
    );
  U1_I60_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I60_1 : X_TRI
    port map (
      I => U1_paf_counter_1(14),
      CTL => U1_I60_1_TINV,
      O => db_out(14)
    );
  U1_I60_1_TINV_300 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_1_TINV
    );
  U1_I64_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I64_14 : X_TRI
    port map (
      I => U1_paf_counter_5(1),
      CTL => U1_I64_14_TINV,
      O => db_out(1)
    );
  U1_I64_14_TINV_301 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_14_TINV
    );
  U1_I43_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I43_6 : X_TRI
    port map (
      I => U1_mask(3),
      CTL => U1_I43_6_TINV,
      O => db_out(9)
    );
  U1_I43_6_TINV_302 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_6_TINV
    );
  U1_I44_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I44_2 : X_TRI
    port map (
      I => blocked(3),
      CTL => U1_I44_2_TINV,
      O => db_out(13)
    );
  U1_I44_2_TINV_303 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_2_TINV
    );
  U1_I48_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I48_15 : X_TRI
    port map (
      I => U3_maxw_reached(0),
      CTL => U1_I48_15_TINV,
      O => db_out(0)
    );
  U1_I48_15_TINV_304 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_15_TINV
    );
  U1_I51_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I51_6 : X_TRI
    port map (
      I => U2_byte_par(9),
      CTL => U1_I51_6_TINV,
      O => db_out(9)
    );
  U1_I51_6_TINV_305 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_6_TINV
    );
  U1_I52_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I52_2 : X_TRI
    port map (
      I => U2_byte_par(29),
      CTL => U1_I52_2_TINV,
      O => db_out(13)
    );
  U1_I52_2_TINV_306 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_2_TINV
    );
  U1_I56_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I56_15 : X_TRI
    port map (
      I => U1_resynch_to,
      CTL => U1_I56_15_TINV,
      O => db_out(0)
    );
  U1_I56_15_TINV_307 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_15_TINV
    );
  U1_I60_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I60_2 : X_TRI
    port map (
      I => U1_paf_counter_1(13),
      CTL => U1_I60_2_TINV,
      O => db_out(13)
    );
  U1_I60_2_TINV_308 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_2_TINV
    );
  U1_I64_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I64_15 : X_TRI
    port map (
      I => U1_paf_counter_5(0),
      CTL => U1_I64_15_TINV,
      O => db_out(0)
    );
  U1_I64_15_TINV_309 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_15_TINV
    );
  U1_I43_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I43_7 : X_TRI
    port map (
      I => U1_mask(2),
      CTL => U1_I43_7_TINV,
      O => db_out(8)
    );
  U1_I43_7_TINV_310 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_7_TINV
    );
  U1_I44_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I44_3 : X_TRI
    port map (
      I => blocked(2),
      CTL => U1_I44_3_TINV,
      O => db_out(12)
    );
  U1_I44_3_TINV_311 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_3_TINV
    );
  U1_I51_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I51_7 : X_TRI
    port map (
      I => U2_byte_par(8),
      CTL => U1_I51_7_TINV,
      O => db_out(8)
    );
  U1_I51_7_TINV_312 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_7_TINV
    );
  U1_I52_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I52_3 : X_TRI
    port map (
      I => U2_byte_par(28),
      CTL => U1_I52_3_TINV,
      O => db_out(12)
    );
  U1_I52_3_TINV_313 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_3_TINV
    );
  U1_I60_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I60_3 : X_TRI
    port map (
      I => U1_paf_counter_1(12),
      CTL => U1_I60_3_TINV,
      O => db_out(12)
    );
  U1_I60_3_TINV_314 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_3_TINV
    );
  U1_I43_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I43_8 : X_TRI
    port map (
      I => U1_mask(1),
      CTL => U1_I43_8_TINV,
      O => db_out(7)
    );
  U1_I43_8_TINV_315 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_8_TINV
    );
  U1_I44_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I44_4 : X_TRI
    port map (
      I => blocked(1),
      CTL => U1_I44_4_TINV,
      O => db_out(11)
    );
  U1_I44_4_TINV_316 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_4_TINV
    );
  U1_I51_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I51_8 : X_TRI
    port map (
      I => U2_byte_par(7),
      CTL => U1_I51_8_TINV,
      O => db_out(7)
    );
  U1_I51_8_TINV_317 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_8_TINV
    );
  U1_I52_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I52_4 : X_TRI
    port map (
      I => U2_byte_par(27),
      CTL => U1_I52_4_TINV,
      O => db_out(11)
    );
  U1_I52_4_TINV_318 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_4_TINV
    );
  U1_I60_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I60_4 : X_TRI
    port map (
      I => U1_paf_counter_1(11),
      CTL => U1_I60_4_TINV,
      O => db_out(11)
    );
  U1_I60_4_TINV_319 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_4_TINV
    );
  U1_I45_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I45_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I45_0_TINV,
      O => db_out(15)
    );
  U1_I45_0_TINV_320 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_0_TINV
    );
  U1_I53_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I53_0 : X_TRI
    port map (
      I => U2_disparity(15),
      CTL => U1_I53_0_TINV,
      O => db_out(15)
    );
  U1_I53_0_TINV_321 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_0_TINV
    );
  U1_I61_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I61_0 : X_TRI
    port map (
      I => U1_paf_counter_2(15),
      CTL => U1_I61_0_TINV,
      O => db_out(15)
    );
  U1_I61_0_TINV_322 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_0_TINV
    );
  U1_I43_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I43_9 : X_TRI
    port map (
      I => U1_mask(0),
      CTL => U1_I43_9_TINV,
      O => db_out(6)
    );
  U1_I43_9_TINV_323 : X_INV
    port map (
      I => U1_I43_N1762,
      O => U1_I43_9_TINV
    );
  U1_I44_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I44_5 : X_TRI
    port map (
      I => blocked(0),
      CTL => U1_I44_5_TINV,
      O => db_out(10)
    );
  U1_I44_5_TINV_324 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_5_TINV
    );
  U1_I45_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I45_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I45_1_TINV,
      O => db_out(14)
    );
  U1_I45_1_TINV_325 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_1_TINV
    );
  U1_I49_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I49_10 : X_TRI
    port map (
      I => U2_pae_paf_reg(5),
      CTL => U1_I49_10_TINV,
      O => db_out(5)
    );
  U1_I49_10_TINV_326 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_10_TINV
    );
  U1_I51_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I51_9 : X_TRI
    port map (
      I => U2_byte_par(6),
      CTL => U1_I51_9_TINV,
      O => db_out(6)
    );
  U1_I51_9_TINV_327 : X_INV
    port map (
      I => U1_I51_N1762,
      O => U1_I51_9_TINV
    );
  U1_I52_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I52_5 : X_TRI
    port map (
      I => U2_byte_par(26),
      CTL => U1_I52_5_TINV,
      O => db_out(10)
    );
  U1_I52_5_TINV_328 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_5_TINV
    );
  U1_I53_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I53_1 : X_TRI
    port map (
      I => U2_disparity(14),
      CTL => U1_I53_1_TINV,
      O => db_out(14)
    );
  U1_I53_1_TINV_329 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_1_TINV
    );
  U1_I57_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I57_10 : X_TRI
    port map (
      I => U1_fout_reg(5),
      CTL => U1_I57_10_TINV,
      O => db_out(5)
    );
  U1_I57_10_TINV_330 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_10_TINV
    );
  U1_I60_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I60_5 : X_TRI
    port map (
      I => U1_paf_counter_1(10),
      CTL => U1_I60_5_TINV,
      O => db_out(10)
    );
  U1_I60_5_TINV_331 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_5_TINV
    );
  U1_I61_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I61_1 : X_TRI
    port map (
      I => U1_paf_counter_2(14),
      CTL => U1_I61_1_TINV,
      O => db_out(14)
    );
  U1_I61_1_TINV_332 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_1_TINV
    );
  U1_I65_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I65_10 : X_TRI
    port map (
      I => U1_db_error1(5),
      CTL => U1_I65_10_TINV,
      O => db_out(5)
    );
  U1_I65_10_TINV_333 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_10_TINV
    );
  U1_I44_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I44_6 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I44_6_TINV,
      O => db_out(9)
    );
  U1_I44_6_TINV_334 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_6_TINV
    );
  U1_I45_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I45_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I45_2_TINV,
      O => db_out(13)
    );
  U1_I45_2_TINV_335 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_2_TINV
    );
  U1_I49_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I49_11 : X_TRI
    port map (
      I => U2_pae_paf_reg(4),
      CTL => U1_I49_11_TINV,
      O => db_out(4)
    );
  U1_I49_11_TINV_336 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_11_TINV
    );
  U1_I52_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I52_6 : X_TRI
    port map (
      I => U2_byte_par(25),
      CTL => U1_I52_6_TINV,
      O => db_out(9)
    );
  U1_I52_6_TINV_337 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_6_TINV
    );
  U1_I53_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I53_2 : X_TRI
    port map (
      I => U2_disparity(13),
      CTL => U1_I53_2_TINV,
      O => db_out(13)
    );
  U1_I53_2_TINV_338 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_2_TINV
    );
  U1_I57_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I57_11 : X_TRI
    port map (
      I => U1_fout_reg(4),
      CTL => U1_I57_11_TINV,
      O => db_out(4)
    );
  U1_I57_11_TINV_339 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_11_TINV
    );
  U1_I60_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I60_6 : X_TRI
    port map (
      I => U1_paf_counter_1(9),
      CTL => U1_I60_6_TINV,
      O => db_out(9)
    );
  U1_I60_6_TINV_340 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_6_TINV
    );
  U1_I61_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I61_2 : X_TRI
    port map (
      I => U1_paf_counter_2(13),
      CTL => U1_I61_2_TINV,
      O => db_out(13)
    );
  U1_I61_2_TINV_341 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_2_TINV
    );
  U1_I65_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I65_11 : X_TRI
    port map (
      I => U1_db_error1(4),
      CTL => U1_I65_11_TINV,
      O => db_out(4)
    );
  U1_I65_11_TINV_342 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_11_TINV
    );
  U1_I44_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I44_7 : X_TRI
    port map (
      I => U1_dis_errorw,
      CTL => U1_I44_7_TINV,
      O => db_out(8)
    );
  U1_I44_7_TINV_343 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_7_TINV
    );
  U1_I45_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I45_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I45_3_TINV,
      O => db_out(12)
    );
  U1_I45_3_TINV_344 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_3_TINV
    );
  U1_I49_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I49_12 : X_TRI
    port map (
      I => U2_pae_paf_reg(3),
      CTL => U1_I49_12_TINV,
      O => db_out(3)
    );
  U1_I49_12_TINV_345 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_12_TINV
    );
  U1_I52_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I52_7 : X_TRI
    port map (
      I => U2_byte_par(24),
      CTL => U1_I52_7_TINV,
      O => db_out(8)
    );
  U1_I52_7_TINV_346 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_7_TINV
    );
  U1_I53_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I53_3 : X_TRI
    port map (
      I => U2_disparity(12),
      CTL => U1_I53_3_TINV,
      O => db_out(12)
    );
  U1_I53_3_TINV_347 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_3_TINV
    );
  U1_I57_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I57_12 : X_TRI
    port map (
      I => U1_fout_reg(3),
      CTL => U1_I57_12_TINV,
      O => db_out(3)
    );
  U1_I57_12_TINV_348 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_12_TINV
    );
  U1_I60_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I60_7 : X_TRI
    port map (
      I => U1_paf_counter_1(8),
      CTL => U1_I60_7_TINV,
      O => db_out(8)
    );
  U1_I60_7_TINV_349 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_7_TINV
    );
  U1_I61_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I61_3 : X_TRI
    port map (
      I => U1_paf_counter_2(12),
      CTL => U1_I61_3_TINV,
      O => db_out(12)
    );
  U1_I61_3_TINV_350 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_3_TINV
    );
  U1_I65_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I65_12 : X_TRI
    port map (
      I => U1_db_error1(3),
      CTL => U1_I65_12_TINV,
      O => db_out(3)
    );
  U1_I65_12_TINV_351 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_12_TINV
    );
  U1_I44_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I44_8 : X_TRI
    port map (
      I => U1_dis_evid_bloq,
      CTL => U1_I44_8_TINV,
      O => db_out(7)
    );
  U1_I44_8_TINV_352 : X_INV
    port map (
      I => U1_I44_N1762,
      O => U1_I44_8_TINV
    );
  U1_I45_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I45_4 : X_TRI
    port map (
      I => U1_hasunlock(5),
      CTL => U1_I45_4_TINV,
      O => db_out(11)
    );
  U1_I45_4_TINV_353 : X_INV
    port map (
      I => U1_I45_N1762,
      O => U1_I45_4_TINV
    );
  U1_I49_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I49_13 : X_TRI
    port map (
      I => U2_pae_paf_reg(2),
      CTL => U1_I49_13_TINV,
      O => db_out(2)
    );
  U1_I49_13_TINV_354 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_13_TINV
    );
  U1_I52_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I52_8 : X_TRI
    port map (
      I => U2_byte_par(23),
      CTL => U1_I52_8_TINV,
      O => db_out(7)
    );
  U1_I52_8_TINV_355 : X_INV
    port map (
      I => U1_I52_N1762,
      O => U1_I52_8_TINV
    );
  U1_I53_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I53_4 : X_TRI
    port map (
      I => U2_disparity(11),
      CTL => U1_I53_4_TINV,
      O => db_out(11)
    );
  U1_I53_4_TINV_356 : X_INV
    port map (
      I => U1_I53_N1762,
      O => U1_I53_4_TINV
    );
  U1_I57_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I57_13 : X_TRI
    port map (
      I => U1_fout_reg(2),
      CTL => U1_I57_13_TINV,
      O => db_out(2)
    );
  U1_I57_13_TINV_357 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_13_TINV
    );
  U1_I60_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I60_8 : X_TRI
    port map (
      I => U1_paf_counter_1(7),
      CTL => U1_I60_8_TINV,
      O => db_out(7)
    );
  U1_I60_8_TINV_358 : X_INV
    port map (
      I => U1_I60_N1762,
      O => U1_I60_8_TINV
    );
  U1_I61_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I61_4 : X_TRI
    port map (
      I => U1_paf_counter_2(11),
      CTL => U1_I61_4_TINV,
      O => db_out(11)
    );
  U1_I61_4_TINV_359 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_4_TINV
    );
  U1_I65_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I65_13 : X_TRI
    port map (
      I => U1_db_error1(2),
      CTL => U1_I65_13_TINV,
      O => db_out(2)
    );
  U1_I65_13_TINV_360 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_13_TINV
    );
  soft_reset1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => vspare_0_IBUF,
      ADR1 => reset2,
      ADR2 => reset_IBUF,
      ADR3 => reset1,
      O => U3_dontread_0_FROM
    );
  U3_n0120_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => U1_mask(0),
      ADR1 => soft_reset,
      ADR2 => U3_dontread(0),
      ADR3 => U3_sel_read(0),
      O => U3_n0120(0)
    );
  U3_dontread_0_XUSED : X_BUF
    port map (
      I => U3_dontread_0_FROM,
      O => soft_reset
    );
  U3_n0102_1_41 : X_LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      ADR0 => CHOICE856,
      ADR1 => U3_N31407,
      ADR2 => U3_fmt_error_ff_2_1_Q,
      ADR3 => U3_N31636,
      O => CHOICE858_FROM
    );
  U3_n0102_4_4 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => U3_N31636,
      ADR1 => CHOICE509,
      ADR2 => CHOICE512,
      ADR3 => CHOICE515,
      O => CHOICE858_GROM
    );
  CHOICE858_XUSED : X_BUF
    port map (
      I => CHOICE858_FROM,
      O => CHOICE858
    );
  CHOICE858_YUSED : X_BUF
    port map (
      I => CHOICE858_GROM,
      O => CHOICE789
    );
  U3_Ker315028 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_state_FFd17,
      ADR2 => U3_state_FFd40,
      ADR3 => U3_state_FFd2,
      O => CHOICE564_FROM
    );
  U3_n0102_4_9 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_dontread(4),
      ADR2 => U3_state_FFd17,
      ADR3 => evid_4_IBUF,
      O => CHOICE564_GROM
    );
  CHOICE564_XUSED : X_BUF
    port map (
      I => CHOICE564_FROM,
      O => CHOICE564
    );
  CHOICE564_YUSED : X_BUF
    port map (
      I => CHOICE564_GROM,
      O => CHOICE792
    );
  U3_n0102_2_50 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_dontread(2),
      ADR2 => U3_state_FFd17,
      ADR3 => evid_2_IBUF,
      O => CHOICE906_FROM
    );
  U3_n0102_6_6 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_evid_mis(0),
      ADR2 => U3_state_FFd17,
      ADR3 => evid_6_IBUF,
      O => CHOICE906_GROM
    );
  CHOICE906_XUSED : X_BUF
    port map (
      I => CHOICE906_FROM,
      O => CHOICE906
    );
  CHOICE906_YUSED : X_BUF
    port map (
      I => CHOICE906_GROM,
      O => CHOICE808
    );
  U3_n0102_11_18 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_evid_mis(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE759_FROM
    );
  U3_n0102_8_5 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_evid_mis(2),
      ADR2 => U3_state_FFd17,
      ADR3 => evid_8_IBUF,
      O => CHOICE759_GROM
    );
  CHOICE759_XUSED : X_BUF
    port map (
      I => CHOICE759_FROM,
      O => CHOICE759
    );
  CHOICE759_YUSED : X_BUF
    port map (
      I => CHOICE759_GROM,
      O => CHOICE709
    );
  U3_Ker31405_SW2 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => U1_dis_errorw,
      ADR1 => U3_state_FFd38,
      ADR2 => ceros_id_0_IBUF,
      ADR3 => tp_2_OBUF,
      O => U3_state_FFd17_FROM
    );
  U3_state_FFd18_In1 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => U3_error_evid,
      ADR1 => U1_dis_evid_wrong,
      ADR2 => tp_2_OBUF,
      ADR3 => U3_state_FFd22,
      O => U3_state_FFd18_In
    );
  U3_state_FFd17_XUSED : X_BUF
    port map (
      I => U3_state_FFd17_FROM,
      O => N44306
    );
  U3_state_FFd17_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd17_SRMUX_OUTPUTNOT
    );
  Q_n005130_SW0 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => add_5_IBUF,
      ADR2 => CHOICE260,
      ADR3 => VCC,
      O => N44494_FROM
    );
  Q_n005130 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => enw1,
      ADR1 => enw2,
      ADR2 => add_4_IBUF,
      ADR3 => N44494,
      O => N44494_GROM
    );
  N44494_XUSED : X_BUF
    port map (
      I => N44494_FROM,
      O => N44494
    );
  N44494_YUSED : X_BUF
    port map (
      I => N44494_GROM,
      O => Q_n0051
    );
  U3_n0102_13_34 : X_LUT4
    generic map(
      INIT => X"F2F2"
    )
    port map (
      ADR0 => CHOICE615,
      ADR1 => U3_this_ef23_2,
      ADR2 => CHOICE613,
      ADR3 => VCC,
      O => CHOICE618_FROM
    );
  U3_n0102_15_68_SW0 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => CHOICE829,
      ADR1 => CHOICE831,
      ADR2 => U3_this_ef23_2,
      ADR3 => U3_state_FFd36_In,
      O => CHOICE618_GROM
    );
  CHOICE618_XUSED : X_BUF
    port map (
      I => CHOICE618_FROM,
      O => CHOICE618
    );
  CHOICE618_YUSED : X_BUF
    port map (
      I => CHOICE618_GROM,
      O => N44586
    );
  U3_state_FFd23_In_SW1 : X_LUT4
    generic map(
      INIT => X"5155"
    )
    port map (
      ADR0 => U3_state_FFd20,
      ADR1 => U3_state_FFd25,
      ADR2 => U1_dis_head_trail,
      ADR3 => U3_n0049,
      O => U3_state_FFd23_FROM
    );
  U3_state_FFd23_In_361 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => CHOICE683,
      ADR1 => CHOICE686,
      ADR2 => CHOICE689,
      ADR3 => N44518,
      O => U3_state_FFd23_In
    );
  U3_state_FFd23_XUSED : X_BUF
    port map (
      I => U3_state_FFd23_FROM,
      O => N44518
    );
  U3_state_FFd23_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd23_SRMUX_OUTPUTNOT
    );
  U3_n0096_4_3 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => U3_state_FFd40,
      ADR1 => ceros_id_0_IBUF,
      ADR2 => ceros_id_1_IBUF,
      ADR3 => VCC,
      O => CHOICE960_FROM
    );
  U3_n0096_2_17 : X_LUT4
    generic map(
      INIT => X"2828"
    )
    port map (
      ADR0 => U3_state_FFd40,
      ADR1 => ceros_id_0_IBUF,
      ADR2 => ceros_id_1_IBUF,
      ADR3 => VCC,
      O => CHOICE960_GROM
    );
  CHOICE960_XUSED : X_BUF
    port map (
      I => CHOICE960_FROM,
      O => CHOICE960
    );
  CHOICE960_YUSED : X_BUF
    port map (
      I => CHOICE960_GROM,
      O => CHOICE970
    );
  I18_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"DDDD"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => etr_x_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => I18_N1762_FROM
    );
  U1_I57_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29944,
      ADR3 => add_3_IBUF,
      O => I18_N1762_GROM
    );
  I18_N1762_XUSED : X_BUF
    port map (
      I => I18_N1762_FROM,
      O => I18_N1762
    );
  I18_N1762_YUSED : X_BUF
    port map (
      I => I18_N1762_GROM,
      O => U1_I57_N1762
    );
  U1_I45_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N30000,
      ADR3 => U1_N30021,
      O => U1_I45_N1762_FROM
    );
  U1_I49_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29930,
      ADR3 => U1_N30000,
      O => U1_I45_N1762_GROM
    );
  U1_I45_N1762_XUSED : X_BUF
    port map (
      I => U1_I45_N1762_FROM,
      O => U1_I45_N1762
    );
  U1_I45_N1762_YUSED : X_BUF
    port map (
      I => U1_I45_N1762_GROM,
      O => U1_I49_N1762
    );
  U3_n009867_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd30,
      ADR1 => U3_state_FFd11,
      ADR2 => U3_state_FFd6,
      ADR3 => U3_state_FFd31,
      O => N44534_FROM
    );
  U3_n009867 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31749,
      ADR1 => U3_state_FFd32,
      ADR2 => U3_state_FFd16,
      ADR3 => N44534,
      O => N44534_GROM
    );
  N44534_XUSED : X_BUF
    port map (
      I => N44534_FROM,
      O => N44534
    );
  N44534_YUSED : X_BUF
    port map (
      I => N44534_GROM,
      O => CHOICE489
    );
  U1_n00091 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => U1_N30014,
      ADR1 => U1_N29954,
      ADR2 => add_1_IBUF,
      ADR3 => add_0_IBUF,
      O => U1_n0009_FROM
    );
  U1_n00081 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N30021,
      ADR3 => U1_N29954,
      O => U1_n0009_GROM
    );
  U1_n0009_XUSED : X_BUF
    port map (
      I => U1_n0009_FROM,
      O => U1_n0009
    );
  U1_n0009_YUSED : X_BUF
    port map (
      I => U1_n0009_GROM,
      O => U1_n0008
    );
  U3_n0102_5_53 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_evid_mis(5),
      ADR1 => U3_sel_read(5),
      ADR2 => U3_evid_mis(4),
      ADR3 => U3_sel_read(4),
      O => CHOICE643_FROM
    );
  U3_this_hasunlock4 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U1_hasunlock(5),
      ADR1 => U3_sel_read(5),
      ADR2 => U1_hasunlock(4),
      ADR3 => U3_sel_read(4),
      O => CHOICE643_GROM
    );
  CHOICE643_XUSED : X_BUF
    port map (
      I => CHOICE643_FROM,
      O => CHOICE643
    );
  CHOICE643_YUSED : X_BUF
    port map (
      I => CHOICE643_GROM,
      O => CHOICE520
    );
  U3_Ker31405_SW0 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => U3_dontread(1),
      ADR1 => U3_dontread(0),
      ADR2 => U3_dontread(5),
      ADR3 => U3_dontread(4),
      O => N41351_FROM
    );
  U3_n0102_0_80 : X_LUT4
    generic map(
      INIT => X"5551"
    )
    port map (
      ADR0 => N44306,
      ADR1 => N41351,
      ADR2 => U3_dontread(3),
      ADR3 => U3_dontread(2),
      O => N41351_GROM
    );
  N41351_XUSED : X_BUF
    port map (
      I => N41351_FROM,
      O => N41351
    );
  N41351_YUSED : X_BUF
    port map (
      I => N41351_GROM,
      O => CHOICE944
    );
  U1_n01261 : X_LUT4
    generic map(
      INIT => X"7777"
    )
    port map (
      ADR0 => U1_per_fifo_aux_2,
      ADR1 => U1_per_paepaf_reg,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_n0126_GROM
    );
  U1_n0126_YUSED : X_BUF
    port map (
      I => U1_n0126_GROM,
      O => U1_n0126
    );
  U1_Ker300121 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => add_2_IBUF,
      ADR2 => add_5_IBUF,
      ADR3 => add_4_IBUF,
      O => U1_N30014_FROM
    );
  U1_I54_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29992,
      ADR3 => U1_N30014,
      O => U1_N30014_GROM
    );
  U1_N30014_XUSED : X_BUF
    port map (
      I => U1_N30014_FROM,
      O => U1_N30014
    );
  U1_N30014_YUSED : X_BUF
    port map (
      I => U1_N30014_GROM,
      O => U1_I54_N1762
    );
  U3_Ker31675_SW0 : X_LUT4
    generic map(
      INIT => X"F2F2"
    )
    port map (
      ADR0 => U3_state_FFd9,
      ADR1 => U3_n0049,
      ADR2 => U3_state_FFd5,
      ADR3 => VCC,
      O => N39317_FROM
    );
  U3_n0102_10_13_SW0 : X_LUT4
    generic map(
      INIT => X"5551"
    )
    port map (
      ADR0 => U3_state_FFd14,
      ADR1 => U3_state_FFd9,
      ADR2 => U3_n0049,
      ADR3 => U3_fmt_error_ff_2_3_Q,
      O => N39317_GROM
    );
  N39317_XUSED : X_BUF
    port map (
      I => N39317_FROM,
      O => N39317
    );
  N39317_YUSED : X_BUF
    port map (
      I => N39317_GROM,
      O => N44380
    );
  U1_Ker299521_SW0 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => add_0_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => cs_IBUF,
      ADR3 => VCC,
      O => N44294_FROM
    );
  U1_enw_dispar1 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => enw1,
      ADR1 => enw2,
      ADR2 => U1_N30014,
      ADR3 => N44294,
      O => N44294_GROM
    );
  N44294_XUSED : X_BUF
    port map (
      I => N44294_FROM,
      O => N44294
    );
  N44294_YUSED : X_BUF
    port map (
      I => N44294_GROM,
      O => enw_dispar
    );
  U1_I66_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29937,
      ADR3 => U1_N30000,
      O => U1_I66_N1762_FROM
    );
  U1_I53_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N30000,
      ADR3 => U1_N30014,
      O => U1_I66_N1762_GROM
    );
  U1_I66_N1762_XUSED : X_BUF
    port map (
      I => U1_I66_N1762_FROM,
      O => U1_I66_N1762
    );
  U1_I66_N1762_YUSED : X_BUF
    port map (
      I => U1_I66_N1762_GROM,
      O => U1_I53_N1762
    );
  U1_n00771 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => U1_N30021,
      ADR1 => U1_N29954,
      ADR2 => add_1_IBUF,
      ADR3 => add_0_IBUF,
      O => U1_paf_reg_5_FROM
    );
  U1_Mmux_n0014_Result_5_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => U1_n0077,
      ADR1 => N44094,
      ADR2 => U1_paf_reg(5),
      ADR3 => paf_5_IBUF,
      O => U1_n0014(5)
    );
  U1_paf_reg_5_XUSED : X_BUF
    port map (
      I => U1_paf_reg_5_FROM,
      O => U1_n0077
    );
  U1_Ker300191 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => add_2_IBUF,
      ADR2 => add_5_IBUF,
      ADR3 => add_4_IBUF,
      O => U1_N30021_FROM
    );
  U1_n00121 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => U1_N29954,
      ADR1 => add_1_IBUF,
      ADR2 => add_0_IBUF,
      ADR3 => U1_N30021,
      O => U1_N30021_GROM
    );
  U1_N30021_XUSED : X_BUF
    port map (
      I => U1_N30021_FROM,
      O => U1_N30021
    );
  U1_N30021_YUSED : X_BUF
    port map (
      I => U1_N30021_GROM,
      O => U1_n0012
    );
  U3_Ker31534_SW1_SW0 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_state_FFd40,
      ADR1 => U3_sel_read(5),
      ADR2 => U1_dis_ffreg_mask,
      ADR3 => U3_state_FFd31,
      O => N44594_FROM
    );
  U3_Ker31534_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => N44255,
      ADR1 => U3_state_FFd39,
      ADR2 => U3_state_FFd25,
      ADR3 => N44594,
      O => N44594_GROM
    );
  N44594_XUSED : X_BUF
    port map (
      I => N44594_FROM,
      O => N44594
    );
  N44594_YUSED : X_BUF
    port map (
      I => N44594_GROM,
      O => N44340
    );
  spaf_SW0 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => paf_2_IBUF,
      ADR1 => paf_1_IBUF,
      ADR2 => paf_0_IBUF,
      ADR3 => VCC,
      O => N37936_FROM
    );
  spaf : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => paf_5_IBUF,
      ADR1 => paf_4_IBUF,
      ADR2 => paf_3_IBUF,
      ADR3 => N37936,
      O => N37936_GROM
    );
  N37936_XUSED : X_BUF
    port map (
      I => N37936_FROM,
      O => N37936
    );
  N37936_YUSED : X_BUF
    port map (
      I => N37936_GROM,
      O => spaf_p_OBUF
    );
  U3_n0102_5_15 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd17,
      ADR1 => evid_5_IBUF,
      ADR2 => U3_state_FFd18,
      ADR3 => U3_state_FFd7,
      O => CHOICE629_FROM
    );
  U3_Ker315023 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd1,
      ADR1 => U3_state_FFd37,
      ADR2 => U3_state_FFd18,
      ADR3 => VCC,
      O => CHOICE629_GROM
    );
  CHOICE629_XUSED : X_BUF
    port map (
      I => CHOICE629_FROM,
      O => CHOICE629
    );
  CHOICE629_YUSED : X_BUF
    port map (
      I => CHOICE629_GROM,
      O => CHOICE561
    );
  U3_Ker31507_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd19,
      ADR1 => U3_state_FFd14,
      ADR2 => U3_state_FFd36,
      ADR3 => U3_state_FFd18,
      O => N40761_FROM
    );
  U3_Ker31507 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31827,
      ADR1 => U3_state_FFd11,
      ADR2 => U3_state_FFd7,
      ADR3 => N40761,
      O => N40761_GROM
    );
  N40761_XUSED : X_BUF
    port map (
      I => N40761_FROM,
      O => N40761
    );
  N40761_YUSED : X_BUF
    port map (
      I => N40761_GROM,
      O => U3_N31509
    );
  U3_Ker316341 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U3_state_FFd30,
      ADR2 => U3_state_FFd2,
      ADR3 => U3_state_FFd1,
      O => U3_N31636_FROM
    );
  U3_n0102_0_81 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE944,
      ADR1 => CHOICE931,
      ADR2 => N44375,
      ADR3 => U3_N31636,
      O => U3_N31636_GROM
    );
  U3_N31636_XUSED : X_BUF
    port map (
      I => U3_N31636_FROM,
      O => U3_N31636
    );
  U3_N31636_YUSED : X_BUF
    port map (
      I => U3_N31636_GROM,
      O => CHOICE945
    );
  U3_n0102_15_47 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => U3_state_FFd13,
      ADR1 => U3_state_FFd5,
      ADR2 => U3_fmt_error_ff_2_3_Q,
      ADR3 => U3_state_FFd10,
      O => CHOICE837_FROM
    );
  U3_Ker316191 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_n0050,
      ADR1 => U1_dis_maxw_mask,
      ADR2 => U3_state_FFd10,
      ADR3 => VCC,
      O => CHOICE837_GROM
    );
  CHOICE837_XUSED : X_BUF
    port map (
      I => CHOICE837_FROM,
      O => CHOICE837
    );
  CHOICE837_YUSED : X_BUF
    port map (
      I => CHOICE837_GROM,
      O => U3_N31621
    );
  U3_Ker31654_SW2 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd17,
      ADR1 => U3_state_FFd40,
      ADR2 => U3_state_FFd31,
      ADR3 => VCC,
      O => N44282_FROM
    );
  U3_n0096_3_6 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => ceros_id_0_IBUF,
      ADR1 => ceros_id_1_IBUF,
      ADR2 => U3_state_FFd40,
      ADR3 => VCC,
      O => N44282_GROM
    );
  N44282_XUSED : X_BUF
    port map (
      I => N44282_FROM,
      O => N44282
    );
  N44282_YUSED : X_BUF
    port map (
      I => N44282_GROM,
      O => CHOICE954
    );
  U3_Ker317471 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd12,
      ADR1 => U3_state_FFd8,
      ADR2 => U3_state_FFd4,
      ADR3 => U3_state_FFd3,
      O => U3_N31749_FROM
    );
  U3_n009817 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd29,
      ADR1 => U3_state_FFd27,
      ADR2 => U3_N31749,
      ADR3 => VCC,
      O => U3_N31749_GROM
    );
  U3_N31749_XUSED : X_BUF
    port map (
      I => U3_N31749_FROM,
      O => U3_N31749
    );
  U3_N31749_YUSED : X_BUF
    port map (
      I => U3_N31749_GROM,
      O => CHOICE480
    );
  U3_Ker316921 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd20,
      ADR1 => U3_state_FFd24,
      ADR2 => U3_state_FFd21,
      ADR3 => VCC,
      O => U3_N31694_FROM
    );
  U3_state_FFd28_In5 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31694,
      ADR1 => U3_state_FFd26,
      ADR2 => U3_state_FFd4,
      ADR3 => U3_state_FFd32,
      O => U3_N31694_GROM
    );
  U3_N31694_XUSED : X_BUF
    port map (
      I => U3_N31694_FROM,
      O => U3_N31694
    );
  U3_N31694_YUSED : X_BUF
    port map (
      I => U3_N31694_GROM,
      O => CHOICE273
    );
  U3_state_FFd33_In_SW0 : X_LUT4
    generic map(
      INIT => X"FFFB"
    )
    port map (
      ADR0 => U3_this_ff,
      ADR1 => U3_state_FFd39,
      ADR2 => U3_this_dontread,
      ADR3 => U1_dis_paf_warn,
      O => U3_state_FFd33_FROM
    );
  U3_state_FFd33_In_362 : X_LUT4
    generic map(
      INIT => X"0C5D"
    )
    port map (
      ADR0 => U3_this_paf,
      ADR1 => U3_state_FFd33,
      ADR2 => tp_2_OBUF,
      ADR3 => N40608,
      O => U3_state_FFd33_In
    );
  U3_state_FFd33_XUSED : X_BUF
    port map (
      I => U3_state_FFd33_FROM,
      O => N40608
    );
  U3_state_FFd33_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd33_SRMUX_OUTPUTNOT
    );
  U3_Ker319381 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U1_dis_ffreg_mask,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N31940_FROM
    );
  U3_n01105 : X_LUT4
    generic map(
      INIT => X"A800"
    )
    port map (
      ADR0 => U3_sel_read(5),
      ADR1 => U3_n0216,
      ADR2 => U3_N31940,
      ADR3 => U3_sel_read(0),
      O => U3_N31940_GROM
    );
  U3_N31940_XUSED : X_BUF
    port map (
      I => U3_N31940_FROM,
      O => U3_N31940
    );
  U3_N31940_YUSED : X_BUF
    port map (
      I => U3_N31940_GROM,
      O => CHOICE659
    );
  U3_Ker318981 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => U3_state_FFd29,
      ADR1 => CHOICE683,
      ADR2 => CHOICE686,
      ADR3 => CHOICE689,
      O => U3_N31900_GROM
    );
  U3_N31900_YUSED : X_BUF
    port map (
      I => U3_N31900_GROM,
      O => U3_N31900
    );
  U1_I58_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I58_10 : X_TRI
    port map (
      I => U1_fout_reg(5),
      CTL => U1_I58_10_TINV,
      O => db_out(5)
    );
  U1_I58_10_TINV_363 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_10_TINV
    );
  U1_I61_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I61_9 : X_TRI
    port map (
      I => U1_paf_counter_2(6),
      CTL => U1_I61_9_TINV,
      O => db_out(6)
    );
  U1_I61_9_TINV_364 : X_INV
    port map (
      I => U1_I61_N1762,
      O => U1_I61_9_TINV
    );
  U1_I62_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I62_5 : X_TRI
    port map (
      I => U1_paf_counter_3(10),
      CTL => U1_I62_5_TINV,
      O => db_out(10)
    );
  U1_I62_5_TINV_365 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_5_TINV
    );
  U1_I63_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I63_1 : X_TRI
    port map (
      I => U1_paf_counter_4(14),
      CTL => U1_I63_1_TINV,
      O => db_out(14)
    );
  U1_I63_1_TINV_366 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_1_TINV
    );
  U1_I66_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I66_10 : X_TRI
    port map (
      I => U1_db_error2(5),
      CTL => U1_I66_10_TINV,
      O => db_out(5)
    );
  U1_I66_10_TINV_367 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_10_TINV
    );
  U1_I46_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I46_6 : X_TRI
    port map (
      I => U1_paf_reg(3),
      CTL => U1_I46_6_TINV,
      O => db_out(9)
    );
  U1_I46_6_TINV_368 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_6_TINV
    );
  U1_I47_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I47_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I47_2_TINV,
      O => db_out(13)
    );
  U1_I47_2_TINV_369 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_2_TINV
    );
  U1_I54_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I54_6 : X_TRI
    port map (
      I => U1_timeout_value(9),
      CTL => U1_I54_6_TINV,
      O => db_out(9)
    );
  U1_I54_6_TINV_370 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_6_TINV
    );
  U1_I55_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I55_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_2_TINV,
      O => db_out(13)
    );
  U1_I55_2_TINV_371 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_2_TINV
    );
  U1_I58_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I58_11 : X_TRI
    port map (
      I => U1_fout_reg(4),
      CTL => U1_I58_11_TINV,
      O => db_out(4)
    );
  U1_I58_11_TINV_372 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_11_TINV
    );
  U1_I62_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I62_6 : X_TRI
    port map (
      I => U1_paf_counter_3(9),
      CTL => U1_I62_6_TINV,
      O => db_out(9)
    );
  U1_I62_6_TINV_373 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_6_TINV
    );
  U1_I63_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I63_2 : X_TRI
    port map (
      I => U1_paf_counter_4(13),
      CTL => U1_I63_2_TINV,
      O => db_out(13)
    );
  U1_I63_2_TINV_374 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_2_TINV
    );
  U1_I66_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I66_11 : X_TRI
    port map (
      I => U1_db_error2(4),
      CTL => U1_I66_11_TINV,
      O => db_out(4)
    );
  U1_I66_11_TINV_375 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_11_TINV
    );
  U1_I46_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I46_7 : X_TRI
    port map (
      I => U1_paf_reg(2),
      CTL => U1_I46_7_TINV,
      O => db_out(8)
    );
  U1_I46_7_TINV_376 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_7_TINV
    );
  U1_I47_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I47_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I47_3_TINV,
      O => db_out(12)
    );
  U1_I47_3_TINV_377 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_3_TINV
    );
  U1_I54_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I54_7 : X_TRI
    port map (
      I => U1_timeout_value(8),
      CTL => U1_I54_7_TINV,
      O => db_out(8)
    );
  U1_I54_7_TINV_378 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_7_TINV
    );
  U1_I55_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I55_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_3_TINV,
      O => db_out(12)
    );
  U1_I55_3_TINV_379 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_3_TINV
    );
  U1_I58_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I58_12 : X_TRI
    port map (
      I => U1_fout_reg(3),
      CTL => U1_I58_12_TINV,
      O => db_out(3)
    );
  U1_I58_12_TINV_380 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_12_TINV
    );
  U1_I62_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I62_7 : X_TRI
    port map (
      I => U1_paf_counter_3(8),
      CTL => U1_I62_7_TINV,
      O => db_out(8)
    );
  U1_I62_7_TINV_381 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_7_TINV
    );
  U1_I63_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I63_3 : X_TRI
    port map (
      I => U1_paf_counter_4(12),
      CTL => U1_I63_3_TINV,
      O => db_out(12)
    );
  U1_I63_3_TINV_382 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_3_TINV
    );
  U1_I66_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I66_12 : X_TRI
    port map (
      I => U1_db_error2(3),
      CTL => U1_I66_12_TINV,
      O => db_out(3)
    );
  U1_I66_12_TINV_383 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_12_TINV
    );
  U1_I46_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I46_8 : X_TRI
    port map (
      I => U1_paf_reg(1),
      CTL => U1_I46_8_TINV,
      O => db_out(7)
    );
  U1_I46_8_TINV_384 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_8_TINV
    );
  U1_I47_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I47_4 : X_TRI
    port map (
      I => U3_evid_mis(5),
      CTL => U1_I47_4_TINV,
      O => db_out(11)
    );
  U1_I47_4_TINV_385 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_4_TINV
    );
  U1_I54_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I54_8 : X_TRI
    port map (
      I => U1_timeout_value(7),
      CTL => U1_I54_8_TINV,
      O => db_out(7)
    );
  U1_I54_8_TINV_386 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_8_TINV
    );
  U1_I55_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I55_4 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_4_TINV,
      O => db_out(11)
    );
  U1_I55_4_TINV_387 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_4_TINV
    );
  U1_I58_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I58_13 : X_TRI
    port map (
      I => U1_fout_reg(2),
      CTL => U1_I58_13_TINV,
      O => db_out(2)
    );
  U1_I58_13_TINV_388 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_13_TINV
    );
  U1_I62_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I62_8 : X_TRI
    port map (
      I => U1_paf_counter_3(7),
      CTL => U1_I62_8_TINV,
      O => db_out(7)
    );
  U1_I62_8_TINV_389 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_8_TINV
    );
  U1_I63_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I63_4 : X_TRI
    port map (
      I => U1_paf_counter_4(11),
      CTL => U1_I63_4_TINV,
      O => db_out(11)
    );
  U1_I63_4_TINV_390 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_4_TINV
    );
  U1_I66_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I66_13 : X_TRI
    port map (
      I => U1_db_error2(2),
      CTL => U1_I66_13_TINV,
      O => db_out(2)
    );
  U1_I66_13_TINV_391 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_13_TINV
    );
  U1_I48_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I48_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I48_0_TINV,
      O => db_out(15)
    );
  U1_I48_0_TINV_392 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_0_TINV
    );
  U1_I56_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I56_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_0_TINV,
      O => db_out(15)
    );
  U1_I56_0_TINV_393 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_0_TINV
    );
  U1_I64_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I64_0 : X_TRI
    port map (
      I => U1_paf_counter_5(15),
      CTL => U1_I64_0_TINV,
      O => db_out(15)
    );
  U1_I64_0_TINV_394 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_0_TINV
    );
  U1_I46_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I46_9 : X_TRI
    port map (
      I => U1_paf_reg(0),
      CTL => U1_I46_9_TINV,
      O => db_out(6)
    );
  U1_I46_9_TINV_395 : X_INV
    port map (
      I => U1_I46_N1762,
      O => U1_I46_9_TINV
    );
  U1_I47_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I47_5 : X_TRI
    port map (
      I => U3_evid_mis(4),
      CTL => U1_I47_5_TINV,
      O => db_out(10)
    );
  U1_I47_5_TINV_396 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_5_TINV
    );
  U1_I48_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I48_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I48_1_TINV,
      O => db_out(14)
    );
  U1_I48_1_TINV_397 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_1_TINV
    );
  U1_I54_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I54_9 : X_TRI
    port map (
      I => U1_timeout_value(6),
      CTL => U1_I54_9_TINV,
      O => db_out(6)
    );
  U1_I54_9_TINV_398 : X_INV
    port map (
      I => U1_I54_N1762,
      O => U1_I54_9_TINV
    );
  U1_I55_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I55_5 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_5_TINV,
      O => db_out(10)
    );
  U1_I55_5_TINV_399 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_5_TINV
    );
  U1_I56_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I56_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_1_TINV,
      O => db_out(14)
    );
  U1_I56_1_TINV_400 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_1_TINV
    );
  U1_I58_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I58_14 : X_TRI
    port map (
      I => U1_fout_reg(1),
      CTL => U1_I58_14_TINV,
      O => db_out(1)
    );
  U1_I58_14_TINV_401 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_14_TINV
    );
  U1_I62_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I62_9 : X_TRI
    port map (
      I => U1_paf_counter_3(6),
      CTL => U1_I62_9_TINV,
      O => db_out(6)
    );
  U1_I62_9_TINV_402 : X_INV
    port map (
      I => U1_I62_N1762,
      O => U1_I62_9_TINV
    );
  U1_I63_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I63_5 : X_TRI
    port map (
      I => U1_paf_counter_4(10),
      CTL => U1_I63_5_TINV,
      O => db_out(10)
    );
  U1_I63_5_TINV_403 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_5_TINV
    );
  U1_I64_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I64_1 : X_TRI
    port map (
      I => U1_paf_counter_5(14),
      CTL => U1_I64_1_TINV,
      O => db_out(14)
    );
  U1_I64_1_TINV_404 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_1_TINV
    );
  U1_I66_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I66_14 : X_TRI
    port map (
      I => U1_db_error2(1),
      CTL => U1_I66_14_TINV,
      O => db_out(1)
    );
  U1_I66_14_TINV_405 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_14_TINV
    );
  U1_I47_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I47_6 : X_TRI
    port map (
      I => U3_evid_mis(3),
      CTL => U1_I47_6_TINV,
      O => db_out(9)
    );
  U1_I47_6_TINV_406 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_6_TINV
    );
  U1_I48_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I48_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I48_2_TINV,
      O => db_out(13)
    );
  U1_I48_2_TINV_407 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_2_TINV
    );
  U1_I55_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I55_6 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_6_TINV,
      O => db_out(9)
    );
  U1_I55_6_TINV_408 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_6_TINV
    );
  U1_I56_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I56_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_2_TINV,
      O => db_out(13)
    );
  U1_I56_2_TINV_409 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_2_TINV
    );
  U1_I58_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I58_15 : X_TRI
    port map (
      I => U1_fout_reg(0),
      CTL => U1_I58_15_TINV,
      O => db_out(0)
    );
  U1_I58_15_TINV_410 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_15_TINV
    );
  U1_I63_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I63_6 : X_TRI
    port map (
      I => U1_paf_counter_4(9),
      CTL => U1_I63_6_TINV,
      O => db_out(9)
    );
  U1_I63_6_TINV_411 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_6_TINV
    );
  U1_I64_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I64_2 : X_TRI
    port map (
      I => U1_paf_counter_5(13),
      CTL => U1_I64_2_TINV,
      O => db_out(13)
    );
  U1_I64_2_TINV_412 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_2_TINV
    );
  U1_I66_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I66_15 : X_TRI
    port map (
      I => U1_db_error2(0),
      CTL => U1_I66_15_TINV,
      O => db_out(0)
    );
  U1_I66_15_TINV_413 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_15_TINV
    );
  U1_I47_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I47_7 : X_TRI
    port map (
      I => U3_evid_mis(2),
      CTL => U1_I47_7_TINV,
      O => db_out(8)
    );
  U1_I47_7_TINV_414 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_7_TINV
    );
  U1_I48_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I48_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I48_3_TINV,
      O => db_out(12)
    );
  U1_I48_3_TINV_415 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_3_TINV
    );
  U1_I55_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I55_7 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I55_7_TINV,
      O => db_out(8)
    );
  U1_I55_7_TINV_416 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_7_TINV
    );
  U1_I56_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I56_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_3_TINV,
      O => db_out(12)
    );
  U1_I56_3_TINV_417 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_3_TINV
    );
  U1_I63_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I63_7 : X_TRI
    port map (
      I => U1_paf_counter_4(8),
      CTL => U1_I63_7_TINV,
      O => db_out(8)
    );
  U1_I63_7_TINV_418 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_7_TINV
    );
  U1_I64_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I64_3 : X_TRI
    port map (
      I => U1_paf_counter_5(12),
      CTL => U1_I64_3_TINV,
      O => db_out(12)
    );
  U1_I64_3_TINV_419 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_3_TINV
    );
  U1_I47_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I47_8 : X_TRI
    port map (
      I => U3_evid_mis(1),
      CTL => U1_I47_8_TINV,
      O => db_out(7)
    );
  U1_I47_8_TINV_420 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_8_TINV
    );
  U1_I48_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I48_4 : X_TRI
    port map (
      I => U1_ff_reg(5),
      CTL => U1_I48_4_TINV,
      O => db_out(11)
    );
  U1_I48_4_TINV_421 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_4_TINV
    );
  U1_I55_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I55_8 : X_TRI
    port map (
      I => U1_nmaxwords(7),
      CTL => U1_I55_8_TINV,
      O => db_out(7)
    );
  U1_I55_8_TINV_422 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_8_TINV
    );
  U1_I56_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I56_4 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_4_TINV,
      O => db_out(11)
    );
  U1_I56_4_TINV_423 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_4_TINV
    );
  U1_I63_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I63_8 : X_TRI
    port map (
      I => U1_paf_counter_4(7),
      CTL => U1_I63_8_TINV,
      O => db_out(7)
    );
  U1_I63_8_TINV_424 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_8_TINV
    );
  U1_I64_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I64_4 : X_TRI
    port map (
      I => U1_paf_counter_5(11),
      CTL => U1_I64_4_TINV,
      O => db_out(11)
    );
  U1_I64_4_TINV_425 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_4_TINV
    );
  U1_I49_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I49_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I49_0_TINV,
      O => db_out(15)
    );
  U1_I49_0_TINV_426 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_0_TINV
    );
  U1_I57_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I57_0 : X_TRI
    port map (
      I => U1_fout_reg(15),
      CTL => U1_I57_0_TINV,
      O => db_out(15)
    );
  U1_I57_0_TINV_427 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_0_TINV
    );
  U1_I65_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I65_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I65_0_TINV,
      O => db_out(15)
    );
  U1_I65_0_TINV_428 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_0_TINV
    );
  U1_I47_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I47_9 : X_TRI
    port map (
      I => U3_evid_mis(0),
      CTL => U1_I47_9_TINV,
      O => db_out(6)
    );
  U1_I47_9_TINV_429 : X_INV
    port map (
      I => U1_I47_N1762,
      O => U1_I47_9_TINV
    );
  U1_I48_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I48_5 : X_TRI
    port map (
      I => U1_ff_reg(4),
      CTL => U1_I48_5_TINV,
      O => db_out(10)
    );
  U1_I48_5_TINV_430 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_5_TINV
    );
  U1_I49_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I49_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I49_1_TINV,
      O => db_out(14)
    );
  U1_I49_1_TINV_431 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_1_TINV
    );
  U1_I55_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I55_9 : X_TRI
    port map (
      I => U1_nmaxwords(6),
      CTL => U1_I55_9_TINV,
      O => db_out(6)
    );
  U1_I55_9_TINV_432 : X_INV
    port map (
      I => U1_I55_N1762,
      O => U1_I55_9_TINV
    );
  U1_I56_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I56_5 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_5_TINV,
      O => db_out(10)
    );
  U1_I56_5_TINV_433 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_5_TINV
    );
  U1_I57_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I57_1 : X_TRI
    port map (
      I => U1_fout_reg(14),
      CTL => U1_I57_1_TINV,
      O => db_out(14)
    );
  U1_I57_1_TINV_434 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_1_TINV
    );
  U1_I59_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I59_10 : X_TRI
    port map (
      I => U1_paf_counter_0(5),
      CTL => U1_I59_10_TINV,
      O => db_out(5)
    );
  U1_I59_10_TINV_435 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_10_TINV
    );
  U1_I63_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I63_9 : X_TRI
    port map (
      I => U1_paf_counter_4(6),
      CTL => U1_I63_9_TINV,
      O => db_out(6)
    );
  U1_I63_9_TINV_436 : X_INV
    port map (
      I => U1_I63_N1762,
      O => U1_I63_9_TINV
    );
  U1_I64_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I64_5 : X_TRI
    port map (
      I => U1_paf_counter_5(10),
      CTL => U1_I64_5_TINV,
      O => db_out(10)
    );
  U1_I64_5_TINV_437 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_5_TINV
    );
  U1_I65_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I65_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I65_1_TINV,
      O => db_out(14)
    );
  U1_I65_1_TINV_438 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_1_TINV
    );
  U1_I67_10_PULLUP : X_PU
    port map (
      O => db_out(5)
    );
  U1_I67_10 : X_TRI
    port map (
      I => U1_db_error3(5),
      CTL => U1_I67_10_TINV,
      O => db_out(5)
    );
  U1_I67_10_TINV_439 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_10_TINV
    );
  U1_I48_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I48_6 : X_TRI
    port map (
      I => U1_ff_reg(3),
      CTL => U1_I48_6_TINV,
      O => db_out(9)
    );
  U1_I48_6_TINV_440 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_6_TINV
    );
  U1_I49_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I49_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I49_2_TINV,
      O => db_out(13)
    );
  U1_I49_2_TINV_441 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_2_TINV
    );
  U1_I56_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I56_6 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_6_TINV,
      O => db_out(9)
    );
  U1_I56_6_TINV_442 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_6_TINV
    );
  U1_I57_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I57_2 : X_TRI
    port map (
      I => U1_fout_reg(13),
      CTL => U1_I57_2_TINV,
      O => db_out(13)
    );
  U1_I57_2_TINV_443 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_2_TINV
    );
  U1_I59_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I59_11 : X_TRI
    port map (
      I => U1_paf_counter_0(4),
      CTL => U1_I59_11_TINV,
      O => db_out(4)
    );
  U1_I59_11_TINV_444 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_11_TINV
    );
  U1_I64_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I64_6 : X_TRI
    port map (
      I => U1_paf_counter_5(9),
      CTL => U1_I64_6_TINV,
      O => db_out(9)
    );
  U1_I64_6_TINV_445 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_6_TINV
    );
  U1_I65_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I65_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I65_2_TINV,
      O => db_out(13)
    );
  U1_I65_2_TINV_446 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_2_TINV
    );
  U1_I67_11_PULLUP : X_PU
    port map (
      O => db_out(4)
    );
  U1_I67_11 : X_TRI
    port map (
      I => U1_db_error3(4),
      CTL => U1_I67_11_TINV,
      O => db_out(4)
    );
  U1_I67_11_TINV_447 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_11_TINV
    );
  U1_I48_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I48_7 : X_TRI
    port map (
      I => U1_ff_reg(2),
      CTL => U1_I48_7_TINV,
      O => db_out(8)
    );
  U1_I48_7_TINV_448 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_7_TINV
    );
  U1_I49_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I49_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I49_3_TINV,
      O => db_out(12)
    );
  U1_I49_3_TINV_449 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_3_TINV
    );
  U1_I56_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I56_7 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_7_TINV,
      O => db_out(8)
    );
  U1_I56_7_TINV_450 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_7_TINV
    );
  U1_I57_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I57_3 : X_TRI
    port map (
      I => U1_fout_reg(12),
      CTL => U1_I57_3_TINV,
      O => db_out(12)
    );
  U1_I57_3_TINV_451 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_3_TINV
    );
  U1_I59_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I59_12 : X_TRI
    port map (
      I => U1_paf_counter_0(3),
      CTL => U1_I59_12_TINV,
      O => db_out(3)
    );
  U1_I59_12_TINV_452 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_12_TINV
    );
  U1_I64_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I64_7 : X_TRI
    port map (
      I => U1_paf_counter_5(8),
      CTL => U1_I64_7_TINV,
      O => db_out(8)
    );
  U1_I64_7_TINV_453 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_7_TINV
    );
  U1_I65_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I65_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I65_3_TINV,
      O => db_out(12)
    );
  U1_I65_3_TINV_454 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_3_TINV
    );
  U1_I67_12_PULLUP : X_PU
    port map (
      O => db_out(3)
    );
  U1_I67_12 : X_TRI
    port map (
      I => U1_db_error3(3),
      CTL => U1_I67_12_TINV,
      O => db_out(3)
    );
  U1_I67_12_TINV_455 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_12_TINV
    );
  U1_I48_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I48_8 : X_TRI
    port map (
      I => U1_ff_reg(1),
      CTL => U1_I48_8_TINV,
      O => db_out(7)
    );
  U1_I48_8_TINV_456 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_8_TINV
    );
  U1_I49_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I49_4 : X_TRI
    port map (
      I => U1_recoff,
      CTL => U1_I49_4_TINV,
      O => db_out(11)
    );
  U1_I49_4_TINV_457 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_4_TINV
    );
  U1_I56_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I56_8 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_8_TINV,
      O => db_out(7)
    );
  U1_I56_8_TINV_458 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_8_TINV
    );
  U1_I57_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I57_4 : X_TRI
    port map (
      I => U1_fout_reg(11),
      CTL => U1_I57_4_TINV,
      O => db_out(11)
    );
  U1_I57_4_TINV_459 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_4_TINV
    );
  U1_I59_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I59_13 : X_TRI
    port map (
      I => U1_paf_counter_0(2),
      CTL => U1_I59_13_TINV,
      O => db_out(2)
    );
  U1_I59_13_TINV_460 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_13_TINV
    );
  U1_I64_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I64_8 : X_TRI
    port map (
      I => U1_paf_counter_5(7),
      CTL => U1_I64_8_TINV,
      O => db_out(7)
    );
  U1_I64_8_TINV_461 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_8_TINV
    );
  U1_I65_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I65_4 : X_TRI
    port map (
      I => U1_db_error1(11),
      CTL => U1_I65_4_TINV,
      O => db_out(11)
    );
  U1_I65_4_TINV_462 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_4_TINV
    );
  U1_I67_13_PULLUP : X_PU
    port map (
      O => db_out(2)
    );
  U1_I67_13 : X_TRI
    port map (
      I => U1_db_error3(2),
      CTL => U1_I67_13_TINV,
      O => db_out(2)
    );
  U1_I67_13_TINV_463 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_13_TINV
    );
  U1_I58_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I58_0 : X_TRI
    port map (
      I => U1_fout_reg(15),
      CTL => U1_I58_0_TINV,
      O => db_out(15)
    );
  U1_I58_0_TINV_464 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_0_TINV
    );
  U1_I66_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I66_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I66_0_TINV,
      O => db_out(15)
    );
  U1_I66_0_TINV_465 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_0_TINV
    );
  U1_I48_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I48_9 : X_TRI
    port map (
      I => U1_ff_reg(0),
      CTL => U1_I48_9_TINV,
      O => db_out(6)
    );
  U1_I48_9_TINV_466 : X_INV
    port map (
      I => U1_I48_N1762,
      O => U1_I48_9_TINV
    );
  U1_I49_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I49_5 : X_TRI
    port map (
      I => U2_pae_paf_reg(10),
      CTL => U1_I49_5_TINV,
      O => db_out(10)
    );
  U1_I49_5_TINV_467 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_5_TINV
    );
  U1_I56_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I56_9 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I56_9_TINV,
      O => db_out(6)
    );
  U1_I56_9_TINV_468 : X_INV
    port map (
      I => U1_I56_N1762,
      O => U1_I56_9_TINV
    );
  U1_I57_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I57_5 : X_TRI
    port map (
      I => U1_fout_reg(10),
      CTL => U1_I57_5_TINV,
      O => db_out(10)
    );
  U1_I57_5_TINV_469 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_5_TINV
    );
  U1_I58_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I58_1 : X_TRI
    port map (
      I => U1_fout_reg(14),
      CTL => U1_I58_1_TINV,
      O => db_out(14)
    );
  U1_I58_1_TINV_470 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_1_TINV
    );
  U1_I59_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I59_14 : X_TRI
    port map (
      I => U1_paf_counter_0(1),
      CTL => U1_I59_14_TINV,
      O => db_out(1)
    );
  U1_I59_14_TINV_471 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_14_TINV
    );
  U1_I64_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I64_9 : X_TRI
    port map (
      I => U1_paf_counter_5(6),
      CTL => U1_I64_9_TINV,
      O => db_out(6)
    );
  U1_I64_9_TINV_472 : X_INV
    port map (
      I => U1_I64_N1762,
      O => U1_I64_9_TINV
    );
  U1_I65_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I65_5 : X_TRI
    port map (
      I => U1_db_error1(10),
      CTL => U1_I65_5_TINV,
      O => db_out(10)
    );
  U1_I65_5_TINV_473 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_5_TINV
    );
  U1_I66_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I66_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I66_1_TINV,
      O => db_out(14)
    );
  U1_I66_1_TINV_474 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_1_TINV
    );
  U1_I67_14_PULLUP : X_PU
    port map (
      O => db_out(1)
    );
  U1_I67_14 : X_TRI
    port map (
      I => U1_db_error3(1),
      CTL => U1_I67_14_TINV,
      O => db_out(1)
    );
  U1_I67_14_TINV_475 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_14_TINV
    );
  U1_I49_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I49_6 : X_TRI
    port map (
      I => U2_pae_paf_reg(9),
      CTL => U1_I49_6_TINV,
      O => db_out(9)
    );
  U1_I49_6_TINV_476 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_6_TINV
    );
  U1_I57_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I57_6 : X_TRI
    port map (
      I => U1_fout_reg(9),
      CTL => U1_I57_6_TINV,
      O => db_out(9)
    );
  U1_I57_6_TINV_477 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_6_TINV
    );
  U1_I58_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I58_2 : X_TRI
    port map (
      I => U1_fout_reg(13),
      CTL => U1_I58_2_TINV,
      O => db_out(13)
    );
  U1_I58_2_TINV_478 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_2_TINV
    );
  U1_I59_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I59_15 : X_TRI
    port map (
      I => U1_paf_counter_0(0),
      CTL => U1_I59_15_TINV,
      O => db_out(0)
    );
  U1_I59_15_TINV_479 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_15_TINV
    );
  U1_I65_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I65_6 : X_TRI
    port map (
      I => U1_db_error1(9),
      CTL => U1_I65_6_TINV,
      O => db_out(9)
    );
  U1_I65_6_TINV_480 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_6_TINV
    );
  U1_I66_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I66_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I66_2_TINV,
      O => db_out(13)
    );
  U1_I66_2_TINV_481 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_2_TINV
    );
  U1_I67_15_PULLUP : X_PU
    port map (
      O => db_out(0)
    );
  U1_I67_15 : X_TRI
    port map (
      I => U1_db_error3(0),
      CTL => U1_I67_15_TINV,
      O => db_out(0)
    );
  U1_I67_15_TINV_482 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_15_TINV
    );
  U1_I49_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I49_7 : X_TRI
    port map (
      I => U2_pae_paf_reg(8),
      CTL => U1_I49_7_TINV,
      O => db_out(8)
    );
  U1_I49_7_TINV_483 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_7_TINV
    );
  U1_I57_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I57_7 : X_TRI
    port map (
      I => U1_fout_reg(8),
      CTL => U1_I57_7_TINV,
      O => db_out(8)
    );
  U1_I57_7_TINV_484 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_7_TINV
    );
  U1_I58_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I58_3 : X_TRI
    port map (
      I => U1_fout_reg(12),
      CTL => U1_I58_3_TINV,
      O => db_out(12)
    );
  U1_I58_3_TINV_485 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_3_TINV
    );
  U1_I65_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I65_7 : X_TRI
    port map (
      I => U1_db_error1(8),
      CTL => U1_I65_7_TINV,
      O => db_out(8)
    );
  U1_I65_7_TINV_486 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_7_TINV
    );
  U1_I66_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I66_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I66_3_TINV,
      O => db_out(12)
    );
  U1_I66_3_TINV_487 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_3_TINV
    );
  U1_I49_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I49_8 : X_TRI
    port map (
      I => U2_pae_paf_reg(7),
      CTL => U1_I49_8_TINV,
      O => db_out(7)
    );
  U1_I49_8_TINV_488 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_8_TINV
    );
  U1_I57_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I57_8 : X_TRI
    port map (
      I => U1_fout_reg(7),
      CTL => U1_I57_8_TINV,
      O => db_out(7)
    );
  U1_I57_8_TINV_489 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_8_TINV
    );
  U1_I58_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I58_4 : X_TRI
    port map (
      I => U1_fout_reg(11),
      CTL => U1_I58_4_TINV,
      O => db_out(11)
    );
  U1_I58_4_TINV_490 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_4_TINV
    );
  U1_I65_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I65_8 : X_TRI
    port map (
      I => U1_db_error1(7),
      CTL => U1_I65_8_TINV,
      O => db_out(7)
    );
  U1_I65_8_TINV_491 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_8_TINV
    );
  U1_I66_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I66_4 : X_TRI
    port map (
      I => U1_db_error2(11),
      CTL => U1_I66_4_TINV,
      O => db_out(11)
    );
  U1_I66_4_TINV_492 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_4_TINV
    );
  U1_I59_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I59_0 : X_TRI
    port map (
      I => U1_paf_counter_0(15),
      CTL => U1_I59_0_TINV,
      O => db_out(15)
    );
  U1_I59_0_TINV_493 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_0_TINV
    );
  U1_I67_0_PULLUP : X_PU
    port map (
      O => db_out(15)
    );
  U1_I67_0 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I67_0_TINV,
      O => db_out(15)
    );
  U1_I67_0_TINV_494 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_0_TINV
    );
  U1_I49_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I49_9 : X_TRI
    port map (
      I => U2_pae_paf_reg(6),
      CTL => U1_I49_9_TINV,
      O => db_out(6)
    );
  U1_I49_9_TINV_495 : X_INV
    port map (
      I => U1_I49_N1762,
      O => U1_I49_9_TINV
    );
  U1_I57_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I57_9 : X_TRI
    port map (
      I => U1_fout_reg(6),
      CTL => U1_I57_9_TINV,
      O => db_out(6)
    );
  U1_I57_9_TINV_496 : X_INV
    port map (
      I => U1_I57_N1762,
      O => U1_I57_9_TINV
    );
  U1_I58_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I58_5 : X_TRI
    port map (
      I => U1_fout_reg(10),
      CTL => U1_I58_5_TINV,
      O => db_out(10)
    );
  U1_I58_5_TINV_497 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_5_TINV
    );
  U1_I59_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I59_1 : X_TRI
    port map (
      I => U1_paf_counter_0(14),
      CTL => U1_I59_1_TINV,
      O => db_out(14)
    );
  U1_I59_1_TINV_498 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_1_TINV
    );
  U1_I65_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I65_9 : X_TRI
    port map (
      I => U1_db_error1(6),
      CTL => U1_I65_9_TINV,
      O => db_out(6)
    );
  U1_I65_9_TINV_499 : X_INV
    port map (
      I => U1_I65_N1762,
      O => U1_I65_9_TINV
    );
  U1_I66_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I66_5 : X_TRI
    port map (
      I => U1_db_error2(10),
      CTL => U1_I66_5_TINV,
      O => db_out(10)
    );
  U1_I66_5_TINV_500 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_5_TINV
    );
  U1_I67_1_PULLUP : X_PU
    port map (
      O => db_out(14)
    );
  U1_I67_1 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I67_1_TINV,
      O => db_out(14)
    );
  U1_I67_1_TINV_501 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_1_TINV
    );
  U1_I58_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I58_6 : X_TRI
    port map (
      I => U1_fout_reg(9),
      CTL => U1_I58_6_TINV,
      O => db_out(9)
    );
  U1_I58_6_TINV_502 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_6_TINV
    );
  U1_I59_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I59_2 : X_TRI
    port map (
      I => U1_paf_counter_0(13),
      CTL => U1_I59_2_TINV,
      O => db_out(13)
    );
  U1_I59_2_TINV_503 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_2_TINV
    );
  U1_I66_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I66_6 : X_TRI
    port map (
      I => U1_db_error2(9),
      CTL => U1_I66_6_TINV,
      O => db_out(9)
    );
  U1_I66_6_TINV_504 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_6_TINV
    );
  U1_I67_2_PULLUP : X_PU
    port map (
      O => db_out(13)
    );
  U1_I67_2 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I67_2_TINV,
      O => db_out(13)
    );
  U1_I67_2_TINV_505 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_2_TINV
    );
  U1_I58_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I58_7 : X_TRI
    port map (
      I => U1_fout_reg(8),
      CTL => U1_I58_7_TINV,
      O => db_out(8)
    );
  U1_I58_7_TINV_506 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_7_TINV
    );
  U1_I59_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I59_3 : X_TRI
    port map (
      I => U1_paf_counter_0(12),
      CTL => U1_I59_3_TINV,
      O => db_out(12)
    );
  U1_I59_3_TINV_507 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_3_TINV
    );
  U1_I66_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I66_7 : X_TRI
    port map (
      I => U1_db_error2(8),
      CTL => U1_I66_7_TINV,
      O => db_out(8)
    );
  U1_I66_7_TINV_508 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_7_TINV
    );
  U1_I67_3_PULLUP : X_PU
    port map (
      O => db_out(12)
    );
  U1_I67_3 : X_TRI
    port map (
      I => GLOBAL_LOGIC0,
      CTL => U1_I67_3_TINV,
      O => db_out(12)
    );
  U1_I67_3_TINV_509 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_3_TINV
    );
  U1_I58_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I58_8 : X_TRI
    port map (
      I => U1_fout_reg(7),
      CTL => U1_I58_8_TINV,
      O => db_out(7)
    );
  U1_I58_8_TINV_510 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_8_TINV
    );
  U1_I59_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I59_4 : X_TRI
    port map (
      I => U1_paf_counter_0(11),
      CTL => U1_I59_4_TINV,
      O => db_out(11)
    );
  U1_I59_4_TINV_511 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_4_TINV
    );
  U1_I66_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I66_8 : X_TRI
    port map (
      I => U1_db_error2(7),
      CTL => U1_I66_8_TINV,
      O => db_out(7)
    );
  U1_I66_8_TINV_512 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_8_TINV
    );
  U1_I67_4_PULLUP : X_PU
    port map (
      O => db_out(11)
    );
  U1_I67_4 : X_TRI
    port map (
      I => U1_db_error3(11),
      CTL => U1_I67_4_TINV,
      O => db_out(11)
    );
  U1_I67_4_TINV_513 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_4_TINV
    );
  U1_I58_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I58_9 : X_TRI
    port map (
      I => U1_fout_reg(6),
      CTL => U1_I58_9_TINV,
      O => db_out(6)
    );
  U1_I58_9_TINV_514 : X_INV
    port map (
      I => U1_I58_N1762,
      O => U1_I58_9_TINV
    );
  U1_I59_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I59_5 : X_TRI
    port map (
      I => U1_paf_counter_0(10),
      CTL => U1_I59_5_TINV,
      O => db_out(10)
    );
  U1_I59_5_TINV_515 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_5_TINV
    );
  U1_I66_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I66_9 : X_TRI
    port map (
      I => U1_db_error2(6),
      CTL => U1_I66_9_TINV,
      O => db_out(6)
    );
  U1_I66_9_TINV_516 : X_INV
    port map (
      I => U1_I66_N1762,
      O => U1_I66_9_TINV
    );
  U1_I67_5_PULLUP : X_PU
    port map (
      O => db_out(10)
    );
  U1_I67_5 : X_TRI
    port map (
      I => U1_db_error3(10),
      CTL => U1_I67_5_TINV,
      O => db_out(10)
    );
  U1_I67_5_TINV_517 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_5_TINV
    );
  U1_I59_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I59_6 : X_TRI
    port map (
      I => U1_paf_counter_0(9),
      CTL => U1_I59_6_TINV,
      O => db_out(9)
    );
  U1_I59_6_TINV_518 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_6_TINV
    );
  U1_I67_6_PULLUP : X_PU
    port map (
      O => db_out(9)
    );
  U1_I67_6 : X_TRI
    port map (
      I => U1_db_error3(9),
      CTL => U1_I67_6_TINV,
      O => db_out(9)
    );
  U1_I67_6_TINV_519 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_6_TINV
    );
  U1_I59_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I59_7 : X_TRI
    port map (
      I => U1_paf_counter_0(8),
      CTL => U1_I59_7_TINV,
      O => db_out(8)
    );
  U1_I59_7_TINV_520 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_7_TINV
    );
  U1_I67_7_PULLUP : X_PU
    port map (
      O => db_out(8)
    );
  U1_I67_7 : X_TRI
    port map (
      I => U1_db_error3(8),
      CTL => U1_I67_7_TINV,
      O => db_out(8)
    );
  U1_I67_7_TINV_521 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_7_TINV
    );
  U1_I59_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I59_8 : X_TRI
    port map (
      I => U1_paf_counter_0(7),
      CTL => U1_I59_8_TINV,
      O => db_out(7)
    );
  U1_I59_8_TINV_522 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_8_TINV
    );
  U1_I67_8_PULLUP : X_PU
    port map (
      O => db_out(7)
    );
  U1_I67_8 : X_TRI
    port map (
      I => U1_db_error3(7),
      CTL => U1_I67_8_TINV,
      O => db_out(7)
    );
  U1_I67_8_TINV_523 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_8_TINV
    );
  U1_I59_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I59_9 : X_TRI
    port map (
      I => U1_paf_counter_0(6),
      CTL => U1_I59_9_TINV,
      O => db_out(6)
    );
  U1_I59_9_TINV_524 : X_INV
    port map (
      I => U1_I59_N1762,
      O => U1_I59_9_TINV
    );
  U1_I67_9_PULLUP : X_PU
    port map (
      O => db_out(6)
    );
  U1_I67_9 : X_TRI
    port map (
      I => U1_db_error3(6),
      CTL => U1_I67_9_TINV,
      O => db_out(6)
    );
  U1_I67_9_TINV_525 : X_INV
    port map (
      I => U1_I67_N1762,
      O => U1_I67_9_TINV
    );
  U3_n010616 : X_MUX2
    port map (
      IA => N44690,
      IB => N44692,
      SEL => U3_n0216,
      O => CHOICE1026_F5MUX
    );
  U3_n010616_G : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_sel_read(5),
      ADR1 => U3_sel_read(4),
      ADR2 => U3_sel_read(3),
      ADR3 => VCC,
      O => N44692
    );
  U3_n010616_F : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => U1_dis_ffreg_mask,
      ADR1 => U3_sel_read_5_1,
      ADR2 => U3_sel_read(3),
      ADR3 => U3_state_FFd31,
      O => N44690
    );
  CHOICE1026_XUSED : X_BUF
    port map (
      I => CHOICE1026_F5MUX,
      O => CHOICE1026
    );
  U3_n010716 : X_MUX2
    port map (
      IA => N44705,
      IB => N44707,
      SEL => U3_n0216,
      O => CHOICE996_F5MUX
    );
  U3_n010716_G : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_sel_read_5_1,
      ADR1 => U3_sel_read(3),
      ADR2 => U3_sel_read(2),
      ADR3 => VCC,
      O => N44707
    );
  U3_n010716_F : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => U1_dis_ffreg_mask,
      ADR1 => U3_sel_read_5_1,
      ADR2 => U3_sel_read(2),
      ADR3 => U3_state_FFd31,
      O => N44705
    );
  CHOICE996_XUSED : X_BUF
    port map (
      I => CHOICE996_F5MUX,
      O => CHOICE996
    );
  U3_n010816 : X_MUX2
    port map (
      IA => N44700,
      IB => N44702,
      SEL => U3_n0216,
      O => CHOICE1011_F5MUX
    );
  U3_n010816_G : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_sel_read_5_1,
      ADR1 => U3_sel_read(2),
      ADR2 => U3_sel_read(1),
      ADR3 => VCC,
      O => N44702
    );
  U3_n010816_F : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => U1_dis_ffreg_mask,
      ADR1 => U3_sel_read_5_1,
      ADR2 => U3_sel_read(1),
      ADR3 => U3_state_FFd31,
      O => N44700
    );
  CHOICE1011_XUSED : X_BUF
    port map (
      I => CHOICE1011_F5MUX,
      O => CHOICE1011
    );
  U3_n010916 : X_MUX2
    port map (
      IA => N44695,
      IB => N44697,
      SEL => U3_n0216,
      O => CHOICE981_F5MUX
    );
  U3_n010916_G : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_sel_read_5_1,
      ADR1 => U3_sel_read(1),
      ADR2 => U3_sel_read(0),
      ADR3 => VCC,
      O => N44697
    );
  U3_n010916_F : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => U1_dis_ffreg_mask,
      ADR1 => U3_sel_read_5_1,
      ADR2 => U3_sel_read(0),
      ADR3 => U3_state_FFd31,
      O => N44695
    );
  CHOICE981_XUSED : X_BUF
    port map (
      I => CHOICE981_F5MUX,
      O => CHOICE981
    );
  U3_n0151_1_LOGIC_ZERO_526 : X_ZERO
    port map (
      O => U3_n0151_1_LOGIC_ZERO
    );
  U3_cr_ros_n0151_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U3_n0151_1_LOGIC_ZERO,
      SEL => U3_N21487,
      O => U3_cr_ros_n0151_0_cyo
    );
  U3_cr_ros_n0151_0_lut : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U3_word_count(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21487
    );
  U3_n0151_1_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U3_word_count(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_1_GROM
    );
  U3_n0151_1_COUTUSED : X_BUF
    port map (
      I => U3_n0151_1_CYMUXG,
      O => U3_cr_ros_n0151_1_cyo
    );
  U3_n0151_1_YUSED : X_BUF
    port map (
      I => U3_n0151_1_XORG,
      O => U3_n0151(1)
    );
  U3_cr_ros_n0151_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U3_cr_ros_n0151_0_cyo,
      SEL => U3_n0151_1_GROM,
      O => U3_n0151_1_CYMUXG
    );
  U3_cr_ros_n0151_1_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0151_0_cyo,
      I1 => U3_n0151_1_GROM,
      O => U3_n0151_1_XORG
    );
  U3_n0151_2_LOGIC_ZERO_527 : X_ZERO
    port map (
      O => U3_n0151_2_LOGIC_ZERO
    );
  U3_cr_ros_n0151_2_cy : X_MUX2
    port map (
      IA => U3_n0151_2_LOGIC_ZERO,
      IB => U3_n0151_2_CYINIT,
      SEL => U3_n0151_2_FROM,
      O => U3_cr_ros_n0151_2_cyo
    );
  U3_cr_ros_n0151_2_xor : X_XOR2
    port map (
      I0 => U3_n0151_2_CYINIT,
      I1 => U3_n0151_2_FROM,
      O => U3_n0151_2_XORF
    );
  U3_n0151_2_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_2_FROM
    );
  U3_n0151_2_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_2_GROM
    );
  U3_n0151_2_COUTUSED : X_BUF
    port map (
      I => U3_n0151_2_CYMUXG,
      O => U3_cr_ros_n0151_3_cyo
    );
  U3_n0151_2_XUSED : X_BUF
    port map (
      I => U3_n0151_2_XORF,
      O => U3_n0151(2)
    );
  U3_n0151_2_YUSED : X_BUF
    port map (
      I => U3_n0151_2_XORG,
      O => U3_n0151(3)
    );
  U3_cr_ros_n0151_3_cy : X_MUX2
    port map (
      IA => U3_n0151_2_LOGIC_ZERO,
      IB => U3_cr_ros_n0151_2_cyo,
      SEL => U3_n0151_2_GROM,
      O => U3_n0151_2_CYMUXG
    );
  U3_cr_ros_n0151_3_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0151_2_cyo,
      I1 => U3_n0151_2_GROM,
      O => U3_n0151_2_XORG
    );
  U3_n0151_2_CYINIT_528 : X_BUF
    port map (
      I => U3_cr_ros_n0151_1_cyo,
      O => U3_n0151_2_CYINIT
    );
  U3_n0151_4_LOGIC_ZERO_529 : X_ZERO
    port map (
      O => U3_n0151_4_LOGIC_ZERO
    );
  U3_cr_ros_n0151_4_cy : X_MUX2
    port map (
      IA => U3_n0151_4_LOGIC_ZERO,
      IB => U3_n0151_4_CYINIT,
      SEL => U3_n0151_4_FROM,
      O => U3_cr_ros_n0151_4_cyo
    );
  U3_cr_ros_n0151_4_xor : X_XOR2
    port map (
      I0 => U3_n0151_4_CYINIT,
      I1 => U3_n0151_4_FROM,
      O => U3_n0151_4_XORF
    );
  U3_n0151_4_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_4_FROM
    );
  U3_n0151_4_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_4_GROM
    );
  U3_n0151_4_COUTUSED : X_BUF
    port map (
      I => U3_n0151_4_CYMUXG,
      O => U3_cr_ros_n0151_5_cyo
    );
  U3_n0151_4_XUSED : X_BUF
    port map (
      I => U3_n0151_4_XORF,
      O => U3_n0151(4)
    );
  U3_n0151_4_YUSED : X_BUF
    port map (
      I => U3_n0151_4_XORG,
      O => U3_n0151(5)
    );
  U3_cr_ros_n0151_5_cy : X_MUX2
    port map (
      IA => U3_n0151_4_LOGIC_ZERO,
      IB => U3_cr_ros_n0151_4_cyo,
      SEL => U3_n0151_4_GROM,
      O => U3_n0151_4_CYMUXG
    );
  U3_cr_ros_n0151_5_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0151_4_cyo,
      I1 => U3_n0151_4_GROM,
      O => U3_n0151_4_XORG
    );
  U3_n0151_4_CYINIT_530 : X_BUF
    port map (
      I => U3_cr_ros_n0151_3_cyo,
      O => U3_n0151_4_CYINIT
    );
  U3_n0151_6_LOGIC_ZERO_531 : X_ZERO
    port map (
      O => U3_n0151_6_LOGIC_ZERO
    );
  U3_cr_ros_n0151_6_cy : X_MUX2
    port map (
      IA => U3_n0151_6_LOGIC_ZERO,
      IB => U3_n0151_6_CYINIT,
      SEL => U3_n0151_6_FROM,
      O => U3_cr_ros_n0151_6_cyo
    );
  U3_cr_ros_n0151_6_xor : X_XOR2
    port map (
      I0 => U3_n0151_6_CYINIT,
      I1 => U3_n0151_6_FROM,
      O => U3_n0151_6_XORF
    );
  U3_n0151_6_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_6_FROM
    );
  U3_n0151_6_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_6_GROM
    );
  U3_n0151_6_COUTUSED : X_BUF
    port map (
      I => U3_n0151_6_CYMUXG,
      O => U3_cr_ros_n0151_7_cyo
    );
  U3_n0151_6_XUSED : X_BUF
    port map (
      I => U3_n0151_6_XORF,
      O => U3_n0151(6)
    );
  U3_n0151_6_YUSED : X_BUF
    port map (
      I => U3_n0151_6_XORG,
      O => U3_n0151(7)
    );
  U3_cr_ros_n0151_7_cy : X_MUX2
    port map (
      IA => U3_n0151_6_LOGIC_ZERO,
      IB => U3_cr_ros_n0151_6_cyo,
      SEL => U3_n0151_6_GROM,
      O => U3_n0151_6_CYMUXG
    );
  U3_cr_ros_n0151_7_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0151_6_cyo,
      I1 => U3_n0151_6_GROM,
      O => U3_n0151_6_XORG
    );
  U3_n0151_6_CYINIT_532 : X_BUF
    port map (
      I => U3_cr_ros_n0151_5_cyo,
      O => U3_n0151_6_CYINIT
    );
  U3_n0151_8_LOGIC_ZERO_533 : X_ZERO
    port map (
      O => U3_n0151_8_LOGIC_ZERO
    );
  U3_cr_ros_n0151_8_cy : X_MUX2
    port map (
      IA => U3_n0151_8_LOGIC_ZERO,
      IB => U3_n0151_8_CYINIT,
      SEL => U3_n0151_8_FROM,
      O => U3_cr_ros_n0151_8_cyo
    );
  U3_cr_ros_n0151_8_xor : X_XOR2
    port map (
      I0 => U3_n0151_8_CYINIT,
      I1 => U3_n0151_8_FROM,
      O => U3_n0151_8_XORF
    );
  U3_n0151_8_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_8_FROM
    );
  U3_n0151_8_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_8_GROM
    );
  U3_n0151_8_COUTUSED : X_BUF
    port map (
      I => U3_n0151_8_CYMUXG,
      O => U3_cr_ros_n0151_9_cyo
    );
  U3_n0151_8_XUSED : X_BUF
    port map (
      I => U3_n0151_8_XORF,
      O => U3_n0151(8)
    );
  U3_n0151_8_YUSED : X_BUF
    port map (
      I => U3_n0151_8_XORG,
      O => U3_n0151(9)
    );
  U3_cr_ros_n0151_9_cy : X_MUX2
    port map (
      IA => U3_n0151_8_LOGIC_ZERO,
      IB => U3_cr_ros_n0151_8_cyo,
      SEL => U3_n0151_8_GROM,
      O => U3_n0151_8_CYMUXG
    );
  U3_cr_ros_n0151_9_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0151_8_cyo,
      I1 => U3_n0151_8_GROM,
      O => U3_n0151_8_XORG
    );
  U3_n0151_8_CYINIT_534 : X_BUF
    port map (
      I => U3_cr_ros_n0151_7_cyo,
      O => U3_n0151_8_CYINIT
    );
  U3_n0151_10_LOGIC_ZERO_535 : X_ZERO
    port map (
      O => U3_n0151_10_LOGIC_ZERO
    );
  U3_cr_ros_n0151_10_cy : X_MUX2
    port map (
      IA => U3_n0151_10_LOGIC_ZERO,
      IB => U3_n0151_10_CYINIT,
      SEL => U3_n0151_10_FROM,
      O => U3_cr_ros_n0151_10_cyo
    );
  U3_cr_ros_n0151_10_xor : X_XOR2
    port map (
      I0 => U3_n0151_10_CYINIT,
      I1 => U3_n0151_10_FROM,
      O => U3_n0151_10_XORF
    );
  U3_n0151_10_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0151_10_FROM
    );
  U3_word_count_11_rt_536 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_word_count(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_word_count_11_rt
    );
  U3_n0151_10_XUSED : X_BUF
    port map (
      I => U3_n0151_10_XORF,
      O => U3_n0151(10)
    );
  U3_n0151_10_YUSED : X_BUF
    port map (
      I => U3_n0151_10_XORG,
      O => U3_n0151(11)
    );
  U3_cr_ros_n0151_11_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0151_10_cyo,
      I1 => U3_word_count_11_rt,
      O => U3_n0151_10_XORG
    );
  U3_n0151_10_CYINIT_537 : X_BUF
    port map (
      I => U3_cr_ros_n0151_9_cyo,
      O => U3_n0151_10_CYINIT
    );
  U2_disparity_0_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_0_FFY_RST
    );
  U2_disparity_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_0,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_0_FFY_RST,
      O => U2_disparity(0)
    );
  U2_disparity_0_LOGIC_ZERO_538 : X_ZERO
    port map (
      O => U2_disparity_0_LOGIC_ZERO
    );
  U2_disparity_inst_cy_0_539 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U2_disparity_0_LOGIC_ZERO,
      SEL => enw_dispar_rt,
      O => U2_disparity_inst_cy_0
    );
  enw_dispar_rt_540 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => enw_dispar,
      ADR2 => VCC,
      ADR3 => VCC,
      O => enw_dispar_rt
    );
  U2_disparity_0_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U2_disparity_inst_lut3_0,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_disparity_0_GROM
    );
  U2_disparity_0_COUTUSED : X_BUF
    port map (
      I => U2_disparity_0_CYMUXG,
      O => U2_disparity_inst_cy_1
    );
  U2_disparity_inst_cy_1_541 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U2_disparity_inst_cy_0,
      SEL => U2_disparity_0_GROM,
      O => U2_disparity_0_CYMUXG
    );
  U2_disparity_inst_sum_0_542 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_0,
      I1 => U2_disparity_0_GROM,
      O => U2_disparity_inst_sum_0
    );
  U2_disparity_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_1_FFY_RST
    );
  U2_disparity_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_2,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_1_FFY_RST,
      O => U2_disparity(2)
    );
  U2_disparity_1_LOGIC_ZERO_543 : X_ZERO
    port map (
      O => U2_disparity_1_LOGIC_ZERO
    );
  U2_disparity_inst_cy_2_544 : X_MUX2
    port map (
      IA => U2_disparity_1_LOGIC_ZERO,
      IB => U2_disparity_1_CYINIT,
      SEL => U2_disparity_inst_lut3_1,
      O => U2_disparity_inst_cy_2
    );
  U2_disparity_inst_sum_1_545 : X_XOR2
    port map (
      I0 => U2_disparity_1_CYINIT,
      I1 => U2_disparity_inst_lut3_1,
      O => U2_disparity_inst_sum_1
    );
  U2_disparity_inst_lut3_16 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44074,
      ADR3 => U2_disparity(1),
      O => U2_disparity_inst_lut3_1
    );
  U2_disparity_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44076,
      ADR3 => U2_disparity(2),
      O => U2_disparity_inst_lut3_2
    );
  U2_disparity_1_COUTUSED : X_BUF
    port map (
      I => U2_disparity_1_CYMUXG,
      O => U2_disparity_inst_cy_3
    );
  U2_disparity_inst_cy_3_546 : X_MUX2
    port map (
      IA => U2_disparity_1_LOGIC_ZERO,
      IB => U2_disparity_inst_cy_2,
      SEL => U2_disparity_inst_lut3_2,
      O => U2_disparity_1_CYMUXG
    );
  U2_disparity_inst_sum_2_547 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_2,
      I1 => U2_disparity_inst_lut3_2,
      O => U2_disparity_inst_sum_2
    );
  U2_disparity_1_CYINIT_548 : X_BUF
    port map (
      I => U2_disparity_inst_cy_1,
      O => U2_disparity_1_CYINIT
    );
  U2_disparity_3_LOGIC_ZERO_549 : X_ZERO
    port map (
      O => U2_disparity_3_LOGIC_ZERO
    );
  U2_disparity_inst_cy_4_550 : X_MUX2
    port map (
      IA => U2_disparity_3_LOGIC_ZERO,
      IB => U2_disparity_3_CYINIT,
      SEL => U2_disparity_inst_lut3_3,
      O => U2_disparity_inst_cy_4
    );
  U2_disparity_inst_sum_3_551 : X_XOR2
    port map (
      I0 => U2_disparity_3_CYINIT,
      I1 => U2_disparity_inst_lut3_3,
      O => U2_disparity_inst_sum_3
    );
  U2_disparity_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44078,
      ADR3 => U2_disparity(3),
      O => U2_disparity_inst_lut3_3
    );
  U2_disparity_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44080,
      ADR3 => U2_disparity(4),
      O => U2_disparity_inst_lut3_4
    );
  U2_disparity_3_COUTUSED : X_BUF
    port map (
      I => U2_disparity_3_CYMUXG,
      O => U2_disparity_inst_cy_5
    );
  U2_disparity_inst_cy_5_552 : X_MUX2
    port map (
      IA => U2_disparity_3_LOGIC_ZERO,
      IB => U2_disparity_inst_cy_4,
      SEL => U2_disparity_inst_lut3_4,
      O => U2_disparity_3_CYMUXG
    );
  U2_disparity_inst_sum_4_553 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_4,
      I1 => U2_disparity_inst_lut3_4,
      O => U2_disparity_inst_sum_4
    );
  U2_disparity_3_CYINIT_554 : X_BUF
    port map (
      I => U2_disparity_inst_cy_3,
      O => U2_disparity_3_CYINIT
    );
  U2_disparity_5_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_5_FFX_RST
    );
  U2_disparity_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_5,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_5_FFX_RST,
      O => U2_disparity(5)
    );
  U2_disparity_5_LOGIC_ZERO_555 : X_ZERO
    port map (
      O => U2_disparity_5_LOGIC_ZERO
    );
  U2_disparity_inst_cy_6_556 : X_MUX2
    port map (
      IA => U2_disparity_5_LOGIC_ZERO,
      IB => U2_disparity_5_CYINIT,
      SEL => U2_disparity_inst_lut3_5,
      O => U2_disparity_inst_cy_6
    );
  U2_disparity_inst_sum_5_557 : X_XOR2
    port map (
      I0 => U2_disparity_5_CYINIT,
      I1 => U2_disparity_inst_lut3_5,
      O => U2_disparity_inst_sum_5
    );
  U2_disparity_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44082,
      ADR3 => U2_disparity(5),
      O => U2_disparity_inst_lut3_5
    );
  U2_disparity_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44084,
      ADR3 => U2_disparity(6),
      O => U2_disparity_inst_lut3_6
    );
  U2_disparity_5_COUTUSED : X_BUF
    port map (
      I => U2_disparity_5_CYMUXG,
      O => U2_disparity_inst_cy_7
    );
  U2_disparity_inst_cy_7_558 : X_MUX2
    port map (
      IA => U2_disparity_5_LOGIC_ZERO,
      IB => U2_disparity_inst_cy_6,
      SEL => U2_disparity_inst_lut3_6,
      O => U2_disparity_5_CYMUXG
    );
  U2_disparity_inst_sum_6_559 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_6,
      I1 => U2_disparity_inst_lut3_6,
      O => U2_disparity_inst_sum_6
    );
  U2_disparity_5_CYINIT_560 : X_BUF
    port map (
      I => U2_disparity_inst_cy_5,
      O => U2_disparity_5_CYINIT
    );
  U2_disparity_7_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_7_FFX_RST
    );
  U2_disparity_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_7,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_7_FFX_RST,
      O => U2_disparity(7)
    );
  U2_disparity_7_LOGIC_ZERO_561 : X_ZERO
    port map (
      O => U2_disparity_7_LOGIC_ZERO
    );
  U2_disparity_inst_cy_8_562 : X_MUX2
    port map (
      IA => U2_disparity_7_LOGIC_ZERO,
      IB => U2_disparity_7_CYINIT,
      SEL => U2_disparity_inst_lut3_7,
      O => U2_disparity_inst_cy_8
    );
  U2_disparity_inst_sum_7_563 : X_XOR2
    port map (
      I0 => U2_disparity_7_CYINIT,
      I1 => U2_disparity_inst_lut3_7,
      O => U2_disparity_inst_sum_7
    );
  U2_disparity_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44086,
      ADR3 => U2_disparity(7),
      O => U2_disparity_inst_lut3_7
    );
  U2_disparity_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44088,
      ADR3 => U2_disparity(8),
      O => U2_disparity_inst_lut3_8
    );
  U2_disparity_7_COUTUSED : X_BUF
    port map (
      I => U2_disparity_7_CYMUXG,
      O => U2_disparity_inst_cy_9
    );
  U2_disparity_inst_cy_9_564 : X_MUX2
    port map (
      IA => U2_disparity_7_LOGIC_ZERO,
      IB => U2_disparity_inst_cy_8,
      SEL => U2_disparity_inst_lut3_8,
      O => U2_disparity_7_CYMUXG
    );
  U2_disparity_inst_sum_8_565 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_8,
      I1 => U2_disparity_inst_lut3_8,
      O => U2_disparity_inst_sum_8
    );
  U2_disparity_7_CYINIT_566 : X_BUF
    port map (
      I => U2_disparity_inst_cy_7,
      O => U2_disparity_7_CYINIT
    );
  U2_disparity_9_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_9_FFX_RST
    );
  U2_disparity_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_9,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_9_FFX_RST,
      O => U2_disparity(9)
    );
  U2_disparity_9_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_9_FFY_RST
    );
  U2_disparity_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_10,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_9_FFY_RST,
      O => U2_disparity(10)
    );
  U2_disparity_9_LOGIC_ZERO_567 : X_ZERO
    port map (
      O => U2_disparity_9_LOGIC_ZERO
    );
  U2_disparity_inst_cy_10_568 : X_MUX2
    port map (
      IA => U2_disparity_9_LOGIC_ZERO,
      IB => U2_disparity_9_CYINIT,
      SEL => U2_disparity_inst_lut3_9,
      O => U2_disparity_inst_cy_10
    );
  U2_disparity_inst_sum_9_569 : X_XOR2
    port map (
      I0 => U2_disparity_9_CYINIT,
      I1 => U2_disparity_inst_lut3_9,
      O => U2_disparity_inst_sum_9
    );
  U2_disparity_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44090,
      ADR3 => U2_disparity(9),
      O => U2_disparity_inst_lut3_9
    );
  U2_disparity_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_dispar,
      ADR1 => N44092,
      ADR2 => U2_disparity(10),
      ADR3 => VCC,
      O => U2_disparity_inst_lut3_10
    );
  U2_disparity_9_COUTUSED : X_BUF
    port map (
      I => U2_disparity_9_CYMUXG,
      O => U2_disparity_inst_cy_11
    );
  U2_disparity_inst_cy_11_570 : X_MUX2
    port map (
      IA => U2_disparity_9_LOGIC_ZERO,
      IB => U2_disparity_inst_cy_10,
      SEL => U2_disparity_inst_lut3_10,
      O => U2_disparity_9_CYMUXG
    );
  U2_disparity_inst_sum_10_571 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_10,
      I1 => U2_disparity_inst_lut3_10,
      O => U2_disparity_inst_sum_10
    );
  U2_disparity_9_CYINIT_572 : X_BUF
    port map (
      I => U2_disparity_inst_cy_9,
      O => U2_disparity_9_CYINIT
    );
  U2_disparity_11_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_11_FFY_RST
    );
  U2_disparity_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_12,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_11_FFY_RST,
      O => U2_disparity(12)
    );
  U2_disparity_11_LOGIC_ZERO_573 : X_ZERO
    port map (
      O => U2_disparity_11_LOGIC_ZERO
    );
  U2_disparity_inst_cy_12_574 : X_MUX2
    port map (
      IA => U2_disparity_11_LOGIC_ZERO,
      IB => U2_disparity_11_CYINIT,
      SEL => U2_disparity_inst_lut3_11,
      O => U2_disparity_inst_cy_12
    );
  U2_disparity_inst_sum_11_575 : X_XOR2
    port map (
      I0 => U2_disparity_11_CYINIT,
      I1 => U2_disparity_inst_lut3_11,
      O => U2_disparity_inst_sum_11
    );
  U2_disparity_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_dispar,
      ADR1 => N44094,
      ADR2 => U2_disparity(11),
      ADR3 => VCC,
      O => U2_disparity_inst_lut3_11
    );
  U2_disparity_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_dispar,
      ADR1 => N44096,
      ADR2 => U2_disparity(12),
      ADR3 => VCC,
      O => U2_disparity_inst_lut3_12
    );
  U2_disparity_11_COUTUSED : X_BUF
    port map (
      I => U2_disparity_11_CYMUXG,
      O => U2_disparity_inst_cy_13
    );
  U2_disparity_inst_cy_13_576 : X_MUX2
    port map (
      IA => U2_disparity_11_LOGIC_ZERO,
      IB => U2_disparity_inst_cy_12,
      SEL => U2_disparity_inst_lut3_12,
      O => U2_disparity_11_CYMUXG
    );
  U2_disparity_inst_sum_12_577 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_12,
      I1 => U2_disparity_inst_lut3_12,
      O => U2_disparity_inst_sum_12
    );
  U2_disparity_11_CYINIT_578 : X_BUF
    port map (
      I => U2_disparity_inst_cy_11,
      O => U2_disparity_11_CYINIT
    );
  U2_disparity_13_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_13_FFY_RST
    );
  U2_disparity_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_14,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_13_FFY_RST,
      O => U2_disparity(14)
    );
  U2_disparity_13_LOGIC_ZERO_579 : X_ZERO
    port map (
      O => U2_disparity_13_LOGIC_ZERO
    );
  U2_disparity_inst_cy_14_580 : X_MUX2
    port map (
      IA => U2_disparity_13_LOGIC_ZERO,
      IB => U2_disparity_13_CYINIT,
      SEL => U2_disparity_inst_lut3_13,
      O => U2_disparity_inst_cy_14
    );
  U2_disparity_inst_sum_13_581 : X_XOR2
    port map (
      I0 => U2_disparity_13_CYINIT,
      I1 => U2_disparity_inst_lut3_13,
      O => U2_disparity_inst_sum_13
    );
  U2_disparity_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_dispar,
      ADR1 => N44098,
      ADR2 => U2_disparity(13),
      ADR3 => VCC,
      O => U2_disparity_inst_lut3_13
    );
  U2_disparity_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_dispar,
      ADR1 => N44100,
      ADR2 => U2_disparity(14),
      ADR3 => VCC,
      O => U2_disparity_inst_lut3_14
    );
  U2_disparity_13_COUTUSED : X_BUF
    port map (
      I => U2_disparity_13_CYMUXG,
      O => U2_disparity_inst_cy_15
    );
  U2_disparity_inst_cy_15_582 : X_MUX2
    port map (
      IA => U2_disparity_13_LOGIC_ZERO,
      IB => U2_disparity_inst_cy_14,
      SEL => U2_disparity_inst_lut3_14,
      O => U2_disparity_13_CYMUXG
    );
  U2_disparity_inst_sum_14_583 : X_XOR2
    port map (
      I0 => U2_disparity_inst_cy_14,
      I1 => U2_disparity_inst_lut3_14,
      O => U2_disparity_inst_sum_14
    );
  U2_disparity_13_CYINIT_584 : X_BUF
    port map (
      I => U2_disparity_inst_cy_13,
      O => U2_disparity_13_CYINIT
    );
  U2_disparity_inst_sum_15_585 : X_XOR2
    port map (
      I0 => U2_disparity_15_CYINIT,
      I1 => U2_disparity_inst_lut3_15,
      O => U2_disparity_inst_sum_15
    );
  U2_disparity_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_dispar,
      ADR1 => N44102,
      ADR2 => U2_disparity(15),
      ADR3 => VCC,
      O => U2_disparity_inst_lut3_15
    );
  U2_n0131_SW15 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => parcheck,
      ADR1 => U2_disparity(15),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_disparity_15_GROM
    );
  U2_disparity_15_YUSED : X_BUF
    port map (
      I => U2_disparity_15_GROM,
      O => CHOICE200
    );
  U2_disparity_15_CYINIT_586 : X_BUF
    port map (
      I => U2_disparity_inst_cy_15,
      O => U2_disparity_15_CYINIT
    );
  U3_Neq_stage_cyo1_LOGIC_ZERO_587 : X_ZERO
    port map (
      O => U3_Neq_stage_cyo1_LOGIC_ZERO
    );
  U3_Neq_stage_cyo1_LOGIC_ONE_588 : X_ONE
    port map (
      O => U3_Neq_stage_cyo1_LOGIC_ONE
    );
  U3_Neq_stagecy : X_MUX2
    port map (
      IA => U3_Neq_stage_cyo1_LOGIC_ONE,
      IB => U3_Neq_stage_cyo1_LOGIC_ZERO,
      SEL => U3_N21575,
      O => U3_Neq_stage_cyo
    );
  U3_Neq_stagelut : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => U3_word_count(4),
      ADR1 => U1_nmaxwords(0),
      ADR2 => U3_word_count(5),
      ADR3 => U1_nmaxwords(1),
      O => U3_N21575
    );
  U3_Neq_stagelut1 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => U3_word_count(6),
      ADR1 => U1_nmaxwords(2),
      ADR2 => U3_word_count(7),
      ADR3 => U1_nmaxwords(3),
      O => U3_N21578
    );
  U3_Neq_stage_cyo1_COUTUSED : X_BUF
    port map (
      I => U3_Neq_stage_cyo1_CYMUXG,
      O => U3_Neq_stage_cyo1
    );
  U3_Neq_stagecy_rn_0 : X_MUX2
    port map (
      IA => U3_Neq_stage_cyo1_LOGIC_ONE,
      IB => U3_Neq_stage_cyo,
      SEL => U3_N21578,
      O => U3_Neq_stage_cyo1_CYMUXG
    );
  U3_n0050_LOGIC_ONE_589 : X_ONE
    port map (
      O => U3_n0050_LOGIC_ONE
    );
  U3_Neq_stagecy_rn_1 : X_MUX2
    port map (
      IA => U3_n0050_LOGIC_ONE,
      IB => U3_n0050_CYINIT,
      SEL => U3_N21581,
      O => U3_Neq_stage_cyo2
    );
  U3_Neq_stagelut2 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => U3_word_count(8),
      ADR1 => U1_nmaxwords(4),
      ADR2 => U3_word_count(9),
      ADR3 => U1_nmaxwords(5),
      O => U3_N21581
    );
  U3_Neq_stagelut3 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => U3_word_count(10),
      ADR1 => U1_nmaxwords(6),
      ADR2 => U3_word_count(11),
      ADR3 => U1_nmaxwords(7),
      O => U3_N21584
    );
  U3_n0050_COUTUSED : X_BUF
    port map (
      I => U3_n0050_CYMUXG,
      O => U3_n0050
    );
  U3_Neq_stagecy_rn_2 : X_MUX2
    port map (
      IA => U3_n0050_LOGIC_ONE,
      IB => U3_Neq_stage_cyo2,
      SEL => U3_N21584,
      O => U3_n0050_CYMUXG
    );
  U3_n0050_CYINIT_590 : X_BUF
    port map (
      I => U3_Neq_stage_cyo1,
      O => U3_n0050_CYINIT
    );
  U3_n0251_0_LOGIC_ONE_591 : X_ONE
    port map (
      O => U3_n0251_0_LOGIC_ONE
    );
  U3_cr_ros_n0251_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U3_n0251_0_CYINIT,
      SEL => U3_n0251_0_FROM,
      O => U3_cr_ros_n0251_0_cyo
    );
  U3_cr_ros_n0251_0_xor : X_XOR2
    port map (
      I0 => U3_n0251_0_CYINIT,
      I1 => U3_n0251_0_FROM,
      O => U3_n0251_0_XORF
    );
  U3_n0251_0_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U3_time_counter(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0251_0_FROM
    );
  U3_cr_ros_n0251_1_lut : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U3_time_counter(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21515
    );
  U3_n0251_0_COUTUSED : X_BUF
    port map (
      I => U3_n0251_0_CYMUXG,
      O => U3_cr_ros_n0251_1_cyo
    );
  U3_n0251_0_XUSED : X_BUF
    port map (
      I => U3_n0251_0_XORF,
      O => U3_n0251(0)
    );
  U3_n0251_0_YUSED : X_BUF
    port map (
      I => U3_n0251_0_XORG,
      O => U3_n0251(1)
    );
  U3_cr_ros_n0251_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U3_cr_ros_n0251_0_cyo,
      SEL => U3_N21515,
      O => U3_n0251_0_CYMUXG
    );
  U3_cr_ros_n0251_1_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0251_0_cyo,
      I1 => U3_N21515,
      O => U3_n0251_0_XORG
    );
  U3_n0251_0_CYINIT_592 : X_BUF
    port map (
      I => U3_n0251_0_LOGIC_ONE,
      O => U3_n0251_0_CYINIT
    );
  U3_n0251_2_LOGIC_ONE_593 : X_ONE
    port map (
      O => U3_n0251_2_LOGIC_ONE
    );
  U3_cr_ros_n0251_2_cy : X_MUX2
    port map (
      IA => U3_n0251_2_LOGIC_ONE,
      IB => U3_n0251_2_CYINIT,
      SEL => U3_N21519,
      O => U3_cr_ros_n0251_2_cyo
    );
  U3_cr_ros_n0251_2_xor : X_XOR2
    port map (
      I0 => U3_n0251_2_CYINIT,
      I1 => U3_N21519,
      O => U3_n0251_2_XORF
    );
  U3_cr_ros_n0251_2_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21519
    );
  U3_cr_ros_n0251_3_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21523
    );
  U3_n0251_2_COUTUSED : X_BUF
    port map (
      I => U3_n0251_2_CYMUXG,
      O => U3_cr_ros_n0251_3_cyo
    );
  U3_n0251_2_XUSED : X_BUF
    port map (
      I => U3_n0251_2_XORF,
      O => U3_n0251(2)
    );
  U3_n0251_2_YUSED : X_BUF
    port map (
      I => U3_n0251_2_XORG,
      O => U3_n0251(3)
    );
  U3_cr_ros_n0251_3_cy : X_MUX2
    port map (
      IA => U3_n0251_2_LOGIC_ONE,
      IB => U3_cr_ros_n0251_2_cyo,
      SEL => U3_N21523,
      O => U3_n0251_2_CYMUXG
    );
  U3_cr_ros_n0251_3_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0251_2_cyo,
      I1 => U3_N21523,
      O => U3_n0251_2_XORG
    );
  U3_n0251_2_CYINIT_594 : X_BUF
    port map (
      I => U3_cr_ros_n0251_1_cyo,
      O => U3_n0251_2_CYINIT
    );
  U3_n0251_4_LOGIC_ONE_595 : X_ONE
    port map (
      O => U3_n0251_4_LOGIC_ONE
    );
  U3_cr_ros_n0251_4_cy : X_MUX2
    port map (
      IA => U3_n0251_4_LOGIC_ONE,
      IB => U3_n0251_4_CYINIT,
      SEL => U3_N21527,
      O => U3_cr_ros_n0251_4_cyo
    );
  U3_cr_ros_n0251_4_xor : X_XOR2
    port map (
      I0 => U3_n0251_4_CYINIT,
      I1 => U3_N21527,
      O => U3_n0251_4_XORF
    );
  U3_cr_ros_n0251_4_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21527
    );
  U3_cr_ros_n0251_5_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21531
    );
  U3_n0251_4_COUTUSED : X_BUF
    port map (
      I => U3_n0251_4_CYMUXG,
      O => U3_cr_ros_n0251_5_cyo
    );
  U3_n0251_4_XUSED : X_BUF
    port map (
      I => U3_n0251_4_XORF,
      O => U3_n0251(4)
    );
  U3_n0251_4_YUSED : X_BUF
    port map (
      I => U3_n0251_4_XORG,
      O => U3_n0251(5)
    );
  U3_cr_ros_n0251_5_cy : X_MUX2
    port map (
      IA => U3_n0251_4_LOGIC_ONE,
      IB => U3_cr_ros_n0251_4_cyo,
      SEL => U3_N21531,
      O => U3_n0251_4_CYMUXG
    );
  U3_cr_ros_n0251_5_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0251_4_cyo,
      I1 => U3_N21531,
      O => U3_n0251_4_XORG
    );
  U3_n0251_4_CYINIT_596 : X_BUF
    port map (
      I => U3_cr_ros_n0251_3_cyo,
      O => U3_n0251_4_CYINIT
    );
  U3_n0251_6_LOGIC_ONE_597 : X_ONE
    port map (
      O => U3_n0251_6_LOGIC_ONE
    );
  U3_cr_ros_n0251_6_cy : X_MUX2
    port map (
      IA => U3_n0251_6_LOGIC_ONE,
      IB => U3_n0251_6_CYINIT,
      SEL => U3_N21535,
      O => U3_cr_ros_n0251_6_cyo
    );
  U3_cr_ros_n0251_6_xor : X_XOR2
    port map (
      I0 => U3_n0251_6_CYINIT,
      I1 => U3_N21535,
      O => U3_n0251_6_XORF
    );
  U3_cr_ros_n0251_6_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21535
    );
  U3_cr_ros_n0251_7_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21539
    );
  U3_n0251_6_COUTUSED : X_BUF
    port map (
      I => U3_n0251_6_CYMUXG,
      O => U3_cr_ros_n0251_7_cyo
    );
  U3_n0251_6_XUSED : X_BUF
    port map (
      I => U3_n0251_6_XORF,
      O => U3_n0251(6)
    );
  U3_n0251_6_YUSED : X_BUF
    port map (
      I => U3_n0251_6_XORG,
      O => U3_n0251(7)
    );
  U3_cr_ros_n0251_7_cy : X_MUX2
    port map (
      IA => U3_n0251_6_LOGIC_ONE,
      IB => U3_cr_ros_n0251_6_cyo,
      SEL => U3_N21539,
      O => U3_n0251_6_CYMUXG
    );
  U3_cr_ros_n0251_7_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0251_6_cyo,
      I1 => U3_N21539,
      O => U3_n0251_6_XORG
    );
  U3_n0251_6_CYINIT_598 : X_BUF
    port map (
      I => U3_cr_ros_n0251_5_cyo,
      O => U3_n0251_6_CYINIT
    );
  U3_n0251_8_LOGIC_ONE_599 : X_ONE
    port map (
      O => U3_n0251_8_LOGIC_ONE
    );
  U3_cr_ros_n0251_8_cy : X_MUX2
    port map (
      IA => U3_n0251_8_LOGIC_ONE,
      IB => U3_n0251_8_CYINIT,
      SEL => U3_N21543,
      O => U3_cr_ros_n0251_8_cyo
    );
  U3_cr_ros_n0251_8_xor : X_XOR2
    port map (
      I0 => U3_n0251_8_CYINIT,
      I1 => U3_N21543,
      O => U3_n0251_8_XORF
    );
  U3_cr_ros_n0251_8_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21543
    );
  U3_cr_ros_n0251_9_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21547
    );
  U3_n0251_8_COUTUSED : X_BUF
    port map (
      I => U3_n0251_8_CYMUXG,
      O => U3_cr_ros_n0251_9_cyo
    );
  U3_n0251_8_XUSED : X_BUF
    port map (
      I => U3_n0251_8_XORF,
      O => U3_n0251(8)
    );
  U3_n0251_8_YUSED : X_BUF
    port map (
      I => U3_n0251_8_XORG,
      O => U3_n0251(9)
    );
  U3_cr_ros_n0251_9_cy : X_MUX2
    port map (
      IA => U3_n0251_8_LOGIC_ONE,
      IB => U3_cr_ros_n0251_8_cyo,
      SEL => U3_N21547,
      O => U3_n0251_8_CYMUXG
    );
  U3_cr_ros_n0251_9_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0251_8_cyo,
      I1 => U3_N21547,
      O => U3_n0251_8_XORG
    );
  U3_n0251_8_CYINIT_600 : X_BUF
    port map (
      I => U3_cr_ros_n0251_7_cyo,
      O => U3_n0251_8_CYINIT
    );
  U3_n0251_10_LOGIC_ONE_601 : X_ONE
    port map (
      O => U3_n0251_10_LOGIC_ONE
    );
  U3_cr_ros_n0251_10_cy : X_MUX2
    port map (
      IA => U3_n0251_10_LOGIC_ONE,
      IB => U3_n0251_10_CYINIT,
      SEL => U3_N21551,
      O => U3_cr_ros_n0251_10_cyo
    );
  U3_cr_ros_n0251_10_xor : X_XOR2
    port map (
      I0 => U3_n0251_10_CYINIT,
      I1 => U3_N21551,
      O => U3_n0251_10_XORF
    );
  U3_cr_ros_n0251_10_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21551
    );
  U3_cr_ros_n0251_11_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21555
    );
  U3_n0251_10_COUTUSED : X_BUF
    port map (
      I => U3_n0251_10_CYMUXG,
      O => U3_cr_ros_n0251_11_cyo
    );
  U3_n0251_10_XUSED : X_BUF
    port map (
      I => U3_n0251_10_XORF,
      O => U3_n0251(10)
    );
  U3_n0251_10_YUSED : X_BUF
    port map (
      I => U3_n0251_10_XORG,
      O => U3_n0251(11)
    );
  U3_cr_ros_n0251_11_cy : X_MUX2
    port map (
      IA => U3_n0251_10_LOGIC_ONE,
      IB => U3_cr_ros_n0251_10_cyo,
      SEL => U3_N21555,
      O => U3_n0251_10_CYMUXG
    );
  U3_cr_ros_n0251_11_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0251_10_cyo,
      I1 => U3_N21555,
      O => U3_n0251_10_XORG
    );
  U3_n0251_10_CYINIT_602 : X_BUF
    port map (
      I => U3_cr_ros_n0251_9_cyo,
      O => U3_n0251_10_CYINIT
    );
  U3_cr_ros_n0251_12_xor : X_XOR2
    port map (
      I0 => U3_time_out_CYINIT,
      I1 => U3_N21559,
      O => U3_time_out_XORF
    );
  U3_cr_ros_n0251_12_lut : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => U3_time_counter(12),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21559
    );
  U3_n01181 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_time_start,
      ADR1 => U3_time_counter(12),
      ADR2 => U3_fmt_error_ff_2_1_Q,
      ADR3 => U1_dis_hul_mask,
      O => U3_n0118
    );
  U3_time_out_XUSED : X_BUF
    port map (
      I => U3_time_out_XORF,
      O => U3_n0251(12)
    );
  U3_time_out_CYINIT_603 : X_BUF
    port map (
      I => U3_cr_ros_n0251_11_cyo,
      O => U3_time_out_CYINIT
    );
  U3_Eq_stage_cyo1_LOGIC_ONE_604 : X_ONE
    port map (
      O => U3_Eq_stage_cyo1_LOGIC_ONE
    );
  U3_Eq_stage_cyo1_LOGIC_ZERO_605 : X_ZERO
    port map (
      O => U3_Eq_stage_cyo1_LOGIC_ZERO
    );
  U3_Eq_stagecy : X_MUX2
    port map (
      IA => U3_Eq_stage_cyo1_LOGIC_ZERO,
      IB => U3_Eq_stage_cyo1_LOGIC_ONE,
      SEL => U3_N21469,
      O => U3_Eq_stage_cyo
    );
  U3_Eq_stagelut : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => evid_0_IBUF,
      ADR1 => U3_header2_reg(12),
      ADR2 => evid_1_IBUF,
      ADR3 => U3_header2_reg(13),
      O => U3_N21469
    );
  U3_Eq_stagelut1 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => evid_2_IBUF,
      ADR1 => U3_header2_reg(14),
      ADR2 => evid_3_IBUF,
      ADR3 => U3_header2_reg(15),
      O => U3_N21472
    );
  U3_Eq_stage_cyo1_COUTUSED : X_BUF
    port map (
      I => U3_Eq_stage_cyo1_CYMUXG,
      O => U3_Eq_stage_cyo1
    );
  U3_Eq_stagecy_rn_0 : X_MUX2
    port map (
      IA => U3_Eq_stage_cyo1_LOGIC_ZERO,
      IB => U3_Eq_stage_cyo,
      SEL => U3_N21472,
      O => U3_Eq_stage_cyo1_CYMUXG
    );
  U3_Eq_stage_cyo3_LOGIC_ZERO_606 : X_ZERO
    port map (
      O => U3_Eq_stage_cyo3_LOGIC_ZERO
    );
  U3_Eq_stagecy_rn_1 : X_MUX2
    port map (
      IA => U3_Eq_stage_cyo3_LOGIC_ZERO,
      IB => U3_Eq_stage_cyo3_CYINIT,
      SEL => U3_N21475,
      O => U3_Eq_stage_cyo2
    );
  U3_Eq_stagelut2 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => evid_4_IBUF,
      ADR1 => U3_header1_reg(0),
      ADR2 => evid_5_IBUF,
      ADR3 => U3_header1_reg(1),
      O => U3_N21475
    );
  U3_Eq_stagelut3 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => evid_6_IBUF,
      ADR1 => U3_header1_reg(2),
      ADR2 => evid_7_IBUF,
      ADR3 => U3_header1_reg(3),
      O => U3_N21478
    );
  U3_Eq_stage_cyo3_COUTUSED : X_BUF
    port map (
      I => U3_Eq_stage_cyo3_CYMUXG,
      O => U3_Eq_stage_cyo3
    );
  U3_Eq_stagecy_rn_2 : X_MUX2
    port map (
      IA => U3_Eq_stage_cyo3_LOGIC_ZERO,
      IB => U3_Eq_stage_cyo2,
      SEL => U3_N21478,
      O => U3_Eq_stage_cyo3_CYMUXG
    );
  U3_Eq_stage_cyo3_CYINIT_607 : X_BUF
    port map (
      I => U3_Eq_stage_cyo1,
      O => U3_Eq_stage_cyo3_CYINIT
    );
  U3_n0150_LOGIC_ZERO_608 : X_ZERO
    port map (
      O => U3_n0150_LOGIC_ZERO
    );
  U3_Eq_stagecy_rn_3 : X_MUX2
    port map (
      IA => U3_n0150_LOGIC_ZERO,
      IB => U3_n0150_CYINIT,
      SEL => U3_N21481,
      O => U3_Eq_stage_cyo4
    );
  U3_Eq_stagelut4 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => evid_8_IBUF,
      ADR1 => U3_header1_reg(4),
      ADR2 => evid_9_IBUF,
      ADR3 => U3_header1_reg(5),
      O => U3_N21481
    );
  U3_Eq_stagelut5 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => evid_10_IBUF,
      ADR1 => U3_header1_reg(6),
      ADR2 => evid_11_IBUF,
      ADR3 => U3_header1_reg(7),
      O => U3_N21484
    );
  U3_n0150_COUTUSED : X_BUF
    port map (
      I => U3_n0150_CYMUXG,
      O => U3_n0150
    );
  U3_Eq_stagecy_rn_4 : X_MUX2
    port map (
      IA => U3_n0150_LOGIC_ZERO,
      IB => U3_Eq_stage_cyo4,
      SEL => U3_N21484,
      O => U3_n0150_CYMUXG
    );
  U3_n0150_CYINIT_609 : X_BUF
    port map (
      I => U3_Eq_stage_cyo3,
      O => U3_n0150_CYINIT
    );
  U2_loadcnt_n0002_1_LOGIC_ZERO_610 : X_ZERO
    port map (
      O => U2_loadcnt_n0002_1_LOGIC_ZERO
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U2_loadcnt_n0002_1_LOGIC_ZERO,
      SEL => U2_loadcnt_N21450,
      O => U2_loadcnt_LPM_COUNTER_2_n0002_0_cyo
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_0_lut : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U2_loadcnt(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_loadcnt_N21450
    );
  U2_loadcnt_n0002_1_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U2_loadcnt(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_loadcnt_n0002_1_GROM
    );
  U2_loadcnt_n0002_1_COUTUSED : X_BUF
    port map (
      I => U2_loadcnt_n0002_1_CYMUXG,
      O => U2_loadcnt_LPM_COUNTER_2_n0002_1_cyo
    );
  U2_loadcnt_n0002_1_YUSED : X_BUF
    port map (
      I => U2_loadcnt_n0002_1_XORG,
      O => U2_loadcnt_n0002(1)
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U2_loadcnt_LPM_COUNTER_2_n0002_0_cyo,
      SEL => U2_loadcnt_n0002_1_GROM,
      O => U2_loadcnt_n0002_1_CYMUXG
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_1_xor : X_XOR2
    port map (
      I0 => U2_loadcnt_LPM_COUNTER_2_n0002_0_cyo,
      I1 => U2_loadcnt_n0002_1_GROM,
      O => U2_loadcnt_n0002_1_XORG
    );
  U2_loadcnt_n0002_2_LOGIC_ZERO_611 : X_ZERO
    port map (
      O => U2_loadcnt_n0002_2_LOGIC_ZERO
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_2_cy : X_MUX2
    port map (
      IA => U2_loadcnt_n0002_2_LOGIC_ZERO,
      IB => U2_loadcnt_n0002_2_CYINIT,
      SEL => U2_loadcnt_n0002_2_FROM,
      O => U2_loadcnt_LPM_COUNTER_2_n0002_2_cyo
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_2_xor : X_XOR2
    port map (
      I0 => U2_loadcnt_n0002_2_CYINIT,
      I1 => U2_loadcnt_n0002_2_FROM,
      O => U2_loadcnt_n0002_2_XORF
    );
  U2_loadcnt_n0002_2_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U2_loadcnt(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_loadcnt_n0002_2_FROM
    );
  U2_loadcnt_n0002_2_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U2_loadcnt(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_loadcnt_n0002_2_GROM
    );
  U2_loadcnt_n0002_2_COUTUSED : X_BUF
    port map (
      I => U2_loadcnt_n0002_2_CYMUXG,
      O => U2_loadcnt_LPM_COUNTER_2_n0002_3_cyo
    );
  U2_loadcnt_n0002_2_XUSED : X_BUF
    port map (
      I => U2_loadcnt_n0002_2_XORF,
      O => U2_loadcnt_n0002(2)
    );
  U2_loadcnt_n0002_2_YUSED : X_BUF
    port map (
      I => U2_loadcnt_n0002_2_XORG,
      O => U2_loadcnt_n0002(3)
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_3_cy : X_MUX2
    port map (
      IA => U2_loadcnt_n0002_2_LOGIC_ZERO,
      IB => U2_loadcnt_LPM_COUNTER_2_n0002_2_cyo,
      SEL => U2_loadcnt_n0002_2_GROM,
      O => U2_loadcnt_n0002_2_CYMUXG
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_3_xor : X_XOR2
    port map (
      I0 => U2_loadcnt_LPM_COUNTER_2_n0002_2_cyo,
      I1 => U2_loadcnt_n0002_2_GROM,
      O => U2_loadcnt_n0002_2_XORG
    );
  U2_loadcnt_n0002_2_CYINIT_612 : X_BUF
    port map (
      I => U2_loadcnt_LPM_COUNTER_2_n0002_1_cyo,
      O => U2_loadcnt_n0002_2_CYINIT
    );
  U2_loadcnt_n0002_4_LOGIC_ZERO_613 : X_ZERO
    port map (
      O => U2_loadcnt_n0002_4_LOGIC_ZERO
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_4_cy : X_MUX2
    port map (
      IA => U2_loadcnt_n0002_4_LOGIC_ZERO,
      IB => U2_loadcnt_n0002_4_CYINIT,
      SEL => U2_loadcnt_n0002_4_FROM,
      O => U2_loadcnt_LPM_COUNTER_2_n0002_4_cyo
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_4_xor : X_XOR2
    port map (
      I0 => U2_loadcnt_n0002_4_CYINIT,
      I1 => U2_loadcnt_n0002_4_FROM,
      O => U2_loadcnt_n0002_4_XORF
    );
  U2_loadcnt_n0002_4_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U2_loadcnt(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_loadcnt_n0002_4_FROM
    );
  U2_loadcnt_5_rt_614 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U2_loadcnt(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_loadcnt_5_rt
    );
  U2_loadcnt_n0002_4_XUSED : X_BUF
    port map (
      I => U2_loadcnt_n0002_4_XORF,
      O => U2_loadcnt_n0002(4)
    );
  U2_loadcnt_n0002_4_YUSED : X_BUF
    port map (
      I => U2_loadcnt_n0002_4_XORG,
      O => U2_loadcnt_n0002(5)
    );
  U2_loadcnt_LPM_COUNTER_2_n0002_5_xor : X_XOR2
    port map (
      I0 => U2_loadcnt_LPM_COUNTER_2_n0002_4_cyo,
      I1 => U2_loadcnt_5_rt,
      O => U2_loadcnt_n0002_4_XORG
    );
  U2_loadcnt_n0002_4_CYINIT_615 : X_BUF
    port map (
      I => U2_loadcnt_LPM_COUNTER_2_n0002_3_cyo,
      O => U2_loadcnt_n0002_4_CYINIT
    );
  U1_paf_counter_0_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_0_FFY_RST
    );
  U1_paf_counter_0_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_0,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_0_FFY_RST,
      O => U1_paf_counter_0(0)
    );
  U1_paf_counter_0_0_LOGIC_ZERO_616 : X_ZERO
    port map (
      O => U1_paf_counter_0_0_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_0_617 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U1_paf_counter_0_0_LOGIC_ZERO,
      SEL => U1_enw_paf_counter1_3_rt,
      O => U1_paf_counter_0_inst_cy_0
    );
  U1_enw_paf_counter1_3_rt_618 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U1_enw_paf_counter1_3,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_enw_paf_counter1_3_rt
    );
  U1_paf_counter_0_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U1_enw_paf_counter,
      ADR2 => N44072,
      ADR3 => U1_paf_counter_0(0),
      O => U1_paf_counter_0_inst_lut3_0
    );
  U1_paf_counter_0_0_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_0_CYMUXG,
      O => U1_paf_counter_0_inst_cy_1
    );
  U1_paf_counter_0_inst_cy_1_619 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U1_paf_counter_0_inst_cy_0,
      SEL => U1_paf_counter_0_inst_lut3_0,
      O => U1_paf_counter_0_0_CYMUXG
    );
  U1_paf_counter_0_inst_sum_0_620 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_0,
      I1 => U1_paf_counter_0_inst_lut3_0,
      O => U1_paf_counter_0_inst_sum_0
    );
  U1_paf_counter_0_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_1_FFY_RST
    );
  U1_paf_counter_0_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_2,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_1_FFY_RST,
      O => U1_paf_counter_0(2)
    );
  U1_paf_counter_0_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_1_FFX_RST
    );
  U1_paf_counter_0_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_1,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_1_FFX_RST,
      O => U1_paf_counter_0(1)
    );
  U1_paf_counter_0_1_LOGIC_ZERO_621 : X_ZERO
    port map (
      O => U1_paf_counter_0_1_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_2_622 : X_MUX2
    port map (
      IA => U1_paf_counter_0_1_LOGIC_ZERO,
      IB => U1_paf_counter_0_1_CYINIT,
      SEL => U1_paf_counter_0_inst_lut3_1,
      O => U1_paf_counter_0_inst_cy_2
    );
  U1_paf_counter_0_inst_sum_1_623 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_1_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_1,
      O => U1_paf_counter_0_inst_sum_1
    );
  U1_paf_counter_0_inst_lut3_16 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44074,
      ADR2 => U1_paf_counter_0(1),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_1
    );
  U1_paf_counter_0_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44076,
      ADR2 => U1_paf_counter_0(2),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_2
    );
  U1_paf_counter_0_1_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_1_CYMUXG,
      O => U1_paf_counter_0_inst_cy_3
    );
  U1_paf_counter_0_inst_cy_3_624 : X_MUX2
    port map (
      IA => U1_paf_counter_0_1_LOGIC_ZERO,
      IB => U1_paf_counter_0_inst_cy_2,
      SEL => U1_paf_counter_0_inst_lut3_2,
      O => U1_paf_counter_0_1_CYMUXG
    );
  U1_paf_counter_0_inst_sum_2_625 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_2,
      I1 => U1_paf_counter_0_inst_lut3_2,
      O => U1_paf_counter_0_inst_sum_2
    );
  U1_paf_counter_0_1_CYINIT_626 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_1,
      O => U1_paf_counter_0_1_CYINIT
    );
  U1_paf_counter_0_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_3_FFY_RST
    );
  U1_paf_counter_0_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_4,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_3_FFY_RST,
      O => U1_paf_counter_0(4)
    );
  U1_paf_counter_0_3_LOGIC_ZERO_627 : X_ZERO
    port map (
      O => U1_paf_counter_0_3_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_4_628 : X_MUX2
    port map (
      IA => U1_paf_counter_0_3_LOGIC_ZERO,
      IB => U1_paf_counter_0_3_CYINIT,
      SEL => U1_paf_counter_0_inst_lut3_3,
      O => U1_paf_counter_0_inst_cy_4
    );
  U1_paf_counter_0_inst_sum_3_629 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_3_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_3,
      O => U1_paf_counter_0_inst_sum_3
    );
  U1_paf_counter_0_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44078,
      ADR2 => U1_paf_counter_0(3),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_3
    );
  U1_paf_counter_0_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44080,
      ADR2 => U1_paf_counter_0(4),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_4
    );
  U1_paf_counter_0_3_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_3_CYMUXG,
      O => U1_paf_counter_0_inst_cy_5
    );
  U1_paf_counter_0_inst_cy_5_630 : X_MUX2
    port map (
      IA => U1_paf_counter_0_3_LOGIC_ZERO,
      IB => U1_paf_counter_0_inst_cy_4,
      SEL => U1_paf_counter_0_inst_lut3_4,
      O => U1_paf_counter_0_3_CYMUXG
    );
  U1_paf_counter_0_inst_sum_4_631 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_4,
      I1 => U1_paf_counter_0_inst_lut3_4,
      O => U1_paf_counter_0_inst_sum_4
    );
  U1_paf_counter_0_3_CYINIT_632 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_3,
      O => U1_paf_counter_0_3_CYINIT
    );
  U1_paf_counter_0_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_5_FFY_RST
    );
  U1_paf_counter_0_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_6,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_5_FFY_RST,
      O => U1_paf_counter_0(6)
    );
  U1_paf_counter_0_5_LOGIC_ZERO_633 : X_ZERO
    port map (
      O => U1_paf_counter_0_5_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_6_634 : X_MUX2
    port map (
      IA => U1_paf_counter_0_5_LOGIC_ZERO,
      IB => U1_paf_counter_0_5_CYINIT,
      SEL => U1_paf_counter_0_inst_lut3_5,
      O => U1_paf_counter_0_inst_cy_6
    );
  U1_paf_counter_0_inst_sum_5_635 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_5_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_5,
      O => U1_paf_counter_0_inst_sum_5
    );
  U1_paf_counter_0_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44082,
      ADR2 => U1_paf_counter_0(5),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_5
    );
  U1_paf_counter_0_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44084,
      ADR2 => U1_paf_counter_0(6),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_6
    );
  U1_paf_counter_0_5_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_5_CYMUXG,
      O => U1_paf_counter_0_inst_cy_7
    );
  U1_paf_counter_0_inst_cy_7_636 : X_MUX2
    port map (
      IA => U1_paf_counter_0_5_LOGIC_ZERO,
      IB => U1_paf_counter_0_inst_cy_6,
      SEL => U1_paf_counter_0_inst_lut3_6,
      O => U1_paf_counter_0_5_CYMUXG
    );
  U1_paf_counter_0_inst_sum_6_637 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_6,
      I1 => U1_paf_counter_0_inst_lut3_6,
      O => U1_paf_counter_0_inst_sum_6
    );
  U1_paf_counter_0_5_CYINIT_638 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_5,
      O => U1_paf_counter_0_5_CYINIT
    );
  U1_paf_counter_0_7_LOGIC_ZERO_639 : X_ZERO
    port map (
      O => U1_paf_counter_0_7_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_8_640 : X_MUX2
    port map (
      IA => U1_paf_counter_0_7_LOGIC_ZERO,
      IB => U1_paf_counter_0_7_CYINIT,
      SEL => U1_paf_counter_0_inst_lut3_7,
      O => U1_paf_counter_0_inst_cy_8
    );
  U1_paf_counter_0_inst_sum_7_641 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_7_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_7,
      O => U1_paf_counter_0_inst_sum_7
    );
  U1_paf_counter_0_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44086,
      ADR2 => U1_paf_counter_0(7),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_7
    );
  U1_paf_counter_0_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44088,
      ADR2 => U1_paf_counter_0(8),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_8
    );
  U1_paf_counter_0_7_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_7_CYMUXG,
      O => U1_paf_counter_0_inst_cy_9
    );
  U1_paf_counter_0_inst_cy_9_642 : X_MUX2
    port map (
      IA => U1_paf_counter_0_7_LOGIC_ZERO,
      IB => U1_paf_counter_0_inst_cy_8,
      SEL => U1_paf_counter_0_inst_lut3_8,
      O => U1_paf_counter_0_7_CYMUXG
    );
  U1_paf_counter_0_inst_sum_8_643 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_8,
      I1 => U1_paf_counter_0_inst_lut3_8,
      O => U1_paf_counter_0_inst_sum_8
    );
  U1_paf_counter_0_7_CYINIT_644 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_7,
      O => U1_paf_counter_0_7_CYINIT
    );
  U1_paf_counter_0_9_LOGIC_ZERO_645 : X_ZERO
    port map (
      O => U1_paf_counter_0_9_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_10_646 : X_MUX2
    port map (
      IA => U1_paf_counter_0_9_LOGIC_ZERO,
      IB => U1_paf_counter_0_9_CYINIT,
      SEL => U1_paf_counter_0_inst_lut3_9,
      O => U1_paf_counter_0_inst_cy_10
    );
  U1_paf_counter_0_inst_sum_9_647 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_9_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_9,
      O => U1_paf_counter_0_inst_sum_9
    );
  U1_paf_counter_0_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44090,
      ADR2 => U1_paf_counter_0(9),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_9
    );
  U1_paf_counter_0_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44092,
      ADR2 => U1_paf_counter_0(10),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_10
    );
  U1_paf_counter_0_9_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_9_CYMUXG,
      O => U1_paf_counter_0_inst_cy_11
    );
  U1_paf_counter_0_inst_cy_11_648 : X_MUX2
    port map (
      IA => U1_paf_counter_0_9_LOGIC_ZERO,
      IB => U1_paf_counter_0_inst_cy_10,
      SEL => U1_paf_counter_0_inst_lut3_10,
      O => U1_paf_counter_0_9_CYMUXG
    );
  U1_paf_counter_0_inst_sum_10_649 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_10,
      I1 => U1_paf_counter_0_inst_lut3_10,
      O => U1_paf_counter_0_inst_sum_10
    );
  U1_paf_counter_0_9_CYINIT_650 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_9,
      O => U1_paf_counter_0_9_CYINIT
    );
  U1_paf_counter_0_11_LOGIC_ZERO_651 : X_ZERO
    port map (
      O => U1_paf_counter_0_11_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_12_652 : X_MUX2
    port map (
      IA => U1_paf_counter_0_11_LOGIC_ZERO,
      IB => U1_paf_counter_0_11_CYINIT,
      SEL => U1_paf_counter_0_inst_lut3_11,
      O => U1_paf_counter_0_inst_cy_12
    );
  U1_paf_counter_0_inst_sum_11_653 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_11_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_11,
      O => U1_paf_counter_0_inst_sum_11
    );
  U1_paf_counter_0_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44094,
      ADR2 => U1_paf_counter_0(11),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_11
    );
  U1_paf_counter_0_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44096,
      ADR2 => U1_paf_counter_0(12),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_12
    );
  U1_paf_counter_0_11_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_11_CYMUXG,
      O => U1_paf_counter_0_inst_cy_13
    );
  U1_paf_counter_0_inst_cy_13_654 : X_MUX2
    port map (
      IA => U1_paf_counter_0_11_LOGIC_ZERO,
      IB => U1_paf_counter_0_inst_cy_12,
      SEL => U1_paf_counter_0_inst_lut3_12,
      O => U1_paf_counter_0_11_CYMUXG
    );
  U1_paf_counter_0_inst_sum_12_655 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_12,
      I1 => U1_paf_counter_0_inst_lut3_12,
      O => U1_paf_counter_0_inst_sum_12
    );
  U1_paf_counter_0_11_CYINIT_656 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_11,
      O => U1_paf_counter_0_11_CYINIT
    );
  U1_paf_counter_0_13_LOGIC_ZERO_657 : X_ZERO
    port map (
      O => U1_paf_counter_0_13_LOGIC_ZERO
    );
  U1_paf_counter_0_inst_cy_14_658 : X_MUX2
    port map (
      IA => U1_paf_counter_0_13_LOGIC_ZERO,
      IB => U1_paf_counter_0_13_CYINIT,
      SEL => U1_paf_counter_0_inst_lut3_13,
      O => U1_paf_counter_0_inst_cy_14
    );
  U1_paf_counter_0_inst_sum_13_659 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_13_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_13,
      O => U1_paf_counter_0_inst_sum_13
    );
  U1_paf_counter_0_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44098,
      ADR2 => U1_paf_counter_0(13),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_13
    );
  U1_paf_counter_0_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44100,
      ADR2 => U1_paf_counter_0(14),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_14
    );
  U1_paf_counter_0_13_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_0_13_CYMUXG,
      O => U1_paf_counter_0_inst_cy_15
    );
  U1_paf_counter_0_inst_cy_15_660 : X_MUX2
    port map (
      IA => U1_paf_counter_0_13_LOGIC_ZERO,
      IB => U1_paf_counter_0_inst_cy_14,
      SEL => U1_paf_counter_0_inst_lut3_14,
      O => U1_paf_counter_0_13_CYMUXG
    );
  U1_paf_counter_0_inst_sum_14_661 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_inst_cy_14,
      I1 => U1_paf_counter_0_inst_lut3_14,
      O => U1_paf_counter_0_inst_sum_14
    );
  U1_paf_counter_0_13_CYINIT_662 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_13,
      O => U1_paf_counter_0_13_CYINIT
    );
  U1_paf_counter_0_inst_sum_15_663 : X_XOR2
    port map (
      I0 => U1_paf_counter_0_15_CYINIT,
      I1 => U1_paf_counter_0_inst_lut3_15,
      O => U1_paf_counter_0_inst_sum_15
    );
  U1_paf_counter_0_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44102,
      ADR2 => U1_paf_counter_0(15),
      ADR3 => VCC,
      O => U1_paf_counter_0_inst_lut3_15
    );
  U1_n01831 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => U1_paf_cnt_set(5),
      ADR2 => paf_5_IBUF,
      ADR3 => VCC,
      O => U1_paf_counter_0_15_GROM
    );
  U1_paf_counter_0_15_YUSED : X_BUF
    port map (
      I => U1_paf_counter_0_15_GROM,
      O => U1_n0183
    );
  U1_paf_counter_0_15_CYINIT_664 : X_BUF
    port map (
      I => U1_paf_counter_0_inst_cy_15,
      O => U1_paf_counter_0_15_CYINIT
    );
  U1_paf_counter_1_0_LOGIC_ZERO_665 : X_ZERO
    port map (
      O => U1_paf_counter_1_0_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_0_666 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U1_paf_counter_1_0_LOGIC_ZERO,
      SEL => Q_SIG_0,
      O => U1_paf_counter_1_inst_cy_0
    );
  Q_BEL_0 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U1_enw_paf_counter1_3,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_SIG_0
    );
  U1_paf_counter_1_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U1_enw_paf_counter,
      ADR2 => N44072,
      ADR3 => U1_paf_counter_1(0),
      O => U1_paf_counter_1_inst_lut3_0
    );
  U1_paf_counter_1_0_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_0_CYMUXG,
      O => U1_paf_counter_1_inst_cy_1
    );
  U1_paf_counter_1_inst_cy_1_667 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U1_paf_counter_1_inst_cy_0,
      SEL => U1_paf_counter_1_inst_lut3_0,
      O => U1_paf_counter_1_0_CYMUXG
    );
  U1_paf_counter_1_inst_sum_0_668 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_0,
      I1 => U1_paf_counter_1_inst_lut3_0,
      O => U1_paf_counter_1_inst_sum_0
    );
  U1_paf_counter_1_1_LOGIC_ZERO_669 : X_ZERO
    port map (
      O => U1_paf_counter_1_1_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_2_670 : X_MUX2
    port map (
      IA => U1_paf_counter_1_1_LOGIC_ZERO,
      IB => U1_paf_counter_1_1_CYINIT,
      SEL => U1_paf_counter_1_inst_lut3_1,
      O => U1_paf_counter_1_inst_cy_2
    );
  U1_paf_counter_1_inst_sum_1_671 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_1_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_1,
      O => U1_paf_counter_1_inst_sum_1
    );
  U1_paf_counter_1_inst_lut3_16 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44074,
      ADR2 => U1_paf_counter_1(1),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_1
    );
  U1_paf_counter_1_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44076,
      ADR2 => U1_paf_counter_1(2),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_2
    );
  U1_paf_counter_1_1_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_1_CYMUXG,
      O => U1_paf_counter_1_inst_cy_3
    );
  U1_paf_counter_1_inst_cy_3_672 : X_MUX2
    port map (
      IA => U1_paf_counter_1_1_LOGIC_ZERO,
      IB => U1_paf_counter_1_inst_cy_2,
      SEL => U1_paf_counter_1_inst_lut3_2,
      O => U1_paf_counter_1_1_CYMUXG
    );
  U1_paf_counter_1_inst_sum_2_673 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_2,
      I1 => U1_paf_counter_1_inst_lut3_2,
      O => U1_paf_counter_1_inst_sum_2
    );
  U1_paf_counter_1_1_CYINIT_674 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_1,
      O => U1_paf_counter_1_1_CYINIT
    );
  U1_paf_counter_1_3_LOGIC_ZERO_675 : X_ZERO
    port map (
      O => U1_paf_counter_1_3_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_4_676 : X_MUX2
    port map (
      IA => U1_paf_counter_1_3_LOGIC_ZERO,
      IB => U1_paf_counter_1_3_CYINIT,
      SEL => U1_paf_counter_1_inst_lut3_3,
      O => U1_paf_counter_1_inst_cy_4
    );
  U1_paf_counter_1_inst_sum_3_677 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_3_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_3,
      O => U1_paf_counter_1_inst_sum_3
    );
  U1_paf_counter_1_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44078,
      ADR2 => U1_paf_counter_1(3),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_3
    );
  U1_paf_counter_1_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44080,
      ADR2 => U1_paf_counter_1(4),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_4
    );
  U1_paf_counter_1_3_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_3_CYMUXG,
      O => U1_paf_counter_1_inst_cy_5
    );
  U1_paf_counter_1_inst_cy_5_678 : X_MUX2
    port map (
      IA => U1_paf_counter_1_3_LOGIC_ZERO,
      IB => U1_paf_counter_1_inst_cy_4,
      SEL => U1_paf_counter_1_inst_lut3_4,
      O => U1_paf_counter_1_3_CYMUXG
    );
  U1_paf_counter_1_inst_sum_4_679 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_4,
      I1 => U1_paf_counter_1_inst_lut3_4,
      O => U1_paf_counter_1_inst_sum_4
    );
  U1_paf_counter_1_3_CYINIT_680 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_3,
      O => U1_paf_counter_1_3_CYINIT
    );
  U1_paf_counter_1_5_LOGIC_ZERO_681 : X_ZERO
    port map (
      O => U1_paf_counter_1_5_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_6_682 : X_MUX2
    port map (
      IA => U1_paf_counter_1_5_LOGIC_ZERO,
      IB => U1_paf_counter_1_5_CYINIT,
      SEL => U1_paf_counter_1_inst_lut3_5,
      O => U1_paf_counter_1_inst_cy_6
    );
  U1_paf_counter_1_inst_sum_5_683 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_5_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_5,
      O => U1_paf_counter_1_inst_sum_5
    );
  U1_paf_counter_1_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44082,
      ADR2 => U1_paf_counter_1(5),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_5
    );
  U1_paf_counter_1_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44084,
      ADR2 => U1_paf_counter_1(6),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_6
    );
  U1_paf_counter_1_5_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_5_CYMUXG,
      O => U1_paf_counter_1_inst_cy_7
    );
  U1_paf_counter_1_inst_cy_7_684 : X_MUX2
    port map (
      IA => U1_paf_counter_1_5_LOGIC_ZERO,
      IB => U1_paf_counter_1_inst_cy_6,
      SEL => U1_paf_counter_1_inst_lut3_6,
      O => U1_paf_counter_1_5_CYMUXG
    );
  U1_paf_counter_1_inst_sum_6_685 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_6,
      I1 => U1_paf_counter_1_inst_lut3_6,
      O => U1_paf_counter_1_inst_sum_6
    );
  U1_paf_counter_1_5_CYINIT_686 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_5,
      O => U1_paf_counter_1_5_CYINIT
    );
  U1_paf_counter_1_7_LOGIC_ZERO_687 : X_ZERO
    port map (
      O => U1_paf_counter_1_7_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_8_688 : X_MUX2
    port map (
      IA => U1_paf_counter_1_7_LOGIC_ZERO,
      IB => U1_paf_counter_1_7_CYINIT,
      SEL => U1_paf_counter_1_inst_lut3_7,
      O => U1_paf_counter_1_inst_cy_8
    );
  U1_paf_counter_1_inst_sum_7_689 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_7_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_7,
      O => U1_paf_counter_1_inst_sum_7
    );
  U1_paf_counter_1_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44086,
      ADR2 => U1_paf_counter_1(7),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_7
    );
  U1_paf_counter_1_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44088,
      ADR2 => U1_paf_counter_1(8),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_8
    );
  U1_paf_counter_1_7_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_7_CYMUXG,
      O => U1_paf_counter_1_inst_cy_9
    );
  U1_paf_counter_1_inst_cy_9_690 : X_MUX2
    port map (
      IA => U1_paf_counter_1_7_LOGIC_ZERO,
      IB => U1_paf_counter_1_inst_cy_8,
      SEL => U1_paf_counter_1_inst_lut3_8,
      O => U1_paf_counter_1_7_CYMUXG
    );
  U1_paf_counter_1_inst_sum_8_691 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_8,
      I1 => U1_paf_counter_1_inst_lut3_8,
      O => U1_paf_counter_1_inst_sum_8
    );
  U1_paf_counter_1_7_CYINIT_692 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_7,
      O => U1_paf_counter_1_7_CYINIT
    );
  U1_paf_counter_1_9_LOGIC_ZERO_693 : X_ZERO
    port map (
      O => U1_paf_counter_1_9_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_10_694 : X_MUX2
    port map (
      IA => U1_paf_counter_1_9_LOGIC_ZERO,
      IB => U1_paf_counter_1_9_CYINIT,
      SEL => U1_paf_counter_1_inst_lut3_9,
      O => U1_paf_counter_1_inst_cy_10
    );
  U1_paf_counter_1_inst_sum_9_695 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_9_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_9,
      O => U1_paf_counter_1_inst_sum_9
    );
  U1_paf_counter_1_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44090,
      ADR2 => U1_paf_counter_1(9),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_9
    );
  U1_paf_counter_1_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44092,
      ADR2 => U1_paf_counter_1(10),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_10
    );
  U1_paf_counter_1_9_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_9_CYMUXG,
      O => U1_paf_counter_1_inst_cy_11
    );
  U1_paf_counter_1_inst_cy_11_696 : X_MUX2
    port map (
      IA => U1_paf_counter_1_9_LOGIC_ZERO,
      IB => U1_paf_counter_1_inst_cy_10,
      SEL => U1_paf_counter_1_inst_lut3_10,
      O => U1_paf_counter_1_9_CYMUXG
    );
  U1_paf_counter_1_inst_sum_10_697 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_10,
      I1 => U1_paf_counter_1_inst_lut3_10,
      O => U1_paf_counter_1_inst_sum_10
    );
  U1_paf_counter_1_9_CYINIT_698 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_9,
      O => U1_paf_counter_1_9_CYINIT
    );
  U1_paf_counter_1_11_LOGIC_ZERO_699 : X_ZERO
    port map (
      O => U1_paf_counter_1_11_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_12_700 : X_MUX2
    port map (
      IA => U1_paf_counter_1_11_LOGIC_ZERO,
      IB => U1_paf_counter_1_11_CYINIT,
      SEL => U1_paf_counter_1_inst_lut3_11,
      O => U1_paf_counter_1_inst_cy_12
    );
  U1_paf_counter_1_inst_sum_11_701 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_11_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_11,
      O => U1_paf_counter_1_inst_sum_11
    );
  U1_paf_counter_1_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44094,
      ADR2 => U1_paf_counter_1(11),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_11
    );
  U1_paf_counter_1_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44096,
      ADR2 => U1_paf_counter_1(12),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_12
    );
  U1_paf_counter_1_11_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_11_CYMUXG,
      O => U1_paf_counter_1_inst_cy_13
    );
  U1_paf_counter_1_inst_cy_13_702 : X_MUX2
    port map (
      IA => U1_paf_counter_1_11_LOGIC_ZERO,
      IB => U1_paf_counter_1_inst_cy_12,
      SEL => U1_paf_counter_1_inst_lut3_12,
      O => U1_paf_counter_1_11_CYMUXG
    );
  U1_paf_counter_1_inst_sum_12_703 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_12,
      I1 => U1_paf_counter_1_inst_lut3_12,
      O => U1_paf_counter_1_inst_sum_12
    );
  U1_paf_counter_1_11_CYINIT_704 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_11,
      O => U1_paf_counter_1_11_CYINIT
    );
  U1_paf_counter_1_13_LOGIC_ZERO_705 : X_ZERO
    port map (
      O => U1_paf_counter_1_13_LOGIC_ZERO
    );
  U1_paf_counter_1_inst_cy_14_706 : X_MUX2
    port map (
      IA => U1_paf_counter_1_13_LOGIC_ZERO,
      IB => U1_paf_counter_1_13_CYINIT,
      SEL => U1_paf_counter_1_inst_lut3_13,
      O => U1_paf_counter_1_inst_cy_14
    );
  U1_paf_counter_1_inst_sum_13_707 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_13_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_13,
      O => U1_paf_counter_1_inst_sum_13
    );
  U1_paf_counter_1_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44098,
      ADR2 => U1_paf_counter_1(13),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_13
    );
  U1_paf_counter_1_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44100,
      ADR2 => U1_paf_counter_1(14),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_14
    );
  U1_paf_counter_1_13_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_1_13_CYMUXG,
      O => U1_paf_counter_1_inst_cy_15
    );
  U1_paf_counter_1_inst_cy_15_708 : X_MUX2
    port map (
      IA => U1_paf_counter_1_13_LOGIC_ZERO,
      IB => U1_paf_counter_1_inst_cy_14,
      SEL => U1_paf_counter_1_inst_lut3_14,
      O => U1_paf_counter_1_13_CYMUXG
    );
  U1_paf_counter_1_inst_sum_14_709 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_inst_cy_14,
      I1 => U1_paf_counter_1_inst_lut3_14,
      O => U1_paf_counter_1_inst_sum_14
    );
  U1_paf_counter_1_13_CYINIT_710 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_13,
      O => U1_paf_counter_1_13_CYINIT
    );
  U1_paf_counter_1_inst_sum_15_711 : X_XOR2
    port map (
      I0 => U1_paf_counter_1_15_CYINIT,
      I1 => U1_paf_counter_1_inst_lut3_15,
      O => U1_paf_counter_1_inst_sum_15
    );
  U1_paf_counter_1_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44102,
      ADR2 => U1_paf_counter_1(15),
      ADR3 => VCC,
      O => U1_paf_counter_1_inst_lut3_15
    );
  U1_n01851 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => U1_paf_cnt_set(4),
      ADR2 => paf_4_IBUF,
      ADR3 => VCC,
      O => U1_paf_counter_1_15_GROM
    );
  U1_paf_counter_1_15_YUSED : X_BUF
    port map (
      I => U1_paf_counter_1_15_GROM,
      O => U1_n0185
    );
  U1_paf_counter_1_15_CYINIT_712 : X_BUF
    port map (
      I => U1_paf_counter_1_inst_cy_15,
      O => U1_paf_counter_1_15_CYINIT
    );
  U1_paf_counter_2_0_LOGIC_ZERO_713 : X_ZERO
    port map (
      O => U1_paf_counter_2_0_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_0_714 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U1_paf_counter_2_0_LOGIC_ZERO,
      SEL => Q_SIG_1,
      O => U1_paf_counter_2_inst_cy_0
    );
  Q_BEL_1 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U1_enw_paf_counter1_3,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_SIG_1
    );
  U1_paf_counter_2_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U1_enw_paf_counter,
      ADR2 => N44072,
      ADR3 => U1_paf_counter_2(0),
      O => U1_paf_counter_2_inst_lut3_0
    );
  U1_paf_counter_2_0_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_0_CYMUXG,
      O => U1_paf_counter_2_inst_cy_1
    );
  U1_paf_counter_2_inst_cy_1_715 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U1_paf_counter_2_inst_cy_0,
      SEL => U1_paf_counter_2_inst_lut3_0,
      O => U1_paf_counter_2_0_CYMUXG
    );
  U1_paf_counter_2_inst_sum_0_716 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_0,
      I1 => U1_paf_counter_2_inst_lut3_0,
      O => U1_paf_counter_2_inst_sum_0
    );
  U1_paf_counter_2_1_LOGIC_ZERO_717 : X_ZERO
    port map (
      O => U1_paf_counter_2_1_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_2_718 : X_MUX2
    port map (
      IA => U1_paf_counter_2_1_LOGIC_ZERO,
      IB => U1_paf_counter_2_1_CYINIT,
      SEL => U1_paf_counter_2_inst_lut3_1,
      O => U1_paf_counter_2_inst_cy_2
    );
  U1_paf_counter_2_inst_sum_1_719 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_1_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_1,
      O => U1_paf_counter_2_inst_sum_1
    );
  U1_paf_counter_2_inst_lut3_16 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44074,
      ADR2 => U1_paf_counter_2(1),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_1
    );
  U1_paf_counter_2_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44076,
      ADR2 => U1_paf_counter_2(2),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_2
    );
  U1_paf_counter_2_1_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_1_CYMUXG,
      O => U1_paf_counter_2_inst_cy_3
    );
  U1_paf_counter_2_inst_cy_3_720 : X_MUX2
    port map (
      IA => U1_paf_counter_2_1_LOGIC_ZERO,
      IB => U1_paf_counter_2_inst_cy_2,
      SEL => U1_paf_counter_2_inst_lut3_2,
      O => U1_paf_counter_2_1_CYMUXG
    );
  U1_paf_counter_2_inst_sum_2_721 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_2,
      I1 => U1_paf_counter_2_inst_lut3_2,
      O => U1_paf_counter_2_inst_sum_2
    );
  U1_paf_counter_2_1_CYINIT_722 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_1,
      O => U1_paf_counter_2_1_CYINIT
    );
  U1_paf_counter_2_3_LOGIC_ZERO_723 : X_ZERO
    port map (
      O => U1_paf_counter_2_3_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_4_724 : X_MUX2
    port map (
      IA => U1_paf_counter_2_3_LOGIC_ZERO,
      IB => U1_paf_counter_2_3_CYINIT,
      SEL => U1_paf_counter_2_inst_lut3_3,
      O => U1_paf_counter_2_inst_cy_4
    );
  U1_paf_counter_2_inst_sum_3_725 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_3_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_3,
      O => U1_paf_counter_2_inst_sum_3
    );
  U1_paf_counter_2_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44078,
      ADR2 => U1_paf_counter_2(3),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_3
    );
  U1_paf_counter_2_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44080,
      ADR2 => U1_paf_counter_2(4),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_4
    );
  U1_paf_counter_2_3_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_3_CYMUXG,
      O => U1_paf_counter_2_inst_cy_5
    );
  U1_paf_counter_2_inst_cy_5_726 : X_MUX2
    port map (
      IA => U1_paf_counter_2_3_LOGIC_ZERO,
      IB => U1_paf_counter_2_inst_cy_4,
      SEL => U1_paf_counter_2_inst_lut3_4,
      O => U1_paf_counter_2_3_CYMUXG
    );
  U1_paf_counter_2_inst_sum_4_727 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_4,
      I1 => U1_paf_counter_2_inst_lut3_4,
      O => U1_paf_counter_2_inst_sum_4
    );
  U1_paf_counter_2_3_CYINIT_728 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_3,
      O => U1_paf_counter_2_3_CYINIT
    );
  U1_paf_counter_2_5_LOGIC_ZERO_729 : X_ZERO
    port map (
      O => U1_paf_counter_2_5_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_6_730 : X_MUX2
    port map (
      IA => U1_paf_counter_2_5_LOGIC_ZERO,
      IB => U1_paf_counter_2_5_CYINIT,
      SEL => U1_paf_counter_2_inst_lut3_5,
      O => U1_paf_counter_2_inst_cy_6
    );
  U1_paf_counter_2_inst_sum_5_731 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_5_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_5,
      O => U1_paf_counter_2_inst_sum_5
    );
  U1_paf_counter_2_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44082,
      ADR2 => U1_paf_counter_2(5),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_5
    );
  U1_paf_counter_2_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44084,
      ADR2 => U1_paf_counter_2(6),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_6
    );
  U1_paf_counter_2_5_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_5_CYMUXG,
      O => U1_paf_counter_2_inst_cy_7
    );
  U1_paf_counter_2_inst_cy_7_732 : X_MUX2
    port map (
      IA => U1_paf_counter_2_5_LOGIC_ZERO,
      IB => U1_paf_counter_2_inst_cy_6,
      SEL => U1_paf_counter_2_inst_lut3_6,
      O => U1_paf_counter_2_5_CYMUXG
    );
  U1_paf_counter_2_inst_sum_6_733 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_6,
      I1 => U1_paf_counter_2_inst_lut3_6,
      O => U1_paf_counter_2_inst_sum_6
    );
  U1_paf_counter_2_5_CYINIT_734 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_5,
      O => U1_paf_counter_2_5_CYINIT
    );
  U1_paf_counter_2_7_LOGIC_ZERO_735 : X_ZERO
    port map (
      O => U1_paf_counter_2_7_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_8_736 : X_MUX2
    port map (
      IA => U1_paf_counter_2_7_LOGIC_ZERO,
      IB => U1_paf_counter_2_7_CYINIT,
      SEL => U1_paf_counter_2_inst_lut3_7,
      O => U1_paf_counter_2_inst_cy_8
    );
  U1_paf_counter_2_inst_sum_7_737 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_7_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_7,
      O => U1_paf_counter_2_inst_sum_7
    );
  U1_paf_counter_2_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44086,
      ADR2 => U1_paf_counter_2(7),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_7
    );
  U1_paf_counter_2_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44088,
      ADR2 => U1_paf_counter_2(8),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_8
    );
  U1_paf_counter_2_7_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_7_CYMUXG,
      O => U1_paf_counter_2_inst_cy_9
    );
  U1_paf_counter_2_inst_cy_9_738 : X_MUX2
    port map (
      IA => U1_paf_counter_2_7_LOGIC_ZERO,
      IB => U1_paf_counter_2_inst_cy_8,
      SEL => U1_paf_counter_2_inst_lut3_8,
      O => U1_paf_counter_2_7_CYMUXG
    );
  U1_paf_counter_2_inst_sum_8_739 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_8,
      I1 => U1_paf_counter_2_inst_lut3_8,
      O => U1_paf_counter_2_inst_sum_8
    );
  U1_paf_counter_2_7_CYINIT_740 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_7,
      O => U1_paf_counter_2_7_CYINIT
    );
  U1_paf_counter_2_9_LOGIC_ZERO_741 : X_ZERO
    port map (
      O => U1_paf_counter_2_9_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_10_742 : X_MUX2
    port map (
      IA => U1_paf_counter_2_9_LOGIC_ZERO,
      IB => U1_paf_counter_2_9_CYINIT,
      SEL => U1_paf_counter_2_inst_lut3_9,
      O => U1_paf_counter_2_inst_cy_10
    );
  U1_paf_counter_2_inst_sum_9_743 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_9_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_9,
      O => U1_paf_counter_2_inst_sum_9
    );
  U1_paf_counter_2_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44090,
      ADR2 => U1_paf_counter_2(9),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_9
    );
  U1_paf_counter_2_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44092,
      ADR2 => U1_paf_counter_2(10),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_10
    );
  U1_paf_counter_2_9_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_9_CYMUXG,
      O => U1_paf_counter_2_inst_cy_11
    );
  U1_paf_counter_2_inst_cy_11_744 : X_MUX2
    port map (
      IA => U1_paf_counter_2_9_LOGIC_ZERO,
      IB => U1_paf_counter_2_inst_cy_10,
      SEL => U1_paf_counter_2_inst_lut3_10,
      O => U1_paf_counter_2_9_CYMUXG
    );
  U1_paf_counter_2_inst_sum_10_745 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_10,
      I1 => U1_paf_counter_2_inst_lut3_10,
      O => U1_paf_counter_2_inst_sum_10
    );
  U1_paf_counter_2_9_CYINIT_746 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_9,
      O => U1_paf_counter_2_9_CYINIT
    );
  U1_paf_counter_2_11_LOGIC_ZERO_747 : X_ZERO
    port map (
      O => U1_paf_counter_2_11_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_12_748 : X_MUX2
    port map (
      IA => U1_paf_counter_2_11_LOGIC_ZERO,
      IB => U1_paf_counter_2_11_CYINIT,
      SEL => U1_paf_counter_2_inst_lut3_11,
      O => U1_paf_counter_2_inst_cy_12
    );
  U1_paf_counter_2_inst_sum_11_749 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_11_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_11,
      O => U1_paf_counter_2_inst_sum_11
    );
  U1_paf_counter_2_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44094,
      ADR2 => U1_paf_counter_2(11),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_11
    );
  U1_paf_counter_2_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44096,
      ADR2 => U1_paf_counter_2(12),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_12
    );
  U1_paf_counter_2_11_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_11_CYMUXG,
      O => U1_paf_counter_2_inst_cy_13
    );
  U1_paf_counter_2_inst_cy_13_750 : X_MUX2
    port map (
      IA => U1_paf_counter_2_11_LOGIC_ZERO,
      IB => U1_paf_counter_2_inst_cy_12,
      SEL => U1_paf_counter_2_inst_lut3_12,
      O => U1_paf_counter_2_11_CYMUXG
    );
  U1_paf_counter_2_inst_sum_12_751 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_12,
      I1 => U1_paf_counter_2_inst_lut3_12,
      O => U1_paf_counter_2_inst_sum_12
    );
  U1_paf_counter_2_11_CYINIT_752 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_11,
      O => U1_paf_counter_2_11_CYINIT
    );
  U1_paf_counter_2_13_LOGIC_ZERO_753 : X_ZERO
    port map (
      O => U1_paf_counter_2_13_LOGIC_ZERO
    );
  U1_paf_counter_2_inst_cy_14_754 : X_MUX2
    port map (
      IA => U1_paf_counter_2_13_LOGIC_ZERO,
      IB => U1_paf_counter_2_13_CYINIT,
      SEL => U1_paf_counter_2_inst_lut3_13,
      O => U1_paf_counter_2_inst_cy_14
    );
  U1_paf_counter_2_inst_sum_13_755 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_13_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_13,
      O => U1_paf_counter_2_inst_sum_13
    );
  U1_paf_counter_2_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44098,
      ADR2 => U1_paf_counter_2(13),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_13
    );
  U1_paf_counter_2_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44100,
      ADR2 => U1_paf_counter_2(14),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_14
    );
  U1_paf_counter_2_13_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_2_13_CYMUXG,
      O => U1_paf_counter_2_inst_cy_15
    );
  U1_paf_counter_2_inst_cy_15_756 : X_MUX2
    port map (
      IA => U1_paf_counter_2_13_LOGIC_ZERO,
      IB => U1_paf_counter_2_inst_cy_14,
      SEL => U1_paf_counter_2_inst_lut3_14,
      O => U1_paf_counter_2_13_CYMUXG
    );
  U1_paf_counter_2_inst_sum_14_757 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_inst_cy_14,
      I1 => U1_paf_counter_2_inst_lut3_14,
      O => U1_paf_counter_2_inst_sum_14
    );
  U1_paf_counter_2_13_CYINIT_758 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_13,
      O => U1_paf_counter_2_13_CYINIT
    );
  U1_paf_counter_2_inst_sum_15_759 : X_XOR2
    port map (
      I0 => U1_paf_counter_2_15_CYINIT,
      I1 => U1_paf_counter_2_inst_lut3_15,
      O => U1_paf_counter_2_inst_sum_15
    );
  U1_paf_counter_2_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44102,
      ADR2 => U1_paf_counter_2(15),
      ADR3 => VCC,
      O => U1_paf_counter_2_inst_lut3_15
    );
  U1_n01871 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => U1_paf_cnt_set(3),
      ADR2 => paf_3_IBUF,
      ADR3 => VCC,
      O => U1_paf_counter_2_15_GROM
    );
  U1_paf_counter_2_15_YUSED : X_BUF
    port map (
      I => U1_paf_counter_2_15_GROM,
      O => U1_n0187
    );
  U1_paf_counter_2_15_CYINIT_760 : X_BUF
    port map (
      I => U1_paf_counter_2_inst_cy_15,
      O => U1_paf_counter_2_15_CYINIT
    );
  U1_paf_counter_3_0_LOGIC_ZERO_761 : X_ZERO
    port map (
      O => U1_paf_counter_3_0_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_0_762 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U1_paf_counter_3_0_LOGIC_ZERO,
      SEL => Q_SIG_2,
      O => U1_paf_counter_3_inst_cy_0
    );
  Q_BEL_2 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U1_enw_paf_counter1_3,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_SIG_2
    );
  U1_paf_counter_3_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U1_enw_paf_counter,
      ADR2 => N44072,
      ADR3 => U1_paf_counter_3(0),
      O => U1_paf_counter_3_inst_lut3_0
    );
  U1_paf_counter_3_0_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_0_CYMUXG,
      O => U1_paf_counter_3_inst_cy_1
    );
  U1_paf_counter_3_inst_cy_1_763 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U1_paf_counter_3_inst_cy_0,
      SEL => U1_paf_counter_3_inst_lut3_0,
      O => U1_paf_counter_3_0_CYMUXG
    );
  U1_paf_counter_3_inst_sum_0_764 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_0,
      I1 => U1_paf_counter_3_inst_lut3_0,
      O => U1_paf_counter_3_inst_sum_0
    );
  U1_paf_counter_3_1_LOGIC_ZERO_765 : X_ZERO
    port map (
      O => U1_paf_counter_3_1_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_2_766 : X_MUX2
    port map (
      IA => U1_paf_counter_3_1_LOGIC_ZERO,
      IB => U1_paf_counter_3_1_CYINIT,
      SEL => U1_paf_counter_3_inst_lut3_1,
      O => U1_paf_counter_3_inst_cy_2
    );
  U1_paf_counter_3_inst_sum_1_767 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_1_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_1,
      O => U1_paf_counter_3_inst_sum_1
    );
  U1_paf_counter_3_inst_lut3_16 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44074,
      ADR2 => U1_paf_counter_3(1),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_1
    );
  U1_paf_counter_3_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44076,
      ADR2 => U1_paf_counter_3(2),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_2
    );
  U1_paf_counter_3_1_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_1_CYMUXG,
      O => U1_paf_counter_3_inst_cy_3
    );
  U1_paf_counter_3_inst_cy_3_768 : X_MUX2
    port map (
      IA => U1_paf_counter_3_1_LOGIC_ZERO,
      IB => U1_paf_counter_3_inst_cy_2,
      SEL => U1_paf_counter_3_inst_lut3_2,
      O => U1_paf_counter_3_1_CYMUXG
    );
  U1_paf_counter_3_inst_sum_2_769 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_2,
      I1 => U1_paf_counter_3_inst_lut3_2,
      O => U1_paf_counter_3_inst_sum_2
    );
  U1_paf_counter_3_1_CYINIT_770 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_1,
      O => U1_paf_counter_3_1_CYINIT
    );
  U1_paf_counter_3_3_LOGIC_ZERO_771 : X_ZERO
    port map (
      O => U1_paf_counter_3_3_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_4_772 : X_MUX2
    port map (
      IA => U1_paf_counter_3_3_LOGIC_ZERO,
      IB => U1_paf_counter_3_3_CYINIT,
      SEL => U1_paf_counter_3_inst_lut3_3,
      O => U1_paf_counter_3_inst_cy_4
    );
  U1_paf_counter_3_inst_sum_3_773 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_3_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_3,
      O => U1_paf_counter_3_inst_sum_3
    );
  U1_paf_counter_3_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44078,
      ADR2 => U1_paf_counter_3(3),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_3
    );
  U1_paf_counter_3_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44080,
      ADR2 => U1_paf_counter_3(4),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_4
    );
  U1_paf_counter_3_3_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_3_CYMUXG,
      O => U1_paf_counter_3_inst_cy_5
    );
  U1_paf_counter_3_inst_cy_5_774 : X_MUX2
    port map (
      IA => U1_paf_counter_3_3_LOGIC_ZERO,
      IB => U1_paf_counter_3_inst_cy_4,
      SEL => U1_paf_counter_3_inst_lut3_4,
      O => U1_paf_counter_3_3_CYMUXG
    );
  U1_paf_counter_3_inst_sum_4_775 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_4,
      I1 => U1_paf_counter_3_inst_lut3_4,
      O => U1_paf_counter_3_inst_sum_4
    );
  U1_paf_counter_3_3_CYINIT_776 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_3,
      O => U1_paf_counter_3_3_CYINIT
    );
  U1_paf_counter_3_5_LOGIC_ZERO_777 : X_ZERO
    port map (
      O => U1_paf_counter_3_5_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_6_778 : X_MUX2
    port map (
      IA => U1_paf_counter_3_5_LOGIC_ZERO,
      IB => U1_paf_counter_3_5_CYINIT,
      SEL => U1_paf_counter_3_inst_lut3_5,
      O => U1_paf_counter_3_inst_cy_6
    );
  U1_paf_counter_3_inst_sum_5_779 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_5_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_5,
      O => U1_paf_counter_3_inst_sum_5
    );
  U1_paf_counter_3_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44082,
      ADR2 => U1_paf_counter_3(5),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_5
    );
  U1_paf_counter_3_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44084,
      ADR2 => U1_paf_counter_3(6),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_6
    );
  U1_paf_counter_3_5_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_5_CYMUXG,
      O => U1_paf_counter_3_inst_cy_7
    );
  U1_paf_counter_3_inst_cy_7_780 : X_MUX2
    port map (
      IA => U1_paf_counter_3_5_LOGIC_ZERO,
      IB => U1_paf_counter_3_inst_cy_6,
      SEL => U1_paf_counter_3_inst_lut3_6,
      O => U1_paf_counter_3_5_CYMUXG
    );
  U1_paf_counter_3_inst_sum_6_781 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_6,
      I1 => U1_paf_counter_3_inst_lut3_6,
      O => U1_paf_counter_3_inst_sum_6
    );
  U1_paf_counter_3_5_CYINIT_782 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_5,
      O => U1_paf_counter_3_5_CYINIT
    );
  U1_paf_counter_3_7_LOGIC_ZERO_783 : X_ZERO
    port map (
      O => U1_paf_counter_3_7_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_8_784 : X_MUX2
    port map (
      IA => U1_paf_counter_3_7_LOGIC_ZERO,
      IB => U1_paf_counter_3_7_CYINIT,
      SEL => U1_paf_counter_3_inst_lut3_7,
      O => U1_paf_counter_3_inst_cy_8
    );
  U1_paf_counter_3_inst_sum_7_785 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_7_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_7,
      O => U1_paf_counter_3_inst_sum_7
    );
  U1_paf_counter_3_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44086,
      ADR2 => U1_paf_counter_3(7),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_7
    );
  U1_paf_counter_3_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44088,
      ADR2 => U1_paf_counter_3(8),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_8
    );
  U1_paf_counter_3_7_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_7_CYMUXG,
      O => U1_paf_counter_3_inst_cy_9
    );
  U1_paf_counter_3_inst_cy_9_786 : X_MUX2
    port map (
      IA => U1_paf_counter_3_7_LOGIC_ZERO,
      IB => U1_paf_counter_3_inst_cy_8,
      SEL => U1_paf_counter_3_inst_lut3_8,
      O => U1_paf_counter_3_7_CYMUXG
    );
  U1_paf_counter_3_inst_sum_8_787 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_8,
      I1 => U1_paf_counter_3_inst_lut3_8,
      O => U1_paf_counter_3_inst_sum_8
    );
  U1_paf_counter_3_7_CYINIT_788 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_7,
      O => U1_paf_counter_3_7_CYINIT
    );
  U1_paf_counter_3_10_LOGIC_ZERO_789 : X_ZERO
    port map (
      O => U1_paf_counter_3_10_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_10_790 : X_MUX2
    port map (
      IA => U1_paf_counter_3_10_LOGIC_ZERO,
      IB => U1_paf_counter_3_10_CYINIT,
      SEL => U1_paf_counter_3_inst_lut3_9,
      O => U1_paf_counter_3_inst_cy_10
    );
  U1_paf_counter_3_inst_sum_9_791 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_10_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_9,
      O => U1_paf_counter_3_10_XORF
    );
  U1_paf_counter_3_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44090,
      ADR2 => U1_paf_counter_3(9),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_9
    );
  U1_paf_counter_3_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44092,
      ADR2 => U1_paf_counter_3(10),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_10
    );
  U1_paf_counter_3_10_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_10_CYMUXG,
      O => U1_paf_counter_3_inst_cy_11
    );
  U1_paf_counter_3_10_XUSED : X_BUF
    port map (
      I => U1_paf_counter_3_10_XORF,
      O => U1_paf_counter_3_inst_sum_9
    );
  U1_paf_counter_3_inst_cy_11_792 : X_MUX2
    port map (
      IA => U1_paf_counter_3_10_LOGIC_ZERO,
      IB => U1_paf_counter_3_inst_cy_10,
      SEL => U1_paf_counter_3_inst_lut3_10,
      O => U1_paf_counter_3_10_CYMUXG
    );
  U1_paf_counter_3_inst_sum_10_793 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_10,
      I1 => U1_paf_counter_3_inst_lut3_10,
      O => U1_paf_counter_3_inst_sum_10
    );
  U1_paf_counter_3_10_CYINIT_794 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_9,
      O => U1_paf_counter_3_10_CYINIT
    );
  U1_paf_counter_3_11_LOGIC_ZERO_795 : X_ZERO
    port map (
      O => U1_paf_counter_3_11_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_12_796 : X_MUX2
    port map (
      IA => U1_paf_counter_3_11_LOGIC_ZERO,
      IB => U1_paf_counter_3_11_CYINIT,
      SEL => U1_paf_counter_3_inst_lut3_11,
      O => U1_paf_counter_3_inst_cy_12
    );
  U1_paf_counter_3_inst_sum_11_797 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_11_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_11,
      O => U1_paf_counter_3_inst_sum_11
    );
  U1_paf_counter_3_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44094,
      ADR2 => U1_paf_counter_3(11),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_11
    );
  U1_paf_counter_3_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44096,
      ADR2 => U1_paf_counter_3(12),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_12
    );
  U1_paf_counter_3_11_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_11_CYMUXG,
      O => U1_paf_counter_3_inst_cy_13
    );
  U1_paf_counter_3_inst_cy_13_798 : X_MUX2
    port map (
      IA => U1_paf_counter_3_11_LOGIC_ZERO,
      IB => U1_paf_counter_3_inst_cy_12,
      SEL => U1_paf_counter_3_inst_lut3_12,
      O => U1_paf_counter_3_11_CYMUXG
    );
  U1_paf_counter_3_inst_sum_12_799 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_12,
      I1 => U1_paf_counter_3_inst_lut3_12,
      O => U1_paf_counter_3_inst_sum_12
    );
  U1_paf_counter_3_11_CYINIT_800 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_11,
      O => U1_paf_counter_3_11_CYINIT
    );
  U1_paf_counter_3_13_LOGIC_ZERO_801 : X_ZERO
    port map (
      O => U1_paf_counter_3_13_LOGIC_ZERO
    );
  U1_paf_counter_3_inst_cy_14_802 : X_MUX2
    port map (
      IA => U1_paf_counter_3_13_LOGIC_ZERO,
      IB => U1_paf_counter_3_13_CYINIT,
      SEL => U1_paf_counter_3_inst_lut3_13,
      O => U1_paf_counter_3_inst_cy_14
    );
  U1_paf_counter_3_inst_sum_13_803 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_13_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_13,
      O => U1_paf_counter_3_inst_sum_13
    );
  U1_paf_counter_3_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44098,
      ADR2 => U1_paf_counter_3(13),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_13
    );
  U1_paf_counter_3_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44100,
      ADR2 => U1_paf_counter_3(14),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_14
    );
  U1_paf_counter_3_13_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_3_13_CYMUXG,
      O => U1_paf_counter_3_inst_cy_15
    );
  U1_paf_counter_3_inst_cy_15_804 : X_MUX2
    port map (
      IA => U1_paf_counter_3_13_LOGIC_ZERO,
      IB => U1_paf_counter_3_inst_cy_14,
      SEL => U1_paf_counter_3_inst_lut3_14,
      O => U1_paf_counter_3_13_CYMUXG
    );
  U1_paf_counter_3_inst_sum_14_805 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_inst_cy_14,
      I1 => U1_paf_counter_3_inst_lut3_14,
      O => U1_paf_counter_3_inst_sum_14
    );
  U1_paf_counter_3_13_CYINIT_806 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_13,
      O => U1_paf_counter_3_13_CYINIT
    );
  U1_paf_counter_3_inst_sum_15_807 : X_XOR2
    port map (
      I0 => U1_paf_counter_3_15_CYINIT,
      I1 => U1_paf_counter_3_inst_lut3_15,
      O => U1_paf_counter_3_inst_sum_15
    );
  U1_paf_counter_3_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44102,
      ADR2 => U1_paf_counter_3(15),
      ADR3 => VCC,
      O => U1_paf_counter_3_inst_lut3_15
    );
  U1_n01891 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => U1_paf_cnt_set(2),
      ADR2 => paf_2_IBUF,
      ADR3 => VCC,
      O => U1_paf_counter_3_15_GROM
    );
  U1_paf_counter_3_15_YUSED : X_BUF
    port map (
      I => U1_paf_counter_3_15_GROM,
      O => U1_n0189
    );
  U1_paf_counter_3_15_CYINIT_808 : X_BUF
    port map (
      I => U1_paf_counter_3_inst_cy_15,
      O => U1_paf_counter_3_15_CYINIT
    );
  U1_paf_counter_4_0_LOGIC_ZERO_809 : X_ZERO
    port map (
      O => U1_paf_counter_4_0_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_0_810 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U1_paf_counter_4_0_LOGIC_ZERO,
      SEL => Q_SIG_3,
      O => U1_paf_counter_4_inst_cy_0
    );
  Q_BEL_3 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U1_enw_paf_counter1_3,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_SIG_3
    );
  U1_paf_counter_4_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U1_enw_paf_counter,
      ADR2 => N44072,
      ADR3 => U1_paf_counter_4(0),
      O => U1_paf_counter_4_inst_lut3_0
    );
  U1_paf_counter_4_0_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_0_CYMUXG,
      O => U1_paf_counter_4_inst_cy_1
    );
  U1_paf_counter_4_inst_cy_1_811 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U1_paf_counter_4_inst_cy_0,
      SEL => U1_paf_counter_4_inst_lut3_0,
      O => U1_paf_counter_4_0_CYMUXG
    );
  U1_paf_counter_4_inst_sum_0_812 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_0,
      I1 => U1_paf_counter_4_inst_lut3_0,
      O => U1_paf_counter_4_inst_sum_0
    );
  U1_paf_counter_4_1_LOGIC_ZERO_813 : X_ZERO
    port map (
      O => U1_paf_counter_4_1_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_2_814 : X_MUX2
    port map (
      IA => U1_paf_counter_4_1_LOGIC_ZERO,
      IB => U1_paf_counter_4_1_CYINIT,
      SEL => U1_paf_counter_4_inst_lut3_1,
      O => U1_paf_counter_4_inst_cy_2
    );
  U1_paf_counter_4_inst_sum_1_815 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_1_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_1,
      O => U1_paf_counter_4_inst_sum_1
    );
  U1_paf_counter_4_inst_lut3_16 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44074,
      ADR2 => U1_paf_counter_4(1),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_1
    );
  U1_paf_counter_4_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44076,
      ADR2 => U1_paf_counter_4(2),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_2
    );
  U1_paf_counter_4_1_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_1_CYMUXG,
      O => U1_paf_counter_4_inst_cy_3
    );
  U1_paf_counter_4_inst_cy_3_816 : X_MUX2
    port map (
      IA => U1_paf_counter_4_1_LOGIC_ZERO,
      IB => U1_paf_counter_4_inst_cy_2,
      SEL => U1_paf_counter_4_inst_lut3_2,
      O => U1_paf_counter_4_1_CYMUXG
    );
  U1_paf_counter_4_inst_sum_2_817 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_2,
      I1 => U1_paf_counter_4_inst_lut3_2,
      O => U1_paf_counter_4_inst_sum_2
    );
  U1_paf_counter_4_1_CYINIT_818 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_1,
      O => U1_paf_counter_4_1_CYINIT
    );
  U1_paf_counter_4_3_LOGIC_ZERO_819 : X_ZERO
    port map (
      O => U1_paf_counter_4_3_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_4_820 : X_MUX2
    port map (
      IA => U1_paf_counter_4_3_LOGIC_ZERO,
      IB => U1_paf_counter_4_3_CYINIT,
      SEL => U1_paf_counter_4_inst_lut3_3,
      O => U1_paf_counter_4_inst_cy_4
    );
  U1_paf_counter_4_inst_sum_3_821 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_3_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_3,
      O => U1_paf_counter_4_inst_sum_3
    );
  U1_paf_counter_4_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44078,
      ADR2 => U1_paf_counter_4(3),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_3
    );
  U1_paf_counter_4_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44080,
      ADR2 => U1_paf_counter_4(4),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_4
    );
  U1_paf_counter_4_3_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_3_CYMUXG,
      O => U1_paf_counter_4_inst_cy_5
    );
  U1_paf_counter_4_inst_cy_5_822 : X_MUX2
    port map (
      IA => U1_paf_counter_4_3_LOGIC_ZERO,
      IB => U1_paf_counter_4_inst_cy_4,
      SEL => U1_paf_counter_4_inst_lut3_4,
      O => U1_paf_counter_4_3_CYMUXG
    );
  U1_paf_counter_4_inst_sum_4_823 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_4,
      I1 => U1_paf_counter_4_inst_lut3_4,
      O => U1_paf_counter_4_inst_sum_4
    );
  U1_paf_counter_4_3_CYINIT_824 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_3,
      O => U1_paf_counter_4_3_CYINIT
    );
  U1_paf_counter_4_5_LOGIC_ZERO_825 : X_ZERO
    port map (
      O => U1_paf_counter_4_5_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_6_826 : X_MUX2
    port map (
      IA => U1_paf_counter_4_5_LOGIC_ZERO,
      IB => U1_paf_counter_4_5_CYINIT,
      SEL => U1_paf_counter_4_inst_lut3_5,
      O => U1_paf_counter_4_inst_cy_6
    );
  U1_paf_counter_4_inst_sum_5_827 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_5_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_5,
      O => U1_paf_counter_4_inst_sum_5
    );
  U1_paf_counter_4_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44082,
      ADR2 => U1_paf_counter_4(5),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_5
    );
  U1_paf_counter_4_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44084,
      ADR2 => U1_paf_counter_4(6),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_6
    );
  U1_paf_counter_4_5_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_5_CYMUXG,
      O => U1_paf_counter_4_inst_cy_7
    );
  U1_paf_counter_4_inst_cy_7_828 : X_MUX2
    port map (
      IA => U1_paf_counter_4_5_LOGIC_ZERO,
      IB => U1_paf_counter_4_inst_cy_6,
      SEL => U1_paf_counter_4_inst_lut3_6,
      O => U1_paf_counter_4_5_CYMUXG
    );
  U1_paf_counter_4_inst_sum_6_829 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_6,
      I1 => U1_paf_counter_4_inst_lut3_6,
      O => U1_paf_counter_4_inst_sum_6
    );
  U1_paf_counter_4_5_CYINIT_830 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_5,
      O => U1_paf_counter_4_5_CYINIT
    );
  U1_paf_counter_4_7_LOGIC_ZERO_831 : X_ZERO
    port map (
      O => U1_paf_counter_4_7_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_8_832 : X_MUX2
    port map (
      IA => U1_paf_counter_4_7_LOGIC_ZERO,
      IB => U1_paf_counter_4_7_CYINIT,
      SEL => U1_paf_counter_4_inst_lut3_7,
      O => U1_paf_counter_4_inst_cy_8
    );
  U1_paf_counter_4_inst_sum_7_833 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_7_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_7,
      O => U1_paf_counter_4_inst_sum_7
    );
  U1_paf_counter_4_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44086,
      ADR2 => U1_paf_counter_4(7),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_7
    );
  U1_paf_counter_4_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44088,
      ADR2 => U1_paf_counter_4(8),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_8
    );
  U1_paf_counter_4_7_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_7_CYMUXG,
      O => U1_paf_counter_4_inst_cy_9
    );
  U1_paf_counter_4_inst_cy_9_834 : X_MUX2
    port map (
      IA => U1_paf_counter_4_7_LOGIC_ZERO,
      IB => U1_paf_counter_4_inst_cy_8,
      SEL => U1_paf_counter_4_inst_lut3_8,
      O => U1_paf_counter_4_7_CYMUXG
    );
  U1_paf_counter_4_inst_sum_8_835 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_8,
      I1 => U1_paf_counter_4_inst_lut3_8,
      O => U1_paf_counter_4_inst_sum_8
    );
  U1_paf_counter_4_7_CYINIT_836 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_7,
      O => U1_paf_counter_4_7_CYINIT
    );
  U1_paf_counter_4_9_LOGIC_ZERO_837 : X_ZERO
    port map (
      O => U1_paf_counter_4_9_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_10_838 : X_MUX2
    port map (
      IA => U1_paf_counter_4_9_LOGIC_ZERO,
      IB => U1_paf_counter_4_9_CYINIT,
      SEL => U1_paf_counter_4_inst_lut3_9,
      O => U1_paf_counter_4_inst_cy_10
    );
  U1_paf_counter_4_inst_sum_9_839 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_9_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_9,
      O => U1_paf_counter_4_inst_sum_9
    );
  U1_paf_counter_4_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44090,
      ADR2 => U1_paf_counter_4(9),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_9
    );
  U1_paf_counter_4_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44092,
      ADR2 => U1_paf_counter_4(10),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_10
    );
  U1_paf_counter_4_9_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_9_CYMUXG,
      O => U1_paf_counter_4_inst_cy_11
    );
  U1_paf_counter_4_inst_cy_11_840 : X_MUX2
    port map (
      IA => U1_paf_counter_4_9_LOGIC_ZERO,
      IB => U1_paf_counter_4_inst_cy_10,
      SEL => U1_paf_counter_4_inst_lut3_10,
      O => U1_paf_counter_4_9_CYMUXG
    );
  U1_paf_counter_4_inst_sum_10_841 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_10,
      I1 => U1_paf_counter_4_inst_lut3_10,
      O => U1_paf_counter_4_inst_sum_10
    );
  U1_paf_counter_4_9_CYINIT_842 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_9,
      O => U1_paf_counter_4_9_CYINIT
    );
  U1_paf_counter_4_11_LOGIC_ZERO_843 : X_ZERO
    port map (
      O => U1_paf_counter_4_11_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_12_844 : X_MUX2
    port map (
      IA => U1_paf_counter_4_11_LOGIC_ZERO,
      IB => U1_paf_counter_4_11_CYINIT,
      SEL => U1_paf_counter_4_inst_lut3_11,
      O => U1_paf_counter_4_inst_cy_12
    );
  U1_paf_counter_4_inst_sum_11_845 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_11_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_11,
      O => U1_paf_counter_4_inst_sum_11
    );
  U1_paf_counter_4_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44094,
      ADR2 => U1_paf_counter_4(11),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_11
    );
  U1_paf_counter_4_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44096,
      ADR2 => U1_paf_counter_4(12),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_12
    );
  U1_paf_counter_4_11_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_11_CYMUXG,
      O => U1_paf_counter_4_inst_cy_13
    );
  U1_paf_counter_4_inst_cy_13_846 : X_MUX2
    port map (
      IA => U1_paf_counter_4_11_LOGIC_ZERO,
      IB => U1_paf_counter_4_inst_cy_12,
      SEL => U1_paf_counter_4_inst_lut3_12,
      O => U1_paf_counter_4_11_CYMUXG
    );
  U1_paf_counter_4_inst_sum_12_847 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_12,
      I1 => U1_paf_counter_4_inst_lut3_12,
      O => U1_paf_counter_4_inst_sum_12
    );
  U1_paf_counter_4_11_CYINIT_848 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_11,
      O => U1_paf_counter_4_11_CYINIT
    );
  U1_paf_counter_4_13_LOGIC_ZERO_849 : X_ZERO
    port map (
      O => U1_paf_counter_4_13_LOGIC_ZERO
    );
  U1_paf_counter_4_inst_cy_14_850 : X_MUX2
    port map (
      IA => U1_paf_counter_4_13_LOGIC_ZERO,
      IB => U1_paf_counter_4_13_CYINIT,
      SEL => U1_paf_counter_4_inst_lut3_13,
      O => U1_paf_counter_4_inst_cy_14
    );
  U1_paf_counter_4_inst_sum_13_851 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_13_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_13,
      O => U1_paf_counter_4_inst_sum_13
    );
  U1_paf_counter_4_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44098,
      ADR2 => U1_paf_counter_4(13),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_13
    );
  U1_paf_counter_4_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44100,
      ADR2 => U1_paf_counter_4(14),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_14
    );
  U1_paf_counter_4_13_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_4_13_CYMUXG,
      O => U1_paf_counter_4_inst_cy_15
    );
  U1_paf_counter_4_inst_cy_15_852 : X_MUX2
    port map (
      IA => U1_paf_counter_4_13_LOGIC_ZERO,
      IB => U1_paf_counter_4_inst_cy_14,
      SEL => U1_paf_counter_4_inst_lut3_14,
      O => U1_paf_counter_4_13_CYMUXG
    );
  U1_paf_counter_4_inst_sum_14_853 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_inst_cy_14,
      I1 => U1_paf_counter_4_inst_lut3_14,
      O => U1_paf_counter_4_inst_sum_14
    );
  U1_paf_counter_4_13_CYINIT_854 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_13,
      O => U1_paf_counter_4_13_CYINIT
    );
  U1_paf_counter_4_inst_sum_15_855 : X_XOR2
    port map (
      I0 => U1_paf_counter_4_15_CYINIT,
      I1 => U1_paf_counter_4_inst_lut3_15,
      O => U1_paf_counter_4_inst_sum_15
    );
  U1_paf_counter_4_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44102,
      ADR2 => U1_paf_counter_4(15),
      ADR3 => VCC,
      O => U1_paf_counter_4_inst_lut3_15
    );
  U1_n01911 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => U1_paf_cnt_set(1),
      ADR2 => paf_1_IBUF,
      ADR3 => VCC,
      O => U1_paf_counter_4_15_GROM
    );
  U1_paf_counter_4_15_YUSED : X_BUF
    port map (
      I => U1_paf_counter_4_15_GROM,
      O => U1_n0191
    );
  U1_paf_counter_4_15_CYINIT_856 : X_BUF
    port map (
      I => U1_paf_counter_4_inst_cy_15,
      O => U1_paf_counter_4_15_CYINIT
    );
  U1_paf_counter_5_0_LOGIC_ZERO_857 : X_ZERO
    port map (
      O => U1_paf_counter_5_0_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_0_858 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U1_paf_counter_5_0_LOGIC_ZERO,
      SEL => Q_SIG_4,
      O => U1_paf_counter_5_inst_cy_0
    );
  Q_BEL_4 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U1_enw_paf_counter1_3,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Q_SIG_4
    );
  U1_paf_counter_5_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U1_enw_paf_counter,
      ADR2 => N44072,
      ADR3 => U1_paf_counter_5(0),
      O => U1_paf_counter_5_inst_lut3_0
    );
  U1_paf_counter_5_0_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_0_CYMUXG,
      O => U1_paf_counter_5_inst_cy_1
    );
  U1_paf_counter_5_inst_cy_1_859 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U1_paf_counter_5_inst_cy_0,
      SEL => U1_paf_counter_5_inst_lut3_0,
      O => U1_paf_counter_5_0_CYMUXG
    );
  U1_paf_counter_5_inst_sum_0_860 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_0,
      I1 => U1_paf_counter_5_inst_lut3_0,
      O => U1_paf_counter_5_inst_sum_0
    );
  U1_paf_counter_5_1_LOGIC_ZERO_861 : X_ZERO
    port map (
      O => U1_paf_counter_5_1_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_2_862 : X_MUX2
    port map (
      IA => U1_paf_counter_5_1_LOGIC_ZERO,
      IB => U1_paf_counter_5_1_CYINIT,
      SEL => U1_paf_counter_5_inst_lut3_1,
      O => U1_paf_counter_5_inst_cy_2
    );
  U1_paf_counter_5_inst_sum_1_863 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_1_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_1,
      O => U1_paf_counter_5_inst_sum_1
    );
  U1_paf_counter_5_inst_lut3_16 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44074,
      ADR2 => U1_paf_counter_5(1),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_1
    );
  U1_paf_counter_5_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_2,
      ADR1 => N44076,
      ADR2 => U1_paf_counter_5(2),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_2
    );
  U1_paf_counter_5_1_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_1_CYMUXG,
      O => U1_paf_counter_5_inst_cy_3
    );
  U1_paf_counter_5_inst_cy_3_864 : X_MUX2
    port map (
      IA => U1_paf_counter_5_1_LOGIC_ZERO,
      IB => U1_paf_counter_5_inst_cy_2,
      SEL => U1_paf_counter_5_inst_lut3_2,
      O => U1_paf_counter_5_1_CYMUXG
    );
  U1_paf_counter_5_inst_sum_2_865 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_2,
      I1 => U1_paf_counter_5_inst_lut3_2,
      O => U1_paf_counter_5_inst_sum_2
    );
  U1_paf_counter_5_1_CYINIT_866 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_1,
      O => U1_paf_counter_5_1_CYINIT
    );
  U1_paf_counter_5_3_LOGIC_ZERO_867 : X_ZERO
    port map (
      O => U1_paf_counter_5_3_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_4_868 : X_MUX2
    port map (
      IA => U1_paf_counter_5_3_LOGIC_ZERO,
      IB => U1_paf_counter_5_3_CYINIT,
      SEL => U1_paf_counter_5_inst_lut3_3,
      O => U1_paf_counter_5_inst_cy_4
    );
  U1_paf_counter_5_inst_sum_3_869 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_3_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_3,
      O => U1_paf_counter_5_inst_sum_3
    );
  U1_paf_counter_5_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44078,
      ADR2 => U1_paf_counter_5(3),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_3
    );
  U1_paf_counter_5_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44080,
      ADR2 => U1_paf_counter_5(4),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_4
    );
  U1_paf_counter_5_3_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_3_CYMUXG,
      O => U1_paf_counter_5_inst_cy_5
    );
  U1_paf_counter_5_inst_cy_5_870 : X_MUX2
    port map (
      IA => U1_paf_counter_5_3_LOGIC_ZERO,
      IB => U1_paf_counter_5_inst_cy_4,
      SEL => U1_paf_counter_5_inst_lut3_4,
      O => U1_paf_counter_5_3_CYMUXG
    );
  U1_paf_counter_5_inst_sum_4_871 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_4,
      I1 => U1_paf_counter_5_inst_lut3_4,
      O => U1_paf_counter_5_inst_sum_4
    );
  U1_paf_counter_5_3_CYINIT_872 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_3,
      O => U1_paf_counter_5_3_CYINIT
    );
  U1_paf_counter_5_5_LOGIC_ZERO_873 : X_ZERO
    port map (
      O => U1_paf_counter_5_5_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_6_874 : X_MUX2
    port map (
      IA => U1_paf_counter_5_5_LOGIC_ZERO,
      IB => U1_paf_counter_5_5_CYINIT,
      SEL => U1_paf_counter_5_inst_lut3_5,
      O => U1_paf_counter_5_inst_cy_6
    );
  U1_paf_counter_5_inst_sum_5_875 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_5_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_5,
      O => U1_paf_counter_5_inst_sum_5
    );
  U1_paf_counter_5_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44082,
      ADR2 => U1_paf_counter_5(5),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_5
    );
  U1_paf_counter_5_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44084,
      ADR2 => U1_paf_counter_5(6),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_6
    );
  U1_paf_counter_5_5_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_5_CYMUXG,
      O => U1_paf_counter_5_inst_cy_7
    );
  U1_paf_counter_5_inst_cy_7_876 : X_MUX2
    port map (
      IA => U1_paf_counter_5_5_LOGIC_ZERO,
      IB => U1_paf_counter_5_inst_cy_6,
      SEL => U1_paf_counter_5_inst_lut3_6,
      O => U1_paf_counter_5_5_CYMUXG
    );
  U1_paf_counter_5_inst_sum_6_877 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_6,
      I1 => U1_paf_counter_5_inst_lut3_6,
      O => U1_paf_counter_5_inst_sum_6
    );
  U1_paf_counter_5_5_CYINIT_878 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_5,
      O => U1_paf_counter_5_5_CYINIT
    );
  U1_paf_counter_5_7_LOGIC_ZERO_879 : X_ZERO
    port map (
      O => U1_paf_counter_5_7_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_8_880 : X_MUX2
    port map (
      IA => U1_paf_counter_5_7_LOGIC_ZERO,
      IB => U1_paf_counter_5_7_CYINIT,
      SEL => U1_paf_counter_5_inst_lut3_7,
      O => U1_paf_counter_5_inst_cy_8
    );
  U1_paf_counter_5_inst_sum_7_881 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_7_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_7,
      O => U1_paf_counter_5_inst_sum_7
    );
  U1_paf_counter_5_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_1,
      ADR1 => N44086,
      ADR2 => U1_paf_counter_5(7),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_7
    );
  U1_paf_counter_5_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44088,
      ADR2 => U1_paf_counter_5(8),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_8
    );
  U1_paf_counter_5_7_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_7_CYMUXG,
      O => U1_paf_counter_5_inst_cy_9
    );
  U1_paf_counter_5_inst_cy_9_882 : X_MUX2
    port map (
      IA => U1_paf_counter_5_7_LOGIC_ZERO,
      IB => U1_paf_counter_5_inst_cy_8,
      SEL => U1_paf_counter_5_inst_lut3_8,
      O => U1_paf_counter_5_7_CYMUXG
    );
  U1_paf_counter_5_inst_sum_8_883 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_8,
      I1 => U1_paf_counter_5_inst_lut3_8,
      O => U1_paf_counter_5_inst_sum_8
    );
  U1_paf_counter_5_7_CYINIT_884 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_7,
      O => U1_paf_counter_5_7_CYINIT
    );
  U1_paf_counter_5_9_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_9_FFX_RST
    );
  U1_paf_counter_5_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_9,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_9_FFX_RST,
      O => U1_paf_counter_5(9)
    );
  U1_paf_counter_5_9_LOGIC_ZERO_885 : X_ZERO
    port map (
      O => U1_paf_counter_5_9_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_10_886 : X_MUX2
    port map (
      IA => U1_paf_counter_5_9_LOGIC_ZERO,
      IB => U1_paf_counter_5_9_CYINIT,
      SEL => U1_paf_counter_5_inst_lut3_9,
      O => U1_paf_counter_5_inst_cy_10
    );
  U1_paf_counter_5_inst_sum_9_887 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_9_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_9,
      O => U1_paf_counter_5_inst_sum_9
    );
  U1_paf_counter_5_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44090,
      ADR2 => U1_paf_counter_5(9),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_9
    );
  U1_paf_counter_5_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44092,
      ADR2 => U1_paf_counter_5(10),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_10
    );
  U1_paf_counter_5_9_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_9_CYMUXG,
      O => U1_paf_counter_5_inst_cy_11
    );
  U1_paf_counter_5_inst_cy_11_888 : X_MUX2
    port map (
      IA => U1_paf_counter_5_9_LOGIC_ZERO,
      IB => U1_paf_counter_5_inst_cy_10,
      SEL => U1_paf_counter_5_inst_lut3_10,
      O => U1_paf_counter_5_9_CYMUXG
    );
  U1_paf_counter_5_inst_sum_10_889 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_10,
      I1 => U1_paf_counter_5_inst_lut3_10,
      O => U1_paf_counter_5_inst_sum_10
    );
  U1_paf_counter_5_9_CYINIT_890 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_9,
      O => U1_paf_counter_5_9_CYINIT
    );
  U1_paf_counter_5_11_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_11_FFX_RST
    );
  U1_paf_counter_5_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_11,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_11_FFX_RST,
      O => U1_paf_counter_5(11)
    );
  U1_paf_counter_5_11_LOGIC_ZERO_891 : X_ZERO
    port map (
      O => U1_paf_counter_5_11_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_12_892 : X_MUX2
    port map (
      IA => U1_paf_counter_5_11_LOGIC_ZERO,
      IB => U1_paf_counter_5_11_CYINIT,
      SEL => U1_paf_counter_5_inst_lut3_11,
      O => U1_paf_counter_5_inst_cy_12
    );
  U1_paf_counter_5_inst_sum_11_893 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_11_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_11,
      O => U1_paf_counter_5_inst_sum_11
    );
  U1_paf_counter_5_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44094,
      ADR2 => U1_paf_counter_5(11),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_11
    );
  U1_paf_counter_5_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_4,
      ADR1 => N44096,
      ADR2 => U1_paf_counter_5(12),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_12
    );
  U1_paf_counter_5_11_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_11_CYMUXG,
      O => U1_paf_counter_5_inst_cy_13
    );
  U1_paf_counter_5_inst_cy_13_894 : X_MUX2
    port map (
      IA => U1_paf_counter_5_11_LOGIC_ZERO,
      IB => U1_paf_counter_5_inst_cy_12,
      SEL => U1_paf_counter_5_inst_lut3_12,
      O => U1_paf_counter_5_11_CYMUXG
    );
  U1_paf_counter_5_inst_sum_12_895 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_12,
      I1 => U1_paf_counter_5_inst_lut3_12,
      O => U1_paf_counter_5_inst_sum_12
    );
  U1_paf_counter_5_11_CYINIT_896 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_11,
      O => U1_paf_counter_5_11_CYINIT
    );
  U1_paf_counter_5_13_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_13_FFX_RST
    );
  U1_paf_counter_5_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_13,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_13_FFX_RST,
      O => U1_paf_counter_5(13)
    );
  U1_paf_counter_5_13_LOGIC_ZERO_897 : X_ZERO
    port map (
      O => U1_paf_counter_5_13_LOGIC_ZERO
    );
  U1_paf_counter_5_inst_cy_14_898 : X_MUX2
    port map (
      IA => U1_paf_counter_5_13_LOGIC_ZERO,
      IB => U1_paf_counter_5_13_CYINIT,
      SEL => U1_paf_counter_5_inst_lut3_13,
      O => U1_paf_counter_5_inst_cy_14
    );
  U1_paf_counter_5_inst_sum_13_899 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_13_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_13,
      O => U1_paf_counter_5_inst_sum_13
    );
  U1_paf_counter_5_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44098,
      ADR2 => U1_paf_counter_5(13),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_13
    );
  U1_paf_counter_5_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44100,
      ADR2 => U1_paf_counter_5(14),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_14
    );
  U1_paf_counter_5_13_COUTUSED : X_BUF
    port map (
      I => U1_paf_counter_5_13_CYMUXG,
      O => U1_paf_counter_5_inst_cy_15
    );
  U1_paf_counter_5_inst_cy_15_900 : X_MUX2
    port map (
      IA => U1_paf_counter_5_13_LOGIC_ZERO,
      IB => U1_paf_counter_5_inst_cy_14,
      SEL => U1_paf_counter_5_inst_lut3_14,
      O => U1_paf_counter_5_13_CYMUXG
    );
  U1_paf_counter_5_inst_sum_14_901 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_inst_cy_14,
      I1 => U1_paf_counter_5_inst_lut3_14,
      O => U1_paf_counter_5_inst_sum_14
    );
  U1_paf_counter_5_13_CYINIT_902 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_13,
      O => U1_paf_counter_5_13_CYINIT
    );
  U1_paf_counter_5_15_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_15_FFX_RST
    );
  U1_paf_counter_5_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_15,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_15_FFX_RST,
      O => U1_paf_counter_5(15)
    );
  U1_paf_counter_5_inst_sum_15_903 : X_XOR2
    port map (
      I0 => U1_paf_counter_5_15_CYINIT,
      I1 => U1_paf_counter_5_inst_lut3_15,
      O => U1_paf_counter_5_inst_sum_15
    );
  U1_paf_counter_5_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => N44102,
      ADR2 => U1_paf_counter_5(15),
      ADR3 => VCC,
      O => U1_paf_counter_5_inst_lut3_15
    );
  U1_paf_counter_5_15_CYINIT_904 : X_BUF
    port map (
      I => U1_paf_counter_5_inst_cy_15,
      O => U1_paf_counter_5_15_CYINIT
    );
  U3_n0121_1_LOGIC_ZERO_905 : X_ZERO
    port map (
      O => U3_n0121_1_LOGIC_ZERO
    );
  U3_cr_ros_n0121_0_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1,
      IB => U3_n0121_1_LOGIC_ZERO,
      SEL => U3_N21563,
      O => U3_cr_ros_n0121_0_cyo
    );
  U3_cr_ros_n0121_0_lut : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => GLOBAL_LOGIC1,
      ADR1 => U3_rob_id(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N21563
    );
  U3_n0121_1_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => GLOBAL_LOGIC0,
      ADR1 => U3_rob_id(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0121_1_GROM
    );
  U3_n0121_1_COUTUSED : X_BUF
    port map (
      I => U3_n0121_1_CYMUXG,
      O => U3_cr_ros_n0121_1_cyo
    );
  U3_n0121_1_YUSED : X_BUF
    port map (
      I => U3_n0121_1_XORG,
      O => U3_n0121(1)
    );
  U3_cr_ros_n0121_1_cy : X_MUX2
    port map (
      IA => GLOBAL_LOGIC0,
      IB => U3_cr_ros_n0121_0_cyo,
      SEL => U3_n0121_1_GROM,
      O => U3_n0121_1_CYMUXG
    );
  U3_cr_ros_n0121_1_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0121_0_cyo,
      I1 => U3_n0121_1_GROM,
      O => U3_n0121_1_XORG
    );
  U3_n0121_2_LOGIC_ZERO_906 : X_ZERO
    port map (
      O => U3_n0121_2_LOGIC_ZERO
    );
  U3_cr_ros_n0121_2_cy : X_MUX2
    port map (
      IA => U3_n0121_2_LOGIC_ZERO,
      IB => U3_n0121_2_CYINIT,
      SEL => U3_n0121_2_FROM,
      O => U3_cr_ros_n0121_2_cyo
    );
  U3_cr_ros_n0121_2_xor : X_XOR2
    port map (
      I0 => U3_n0121_2_CYINIT,
      I1 => U3_n0121_2_FROM,
      O => U3_n0121_2_XORF
    );
  U3_n0121_2_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_rob_id(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0121_2_FROM
    );
  U3_n0121_2_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_rob_id(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0121_2_GROM
    );
  U3_n0121_2_COUTUSED : X_BUF
    port map (
      I => U3_n0121_2_CYMUXG,
      O => U3_cr_ros_n0121_3_cyo
    );
  U3_n0121_2_XUSED : X_BUF
    port map (
      I => U3_n0121_2_XORF,
      O => U3_n0121(2)
    );
  U3_n0121_2_YUSED : X_BUF
    port map (
      I => U3_n0121_2_XORG,
      O => U3_n0121(3)
    );
  U3_cr_ros_n0121_3_cy : X_MUX2
    port map (
      IA => U3_n0121_2_LOGIC_ZERO,
      IB => U3_cr_ros_n0121_2_cyo,
      SEL => U3_n0121_2_GROM,
      O => U3_n0121_2_CYMUXG
    );
  U3_cr_ros_n0121_3_xor : X_XOR2
    port map (
      I0 => U3_cr_ros_n0121_2_cyo,
      I1 => U3_n0121_2_GROM,
      O => U3_n0121_2_XORG
    );
  U3_n0121_2_CYINIT_907 : X_BUF
    port map (
      I => U3_cr_ros_n0121_1_cyo,
      O => U3_n0121_2_CYINIT
    );
  U3_cr_ros_n0121_4_xor : X_XOR2
    port map (
      I0 => U3_n0121_4_CYINIT,
      I1 => U3_rob_id_4_rt,
      O => U3_n0121_4_XORF
    );
  U3_rob_id_4_rt_908 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => U3_rob_id(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_rob_id_4_rt
    );
  U3_n0121_4_XUSED : X_BUF
    port map (
      I => U3_n0121_4_XORF,
      O => U3_n0121(4)
    );
  U3_n0121_4_CYINIT_909 : X_BUF
    port map (
      I => U3_cr_ros_n0121_3_cyo,
      O => U3_n0121_4_CYINIT
    );
  U3_n0102_6_44_SW0 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd14,
      ADR1 => U3_trailer_reg_6_Q,
      ADR2 => U3_state_FFd36_In,
      ADR3 => CHOICE808,
      O => U3_n0102_6_44_SW0_O_FROM
    );
  U3_n0102_6_44 : X_LUT4
    generic map(
      INIT => X"FDEC"
    )
    port map (
      ADR0 => U3_state_FFd13_In,
      ADR1 => CHOICE814,
      ADR2 => N44320,
      ADR3 => U3_n0102_6_44_SW0_O,
      O => U3_n0102_6_44_SW0_O_GROM
    );
  U3_n0102_6_44_SW0_O_XUSED : X_BUF
    port map (
      I => U3_n0102_6_44_SW0_O_FROM,
      O => U3_n0102_6_44_SW0_O
    );
  U3_n0102_6_44_SW0_O_YUSED : X_BUF
    port map (
      I => U3_n0102_6_44_SW0_O_GROM,
      O => CHOICE818
    );
  U3_n009899 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_state_FFd14,
      ADR1 => CHOICE489,
      ADR2 => CHOICE493,
      ADR3 => U3_read_fifo_dir,
      O => U3_read_fifo_dir_FROM
    );
  U3_n0098111 : X_LUT4
    generic map(
      INIT => X"BBBA"
    )
    port map (
      ADR0 => U3_n009899_O,
      ADR1 => U3_this_ef23_1,
      ADR2 => CHOICE482,
      ADR3 => U3_N31621,
      O => U3_n0098111_O
    );
  U3_read_fifo_dir_XUSED : X_BUF
    port map (
      I => U3_read_fifo_dir_FROM,
      O => U3_n009899_O
    );
  U3_read_fifo_dir_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_read_fifo_dir_SRMUX_OUTPUTNOT
    );
  U3_read_fifo_p1 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => U3_read_fifo_dir,
      ADR1 => CHOICE683,
      ADR2 => CHOICE686,
      ADR3 => CHOICE689,
      O => read_FROM
    );
  U2_n0131_SW114 : X_LUT4
    generic map(
      INIT => X"EFAA"
    )
    port map (
      ADR0 => enw_dispar,
      ADR1 => read,
      ADR2 => U1_per_fifo,
      ADR3 => CHOICE200,
      O => read_GROM
    );
  read_XUSED : X_BUF
    port map (
      I => read_FROM,
      O => read
    );
  read_YUSED : X_BUF
    port map (
      I => read_GROM,
      O => U2_n0131
    );
  U3_n0102_6_1 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_N31683,
      ADR2 => fout_6_IBUF,
      ADR3 => VCC,
      O => U3_s_data_6_FROM
    );
  U3_n0102_6_67 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31172,
      ADR1 => U3_s_data(6),
      ADR2 => U3_n0102_6_1_O,
      ADR3 => CHOICE818,
      O => U3_n0102_6_67_O
    );
  U3_s_data_6_XUSED : X_BUF
    port map (
      I => U3_s_data_6_FROM,
      O => U3_n0102_6_1_O
    );
  U3_s_data_6_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_6_SRMUX_OUTPUTNOT
    );
  U3_Ker31675 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => U3_state_FFd13,
      ADR1 => N39317,
      ADR2 => U3_fmt_error_ff_2_3_Q,
      ADR3 => U3_state_FFd10,
      O => U3_N31677_FROM
    );
  U3_n0102_8_21 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => fout_8_IBUF,
      ADR1 => U3_N31677,
      ADR2 => CHOICE709,
      ADR3 => CHOICE712,
      O => U3_N31677_GROM
    );
  U3_N31677_XUSED : X_BUF
    port map (
      I => U3_N31677_FROM,
      O => U3_N31677
    );
  U3_N31677_YUSED : X_BUF
    port map (
      I => U3_N31677_GROM,
      O => CHOICE715
    );
  U3_n0102_7_1 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_N31683,
      ADR2 => fout_7_IBUF,
      ADR3 => VCC,
      O => U3_s_data_7_FROM
    );
  U3_n0102_7_47 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31183,
      ADR1 => U3_s_data(7),
      ADR2 => U3_n0102_7_1_O,
      ADR3 => CHOICE703,
      O => U3_n0102_7_47_O
    );
  U3_s_data_7_XUSED : X_BUF
    port map (
      I => U3_s_data_7_FROM,
      O => U3_n0102_7_1_O
    );
  U3_s_data_7_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_7_SRMUX_OUTPUTNOT
    );
  U3_Ker31659 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE679,
      ADR1 => CHOICE676,
      ADR2 => N39520,
      ADR3 => N44314,
      O => U3_s_data_8_FROM
    );
  U3_n0102_8_44 : X_LUT4
    generic map(
      INIT => X"FDEC"
    )
    port map (
      ADR0 => U3_N31661,
      ADR1 => CHOICE715,
      ADR2 => N44350,
      ADR3 => N44348,
      O => U3_n0102_8_44_O
    );
  U3_s_data_8_XUSED : X_BUF
    port map (
      I => U3_s_data_8_FROM,
      O => U3_N31661
    );
  U3_s_data_8_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_8_SRMUX_OUTPUTNOT
    );
  U3_n0102_5_124_SW0 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE651,
      ADR1 => U3_state_FFd10,
      ADR2 => U3_N31683,
      ADR3 => fout_5_IBUF,
      O => U3_s_data_5_FROM
    );
  U3_n0102_5_133 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31709,
      ADR1 => U3_trailer_reg_5_Q,
      ADR2 => CHOICE625,
      ADR3 => U3_n0102_5_124_SW0_O,
      O => U3_n0102_5_133_O
    );
  U3_s_data_5_XUSED : X_BUF
    port map (
      I => U3_s_data_5_FROM,
      O => U3_n0102_5_124_SW0_O
    );
  U3_s_data_5_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_5_SRMUX_OUTPUTNOT
    );
  U3_n0102_9_21 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => fout_9_IBUF,
      ADR1 => U3_N31677,
      ADR2 => CHOICE723,
      ADR3 => CHOICE726,
      O => U3_s_data_9_FROM
    );
  U3_n0102_9_44 : X_LUT4
    generic map(
      INIT => X"FDEC"
    )
    port map (
      ADR0 => U3_N31661,
      ADR1 => U3_n0102_9_21_O,
      ADR2 => N44356,
      ADR3 => N44354,
      O => U3_n0102_9_44_O
    );
  U3_s_data_9_XUSED : X_BUF
    port map (
      I => U3_s_data_9_FROM,
      O => U3_n0102_9_21_O
    );
  U3_s_data_9_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_9_SRMUX_OUTPUTNOT
    );
  U3_n009971 : X_LUT4
    generic map(
      INIT => X"02AA"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U1_dis_maxw_mask,
      ADR2 => U3_n0050,
      ADR3 => U3_this_ef23_2,
      O => U3_txena_dir_FROM
    );
  U3_n009986 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_n009971_O,
      ADR1 => U3_N31683,
      ADR2 => CHOICE463,
      ADR3 => N44490,
      O => U3_n009986_O
    );
  U3_txena_dir_XUSED : X_BUF
    port map (
      I => U3_txena_dir_FROM,
      O => U3_n009971_O
    );
  U3_txena_dir_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_txena_dir_SRMUX_OUTPUTNOT
    );
  U3_n0102_0_129 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31183,
      ADR1 => U3_s_data(0),
      ADR2 => CHOICE919,
      ADR3 => CHOICE948,
      O => U3_n0102_0_129_O
    );
  U3_s_data_0_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_0_SRMUX_OUTPUTNOT
    );
  U3_n0102_1_1 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_N31683,
      ADR2 => fout_1_IBUF,
      ADR3 => VCC,
      O => U3_s_data_1_FROM
    );
  U3_n0102_1_83 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31183,
      ADR1 => U3_s_data(1),
      ADR2 => U3_n0102_1_1_O,
      ADR3 => CHOICE861,
      O => U3_n0102_1_83_O
    );
  U3_s_data_1_XUSED : X_BUF
    port map (
      I => U3_s_data_1_FROM,
      O => U3_n0102_1_1_O
    );
  U3_s_data_1_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_1_SRMUX_OUTPUTNOT
    );
  U3_n0102_2_1 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_N31683,
      ADR2 => fout_2_IBUF,
      ADR3 => VCC,
      O => U3_s_data_2_FROM
    );
  U3_n0102_2_109 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31183,
      ADR1 => U3_s_data(2),
      ADR2 => U3_n0102_2_1_O,
      ADR3 => CHOICE915,
      O => U3_n0102_2_109_O
    );
  U3_s_data_2_XUSED : X_BUF
    port map (
      I => U3_s_data_2_FROM,
      O => U3_n0102_2_1_O
    );
  U3_s_data_2_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_2_SRMUX_OUTPUTNOT
    );
  U3_n0102_3_1 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_N31683,
      ADR2 => fout_3_IBUF,
      ADR3 => VCC,
      O => U3_s_data_3_FROM
    );
  U3_n0102_3_66 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31183,
      ADR1 => U3_s_data(3),
      ADR2 => U3_n0102_3_1_O,
      ADR3 => CHOICE783,
      O => U3_n0102_3_66_O
    );
  U3_s_data_3_XUSED : X_BUF
    port map (
      I => U3_s_data_3_FROM,
      O => U3_n0102_3_1_O
    );
  U3_s_data_3_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_3_SRMUX_OUTPUTNOT
    );
  U3_n0102_4_1 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_N31683,
      ADR2 => fout_4_IBUF,
      ADR3 => VCC,
      O => U3_s_data_4_FROM
    );
  U3_n0102_4_71 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31183,
      ADR1 => U3_s_data(4),
      ADR2 => U3_n0102_4_1_O,
      ADR3 => CHOICE801,
      O => U3_n0102_4_71_O
    );
  U3_s_data_4_XUSED : X_BUF
    port map (
      I => U3_s_data_4_FROM,
      O => U3_n0102_4_1_O
    );
  U3_s_data_4_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_4_SRMUX_OUTPUTNOT
    );
  U3_Mmux_n0115_Result_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44074,
      ADR1 => enw_maxw,
      ADR2 => U3_maxw_reached(1),
      ADR3 => U3_sel_read(1),
      O => U3_Mmux_n0115_Result_1_1_O
    );
  U3_Mmux_n0115_Result_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44072,
      ADR1 => enw_maxw,
      ADR2 => U3_maxw_reached(0),
      ADR3 => U3_sel_read(0),
      O => U3_Mmux_n0115_Result_0_1_O
    );
  U3_Mmux_n0115_Result_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44078,
      ADR1 => enw_maxw,
      ADR2 => U3_maxw_reached(3),
      ADR3 => U3_sel_read(3),
      O => U3_Mmux_n0115_Result_3_1_O
    );
  U3_Mmux_n0115_Result_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44076,
      ADR1 => enw_maxw,
      ADR2 => U3_maxw_reached(2),
      ADR3 => U3_sel_read(2),
      O => U3_Mmux_n0115_Result_2_1_O
    );
  U3_Mmux_n0115_Result_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44082,
      ADR1 => enw_maxw,
      ADR2 => U3_maxw_reached(5),
      ADR3 => U3_sel_read_5_1,
      O => U3_Mmux_n0115_Result_5_1_O
    );
  U3_Mmux_n0115_Result_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44080,
      ADR1 => enw_maxw,
      ADR2 => U3_maxw_reached(4),
      ADR3 => U3_sel_read(4),
      O => U3_Mmux_n0115_Result_4_1_O
    );
  U1_enw_timed_out1 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => U1_N29954,
      ADR1 => add_0_IBUF,
      ADR2 => add_1_IBUF,
      ADR3 => U1_N30021,
      O => U1_hasunlock_5_FROM
    );
  U1_Mmux_n0013_Result_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44094,
      ADR1 => enw_timed_out,
      ADR2 => U1_hasunlock(5),
      ADR3 => lock_5_IBUF,
      O => U1_Mmux_n0013_Result_5_1_O
    );
  U1_hasunlock_5_XUSED : X_BUF
    port map (
      I => U1_hasunlock_5_FROM,
      O => enw_timed_out
    );
  U1_enw_evid_mis1 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29930,
      O => enw_evid_mis_FROM
    );
  U3_n02411 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => enw_evid_mis,
      ADR1 => U3_state_FFd23,
      ADR2 => U3_state_FFd22,
      ADR3 => U3_error_evid,
      O => enw_evid_mis_GROM
    );
  enw_evid_mis_XUSED : X_BUF
    port map (
      I => enw_evid_mis_FROM,
      O => enw_evid_mis
    );
  enw_evid_mis_YUSED : X_BUF
    port map (
      I => enw_evid_mis_GROM,
      O => U3_n0241
    );
  U2_Mmux_n0002_Result_11_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44094,
      ADR2 => U2_word_par(10),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_11_1_O
    );
  U2_Mmux_n0002_Result_10_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44092,
      ADR2 => U2_word_par(9),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_10_1_O
    );
  U2_Mmux_n0002_Result_13_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44098,
      ADR2 => U2_word_par(12),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_13_1_O
    );
  U2_Mmux_n0002_Result_12_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44096,
      ADR2 => U2_word_par(11),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_12_1_O
    );
  U2_Mmux_n0002_Result_15_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44102,
      ADR2 => U2_word_par(14),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_15_1_O
    );
  U2_Mmux_n0002_Result_14_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44100,
      ADR2 => U2_word_par(13),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_14_1_O
    );
  U3_n02521 : X_LUT4
    generic map(
      INIT => X"5D5D"
    )
    port map (
      ADR0 => U3_time_start,
      ADR1 => U3_fmt_error_ff_2_1_Q,
      ADR2 => U1_dis_hul_mask,
      ADR3 => VCC,
      O => U3_time_counter_0_FROM
    );
  U3_Mmux_n0117_Result_0_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(0),
      ADR2 => U3_n0251(0),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_0_1_O
    );
  U3_time_counter_0_XUSED : X_BUF
    port map (
      I => U3_time_counter_0_FROM,
      O => U3_n0252
    );
  U3_Mmux_n0117_Result_1_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(1),
      ADR2 => U3_n0251(1),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_1_1_O
    );
  U3_Mmux_n0117_Result_3_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(3),
      ADR2 => U3_n0251(3),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_3_1_O
    );
  U3_Mmux_n0117_Result_2_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(2),
      ADR2 => U3_n0251(2),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_2_1_O
    );
  U3_Mmux_n0117_Result_5_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(5),
      ADR2 => U3_n0251(5),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_5_1_O
    );
  U3_Mmux_n0117_Result_4_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(4),
      ADR2 => U3_n0251(4),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_4_1_O
    );
  U3_Mmux_n0117_Result_7_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(7),
      ADR2 => U3_n0251(7),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_7_1_O
    );
  U3_Mmux_n0117_Result_6_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(6),
      ADR2 => U3_n0251(6),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_6_1_O
    );
  U3_Mmux_n0117_Result_9_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(9),
      ADR2 => U3_n0251(9),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_9_1_O
    );
  U3_Mmux_n0117_Result_8_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(8),
      ADR2 => U3_n0251(8),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_8_1_O
    );
  U3_Mmux_n0114_Result_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44074,
      ADR1 => enw_timed_out,
      ADR2 => U3_sel_read(1),
      ADR3 => U3_timed_out(1),
      O => U3_Mmux_n0114_Result_1_1_O
    );
  U3_Mmux_n0114_Result_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44072,
      ADR1 => enw_timed_out,
      ADR2 => U3_sel_read(0),
      ADR3 => U3_timed_out(0),
      O => U3_Mmux_n0114_Result_0_1_O
    );
  U3_Mmux_n0114_Result_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44078,
      ADR1 => enw_timed_out,
      ADR2 => U3_sel_read(3),
      ADR3 => U3_timed_out(3),
      O => U3_Mmux_n0114_Result_3_1_O
    );
  U3_Mmux_n0114_Result_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44076,
      ADR1 => enw_timed_out,
      ADR2 => U3_sel_read(2),
      ADR3 => U3_timed_out(2),
      O => U3_Mmux_n0114_Result_2_1_O
    );
  U3_Mmux_n0114_Result_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44082,
      ADR1 => enw_timed_out,
      ADR2 => U3_sel_read_5_1,
      ADR3 => U3_timed_out(5),
      O => U3_Mmux_n0114_Result_5_1_O
    );
  U3_Mmux_n0114_Result_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44080,
      ADR1 => enw_timed_out,
      ADR2 => U3_sel_read(4),
      ADR3 => U3_timed_out(4),
      O => U3_Mmux_n0114_Result_4_1_O
    );
  U1_enw_maxw1 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => add_0_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29930,
      O => U1_ff_reg_5_FROM
    );
  U1_Mmux_n0015_Result_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44094,
      ADR1 => enw_maxw,
      ADR2 => ff_5_IBUF,
      ADR3 => U1_ff_reg(5),
      O => U1_Mmux_n0015_Result_5_1_O
    );
  U1_ff_reg_5_XUSED : X_BUF
    port map (
      I => U1_ff_reg_5_FROM,
      O => enw_maxw
    );
  U3_state_FFd4_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd9,
      ADR2 => U3_state_FFd4,
      ADR3 => U3_time_out,
      O => U3_state_FFd4_In1_O
    );
  U3_state_FFd3_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd5,
      ADR2 => U3_state_FFd3,
      ADR3 => U3_time_out,
      O => U3_state_FFd3_In1_O
    );
  U3_state_FFd4_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd4_SRMUX_OUTPUTNOT
    );
  U3_n0113_13_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_13_Q,
      ADR2 => fout_13_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_13_1_O
    );
  U3_n0113_12_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_12_Q,
      ADR2 => fout_12_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_12_1_O
    );
  U3_state_FFd6_In1 : X_LUT4
    generic map(
      INIT => X"A800"
    )
    port map (
      ADR0 => U3_time_out,
      ADR1 => U3_state_FFd3,
      ADR2 => U3_state_FFd8,
      ADR3 => U3_this_ef23_1,
      O => U3_state_FFd6_In1_O
    );
  U3_state_FFd5_In1 : X_LUT4
    generic map(
      INIT => X"00EA"
    )
    port map (
      ADR0 => U3_state_FFd3,
      ADR1 => U3_state_FFd9,
      ADR2 => U3_n0049,
      ADR3 => U3_this_ef23_1,
      O => U3_state_FFd5_In1_O
    );
  U3_state_FFd6_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd6_SRMUX_OUTPUTNOT
    );
  U3_n0113_1_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_1_Q,
      ADR2 => fout_1_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_1_1_O
    );
  U3_n0113_14_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_14_Q,
      ADR2 => fout_14_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_14_1_O
    );
  U3_state_FFd10_In1 : X_LUT4
    generic map(
      INIT => X"BBBA"
    )
    port map (
      ADR0 => U3_state_FFd14,
      ADR1 => U3_this_ef23_1,
      ADR2 => U3_state_FFd8,
      ADR3 => U3_N31919,
      O => U3_state_FFd10_In1_O
    );
  U3_state_FFd9_In1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd4,
      ADR2 => U3_N31621,
      ADR3 => VCC,
      O => U3_state_FFd9_In1_O
    );
  U3_state_FFd10_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd10_SRMUX_OUTPUTNOT
    );
  U1_Mmux_n0013_Result_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44086,
      ADR1 => enw_timed_out,
      ADR2 => U1_hasunlock(1),
      ADR3 => lock_1_IBUF,
      O => U1_Mmux_n0013_Result_1_1_O
    );
  U1_Mmux_n0013_Result_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44084,
      ADR1 => enw_timed_out,
      ADR2 => U1_hasunlock(0),
      ADR3 => lock_0_IBUF,
      O => U1_Mmux_n0013_Result_0_1_O
    );
  U1_Mmux_n0013_Result_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44090,
      ADR1 => enw_timed_out,
      ADR2 => U1_hasunlock(3),
      ADR3 => lock_3_IBUF,
      O => U1_Mmux_n0013_Result_3_1_O
    );
  U1_Mmux_n0013_Result_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44088,
      ADR1 => enw_timed_out,
      ADR2 => U1_hasunlock(2),
      ADR3 => lock_2_IBUF,
      O => U1_Mmux_n0013_Result_2_1_O
    );
  notblocked_4_13 : X_LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      ADR0 => U1_ff_reg(4),
      ADR1 => lock_4_IBUF,
      ADR2 => U1_hasunlock(4),
      ADR3 => U1_dis_hul_mask,
      O => U1_hasunlock_4_FROM
    );
  U1_Mmux_n0013_Result_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44092,
      ADR1 => enw_timed_out,
      ADR2 => U1_hasunlock(4),
      ADR3 => lock_4_IBUF,
      O => U1_Mmux_n0013_Result_4_1_O
    );
  U1_hasunlock_4_XUSED : X_BUF
    port map (
      I => U1_hasunlock_4_FROM,
      O => CHOICE335
    );
  U3_n0102_10_49_SW0 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_state_FFd36_In,
      ADR1 => CHOICE679,
      ADR2 => N44456,
      ADR3 => U3_s_data(10),
      O => U3_s_data_10_FROM
    );
  U3_n0102_10_62 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE741,
      ADR1 => CHOICE748,
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_10_49_SW0_O,
      O => U3_n0102_10_62_O
    );
  U3_s_data_10_XUSED : X_BUF
    port map (
      I => U3_s_data_10_FROM,
      O => U3_n0102_10_49_SW0_O
    );
  U3_s_data_10_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_10_SRMUX_OUTPUTNOT
    );
  U3_n0102_11_46_SW0 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_state_FFd36_In,
      ADR1 => CHOICE679,
      ADR2 => N44456,
      ADR3 => U3_s_data(11),
      O => U3_s_data_11_FROM
    );
  U3_n0102_11_58 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE758,
      ADR1 => CHOICE765,
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_11_46_SW0_O,
      O => U3_n0102_11_58_O
    );
  U3_s_data_11_XUSED : X_BUF
    port map (
      I => U3_s_data_11_FROM,
      O => U3_n0102_11_46_SW0_O
    );
  U3_s_data_11_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_11_SRMUX_OUTPUTNOT
    );
  U3_s_data_12_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_12_FFY_RST
    );
  U3_s_data_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_12_17_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_12_FFY_RST,
      O => U3_s_data(12)
    );
  U3_n0102_12_5 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(12),
      ADR2 => fout_12_IBUF,
      ADR3 => U3_N31671,
      O => U3_s_data_12_FROM
    );
  U3_n0102_12_17 : X_LUT4
    generic map(
      INIT => X"FDEC"
    )
    port map (
      ADR0 => U3_N31661,
      ADR1 => U3_n0102_12_5_O,
      ADR2 => N44362,
      ADR3 => N44360,
      O => U3_n0102_12_17_O
    );
  U3_s_data_12_XUSED : X_BUF
    port map (
      I => U3_s_data_12_FROM,
      O => U3_n0102_12_5_O
    );
  U3_s_data_12_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_12_SRMUX_OUTPUTNOT
    );
  U3_s_data_13_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_13_FFY_RST
    );
  U3_s_data_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_13_64_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_13_FFY_RST,
      O => U3_s_data(13)
    );
  U3_n0102_13_51 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => fout_13_IBUF,
      ADR1 => CHOICE837,
      ADR2 => U3_state_FFd36_In,
      ADR3 => CHOICE618,
      O => U3_s_data_13_FROM
    );
  U3_n0102_13_64 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n0102_13_51_O,
      ADR1 => CHOICE679,
      ADR2 => N44486,
      ADR3 => U3_s_data(13),
      O => U3_n0102_13_64_O
    );
  U3_s_data_13_XUSED : X_BUF
    port map (
      I => U3_s_data_13_FROM,
      O => U3_n0102_13_51_O
    );
  U3_s_data_13_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_13_SRMUX_OUTPUTNOT
    );
  U3_s_data_14_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_14_FFY_RST
    );
  U3_s_data_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_14_97_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_14_FFY_RST,
      O => U3_s_data(14)
    );
  U3_n0102_14_85 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => fout_14_IBUF,
      ADR1 => CHOICE837,
      ADR2 => U3_N31479,
      ADR3 => CHOICE881,
      O => U3_s_data_14_FROM
    );
  U3_n0102_14_97 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n0102_14_85_O,
      ADR1 => U3_state_FFd33,
      ADR2 => U3_N31661,
      ADR3 => U3_s_data(14),
      O => U3_n0102_14_97_O
    );
  U3_s_data_14_XUSED : X_BUF
    port map (
      I => U3_s_data_14_FROM,
      O => U3_n0102_14_85_O
    );
  U3_s_data_14_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_14_SRMUX_OUTPUTNOT
    );
  U3_s_data_15_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_15_FFY_RST
    );
  U3_s_data_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_15_80_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_15_FFY_RST,
      O => U3_s_data(15)
    );
  U3_n0102_15_68 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => CHOICE837,
      ADR1 => fout_15_IBUF,
      ADR2 => U3_N31548,
      ADR3 => N44586,
      O => U3_s_data_15_FROM
    );
  U3_n0102_15_80 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n0102_15_68_O,
      ADR1 => U3_state_FFd33,
      ADR2 => U3_N31661,
      ADR3 => U3_s_data(15),
      O => U3_n0102_15_80_O
    );
  U3_s_data_15_XUSED : X_BUF
    port map (
      I => U3_s_data_15_FROM,
      O => U3_n0102_15_68_O
    );
  U3_s_data_15_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_s_data_15_SRMUX_OUTPUTNOT
    );
  U3_word_count_11_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_11_FFX_RST
    );
  U3_word_count_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_11_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_11_FFX_RST,
      O => U3_word_count(11)
    );
  U3_word_count_11_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_11_FFY_RST
    );
  U3_word_count_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_10_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_11_FFY_RST,
      O => U3_word_count(10)
    );
  U3_n0100_11_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(11),
      ADR2 => U3_n0151(11),
      ADR3 => U3_N31862,
      O => U3_n0100_11_1_O
    );
  U3_n0100_10_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(10),
      ADR2 => U3_n0151(10),
      ADR3 => U3_N31862,
      O => U3_n0100_10_1_O
    );
  U3_word_count_11_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_word_count_11_SRMUX_OUTPUTNOT
    );
  U1_db_error1_11_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_11_FFY_RST
    );
  U1_db_error1_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_11_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_11_FFY_RST,
      O => U1_db_error1(11)
    );
  U1_n00881 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => add_0_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29937,
      O => U1_db_error1_11_FROM
    );
  U1_Mmux_n0036_Result_11_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44094,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(11),
      ADR3 => U3_timed_out(5),
      O => U1_Mmux_n0036_Result_11_1_O
    );
  U1_db_error1_11_XUSED : X_BUF
    port map (
      I => U1_db_error1_11_FROM,
      O => U1_n0088
    );
  U3_this_ef14 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => ef_3_IBUF,
      ADR1 => U3_sel_read(3),
      ADR2 => ef_2_IBUF,
      ADR3 => U3_sel_read(2),
      O => CHOICE689_FROM
    );
  U3_this_ef23 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE683,
      ADR1 => CHOICE686,
      ADR2 => CHOICE689,
      ADR3 => VCC,
      O => CHOICE689_GROM
    );
  CHOICE689_XUSED : X_BUF
    port map (
      I => CHOICE689_FROM,
      O => CHOICE689
    );
  CHOICE689_YUSED : X_BUF
    port map (
      I => CHOICE689_GROM,
      O => U3_fmt_error_ff_2_3_Q
    );
  U3_n011015 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_n0253,
      ADR1 => CHOICE661,
      ADR2 => U3_state_FFd40,
      ADR3 => CHOICE659,
      O => U3_sel_read_0_FROM
    );
  U3_n011021 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n011015_O,
      ADR1 => U3_N31536,
      ADR2 => N44328,
      ADR3 => U3_sel_read(0),
      O => U3_n0110
    );
  U3_sel_read_0_XUSED : X_BUF
    port map (
      I => U3_sel_read_0_FROM,
      O => U3_n011015_O
    );
  U3_sel_read_0_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_sel_read_0_SRMUX_OUTPUTNOT
    );
  U3_this_hasunlock9 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U1_hasunlock(3),
      ADR1 => U3_sel_read(3),
      ADR2 => U1_hasunlock(2),
      ADR3 => U3_sel_read(2),
      O => U3_this_hasunlock9_O_FROM
    );
  U3_this_hasunlock23 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE520,
      ADR1 => U3_this_hasunlock9_O,
      ADR2 => CHOICE526,
      ADR3 => VCC,
      O => U3_this_hasunlock9_O_GROM
    );
  U3_this_hasunlock9_O_XUSED : X_BUF
    port map (
      I => U3_this_hasunlock9_O_FROM,
      O => U3_this_hasunlock9_O
    );
  U3_this_hasunlock9_O_YUSED : X_BUF
    port map (
      I => U3_this_hasunlock9_O_GROM,
      O => U3_fmt_error_ff_2_1_Q
    );
  U3_n010417 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => U1_dis_head_trail,
      ADR1 => U3_this_ef23_2,
      ADR2 => U3_n0049,
      ADR3 => U3_state_FFd25,
      O => U3_trail_FROM
    );
  U3_n010420 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n010417_O,
      ADR1 => U3_N31790,
      ADR2 => N44470,
      ADR3 => U3_trail,
      O => U3_n010420_O
    );
  U3_trail_XUSED : X_BUF
    port map (
      I => U3_trail_FROM,
      O => U3_n010417_O
    );
  U3_trail_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_trail_SRMUX_OUTPUTNOT
    );
  U3_Ker315701 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31790,
      ADR1 => N39701,
      ADR2 => U3_state_FFd29,
      ADR3 => N44282,
      O => U3_sel_read_5_FROM
    );
  U3_n010539 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE601,
      ADR1 => U3_N31572,
      ADR2 => CHOICE590,
      ADR3 => U3_sel_read_5_1,
      O => U3_n010539_O
    );
  U3_sel_read_5_XUSED : X_BUF
    port map (
      I => U3_sel_read_5_FROM,
      O => U3_N31572
    );
  U3_sel_read_5_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_sel_read_5_SRMUX_OUTPUTNOT
    );
  U3_n010527 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_n0218,
      ADR1 => U3_sel_read(5),
      ADR2 => U3_sel_read(4),
      ADR3 => U3_this_ef23_2,
      O => U3_n010527_O_FROM
    );
  U3_n010528 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => CHOICE596,
      ADR1 => U3_n010527_O,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n010527_O_GROM
    );
  U3_n010527_O_XUSED : X_BUF
    port map (
      I => U3_n010527_O_FROM,
      O => U3_n010527_O
    );
  U3_n010527_O_YUSED : X_BUF
    port map (
      I => U3_n010527_O_GROM,
      O => CHOICE601
    );
  U3_n010634 : X_LUT4
    generic map(
      INIT => X"A808"
    )
    port map (
      ADR0 => U3_n0218,
      ADR1 => U3_sel_read(3),
      ADR2 => U3_n0253,
      ADR3 => U3_sel_read(4),
      O => U3_sel_read_4_FROM
    );
  U3_n010650 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31192,
      ADR1 => U3_sel_read(4),
      ADR2 => CHOICE1026,
      ADR3 => U3_n010634_O,
      O => U3_n0106
    );
  U3_sel_read_4_XUSED : X_BUF
    port map (
      I => U3_sel_read_4_FROM,
      O => U3_n010634_O
    );
  U3_sel_read_4_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_sel_read_4_SRMUX_OUTPUTNOT
    );
  U3_n010734 : X_LUT4
    generic map(
      INIT => X"A808"
    )
    port map (
      ADR0 => U3_n0218,
      ADR1 => U3_sel_read(2),
      ADR2 => U3_n0253,
      ADR3 => U3_sel_read(3),
      O => U3_sel_read_3_FROM
    );
  U3_n010750 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31192,
      ADR1 => U3_sel_read(3),
      ADR2 => CHOICE996,
      ADR3 => U3_n010734_O,
      O => U3_n0107
    );
  U3_sel_read_3_XUSED : X_BUF
    port map (
      I => U3_sel_read_3_FROM,
      O => U3_n010734_O
    );
  U3_sel_read_3_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_sel_read_3_SRMUX_OUTPUTNOT
    );
  U3_n010834 : X_LUT4
    generic map(
      INIT => X"A808"
    )
    port map (
      ADR0 => U3_n0218,
      ADR1 => U3_sel_read(1),
      ADR2 => U3_n0253,
      ADR3 => U3_sel_read(2),
      O => U3_sel_read_2_FROM
    );
  U3_n010850 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31192,
      ADR1 => U3_sel_read(2),
      ADR2 => CHOICE1011,
      ADR3 => U3_n010834_O,
      O => U3_n0108
    );
  U3_sel_read_2_XUSED : X_BUF
    port map (
      I => U3_sel_read_2_FROM,
      O => U3_n010834_O
    );
  U3_sel_read_2_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_sel_read_2_SRMUX_OUTPUTNOT
    );
  U3_Ker3172314 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_N31564,
      ADR1 => U3_state_FFd9,
      ADR2 => U3_state_FFd5,
      ADR3 => U3_fmt_error_ff_2_3_Q,
      O => CHOICE679_FROM
    );
  U3_Ker31181 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE679,
      ADR1 => N39571,
      ADR2 => CHOICE676,
      ADR3 => N44430,
      O => CHOICE679_GROM
    );
  CHOICE679_XUSED : X_BUF
    port map (
      I => CHOICE679_FROM,
      O => CHOICE679
    );
  CHOICE679_YUSED : X_BUF
    port map (
      I => CHOICE679_GROM,
      O => U3_N31183
    );
  U3_Ker311901 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31790,
      ADR1 => N39701,
      ADR2 => U3_N31808,
      ADR3 => N44340,
      O => U3_sel_read_1_FROM
    );
  U3_n010950 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31192,
      ADR1 => U3_sel_read(1),
      ADR2 => CHOICE981,
      ADR3 => CHOICE986,
      O => U3_n0109
    );
  U3_sel_read_1_XUSED : X_BUF
    port map (
      I => U3_sel_read_1_FROM,
      O => U3_N31192
    );
  U3_sel_read_1_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_sel_read_1_SRMUX_OUTPUTNOT
    );
  U2_Mmux_n0038_Result_1_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44074,
      ADR2 => U2_pae_paf_reg(2),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_1_1_O
    );
  U2_Mmux_n0038_Result_0_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44072,
      ADR2 => U2_pae_paf_reg(1),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_0_1_O
    );
  U2_Mmux_n0038_Result_3_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44078,
      ADR2 => U2_pae_paf_reg(4),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_3_1_O
    );
  U2_Mmux_n0038_Result_2_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44076,
      ADR2 => U2_pae_paf_reg(3),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_2_1_O
    );
  U2_Mmux_n0038_Result_5_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44082,
      ADR2 => U2_pae_paf_reg(6),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_5_1_O
    );
  U2_Mmux_n0038_Result_4_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44080,
      ADR2 => U2_pae_paf_reg(5),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_4_1_O
    );
  U1_n00901 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29937,
      O => U1_db_error2_11_FROM
    );
  U1_Mmux_n0037_Result_11_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44094,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(11),
      ADR3 => U1_ff_reg(5),
      O => U1_Mmux_n0037_Result_11_1_O
    );
  U1_db_error2_11_XUSED : X_BUF
    port map (
      I => U1_db_error2_11_FROM,
      O => U1_n0090
    );
  U2_Mmux_n0038_Result_7_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44086,
      ADR2 => U2_pae_paf_reg(8),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_7_1_O
    );
  U2_Mmux_n0038_Result_6_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44084,
      ADR2 => U2_pae_paf_reg(7),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_6_1_O
    );
  U2_Mmux_n0038_Result_9_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44090,
      ADR2 => U2_pae_paf_reg(10),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_9_1_O
    );
  U2_Mmux_n0038_Result_8_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44088,
      ADR2 => U2_pae_paf_reg(9),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_8_1_O
    );
  U3_Ker31562_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd29,
      ADR1 => U3_state_FFd27,
      ADR2 => U3_state_FFd25,
      ADR3 => VCC,
      O => CHOICE556_FROM
    );
  U3_Ker31562 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd22,
      ADR1 => U3_state_FFd23,
      ADR2 => U3_state_FFd28,
      ADR3 => CHOICE556,
      O => CHOICE556_GROM
    );
  CHOICE556_XUSED : X_BUF
    port map (
      I => CHOICE556_FROM,
      O => CHOICE556
    );
  CHOICE556_YUSED : X_BUF
    port map (
      I => CHOICE556_GROM,
      O => U3_N31564
    );
  U3_Ker31546_SW0 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd34,
      ADR1 => U3_state_FFd33,
      ADR2 => tp_2_OBUF,
      ADR3 => VCC,
      O => U3_Ker31546_SW0_O_FROM
    );
  U3_Ker31546 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd18,
      ADR1 => U3_state_FFd11,
      ADR2 => U3_state_FFd7,
      ADR3 => U3_Ker31546_SW0_O,
      O => U3_Ker31546_SW0_O_GROM
    );
  U3_Ker31546_SW0_O_XUSED : X_BUF
    port map (
      I => U3_Ker31546_SW0_O_FROM,
      O => U3_Ker31546_SW0_O
    );
  U3_Ker31546_SW0_O_YUSED : X_BUF
    port map (
      I => U3_Ker31546_SW0_O_GROM,
      O => U3_N31548
    );
  U3_Ker31554_SW1 : X_LUT4
    generic map(
      INIT => X"00EA"
    )
    port map (
      ADR0 => U3_state_FFd15,
      ADR1 => U3_n0049,
      ADR2 => U3_state_FFd9,
      ADR3 => CHOICE689,
      O => U3_Ker31554_SW1_O_FROM
    );
  U3_Ker31554 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => CHOICE683,
      ADR1 => U3_Ker31554_SW1_O,
      ADR2 => CHOICE686,
      ADR3 => U3_state_FFd19,
      O => U3_Ker31554_SW1_O_GROM
    );
  U3_Ker31554_SW1_O_XUSED : X_BUF
    port map (
      I => U3_Ker31554_SW1_O_FROM,
      O => U3_Ker31554_SW1_O
    );
  U3_Ker31554_SW1_O_YUSED : X_BUF
    port map (
      I => U3_Ker31554_SW1_O_GROM,
      O => U3_N31556
    );
  U3_n009536 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => U3_n0150,
      ADR1 => U3_state_FFd25,
      ADR2 => U3_this_ef23_2,
      ADR3 => U3_state_FFd18,
      O => U3_error_evid_FROM
    );
  U3_n009539 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n009536_O,
      ADR1 => U3_N31572,
      ADR2 => CHOICE580,
      ADR3 => U3_error_evid,
      O => U3_n009539_O
    );
  U3_error_evid_XUSED : X_BUF
    port map (
      I => U3_error_evid_FROM,
      O => U3_n009536_O
    );
  U3_error_evid_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_error_evid_SRMUX_OUTPUTNOT
    );
  U3_n024317 : X_LUT4
    generic map(
      INIT => X"082A"
    )
    port map (
      ADR0 => U3_state_FFd11,
      ADR1 => U3_fmt_error_ff_2_1_Q,
      ADR2 => U1_dis_hul_mask,
      ADR3 => U1_dis_timo_mask,
      O => U3_n024317_O_FROM
    );
  U3_n024344 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_n024317_O,
      ADR1 => CHOICE428,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n024317_O_GROM
    );
  U3_n024317_O_XUSED : X_BUF
    port map (
      I => U3_n024317_O_FROM,
      O => U3_n024317_O
    );
  U3_n024317_O_YUSED : X_BUF
    port map (
      I => U3_n024317_O_GROM,
      O => U3_n0243
    );
  U3_Mmux_n0117_Result_11_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(11),
      ADR2 => U3_n0251(11),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_11_1_O
    );
  U3_Mmux_n0117_Result_10_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => U3_n0252,
      ADR1 => U1_timeout_value(10),
      ADR2 => U3_n0251(10),
      ADR3 => VCC,
      O => U3_Mmux_n0117_Result_10_1_O
    );
  U1_Ker299521 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => enw2,
      ADR1 => enw1,
      ADR2 => cs_IBUF,
      ADR3 => VCC,
      O => U1_N29954_FROM
    );
  U1_enw_word_par1 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29930,
      O => U1_N29954_GROM
    );
  U1_N29954_XUSED : X_BUF
    port map (
      I => U1_N29954_FROM,
      O => U1_N29954
    );
  U1_N29954_YUSED : X_BUF
    port map (
      I => U1_N29954_GROM,
      O => enw_word_par
    );
  U3_this_ef4 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => ef_1_IBUF,
      ADR1 => U3_sel_read(1),
      ADR2 => ef_0_IBUF,
      ADR3 => U3_sel_read(0),
      O => CHOICE683_FROM
    );
  U3_this_ef23_2_910 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE683,
      ADR1 => CHOICE686,
      ADR2 => CHOICE689,
      ADR3 => VCC,
      O => CHOICE683_GROM
    );
  CHOICE683_XUSED : X_BUF
    port map (
      I => CHOICE683_FROM,
      O => CHOICE683
    );
  CHOICE683_YUSED : X_BUF
    port map (
      I => CHOICE683_GROM,
      O => U3_this_ef23_2
    );
  U3_Ker31534 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31790,
      ADR1 => N39701,
      ADR2 => N39677,
      ADR3 => N44255,
      O => U3_ros_done_FROM
    );
  U3_n009724 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE574,
      ADR1 => U3_N31536,
      ADR2 => CHOICE570,
      ADR3 => U3_ros_done,
      O => U3_n009724_O
    );
  U3_ros_done_XUSED : X_BUF
    port map (
      I => U3_ros_done_FROM,
      O => U3_N31536
    );
  U3_ros_done_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_ros_done_SRMUX_OUTPUTNOT
    );
  U1_n00921 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29937,
      O => U1_db_error3_11_FROM
    );
  U1_Mmux_n0038_Result_11_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44094,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(11),
      ADR3 => U1_paf_reg(5),
      O => U1_Mmux_n0038_Result_11_1_O
    );
  U1_db_error3_11_XUSED : X_BUF
    port map (
      I => U1_db_error3_11_FROM,
      O => U1_n0092
    );
  U3_Ker3114418_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_N31790,
      ADR1 => U3_N31504,
      ADR2 => N44366,
      ADR3 => VCC,
      O => U3_word_count_0_FROM
    );
  U3_n0100_0_1 : X_LUT4
    generic map(
      INIT => X"FCAC"
    )
    port map (
      ADR0 => CHOICE554,
      ADR1 => U3_N31862,
      ADR2 => U3_word_count(0),
      ADR3 => U3_Ker3114418_SW0_O,
      O => U3_n0100_0_1_O
    );
  U3_word_count_0_XUSED : X_BUF
    port map (
      I => U3_word_count_0_FROM,
      O => U3_Ker3114418_SW0_O
    );
  U3_word_count_0_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_word_count_0_SRMUX_OUTPUTNOT
    );
  U3_Ker318601 : X_LUT4
    generic map(
      INIT => X"00A8"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_n0050,
      ADR2 => U1_dis_maxw_mask,
      ADR3 => U3_fmt_error_ff_2_3_Q,
      O => U3_word_count_1_FROM
    );
  U3_n0100_1_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(1),
      ADR2 => U3_n0151(1),
      ADR3 => U3_N31862,
      O => U3_n0100_1_1_O
    );
  U3_word_count_1_XUSED : X_BUF
    port map (
      I => U3_word_count_1_FROM,
      O => U3_N31862
    );
  U3_word_count_1_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_word_count_1_SRMUX_OUTPUTNOT
    );
  U3_Ker316811 : X_LUT4
    generic map(
      INIT => X"BBBA"
    )
    port map (
      ADR0 => U3_state_FFd13,
      ADR1 => U3_fmt_error_ff_2_3_Q,
      ADR2 => U3_state_FFd5,
      ADR3 => U3_state_FFd9,
      O => U3_N31683_FROM
    );
  U3_n0102_0_1 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_N31683,
      ADR2 => fout_0_IBUF,
      ADR3 => VCC,
      O => U3_N31683_GROM
    );
  U3_N31683_XUSED : X_BUF
    port map (
      I => U3_N31683_FROM,
      O => U3_N31683
    );
  U3_N31683_YUSED : X_BUF
    port map (
      I => U3_N31683_GROM,
      O => CHOICE919
    );
  U3_this_ef9 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => ef_5_IBUF,
      ADR1 => U3_sel_read(5),
      ADR2 => ef_4_IBUF,
      ADR3 => U3_sel_read(4),
      O => CHOICE686_FROM
    );
  U3_n0102_3_2 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => U3_N31636,
      ADR1 => CHOICE683,
      ADR2 => CHOICE686,
      ADR3 => CHOICE689,
      O => CHOICE686_GROM
    );
  CHOICE686_XUSED : X_BUF
    port map (
      I => CHOICE686_FROM,
      O => CHOICE686
    );
  CHOICE686_YUSED : X_BUF
    port map (
      I => CHOICE686_GROM,
      O => CHOICE771
    );
  U3_Ker3112814 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_state_FFd25,
      ADR1 => U3_fmt_error_ff_2_3_Q,
      ADR2 => U3_n0049,
      ADR3 => U1_dis_head_trail,
      O => U3_Ker3112814_O_FROM
    );
  U3_Ker3112824 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31790,
      ADR1 => U3_Ker3112814_O,
      ADR2 => U3_N31504,
      ADR3 => N44324,
      O => U3_Ker3112814_O_GROM
    );
  U3_Ker3112814_O_XUSED : X_BUF
    port map (
      I => U3_Ker3112814_O_FROM,
      O => U3_Ker3112814_O
    );
  U3_Ker3112814_O_YUSED : X_BUF
    port map (
      I => U3_Ker3112814_O_GROM,
      O => U3_N31130
    );
  U3_Ker3114410 : X_LUT4
    generic map(
      INIT => X"888A"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_fmt_error_ff_2_3_Q,
      ADR2 => U1_dis_maxw_mask,
      ADR3 => U3_n0050,
      O => CHOICE554_FROM
    );
  U3_Ker3114418 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE554,
      ADR1 => U3_N31790,
      ADR2 => U3_N31504,
      ADR3 => N44366,
      O => CHOICE554_GROM
    );
  CHOICE554_XUSED : X_BUF
    port map (
      I => CHOICE554_FROM,
      O => CHOICE554
    );
  CHOICE554_YUSED : X_BUF
    port map (
      I => CHOICE554_GROM,
      O => U3_N31146
    );
  U3_Ker311591 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_this_ef23_2,
      ADR1 => U3_state_FFd29,
      ADR2 => U3_N31790,
      ADR3 => N44434,
      O => U3_header1_reg_1_FROM
    );
  U3_n0111_1_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(1),
      ADR1 => U3_N31161,
      ADR2 => fout_1_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_1_1_O
    );
  U3_header1_reg_1_XUSED : X_BUF
    port map (
      I => U3_header1_reg_1_FROM,
      O => U3_N31161
    );
  U3_Ker31659_SW3 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => N44314,
      ADR1 => U3_state_FFd33,
      ADR2 => tp_2_OBUF,
      ADR3 => N39520,
      O => U3_Ker31659_SW3_O_FROM
    );
  U3_n0102_5_9 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => U3_s_data(5),
      ADR1 => CHOICE679,
      ADR2 => CHOICE676,
      ADR3 => U3_Ker31659_SW3_O,
      O => U3_Ker31659_SW3_O_GROM
    );
  U3_Ker31659_SW3_O_XUSED : X_BUF
    port map (
      I => U3_Ker31659_SW3_O_FROM,
      O => U3_Ker31659_SW3_O
    );
  U3_Ker31659_SW3_O_YUSED : X_BUF
    port map (
      I => U3_Ker31659_SW3_O_GROM,
      O => CHOICE625
    );
  U3_Ker311091 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31790,
      ADR1 => U3_N31504,
      ADR2 => N39486,
      ADR3 => N44422,
      O => U3_header2_reg_1_FROM
    );
  U3_n0112_1_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_1_IBUF,
      ADR2 => U3_header2_reg(1),
      ADR3 => U3_N31111,
      O => U3_n0112_1_1_O
    );
  U3_header2_reg_1_XUSED : X_BUF
    port map (
      I => U3_header2_reg_1_FROM,
      O => U3_N31111
    );
  U3_Ker318061 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => U3_state_FFd35,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N31808_FROM
    );
  U3_Ker3150217 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31761,
      ADR1 => U3_N31808,
      ADR2 => CHOICE561,
      ADR3 => CHOICE564,
      O => U3_N31808_GROM
    );
  U3_N31808_XUSED : X_BUF
    port map (
      I => U3_N31808_FROM,
      O => U3_N31808
    );
  U3_N31808_YUSED : X_BUF
    port map (
      I => U3_N31808_GROM,
      O => U3_N31504
    );
  U3_state_FFd12_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd15,
      ADR2 => U3_state_FFd12,
      ADR3 => U3_time_out,
      O => U3_state_FFd12_In1_O
    );
  U3_state_FFd11_In : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => N38705,
      ADR2 => U3_state_FFd12,
      ADR3 => U3_time_out,
      O => U3_state_FFd11_In_O
    );
  U3_state_FFd12_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd12_SRMUX_OUTPUTNOT
    );
  U3_state_FFd24_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd27_1,
      ADR2 => U3_state_FFd24,
      ADR3 => U3_time_out,
      O => U3_state_FFd24_In1_O
    );
  U3_state_FFd20_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd23,
      ADR2 => U3_state_FFd20,
      ADR3 => U3_time_out,
      O => U3_state_FFd20_In1_O
    );
  U3_state_FFd24_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd24_SRMUX_OUTPUTNOT
    );
  U3_state_FFd22_In1 : X_LUT4
    generic map(
      INIT => X"F2F2"
    )
    port map (
      ADR0 => U3_state_FFd22,
      ADR1 => tp_2_OBUF,
      ADR2 => U3_N31845,
      ADR3 => VCC,
      O => U3_state_FFd22_In1_O
    );
  U3_state_FFd21_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd25,
      ADR2 => U3_state_FFd21,
      ADR3 => U3_time_out,
      O => U3_state_FFd21_In1_O
    );
  U3_state_FFd22_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd22_SRMUX_OUTPUTNOT
    );
  U3_n009910_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_state_FFd17,
      ADR2 => U3_state_FFd6,
      ADR3 => VCC,
      O => U3_state_FFd16_FROM
    );
  U3_state_FFd15_In1 : X_LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      ADR0 => U3_state_FFd12,
      ADR1 => U3_this_ef23_1,
      ADR2 => U3_trail,
      ADR3 => U3_state_FFd16,
      O => U3_state_FFd15_In1_O
    );
  U3_state_FFd16_XUSED : X_BUF
    port map (
      I => U3_state_FFd16_FROM,
      O => N44590
    );
  U3_state_FFd16_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd16_SRMUX_OUTPUTNOT
    );
  U3_Ker318431 : X_LUT4
    generic map(
      INIT => X"00A2"
    )
    port map (
      ADR0 => U3_state_FFd25,
      ADR1 => U3_n0049,
      ADR2 => U1_dis_head_trail,
      ADR3 => U3_fmt_error_ff_2_3_Q,
      O => U3_trailer_reg_0_FROM
    );
  U3_n0113_0_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_0_Q,
      ADR2 => fout_0_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_0_1_O
    );
  U3_trailer_reg_0_XUSED : X_BUF
    port map (
      I => U3_trailer_reg_0_FROM,
      O => U3_N31845
    );
  U3_state_FFd32_In30_SW0 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => U3_time_out,
      ADR1 => U3_state_FFd32,
      ADR2 => U3_this_ef23_2,
      ADR3 => N44662,
      O => U3_state_FFd32_FROM
    );
  U3_state_FFd32_In30 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => U3_this_dontread,
      ADR1 => CHOICE440,
      ADR2 => U3_state_FFd39,
      ADR3 => U3_state_FFd32_In30_SW0_O,
      O => U3_state_FFd32_In30_O
    );
  U3_state_FFd32_XUSED : X_BUF
    port map (
      I => U3_state_FFd32_FROM,
      O => U3_state_FFd32_In30_SW0_O
    );
  U3_state_FFd32_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd32_SRMUX_OUTPUTNOT
    );
  U3_state_FFd26_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd29,
      ADR2 => U3_state_FFd26,
      ADR3 => U3_time_out,
      O => U3_state_FFd26_In1_O
    );
  U3_state_FFd25_In1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd27_1,
      ADR2 => U3_state_FFd21,
      ADR3 => VCC,
      O => U3_state_FFd25_In1_O
    );
  U3_state_FFd26_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd26_SRMUX_OUTPUTNOT
    );
  U3_this_ef23_1_911 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE683,
      ADR1 => CHOICE686,
      ADR2 => CHOICE689,
      ADR3 => VCC,
      O => U3_state_FFd27_1_FROM
    );
  U3_state_FFd27_In1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd29,
      ADR2 => U3_state_FFd24,
      ADR3 => VCC,
      O => U3_state_FFd27_1_GROM
    );
  U3_state_FFd27_1_XUSED : X_BUF
    port map (
      I => U3_state_FFd27_1_FROM,
      O => U3_this_ef23_1
    );
  U3_state_FFd27_1_YUSED : X_BUF
    port map (
      I => U3_state_FFd27_1_GROM,
      O => U3_state_FFd27_In
    );
  U3_state_FFd27_1_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd27_1_SRMUX_OUTPUTNOT
    );
  U3_n009877 : X_LUT4
    generic map(
      INIT => X"BBBA"
    )
    port map (
      ADR0 => U3_N31504,
      ADR1 => U3_time_out,
      ADR2 => U3_N31694,
      ADR3 => U3_state_FFd26,
      O => U3_state_FFd28_FROM
    );
  U3_state_FFd28_In20 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => CHOICE277,
      ADR2 => U3_time_out,
      ADR3 => CHOICE273,
      O => U3_state_FFd28_In20_O
    );
  U3_state_FFd28_XUSED : X_BUF
    port map (
      I => U3_state_FFd28_FROM,
      O => CHOICE493
    );
  U3_state_FFd28_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd28_SRMUX_OUTPUTNOT
    );
  U3_state_FFd30_In1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => tp_2_OBUF,
      ADR1 => U3_state_FFd33,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_state_FFd30_In
    );
  U3_state_FFd29_In1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_state_FFd26,
      ADR2 => U3_state_FFd32,
      ADR3 => VCC,
      O => U3_state_FFd29_In1_O
    );
  U3_state_FFd30_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd30_SRMUX_OUTPUTNOT
    );
  U3_state_FFd40_LOGIC_ZERO_912 : X_ZERO
    port map (
      O => U3_state_FFd40_LOGIC_ZERO
    );
  U3_N312351 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => U3_n0216,
      ADR1 => U3_n0218,
      ADR2 => U3_this_ef23_2,
      ADR3 => U3_N31940,
      O => U3_state_FFd40_FROM
    );
  U3_state_FFd39_In1 : X_LUT4
    generic map(
      INIT => X"F2F2"
    )
    port map (
      ADR0 => U3_N31235,
      ADR1 => U3_sel_read_5_1,
      ADR2 => U3_state_FFd40,
      ADR3 => VCC,
      O => U3_state_FFd39_In1_O
    );
  U3_state_FFd40_XUSED : X_BUF
    port map (
      I => U3_state_FFd40_FROM,
      O => U3_N31235
    );
  U3_state_FFd40_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd40_SRMUX_OUTPUTNOT
    );
  U3_n0096_2_20 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_n0121(2),
      ADR1 => U3_N31911,
      ADR2 => CHOICE970,
      ADR3 => VCC,
      O => U3_rob_id_2_FROM
    );
  U3_n0096_2_28 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n0096_2_20_O,
      ADR1 => U3_N31219,
      ADR2 => N44215,
      ADR3 => U3_rob_id(2),
      O => U3_n0096_2_28_O
    );
  U3_rob_id_2_XUSED : X_BUF
    port map (
      I => U3_rob_id_2_FROM,
      O => U3_n0096_2_20_O
    );
  U3_rob_id_2_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_rob_id_2_SRMUX_OUTPUTNOT
    );
  U3_n0096_3_9 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_n0121(3),
      ADR1 => U3_N31911,
      ADR2 => CHOICE954,
      ADR3 => VCC,
      O => U3_rob_id_3_FROM
    );
  U3_n0096_3_14 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n0096_3_9_O,
      ADR1 => U3_N31219,
      ADR2 => N44215,
      ADR3 => U3_rob_id(3),
      O => U3_n0096_3_14_O
    );
  U3_rob_id_3_XUSED : X_BUF
    port map (
      I => U3_rob_id_3_FROM,
      O => U3_n0096_3_9_O
    );
  U3_rob_id_3_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_rob_id_3_SRMUX_OUTPUTNOT
    );
  U2_Mmux_n0025_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44094,
      ADR2 => U2_byte_par(9),
      ADR3 => VCC,
      O => U2_Mmux_n0025_Result1_O
    );
  U2_Mmux_n0026_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44092,
      ADR2 => U2_byte_par(8),
      ADR3 => VCC,
      O => U2_Mmux_n0026_Result1_O
    );
  U2_Mmux_n0023_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44098,
      ADR2 => U2_byte_par(11),
      ADR3 => VCC,
      O => U2_Mmux_n0023_Result1_O
    );
  U2_Mmux_n0024_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44096,
      ADR2 => U2_byte_par(10),
      ADR3 => VCC,
      O => U2_Mmux_n0024_Result1_O
    );
  U2_Mmux_n0014_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44082,
      ADR2 => U2_byte_par(19),
      ADR3 => VCC,
      O => U2_Mmux_n0014_Result1_O
    );
  U2_Mmux_n0015_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44080,
      ADR2 => U2_byte_par(18),
      ADR3 => VCC,
      O => U2_Mmux_n0015_Result1_O
    );
  U2_Mmux_n0002_Result_1_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44074,
      ADR2 => U2_word_par(0),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_1_1_O
    );
  U2_Mmux_n0002_Result_0_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44072,
      ADR2 => parcheck,
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_0_1_O
    );
  U2_Mmux_n0004_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44102,
      ADR2 => U2_byte_par(29),
      ADR3 => VCC,
      O => U2_Mmux_n0004_Result1_O
    );
  U2_Mmux_n0005_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44100,
      ADR2 => U2_byte_par(28),
      ADR3 => VCC,
      O => U2_Mmux_n0005_Result1_O
    );
  U2_Mmux_n0021_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44102,
      ADR2 => U2_byte_par(13),
      ADR3 => VCC,
      O => U2_Mmux_n0021_Result1_O
    );
  U2_Mmux_n0022_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44100,
      ADR2 => U2_byte_par(12),
      ADR3 => VCC,
      O => U2_Mmux_n0022_Result1_O
    );
  U2_Mmux_n0012_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44086,
      ADR2 => U2_byte_par(21),
      ADR3 => VCC,
      O => U2_Mmux_n0012_Result1_O
    );
  U2_Mmux_n0013_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44084,
      ADR2 => U2_byte_par(20),
      ADR3 => VCC,
      O => U2_Mmux_n0013_Result1_O
    );
  U2_Mmux_n0002_Result_3_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44078,
      ADR2 => U2_word_par(2),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_3_1_O
    );
  U2_Mmux_n0002_Result_2_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44076,
      ADR2 => U2_word_par(1),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_2_1_O
    );
  U2_Mmux_n0010_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44090,
      ADR2 => U2_byte_par(23),
      ADR3 => VCC,
      O => U2_Mmux_n0010_Result1_O
    );
  U2_Mmux_n0011_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44088,
      ADR2 => U2_byte_par(22),
      ADR3 => VCC,
      O => U2_Mmux_n0011_Result1_O
    );
  U2_Mmux_n0018_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44074,
      ADR2 => U2_byte_par(15),
      ADR3 => VCC,
      O => U2_Mmux_n0018_Result1_O
    );
  U2_Mmux_n0019_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44072,
      ADR2 => U2_byte_par(14),
      ADR3 => VCC,
      O => U2_Mmux_n0019_Result1_O
    );
  U2_Mmux_n0002_Result_5_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44082,
      ADR2 => U2_word_par(4),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_5_1_O
    );
  U2_Mmux_n0002_Result_4_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44080,
      ADR2 => U2_word_par(3),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_4_1_O
    );
  U2_Mmux_n0008_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44094,
      ADR2 => U2_byte_par(25),
      ADR3 => VCC,
      O => U2_Mmux_n0008_Result1_O
    );
  U2_Mmux_n0009_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44092,
      ADR2 => U2_byte_par(24),
      ADR3 => VCC,
      O => U2_Mmux_n0009_Result1_O
    );
  U2_Mmux_n0016_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44078,
      ADR2 => U2_byte_par(17),
      ADR3 => VCC,
      O => U2_Mmux_n0016_Result1_O
    );
  U2_Mmux_n0017_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44076,
      ADR2 => U2_byte_par(16),
      ADR3 => VCC,
      O => U2_Mmux_n0017_Result1_O
    );
  U2_Mmux_n0002_Result_7_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44086,
      ADR2 => U2_word_par(6),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_7_1_O
    );
  U2_Mmux_n0002_Result_6_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44084,
      ADR2 => U2_word_par(5),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_6_1_O
    );
  U2_Mmux_n0006_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44098,
      ADR2 => U2_byte_par(27),
      ADR3 => VCC,
      O => U2_Mmux_n0006_Result1_O
    );
  U2_Mmux_n0007_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => N44096,
      ADR2 => U2_byte_par(26),
      ADR3 => VCC,
      O => U2_Mmux_n0007_Result1_O
    );
  U2_Mmux_n0002_Result_9_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44090,
      ADR2 => U2_word_par(8),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_9_1_O
    );
  U2_Mmux_n0002_Result_8_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => N44088,
      ADR2 => U2_word_par(7),
      ADR3 => VCC,
      O => U2_Mmux_n0002_Result_8_1_O
    );
  U3_n0112_11_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => fout_11_IBUF,
      ADR2 => U3_header2_reg(11),
      ADR3 => U3_N31111,
      O => U3_n0112_11_1_O
    );
  U3_n0112_10_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => fout_10_IBUF,
      ADR2 => U3_header2_reg(10),
      ADR3 => U3_N31111,
      O => U3_n0112_10_1_O
    );
  U3_n0112_13_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => fout_13_IBUF,
      ADR2 => U3_header2_reg(13),
      ADR3 => U3_N31111,
      O => U3_n0112_13_1_O
    );
  U3_n0112_12_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => fout_12_IBUF,
      ADR2 => U3_header2_reg(12),
      ADR3 => U3_N31111,
      O => U3_n0112_12_1_O
    );
  U3_n0112_15_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_15_IBUF,
      ADR2 => U3_header2_reg(15),
      ADR3 => U3_N31111,
      O => U3_n0112_15_1_O
    );
  U3_n0112_14_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => fout_14_IBUF,
      ADR2 => U3_header2_reg(14),
      ADR3 => U3_N31111,
      O => U3_n0112_14_1_O
    );
  U3_n0113_3_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_3_Q,
      ADR2 => fout_3_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_3_1_O
    );
  U3_n0113_2_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_2_Q,
      ADR2 => fout_2_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_2_1_O
    );
  U3_n0113_5_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_5_Q,
      ADR2 => fout_5_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_5_1_O
    );
  U3_n0113_4_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_4_Q,
      ADR2 => fout_4_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_4_1_O
    );
  U3_n0113_7_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_7_Q,
      ADR2 => fout_7_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_7_1_O
    );
  U3_n0113_6_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_6_Q,
      ADR2 => fout_6_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_6_1_O
    );
  U3_n0113_9_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_9_Q,
      ADR2 => fout_9_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_9_1_O
    );
  U3_n0113_8_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31130,
      ADR1 => U3_trailer_reg_8_Q,
      ADR2 => fout_8_IBUF,
      ADR3 => U3_N31845,
      O => U3_n0113_8_1_O
    );
  U3_Ker312541 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31749,
      ADR1 => U3_state_FFd32,
      ADR2 => U3_state_FFd26,
      ADR3 => U3_N31694,
      O => U3_N31256_FROM
    );
  U3_Ker3178819 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31256,
      ADR1 => CHOICE1036,
      ADR2 => U3_state_FFd16,
      ADR3 => N44666,
      O => U3_N31256_GROM
    );
  U3_N31256_XUSED : X_BUF
    port map (
      I => U3_N31256_FROM,
      O => U3_N31256
    );
  U3_N31256_YUSED : X_BUF
    port map (
      I => U3_N31256_GROM,
      O => U3_N31790
    );
  U3_n0100_3_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(3),
      ADR2 => U3_n0151(3),
      ADR3 => U3_N31862,
      O => U3_n0100_3_1_O
    );
  U3_n0100_2_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(2),
      ADR2 => U3_n0151(2),
      ADR3 => U3_N31862,
      O => U3_n0100_2_1_O
    );
  U3_word_count_3_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_word_count_3_SRMUX_OUTPUTNOT
    );
  U3_n0100_5_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(5),
      ADR2 => U3_n0151(5),
      ADR3 => U3_N31862,
      O => U3_n0100_5_1_O
    );
  U3_n0100_4_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(4),
      ADR2 => U3_n0151(4),
      ADR3 => U3_N31862,
      O => U3_n0100_4_1_O
    );
  U3_word_count_5_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_word_count_5_SRMUX_OUTPUTNOT
    );
  U3_n0100_7_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(7),
      ADR2 => U3_n0151(7),
      ADR3 => U3_N31862,
      O => U3_n0100_7_1_O
    );
  U3_n0100_6_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(6),
      ADR2 => U3_n0151(6),
      ADR3 => U3_N31862,
      O => U3_n0100_6_1_O
    );
  U3_word_count_7_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_word_count_7_SRMUX_OUTPUTNOT
    );
  U3_n0100_9_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(9),
      ADR2 => U3_n0151(9),
      ADR3 => U3_N31862,
      O => U3_n0100_9_1_O
    );
  U3_n0100_8_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_N31146,
      ADR1 => U3_word_count(8),
      ADR2 => U3_n0151(8),
      ADR3 => U3_N31862,
      O => U3_n0100_8_1_O
    );
  U3_word_count_9_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_word_count_9_SRMUX_OUTPUTNOT
    );
  U3_Ker31405 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => U3_dontread(3),
      ADR1 => N41351,
      ADR2 => U3_dontread(2),
      ADR3 => U1_dis_errorw,
      O => U3_N31407_FROM
    );
  U3_Ker31181_SW0 : X_LUT4
    generic map(
      INIT => X"B0B0"
    )
    port map (
      ADR0 => U3_N31407,
      ADR1 => tp_2_OBUF,
      ADR2 => U3_state_FFd38,
      ADR3 => VCC,
      O => U3_N31407_GROM
    );
  U3_N31407_XUSED : X_BUF
    port map (
      I => U3_N31407_FROM,
      O => U3_N31407
    );
  U3_N31407_YUSED : X_BUF
    port map (
      I => U3_N31407_GROM,
      O => N39571
    );
  U3_n0102_8_30_SW1 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd33,
      ADR1 => U3_s_data(8),
      ADR2 => U3_state_FFd36_In,
      ADR3 => VCC,
      O => U3_n0102_8_30_SW1_O_FROM
    );
  U3_Ker311701_SW0 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31556,
      ADR1 => U3_rob_id(0),
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_8_30_SW1_O,
      O => U3_n0102_8_30_SW1_O_GROM
    );
  U3_n0102_8_30_SW1_O_XUSED : X_BUF
    port map (
      I => U3_n0102_8_30_SW1_O_FROM,
      O => U3_n0102_8_30_SW1_O
    );
  U3_n0102_8_30_SW1_O_YUSED : X_BUF
    port map (
      I => U3_n0102_8_30_SW1_O_GROM,
      O => N44348
    );
  U3_n0102_8_30_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd36_In,
      ADR1 => U3_s_data(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0102_8_30_SW0_O_FROM
    );
  U3_Ker311701_SW1 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31556,
      ADR1 => U3_rob_id(0),
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_8_30_SW0_O,
      O => U3_n0102_8_30_SW0_O_GROM
    );
  U3_n0102_8_30_SW0_O_XUSED : X_BUF
    port map (
      I => U3_n0102_8_30_SW0_O_FROM,
      O => U3_n0102_8_30_SW0_O
    );
  U3_n0102_8_30_SW0_O_YUSED : X_BUF
    port map (
      I => U3_n0102_8_30_SW0_O_GROM,
      O => N44350
    );
  U3_n0102_9_30_SW1 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd33,
      ADR1 => U3_s_data(9),
      ADR2 => U3_state_FFd36_In,
      ADR3 => VCC,
      O => U3_n0102_9_30_SW1_O_FROM
    );
  U3_Ker311701_SW2 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31556,
      ADR1 => U3_rob_id(1),
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_9_30_SW1_O,
      O => U3_n0102_9_30_SW1_O_GROM
    );
  U3_n0102_9_30_SW1_O_XUSED : X_BUF
    port map (
      I => U3_n0102_9_30_SW1_O_FROM,
      O => U3_n0102_9_30_SW1_O
    );
  U3_n0102_9_30_SW1_O_YUSED : X_BUF
    port map (
      I => U3_n0102_9_30_SW1_O_GROM,
      O => N44354
    );
  U3_n0102_9_30_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd36_In,
      ADR1 => U3_s_data(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0102_9_30_SW0_O_FROM
    );
  U3_Ker311701_SW3 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31556,
      ADR1 => U3_rob_id(1),
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_9_30_SW0_O,
      O => U3_n0102_9_30_SW0_O_GROM
    );
  U3_n0102_9_30_SW0_O_XUSED : X_BUF
    port map (
      I => U3_n0102_9_30_SW0_O_FROM,
      O => U3_n0102_9_30_SW0_O
    );
  U3_n0102_9_30_SW0_O_YUSED : X_BUF
    port map (
      I => U3_n0102_9_30_SW0_O_GROM,
      O => N44356
    );
  U3_n0102_12_8_SW1 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd33,
      ADR1 => U3_s_data(12),
      ADR2 => U3_state_FFd36_In,
      ADR3 => VCC,
      O => U3_n0102_12_8_SW1_O_FROM
    );
  U3_Ker311701_SW4 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31556,
      ADR1 => U3_rob_id(4),
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_12_8_SW1_O,
      O => U3_n0102_12_8_SW1_O_GROM
    );
  U3_n0102_12_8_SW1_O_XUSED : X_BUF
    port map (
      I => U3_n0102_12_8_SW1_O_FROM,
      O => U3_n0102_12_8_SW1_O
    );
  U3_n0102_12_8_SW1_O_YUSED : X_BUF
    port map (
      I => U3_n0102_12_8_SW1_O_GROM,
      O => N44360
    );
  U3_n0102_12_8_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd36_In,
      ADR1 => U3_s_data(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0102_12_8_SW0_O_FROM
    );
  U3_Ker311701_SW5 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31556,
      ADR1 => U3_rob_id(4),
      ADR2 => U3_N31548,
      ADR3 => U3_n0102_12_8_SW0_O,
      O => U3_n0102_12_8_SW0_O_GROM
    );
  U3_n0102_12_8_SW0_O_XUSED : X_BUF
    port map (
      I => U3_n0102_12_8_SW0_O_FROM,
      O => U3_n0102_12_8_SW0_O
    );
  U3_n0102_12_8_SW0_O_YUSED : X_BUF
    port map (
      I => U3_n0102_12_8_SW0_O_GROM,
      O => N44362
    );
  U3_n0112_0_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => fout_0_IBUF,
      ADR2 => U3_header2_reg(0),
      ADR3 => U3_N31111,
      O => U3_n0112_0_1_O
    );
  U3_n0111_0_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(0),
      ADR1 => U3_N31161,
      ADR2 => fout_0_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_0_1_O
    );
  U3_n0111_3_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(3),
      ADR1 => U3_N31161,
      ADR2 => fout_3_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_3_1_O
    );
  U3_n0111_2_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(2),
      ADR1 => U3_N31161,
      ADR2 => fout_2_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_2_1_O
    );
  U3_n0111_5_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(5),
      ADR1 => U3_N31161,
      ADR2 => fout_5_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_5_1_O
    );
  U3_n0111_4_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(4),
      ADR1 => U3_N31161,
      ADR2 => fout_4_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_4_1_O
    );
  U3_n0111_7_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(7),
      ADR1 => U3_N31161,
      ADR2 => fout_7_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_7_1_O
    );
  U3_n0111_6_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_header1_reg(6),
      ADR1 => U3_N31161,
      ADR2 => fout_6_IBUF,
      ADR3 => U3_N31900,
      O => U3_n0111_6_1_O
    );
  U2_Mmux_n0038_Result_11_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44072,
      ADR2 => U2_pae_paf_reg(12),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_11_1_O
    );
  U2_Mmux_n0038_Result_10_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44092,
      ADR2 => U2_pae_paf_reg(11),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_10_1_O
    );
  U2_Mmux_n0038_Result_13_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44076,
      ADR2 => U2_pae_paf_reg(14),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_13_1_O
    );
  U2_Mmux_n0038_Result_12_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44074,
      ADR2 => U2_pae_paf_reg(13),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_12_1_O
    );
  U2_Mmux_n0038_Result_21_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44092,
      ADR2 => U2_pae_paf_reg(0),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_21_1_O
    );
  U2_Mmux_n0038_Result_20_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44090,
      ADR2 => U2_pae_paf_reg(21),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_20_1_O
    );
  U2_Mmux_n0038_Result_15_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44080,
      ADR2 => U2_pae_paf_reg(16),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_15_1_O
    );
  U2_Mmux_n0038_Result_14_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44078,
      ADR2 => U2_pae_paf_reg(15),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_14_1_O
    );
  U2_Mmux_n0038_Result_17_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44084,
      ADR2 => U2_pae_paf_reg(18),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_17_1_O
    );
  U2_Mmux_n0038_Result_16_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44082,
      ADR2 => U2_pae_paf_reg(17),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_16_1_O
    );
  U1_enw_paf_value1 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29930,
      O => U2_pae_paf_reg_18_FROM
    );
  U2_Mmux_n0038_Result_18_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44086,
      ADR2 => U2_pae_paf_reg(19),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_18_1_O
    );
  U2_pae_paf_reg_18_XUSED : X_BUF
    port map (
      I => U2_pae_paf_reg_18_FROM,
      O => enw_paf_value
    );
  U2_Mmux_n0038_Result_19_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_paf_value,
      ADR1 => N44088,
      ADR2 => U2_pae_paf_reg(20),
      ADR3 => VCC,
      O => U2_Mmux_n0038_Result_19_1_O
    );
  U3_Ker312171 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31790,
      ADR1 => N39701,
      ADR2 => U3_N31808,
      ADR3 => N44426,
      O => U3_rob_id_0_FROM
    );
  U3_n0096_0_1 : X_LUT4
    generic map(
      INIT => X"FCAC"
    )
    port map (
      ADR0 => U3_N31219,
      ADR1 => U3_N31911,
      ADR2 => U3_rob_id(0),
      ADR3 => N44215,
      O => U3_n0096_0_1_O
    );
  U3_rob_id_0_XUSED : X_BUF
    port map (
      I => U3_rob_id_0_FROM,
      O => U3_N31219
    );
  U3_rob_id_0_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_rob_id_0_SRMUX_OUTPUTNOT
    );
  U3_state_FFd13_In1 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => U3_state_FFd15,
      ADR1 => CHOICE683,
      ADR2 => CHOICE686,
      ADR3 => CHOICE689,
      O => U3_state_FFd13_FROM
    );
  U3_Ker317071 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd14,
      ADR1 => U3_state_FFd13_In,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_state_FFd13_GROM
    );
  U3_state_FFd13_XUSED : X_BUF
    port map (
      I => U3_state_FFd13_FROM,
      O => U3_state_FFd13_In
    );
  U3_state_FFd13_YUSED : X_BUF
    port map (
      I => U3_state_FFd13_GROM,
      O => U3_N31709
    );
  U3_state_FFd13_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd13_SRMUX_OUTPUTNOT
    );
  U3_Ker317234 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd40,
      ADR1 => U3_state_FFd37,
      ADR2 => U3_state_FFd35,
      ADR3 => U3_state_FFd39,
      O => U3_Ker317234_O_FROM
    );
  U3_Ker317235 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31749,
      ADR1 => U3_N31694,
      ADR2 => U3_Ker317234_O,
      ADR3 => N44290,
      O => U3_Ker317234_O_GROM
    );
  U3_Ker317234_O_XUSED : X_BUF
    port map (
      I => U3_Ker317234_O_FROM,
      O => U3_Ker317234_O
    );
  U3_Ker317234_O_YUSED : X_BUF
    port map (
      I => U3_Ker317234_O_GROM,
      O => CHOICE676
    );
  U2_Mmux_n0035_Result1 : X_LUT4
    generic map(
      INIT => X"8DD8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44074,
      ADR2 => U2_Mxor_cpar_1_Xo(4),
      ADR3 => U2_Mxor_cpar_1_Xo(5),
      O => U2_Mmux_n0035_Result1_O
    );
  U2_Mmux_n0036_Result1 : X_LUT4
    generic map(
      INIT => X"8DD8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44072,
      ADR2 => U2_Mxor_cpar_0_Xo(4),
      ADR3 => U2_Mxor_cpar_0_Xo(5),
      O => U2_Mmux_n0036_Result1_O
    );
  U2_Mmux_n0033_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44078,
      ADR2 => U2_byte_par(1),
      ADR3 => VCC,
      O => U2_Mmux_n0033_Result1_O
    );
  U2_Mmux_n0034_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44076,
      ADR2 => U2_byte_par(0),
      ADR3 => VCC,
      O => U2_Mmux_n0034_Result1_O
    );
  U2_Mmux_n0031_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44082,
      ADR2 => U2_byte_par(3),
      ADR3 => VCC,
      O => U2_Mmux_n0031_Result1_O
    );
  U2_Mmux_n0032_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44080,
      ADR2 => U2_byte_par(2),
      ADR3 => VCC,
      O => U2_Mmux_n0032_Result1_O
    );
  U3_Ker319091 : X_LUT4
    generic map(
      INIT => X"1303"
    )
    port map (
      ADR0 => U3_fmt_error_ff_2_3_Q,
      ADR1 => U3_sel_read(5),
      ADR2 => N44302,
      ADR3 => U3_n0218,
      O => U3_N31911_FROM
    );
  U3_n0096_4_6 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_n0121(4),
      ADR1 => U3_N31911,
      ADR2 => CHOICE960,
      ADR3 => VCC,
      O => U3_N31911_GROM
    );
  U3_N31911_XUSED : X_BUF
    port map (
      I => U3_N31911_FROM,
      O => U3_N31911
    );
  U3_N31911_YUSED : X_BUF
    port map (
      I => U3_N31911_GROM,
      O => CHOICE962
    );
  U2_Mmux_n0029_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44086,
      ADR2 => U2_byte_par(5),
      ADR3 => VCC,
      O => U2_Mmux_n0029_Result1_O
    );
  U2_Mmux_n0030_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44084,
      ADR2 => U2_byte_par(4),
      ADR3 => VCC,
      O => U2_Mmux_n0030_Result1_O
    );
  U2_Mmux_n0027_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44090,
      ADR2 => U2_byte_par(7),
      ADR3 => VCC,
      O => U2_Mmux_n0027_Result1_O
    );
  U2_Mmux_n0028_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => enw_byte_par0,
      ADR1 => N44088,
      ADR2 => U2_byte_par(6),
      ADR3 => VCC,
      O => U2_Mmux_n0028_Result1_O
    );
  U3_n02531 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_sel_read(5),
      ADR1 => CHOICE683,
      ADR2 => CHOICE686,
      ADR3 => CHOICE689,
      O => U3_n0253_FROM
    );
  U3_Ker31197_SW4 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => N39609,
      ADR1 => U3_state_FFd23,
      ADR2 => U3_state_FFd5,
      ADR3 => U3_n0253,
      O => U3_n0253_GROM
    );
  U3_n0253_XUSED : X_BUF
    port map (
      I => U3_n0253_FROM,
      O => U3_n0253
    );
  U3_n0253_YUSED : X_BUF
    port map (
      I => U3_n0253_GROM,
      O => N44215
    );
  U3_n0112_3_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_3_IBUF,
      ADR2 => U3_header2_reg(3),
      ADR3 => U3_N31111,
      O => U3_n0112_3_1_O
    );
  U3_n0112_2_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_2_IBUF,
      ADR2 => U3_header2_reg(2),
      ADR3 => U3_N31111,
      O => U3_n0112_2_1_O
    );
  U3_n0112_5_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_5_IBUF,
      ADR2 => U3_header2_reg(5),
      ADR3 => U3_N31111,
      O => U3_n0112_5_1_O
    );
  U3_n0112_4_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_4_IBUF,
      ADR2 => U3_header2_reg(4),
      ADR3 => U3_N31111,
      O => U3_n0112_4_1_O
    );
  U3_n0112_7_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_7_IBUF,
      ADR2 => U3_header2_reg(7),
      ADR3 => U3_N31111,
      O => U3_n0112_7_1_O
    );
  U3_n0112_6_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_6_IBUF,
      ADR2 => U3_header2_reg(6),
      ADR3 => U3_N31111,
      O => U3_n0112_6_1_O
    );
  U3_n0112_9_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_9_IBUF,
      ADR2 => U3_header2_reg(9),
      ADR3 => U3_N31111,
      O => U3_n0112_9_1_O
    );
  U3_n0112_8_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd27_1,
      ADR1 => fout_8_IBUF,
      ADR2 => U3_header2_reg(8),
      ADR3 => U3_N31111,
      O => U3_n0112_8_1_O
    );
  U3_n02161 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd13,
      ADR1 => U3_state_FFd2,
      ADR2 => U3_state_FFd1,
      ADR3 => U3_state_FFd37,
      O => U3_n0216_FROM
    );
  U3_N312351_SW0 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => U3_n0216,
      ADR1 => U3_state_FFd31,
      ADR2 => U1_dis_ffreg_mask,
      ADR3 => VCC,
      O => U3_n0216_GROM
    );
  U3_n0216_XUSED : X_BUF
    port map (
      I => U3_n0216_FROM,
      O => U3_n0216
    );
  U3_n0216_YUSED : X_BUF
    port map (
      I => U3_n0216_GROM,
      O => N44302
    );
  U3_n0096_1_SW0 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => ceros_id_0_IBUF,
      ADR1 => U3_state_FFd40,
      ADR2 => U3_N31911,
      ADR3 => U3_n0121(1),
      O => U3_rob_id_1_FROM
    );
  U3_n0096_1_Q : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_n0096_1_SW0_O,
      ADR1 => U3_N31219,
      ADR2 => N44215,
      ADR3 => U3_rob_id(1),
      O => U3_n0096_1_O
    );
  U3_rob_id_1_XUSED : X_BUF
    port map (
      I => U3_rob_id_1_FROM,
      O => U3_n0096_1_SW0_O
    );
  U3_rob_id_1_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_rob_id_1_SRMUX_OUTPUTNOT
    );
  U3_n0096_4_10 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE962,
      ADR1 => U3_N31219,
      ADR2 => N44215,
      ADR3 => U3_rob_id(4),
      O => U3_n0096_4_10_O
    );
  U3_rob_id_4_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_rob_id_4_SRMUX_OUTPUTNOT
    );
  U1_enw_byte_par01 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N30014,
      ADR3 => U1_N29954,
      O => enw_byte_par0_FROM
    );
  U2_n01141 : X_LUT4
    generic map(
      INIT => X"4445"
    )
    port map (
      ADR0 => enw_word_par,
      ADR1 => enw_byte_par0,
      ADR2 => enw_byte_par1,
      ADR3 => U1_per_fifo,
      O => enw_byte_par0_GROM
    );
  enw_byte_par0_XUSED : X_BUF
    port map (
      I => enw_byte_par0_FROM,
      O => enw_byte_par0
    );
  enw_byte_par0_YUSED : X_BUF
    port map (
      I => enw_byte_par0_GROM,
      O => U2_n0114
    );
  U1_Mmux_n0038_Result_10_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44092,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(10),
      ADR3 => U1_paf_reg(4),
      O => U1_Mmux_n0038_Result_10_1_O
    );
  U1_Mmux_n0036_Result_10_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44092,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(10),
      ADR3 => U3_timed_out(4),
      O => U1_Mmux_n0036_Result_10_1_O
    );
  U3_n0102_0_38 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U1_ff_reg(5),
      ADR1 => U3_sel_read(5),
      ADR2 => U1_ff_reg(4),
      ADR3 => U3_sel_read(4),
      O => U1_db_error2_10_FROM
    );
  U1_Mmux_n0037_Result_10_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44092,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(10),
      ADR3 => U1_ff_reg(4),
      O => U1_Mmux_n0037_Result_10_1_O
    );
  U1_db_error2_10_XUSED : X_BUF
    port map (
      I => U1_db_error2_10_FROM,
      O => CHOICE934
    );
  U3_Ker316691 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_state_FFd5,
      ADR2 => U3_fmt_error_ff_2_3_Q,
      ADR3 => U3_state_FFd13,
      O => U3_N31671_FROM
    );
  U3_n0102_10_15 : X_LUT4
    generic map(
      INIT => X"A0B3"
    )
    port map (
      ADR0 => U3_N31671,
      ADR1 => U3_this_paf,
      ADR2 => fout_10_IBUF,
      ADR3 => N44380,
      O => U3_N31671_GROM
    );
  U3_N31671_XUSED : X_BUF
    port map (
      I => U3_N31671_FROM,
      O => U3_N31671
    );
  U3_N31671_YUSED : X_BUF
    port map (
      I => U3_N31671_GROM,
      O => CHOICE741
    );
  U3_Ker317591 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd34,
      ADR1 => U3_state_FFd33,
      ADR2 => U3_state_FFd19,
      ADR3 => U3_state_FFd7,
      O => U3_N31761_FROM
    );
  U3_Ker31654_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => U3_state_FFd10,
      ADR2 => U3_N31761,
      ADR3 => VCC,
      O => U3_N31761_GROM
    );
  U3_N31761_XUSED : X_BUF
    port map (
      I => U3_N31761_FROM,
      O => U3_N31761
    );
  U3_N31761_YUSED : X_BUF
    port map (
      I => U3_N31761_GROM,
      O => N39701
    );
  U3_Ker311284 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd10,
      ADR1 => U3_state_FFd39,
      ADR2 => U3_state_FFd29,
      ADR3 => U3_state_FFd27,
      O => U3_Ker311284_O_FROM
    );
  U3_Ker31718_SW1 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => N39486,
      ADR1 => U3_Ker311284_O,
      ADR2 => U3_state_FFd31,
      ADR3 => VCC,
      O => U3_Ker311284_O_GROM
    );
  U3_Ker311284_O_XUSED : X_BUF
    port map (
      I => U3_Ker311284_O_FROM,
      O => U3_Ker311284_O
    );
  U3_Ker311284_O_YUSED : X_BUF
    port map (
      I => U3_Ker311284_O_GROM,
      O => N44324
    );
  U3_Ker31718_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd13,
      ADR1 => U3_state_FFd23,
      ADR2 => U3_state_FFd5,
      ADR3 => VCC,
      O => N39486_FROM
    );
  U3_Ker31718_SW2 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE556,
      ADR1 => N39486,
      ADR2 => U3_state_FFd31,
      ADR3 => VCC,
      O => N39486_GROM
    );
  N39486_XUSED : X_BUF
    port map (
      I => N39486_FROM,
      O => N39486
    );
  N39486_YUSED : X_BUF
    port map (
      I => N39486_GROM,
      O => N44366
    );
  U3_Ker316491_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd39,
      ADR1 => U3_state_FFd10,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_Ker316491_SW0_O_FROM
    );
  U3_Ker31718_SW3 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_Ker316491_SW0_O,
      ADR1 => U3_state_FFd29,
      ADR2 => U3_state_FFd25,
      ADR3 => U3_state_FFd31,
      O => U3_Ker316491_SW0_O_GROM
    );
  U3_Ker316491_SW0_O_XUSED : X_BUF
    port map (
      I => U3_Ker316491_SW0_O_FROM,
      O => U3_Ker316491_SW0_O
    );
  U3_Ker316491_SW0_O_YUSED : X_BUF
    port map (
      I => U3_Ker316491_SW0_O_GROM,
      O => N44422
    );
  U3_n0102_11_11 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => parcheck,
      ADR1 => U3_state_FFd14,
      ADR2 => U3_N31919,
      ADR3 => U3_this_ef23_2,
      O => U3_n0102_11_11_O_FROM
    );
  U3_n0102_11_13 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => fout_11_IBUF,
      ADR1 => U3_N31671,
      ADR2 => U3_n0102_11_11_O,
      ADR3 => VCC,
      O => U3_n0102_11_11_O_GROM
    );
  U3_n0102_11_11_O_XUSED : X_BUF
    port map (
      I => U3_n0102_11_11_O_FROM,
      O => U3_n0102_11_11_O
    );
  U3_n0102_11_11_O_YUSED : X_BUF
    port map (
      I => U3_n0102_11_11_O_GROM,
      O => CHOICE758
    );
  U3_Ker31405_SW1 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => U1_dis_errorw,
      ADR2 => tp_2_OBUF,
      ADR3 => VCC,
      O => U3_state_FFd36_FROM
    );
  U3_state_FFd36_In1 : X_LUT4
    generic map(
      INIT => X"5551"
    )
    port map (
      ADR0 => U3_Ker31405_SW1_O,
      ADR1 => N41351,
      ADR2 => U3_dontread(3),
      ADR3 => U3_dontread(2),
      O => U3_state_FFd36_GROM
    );
  U3_state_FFd36_XUSED : X_BUF
    port map (
      I => U3_state_FFd36_FROM,
      O => U3_Ker31405_SW1_O
    );
  U3_state_FFd36_YUSED : X_BUF
    port map (
      I => U3_state_FFd36_GROM,
      O => U3_state_FFd36_In
    );
  U3_state_FFd36_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd36_SRMUX_OUTPUTNOT
    );
  U1_Mmux_n0015_Result_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44086,
      ADR1 => enw_maxw,
      ADR2 => ff_1_IBUF,
      ADR3 => U1_ff_reg(1),
      O => U1_Mmux_n0015_Result_1_1_O
    );
  U1_Mmux_n0015_Result_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44084,
      ADR1 => enw_maxw,
      ADR2 => ff_0_IBUF,
      ADR3 => U1_ff_reg(0),
      O => U1_Mmux_n0015_Result_0_1_O
    );
  U1_Mmux_n0015_Result_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44090,
      ADR1 => enw_maxw,
      ADR2 => ff_3_IBUF,
      ADR3 => U1_ff_reg(3),
      O => U1_Mmux_n0015_Result_3_1_O
    );
  U1_Mmux_n0015_Result_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44088,
      ADR1 => enw_maxw,
      ADR2 => ff_2_IBUF,
      ADR3 => U1_ff_reg(2),
      O => U1_Mmux_n0015_Result_2_1_O
    );
  U1_enw_byte_par11 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => U1_N29954,
      ADR1 => add_1_IBUF,
      ADR2 => add_0_IBUF,
      ADR3 => U1_N30014,
      O => enw_byte_par1_FROM
    );
  U2_n00971 : X_LUT4
    generic map(
      INIT => X"000B"
    )
    port map (
      ADR0 => enw_byte_par1,
      ADR1 => U1_per_fifo,
      ADR2 => enw_byte_par0,
      ADR3 => enw_word_par,
      O => enw_byte_par1_GROM
    );
  enw_byte_par1_XUSED : X_BUF
    port map (
      I => enw_byte_par1_FROM,
      O => enw_byte_par1
    );
  enw_byte_par1_YUSED : X_BUF
    port map (
      I => enw_byte_par1_GROM,
      O => U2_n0097
    );
  U3_this_ff4 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => ff_5_IBUF,
      ADR1 => U3_sel_read(5),
      ADR2 => ff_4_IBUF,
      ADR3 => U3_sel_read(4),
      O => U1_ff_reg_4_FROM
    );
  U1_Mmux_n0015_Result_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44092,
      ADR1 => enw_maxw,
      ADR2 => ff_4_IBUF,
      ADR3 => U1_ff_reg(4),
      O => U1_Mmux_n0015_Result_4_1_O
    );
  U1_ff_reg_4_XUSED : X_BUF
    port map (
      I => U1_ff_reg_4_FROM,
      O => CHOICE394
    );
  U1_Mmux_n0036_Result_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44074,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(1),
      ADR3 => U1_hasunlock(1),
      O => U1_Mmux_n0036_Result_1_1_O
    );
  U1_Mmux_n0036_Result_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44072,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(0),
      ADR3 => U1_hasunlock(0),
      O => U1_Mmux_n0036_Result_0_1_O
    );
  U1_Mmux_n0036_Result_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44078,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(3),
      ADR3 => U1_hasunlock(3),
      O => U1_Mmux_n0036_Result_3_1_O
    );
  U1_Mmux_n0036_Result_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44076,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(2),
      ADR3 => U1_hasunlock(2),
      O => U1_Mmux_n0036_Result_2_1_O
    );
  U1_Mmux_n0037_Result_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44074,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(1),
      ADR3 => U3_evid_mis(1),
      O => U1_Mmux_n0037_Result_1_1_O
    );
  U1_Mmux_n0037_Result_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44072,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(0),
      ADR3 => U3_evid_mis(0),
      O => U1_Mmux_n0037_Result_0_1_O
    );
  U1_Mmux_n0036_Result_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44082,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(5),
      ADR3 => U1_hasunlock(5),
      O => U1_Mmux_n0036_Result_5_1_O
    );
  U1_Mmux_n0036_Result_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44080,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(4),
      ADR3 => U1_hasunlock(4),
      O => U1_Mmux_n0036_Result_4_1_O
    );
  U1_Mmux_n0037_Result_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44078,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(3),
      ADR3 => U3_evid_mis(3),
      O => U1_Mmux_n0037_Result_3_1_O
    );
  U1_Mmux_n0037_Result_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44076,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(2),
      ADR3 => U3_evid_mis(2),
      O => U1_Mmux_n0037_Result_2_1_O
    );
  U1_Mmux_n0036_Result_7_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44086,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(7),
      ADR3 => U3_timed_out(1),
      O => U1_Mmux_n0036_Result_7_1_O
    );
  U1_Mmux_n0036_Result_6_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44084,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(6),
      ADR3 => U3_timed_out(0),
      O => U1_Mmux_n0036_Result_6_1_O
    );
  U1_Mmux_n0037_Result_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44082,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(5),
      ADR3 => U3_evid_mis(5),
      O => U1_Mmux_n0037_Result_5_1_O
    );
  U1_Mmux_n0037_Result_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44080,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(4),
      ADR3 => U3_evid_mis(4),
      O => U1_Mmux_n0037_Result_4_1_O
    );
  U1_Mmux_n0036_Result_9_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44090,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(9),
      ADR3 => U3_timed_out(3),
      O => U1_Mmux_n0036_Result_9_1_O
    );
  U1_Mmux_n0036_Result_8_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44088,
      ADR1 => U1_n0088,
      ADR2 => U1_db_error1(8),
      ADR3 => U3_timed_out(2),
      O => U1_Mmux_n0036_Result_8_1_O
    );
  U1_Mmux_n0038_Result_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44074,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(1),
      ADR3 => U3_maxw_reached(1),
      O => U1_Mmux_n0038_Result_1_1_O
    );
  U1_Mmux_n0038_Result_0_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44072,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(0),
      ADR3 => U3_maxw_reached(0),
      O => U1_Mmux_n0038_Result_0_1_O
    );
  U1_Mmux_n0037_Result_7_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44086,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(7),
      ADR3 => U1_ff_reg(1),
      O => U1_Mmux_n0037_Result_7_1_O
    );
  U1_Mmux_n0037_Result_6_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44084,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(6),
      ADR3 => U1_ff_reg(0),
      O => U1_Mmux_n0037_Result_6_1_O
    );
  U1_Mmux_n0038_Result_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44078,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(3),
      ADR3 => U3_maxw_reached(3),
      O => U1_Mmux_n0038_Result_3_1_O
    );
  U1_Mmux_n0038_Result_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44076,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(2),
      ADR3 => U3_maxw_reached(2),
      O => U1_Mmux_n0038_Result_2_1_O
    );
  U1_Mmux_n0038_Result_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44082,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(5),
      ADR3 => U3_maxw_reached(5),
      O => U1_Mmux_n0038_Result_5_1_O
    );
  U1_Mmux_n0038_Result_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44080,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(4),
      ADR3 => U3_maxw_reached(4),
      O => U1_Mmux_n0038_Result_4_1_O
    );
  U1_Mmux_n0037_Result_9_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44090,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(9),
      ADR3 => U1_ff_reg(3),
      O => U1_Mmux_n0037_Result_9_1_O
    );
  U1_Mmux_n0037_Result_8_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44088,
      ADR1 => U1_n0090,
      ADR2 => U1_db_error2(8),
      ADR3 => U1_ff_reg(2),
      O => U1_Mmux_n0037_Result_8_1_O
    );
  U1_Mmux_n0038_Result_7_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44086,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(7),
      ADR3 => U1_paf_reg(1),
      O => U1_Mmux_n0038_Result_7_1_O
    );
  U1_Mmux_n0038_Result_6_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44084,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(6),
      ADR3 => U1_paf_reg(0),
      O => U1_Mmux_n0038_Result_6_1_O
    );
  U1_Mmux_n0038_Result_9_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44090,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(9),
      ADR3 => U1_paf_reg(3),
      O => U1_Mmux_n0038_Result_9_1_O
    );
  U1_Mmux_n0038_Result_8_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => N44088,
      ADR1 => U1_n0092,
      ADR2 => U1_db_error3(8),
      ADR3 => U1_paf_reg(2),
      O => U1_Mmux_n0038_Result_8_1_O
    );
  U3_n0102_0_22 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_rob_id(0),
      ADR1 => U3_N31548,
      ADR2 => CHOICE922,
      ADR3 => CHOICE925,
      O => U3_n0102_0_22_O_FROM
    );
  U3_n0102_0_107 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31709,
      ADR1 => U3_trailer_reg_0_Q,
      ADR2 => U3_n0102_0_22_O,
      ADR3 => CHOICE945,
      O => U3_n0102_0_22_O_GROM
    );
  U3_n0102_0_22_O_XUSED : X_BUF
    port map (
      I => U3_n0102_0_22_O_FROM,
      O => U3_n0102_0_22_O
    );
  U3_n0102_0_22_O_YUSED : X_BUF
    port map (
      I => U3_n0102_0_22_O_GROM,
      O => CHOICE948
    );
  U3_n0102_1_22 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_rob_id(1),
      ADR1 => U3_N31548,
      ADR2 => CHOICE846,
      ADR3 => CHOICE849,
      O => U3_n0102_1_22_O_FROM
    );
  U3_n0102_1_59 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31709,
      ADR1 => U3_trailer_reg_1_Q,
      ADR2 => U3_n0102_1_22_O,
      ADR3 => CHOICE858,
      O => U3_n0102_1_22_O_GROM
    );
  U3_n0102_1_22_O_XUSED : X_BUF
    port map (
      I => U3_n0102_1_22_O_FROM,
      O => U3_n0102_1_22_O
    );
  U3_n0102_1_22_O_YUSED : X_BUF
    port map (
      I => U3_n0102_1_22_O_GROM,
      O => CHOICE861
    );
  U3_n0102_3_23 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_rob_id(3),
      ADR1 => U3_N31548,
      ADR2 => CHOICE774,
      ADR3 => CHOICE777,
      O => U3_n0102_3_23_O_FROM
    );
  U3_n0102_3_44 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_trailer_reg_3_Q,
      ADR1 => U3_N31709,
      ADR2 => CHOICE771,
      ADR3 => U3_n0102_3_23_O,
      O => U3_n0102_3_23_O_GROM
    );
  U3_n0102_3_23_O_XUSED : X_BUF
    port map (
      I => U3_n0102_3_23_O_FROM,
      O => U3_n0102_3_23_O
    );
  U3_n0102_3_23_O_YUSED : X_BUF
    port map (
      I => U3_n0102_3_23_O_GROM,
      O => CHOICE783
    );
  U3_n0102_2_66 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_rob_id(2),
      ADR1 => U3_N31548,
      ADR2 => CHOICE906,
      ADR3 => CHOICE909,
      O => U3_n0102_2_66_O_FROM
    );
  U3_n0102_2_87 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_trailer_reg_2_Q,
      ADR1 => U3_N31709,
      ADR2 => CHOICE903,
      ADR3 => U3_n0102_2_66_O,
      O => U3_n0102_2_66_O_GROM
    );
  U3_n0102_2_66_O_XUSED : X_BUF
    port map (
      I => U3_n0102_2_66_O_FROM,
      O => U3_n0102_2_66_O
    );
  U3_n0102_2_66_O_YUSED : X_BUF
    port map (
      I => U3_n0102_2_66_O_GROM,
      O => CHOICE915
    );
  U3_Ker31659_SW1 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => U3_state_FFd15,
      ADR1 => CHOICE683,
      ADR2 => CHOICE686,
      ADR3 => CHOICE689,
      O => N44314_FROM
    );
  U3_Ker31659_SW5 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE676,
      ADR1 => N44314,
      ADR2 => N39520,
      ADR3 => U3_state_FFd33,
      O => N44314_GROM
    );
  N44314_XUSED : X_BUF
    port map (
      I => N44314_FROM,
      O => N44314
    );
  N44314_YUSED : X_BUF
    port map (
      I => N44314_GROM,
      O => N44456
    );
  U3_header2_reg_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_11_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_11_FFX_RST,
      O => U3_header2_reg(11)
    );
  U3_header2_reg_11_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_11_FFX_RST
    );
  U3_header2_reg_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_12_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_13_FFY_RST,
      O => U3_header2_reg(12)
    );
  U3_header2_reg_13_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_13_FFY_RST
    );
  U3_header2_reg_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_13_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_13_FFX_RST,
      O => U3_header2_reg(13)
    );
  U3_header2_reg_13_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_13_FFX_RST
    );
  U3_header2_reg_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_14_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_15_FFY_RST,
      O => U3_header2_reg(14)
    );
  U3_header2_reg_15_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_15_FFY_RST
    );
  U3_header2_reg_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_15_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_15_FFX_RST,
      O => U3_header2_reg(15)
    );
  U3_header2_reg_15_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_15_FFX_RST
    );
  U3_trailer_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_2_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_3_FFY_RST,
      O => U3_trailer_reg_2_Q
    );
  U3_trailer_reg_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_3_FFY_RST
    );
  U3_trailer_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_3_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_3_FFX_RST,
      O => U3_trailer_reg_3_Q
    );
  U3_trailer_reg_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_3_FFX_RST
    );
  U3_trailer_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_4_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_5_FFY_RST,
      O => U3_trailer_reg_4_Q
    );
  U3_trailer_reg_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_5_FFY_RST
    );
  U3_trailer_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_5_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_5_FFX_RST,
      O => U3_trailer_reg_5_Q
    );
  U3_trailer_reg_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_5_FFX_RST
    );
  U3_trailer_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_6_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_7_FFY_RST,
      O => U3_trailer_reg_6_Q
    );
  U3_trailer_reg_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_7_FFY_RST
    );
  U3_trailer_reg_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_8_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_9_FFY_RST,
      O => U3_trailer_reg_8_Q
    );
  U3_trailer_reg_9_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_9_FFY_RST
    );
  U3_header2_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_2_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_3_FFY_RST,
      O => U3_header2_reg(2)
    );
  U3_header2_reg_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_3_FFY_RST
    );
  U3_header2_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_3_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_3_FFX_RST,
      O => U3_header2_reg(3)
    );
  U3_header2_reg_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_3_FFX_RST
    );
  U3_header2_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_4_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_5_FFY_RST,
      O => U3_header2_reg(4)
    );
  U3_header2_reg_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_5_FFY_RST
    );
  U3_header2_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_5_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_5_FFX_RST,
      O => U3_header2_reg(5)
    );
  U3_header2_reg_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_5_FFX_RST
    );
  U3_header2_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_6_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_7_FFY_RST,
      O => U3_header2_reg(6)
    );
  U3_header2_reg_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_7_FFY_RST
    );
  U3_header2_reg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_7_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_7_FFX_RST,
      O => U3_header2_reg(7)
    );
  U3_header2_reg_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_7_FFX_RST
    );
  U3_header2_reg_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_8_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_9_FFY_RST,
      O => U3_header2_reg(8)
    );
  U3_header2_reg_9_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_9_FFY_RST
    );
  U3_header2_reg_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_9_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_9_FFX_RST,
      O => U3_header2_reg(9)
    );
  U3_header2_reg_9_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_9_FFX_RST
    );
  U3_rob_id_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0096_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_rob_id_1_FFY_RST,
      O => U3_rob_id(1)
    );
  U3_rob_id_1_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_rob_id_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_rob_id_1_FFY_RST
    );
  U3_rob_id_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0096_4_10_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_rob_id_4_FFY_RST,
      O => U3_rob_id(4)
    );
  U3_rob_id_4_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_rob_id_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_rob_id_4_FFY_RST
    );
  U1_ff_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0015_Result_0_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_ff_reg_1_FFY_RST,
      O => U1_ff_reg(0)
    );
  U1_ff_reg_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_ff_reg_1_FFY_RST
    );
  U1_ff_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0015_Result_1_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_ff_reg_1_FFX_RST,
      O => U1_ff_reg(1)
    );
  U1_ff_reg_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_ff_reg_1_FFX_RST
    );
  U1_ff_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0015_Result_2_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_ff_reg_3_FFY_RST,
      O => U1_ff_reg(2)
    );
  U1_ff_reg_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_ff_reg_3_FFY_RST
    );
  U1_ff_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0015_Result_3_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_ff_reg_3_FFX_RST,
      O => U1_ff_reg(3)
    );
  U1_ff_reg_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_ff_reg_3_FFX_RST
    );
  U1_ff_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0015_Result_4_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_ff_reg_4_FFY_RST,
      O => U1_ff_reg(4)
    );
  U1_ff_reg_4_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_ff_reg_4_FFY_RST
    );
  U1_db_error1_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_0_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_1_FFY_RST,
      O => U1_db_error1(0)
    );
  U1_db_error1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_1_FFY_RST
    );
  U1_db_error1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_1_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_1_FFX_RST,
      O => U1_db_error1(1)
    );
  U1_db_error1_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_1_FFX_RST
    );
  U1_db_error1_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_2_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_3_FFY_RST,
      O => U1_db_error1(2)
    );
  U1_db_error1_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_3_FFY_RST
    );
  U1_db_error2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_0_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_1_FFY_RST,
      O => U1_db_error2(0)
    );
  U1_db_error2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_1_FFY_RST
    );
  U1_db_error1_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_3_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_3_FFX_RST,
      O => U1_db_error1(3)
    );
  U1_db_error1_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_3_FFX_RST
    );
  U3_word_count_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_9_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_9_FFX_RST,
      O => U3_word_count(9)
    );
  U3_word_count_9_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_9_FFX_RST
    );
  U3_header1_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_0_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_0_FFY_RST,
      O => U3_header1_reg(0)
    );
  U3_header2_reg_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_0_FFY_RST
    );
  U3_header2_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_0_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_0_FFX_RST,
      O => U3_header2_reg(0)
    );
  U3_header2_reg_0_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_0_FFX_RST
    );
  U3_header1_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_3_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header1_reg_3_FFX_RST,
      O => U3_header1_reg(3)
    );
  U3_header1_reg_3_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header1_reg_3_FFX_RST
    );
  U3_header1_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_2_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header1_reg_3_FFY_RST,
      O => U3_header1_reg(2)
    );
  U3_header1_reg_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header1_reg_3_FFY_RST
    );
  U3_header1_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_4_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header1_reg_5_FFY_RST,
      O => U3_header1_reg(4)
    );
  U3_header1_reg_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header1_reg_5_FFY_RST
    );
  U1_Ker299421 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => add_5_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => add_4_IBUF,
      ADR3 => VCC,
      O => U1_etr_fifo_reg_FROM
    );
  U1_etr_fifo1 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => U1_N29944,
      ADR1 => etr_x_IBUF,
      ADR2 => add_3_IBUF,
      ADR3 => VCC,
      O => U1_etr_fifo_reg_GROM
    );
  U1_etr_fifo_reg_XUSED : X_BUF
    port map (
      I => U1_etr_fifo_reg_FROM,
      O => U1_N29944
    );
  U1_etr_fifo_reg_YUSED : X_BUF
    port map (
      I => U1_etr_fifo_reg_GROM,
      O => etr_fifo
    );
  U1_Ker299351 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_2_IBUF,
      ADR1 => add_4_IBUF,
      ADR2 => add_5_IBUF,
      ADR3 => add_3_IBUF,
      O => U1_N29937_FROM
    );
  U1_n00161 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => U1_N29954,
      ADR3 => U1_N29937,
      O => U1_N29937_GROM
    );
  U1_N29937_XUSED : X_BUF
    port map (
      I => U1_N29937_FROM,
      O => U1_N29937
    );
  U1_N29937_YUSED : X_BUF
    port map (
      I => U1_N29937_GROM,
      O => U1_n0016
    );
  U1_I50_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29930,
      ADR3 => U1_N29992,
      O => U1_I50_N1762_FROM
    );
  U1_I58_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => etr_x_IBUF,
      ADR2 => N37571,
      ADR3 => add_5_IBUF,
      O => U1_I50_N1762_GROM
    );
  U1_I50_N1762_XUSED : X_BUF
    port map (
      I => U1_I50_N1762_FROM,
      O => U1_I50_N1762
    );
  U1_I50_N1762_YUSED : X_BUF
    port map (
      I => U1_I50_N1762_GROM,
      O => U1_I58_N1762
    );
  U1_Ker299281 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => add_2_IBUF,
      ADR1 => add_3_IBUF,
      ADR2 => add_5_IBUF,
      ADR3 => add_4_IBUF,
      O => U1_N29930_FROM
    );
  U3_n02401 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => U1_N29974,
      ADR1 => U3_state_FFd7,
      ADR2 => U1_N29954,
      ADR3 => U1_N29930,
      O => U1_N29930_GROM
    );
  U1_N29930_XUSED : X_BUF
    port map (
      I => U1_N29930_FROM,
      O => U1_N29930
    );
  U1_N29930_YUSED : X_BUF
    port map (
      I => U1_N29930_GROM,
      O => U3_n0240
    );
  U1_Ker299471 : X_LUT4
    generic map(
      INIT => X"1010"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => VCC,
      O => U1_N29949_FROM
    );
  U1_n01811 : X_LUT4
    generic map(
      INIT => X"CD01"
    )
    port map (
      ADR0 => paf_4_IBUF,
      ADR1 => U1_enw_paf_counter,
      ADR2 => U1_paf_cnt_set(4),
      ADR3 => U1_N29949,
      O => U1_N29949_GROM
    );
  U1_N29949_XUSED : X_BUF
    port map (
      I => U1_N29949_FROM,
      O => U1_N29949
    );
  U1_N29949_YUSED : X_BUF
    port map (
      I => U1_N29949_GROM,
      O => U1_n0181
    );
  U1_Ker299721 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => add_0_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_N29974_FROM
    );
  U1_I64_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => U1_etr_paf_counter,
      ADR1 => cs_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => U1_N29974,
      O => U1_N29974_GROM
    );
  U1_N29974_XUSED : X_BUF
    port map (
      I => U1_N29974_FROM,
      O => U1_N29974
    );
  U1_N29974_YUSED : X_BUF
    port map (
      I => U1_N29974_GROM,
      O => U1_I64_N1762
    );
  U1_Ker299811 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_N29983_FROM
    );
  U1_I59_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => U1_etr_paf_counter,
      ADR2 => add_2_IBUF,
      ADR3 => U1_N29983,
      O => U1_N29983_GROM
    );
  U1_N29983_XUSED : X_BUF
    port map (
      I => U1_N29983_FROM,
      O => U1_N29983
    );
  U1_N29983_YUSED : X_BUF
    port map (
      I => U1_N29983_GROM,
      O => U1_I59_N1762
    );
  U1_Ker299901 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_N29992_FROM
    );
  U1_I62_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => U1_etr_paf_counter,
      ADR2 => add_2_IBUF,
      ADR3 => U1_N29992,
      O => U1_N29992_GROM
    );
  U1_N29992_XUSED : X_BUF
    port map (
      I => U1_N29992_FROM,
      O => U1_N29992
    );
  U1_N29992_YUSED : X_BUF
    port map (
      I => U1_N29992_GROM,
      O => U1_I62_N1762
    );
  U3_state_FFd32_In7 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => U3_this_ff,
      ADR1 => U1_dis_paf_warn,
      ADR2 => U3_this_paf,
      ADR3 => VCC,
      O => CHOICE440_GROM
    );
  CHOICE440_YUSED : X_BUF
    port map (
      I => CHOICE440_GROM,
      O => CHOICE440
    );
  U1_Ker299981 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_N30000_FROM
    );
  U1_I61_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => U1_etr_paf_counter,
      ADR2 => add_2_IBUF,
      ADR3 => U1_N30000,
      O => U1_N30000_GROM
    );
  U1_N30000_XUSED : X_BUF
    port map (
      I => U1_N30000_FROM,
      O => U1_N30000
    );
  U1_N30000_YUSED : X_BUF
    port map (
      I => U1_N30000_GROM,
      O => U1_I61_N1762
    );
  U1_I55_EnableTr_INV_SW0 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => add_2_IBUF,
      ADR1 => add_5_IBUF,
      ADR2 => etr_x_IBUF,
      ADR3 => U1_N29983,
      O => N38020_FROM
    );
  U1_I55_EnableTr_INV : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => N38020,
      ADR2 => add_4_IBUF,
      ADR3 => add_3_IBUF,
      O => N38020_GROM
    );
  N38020_XUSED : X_BUF
    port map (
      I => N38020_FROM,
      O => N38020
    );
  N38020_YUSED : X_BUF
    port map (
      I => N38020_GROM,
      O => U1_I55_N1762
    );
  U3_dontread_4_n00011 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_4_n0001_FROM
    );
  U3_dontread_4_n00001 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_4_n0001_GROM
    );
  U3_dontread_4_n0001_XUSED : X_BUF
    port map (
      I => U3_dontread_4_n0001_FROM,
      O => U3_dontread_4_n0001
    );
  U3_dontread_4_n0001_YUSED : X_BUF
    port map (
      I => U3_dontread_4_n0001_GROM,
      O => U3_dontread_4_n0000
    );
  U2_n00451 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => reset_IBUF,
      ADR1 => U2_fwrg4,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_n0045_FROM
    );
  U2_n00441 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => U2_fwrg5,
      ADR1 => reset_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_n0045_GROM
    );
  U2_n0045_XUSED : X_BUF
    port map (
      I => U2_n0045_FROM,
      O => U2_n0045
    );
  U2_n0045_YUSED : X_BUF
    port map (
      I => U2_n0045_GROM,
      O => U2_n0044
    );
  U1_enw_paf_counter1_1_913 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => enw2,
      ADR2 => enw1,
      ADR3 => U1_N29944,
      O => U1_enw_paf_counter1_1_GROM
    );
  U1_enw_paf_counter1_1_YUSED : X_BUF
    port map (
      I => U1_enw_paf_counter1_1_GROM,
      O => U1_enw_paf_counter1_1
    );
  U1_enw_paf_counter1_3_914 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => enw2,
      ADR2 => enw1,
      ADR3 => U1_N29944,
      O => U1_enw_paf_counter1_3_FROM
    );
  U1_n01931 : X_LUT4
    generic map(
      INIT => X"5151"
    )
    port map (
      ADR0 => U1_enw_paf_counter1_3,
      ADR1 => U1_paf_cnt_set(0),
      ADR2 => paf_0_IBUF,
      ADR3 => VCC,
      O => U1_enw_paf_counter1_3_GROM
    );
  U1_enw_paf_counter1_3_XUSED : X_BUF
    port map (
      I => U1_enw_paf_counter1_3_FROM,
      O => U1_enw_paf_counter1_3
    );
  U1_enw_paf_counter1_3_YUSED : X_BUF
    port map (
      I => U1_enw_paf_counter1_3_GROM,
      O => U1_n0193
    );
  U3_n0102_0_11 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(0),
      ADR2 => U3_state_FFd36,
      ADR3 => U3_dontread(0),
      O => CHOICE925_FROM
    );
  U3_n0102_10_21 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_evid_mis(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE925_GROM
    );
  CHOICE925_XUSED : X_BUF
    port map (
      I => CHOICE925_FROM,
      O => CHOICE925
    );
  CHOICE925_YUSED : X_BUF
    port map (
      I => CHOICE925_GROM,
      O => CHOICE742
    );
  U3_n0101_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd28,
      ADR1 => U3_state_FFd14,
      ADR2 => U3_state_FFd13,
      ADR3 => VCC,
      O => U3_time_start_FROM
    );
  U3_n0101_915 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_N31256,
      ADR1 => U3_N31504,
      ADR2 => N38770,
      ADR3 => U3_time_start,
      O => U3_n0101
    );
  U3_time_start_XUSED : X_BUF
    port map (
      I => U3_time_start_FROM,
      O => N38770
    );
  U3_time_start_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_time_start_SRMUX_OUTPUTNOT
    );
  U3_n0102_5_25 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_dontread(5),
      ADR2 => U3_state_FFd34,
      ADR3 => tp_2_OBUF,
      O => CHOICE635_FROM
    );
  U3_Ker3172315_SW0 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => U3_state_FFd34,
      ADR1 => U3_state_FFd33,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE635_GROM
    );
  CHOICE635_XUSED : X_BUF
    port map (
      I => CHOICE635_FROM,
      O => CHOICE635
    );
  CHOICE635_YUSED : X_BUF
    port map (
      I => CHOICE635_GROM,
      O => N44332
    );
  U3_state_FFd34_In_SW1 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => U3_state_FFd39,
      ADR1 => CHOICE394,
      ADR2 => CHOICE397,
      ADR3 => CHOICE400,
      O => U3_state_FFd34_FROM
    );
  U3_state_FFd34_In_916 : X_LUT4
    generic map(
      INIT => X"5D0C"
    )
    port map (
      ADR0 => U3_this_dontread,
      ADR1 => U3_state_FFd34,
      ADR2 => tp_2_OBUF,
      ADR3 => N44614,
      O => U3_state_FFd34_In
    );
  U3_state_FFd34_XUSED : X_BUF
    port map (
      I => U3_state_FFd34_FROM,
      O => N44614
    );
  U3_state_FFd34_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd34_SRMUX_OUTPUTNOT
    );
  U3_n0102_10_26 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd17,
      ADR1 => evid_10_IBUF,
      ADR2 => U3_state_FFd16,
      ADR3 => U3_header2_reg(10),
      O => CHOICE745_FROM
    );
  U3_n0102_10_35 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_rob_id(2),
      ADR1 => U3_N31556,
      ADR2 => CHOICE742,
      ADR3 => CHOICE745,
      O => CHOICE745_GROM
    );
  CHOICE745_XUSED : X_BUF
    port map (
      I => CHOICE745_FROM,
      O => CHOICE745
    );
  CHOICE745_YUSED : X_BUF
    port map (
      I => CHOICE745_GROM,
      O => CHOICE748
    );
  U3_Ker31654_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd29,
      ADR1 => U3_state_FFd17,
      ADR2 => U3_state_FFd36,
      ADR3 => U3_state_FFd18,
      O => N44255_FROM
    );
  U3_Ker31534_SW2 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U1_dis_ffreg_mask,
      ADR2 => N39677,
      ADR3 => N44255,
      O => N44255_GROM
    );
  N44255_XUSED : X_BUF
    port map (
      I => N44255_FROM,
      O => N44255
    );
  N44255_YUSED : X_BUF
    port map (
      I => N44255_GROM,
      O => N44426
    );
  U3_Ker31718_SW5 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31504,
      ADR1 => N39486,
      ADR2 => CHOICE530,
      ADR3 => U3_state_FFd31,
      O => N44470_FROM
    );
  U3_Ker31718_SW4 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_N31504,
      ADR1 => N39486,
      ADR2 => N44336,
      ADR3 => U3_state_FFd31,
      O => N44470_GROM
    );
  N44470_XUSED : X_BUF
    port map (
      I => N44470_FROM,
      O => N44470
    );
  N44470_YUSED : X_BUF
    port map (
      I => N44470_GROM,
      O => N44434
    );
  U3_n0102_11_23 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd17,
      ADR1 => evid_11_IBUF,
      ADR2 => U3_state_FFd16,
      ADR3 => U3_header2_reg(11),
      O => CHOICE762_FROM
    );
  U3_n0102_11_32 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_rob_id(3),
      ADR1 => U3_N31556,
      ADR2 => CHOICE759,
      ADR3 => CHOICE762,
      O => CHOICE762_GROM
    );
  CHOICE762_XUSED : X_BUF
    port map (
      I => CHOICE762_FROM,
      O => CHOICE762
    );
  CHOICE762_YUSED : X_BUF
    port map (
      I => CHOICE762_GROM,
      O => CHOICE765
    );
  U2_n00961 : X_LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      ADR0 => U1_per_fifo,
      ADR1 => enw_byte_par0,
      ADR2 => enw_byte_par1,
      ADR3 => enw_word_par,
      O => U2_n0096_GROM
    );
  U2_n0096_YUSED : X_BUF
    port map (
      I => U2_n0096_GROM,
      O => U2_n0096
    );
  ULED1_q1_LOGIC_ONE_917 : X_ONE
    port map (
      O => ULED1_q1_LOGIC_ONE
    );
  U2_Mxor_cpar_0_Xo_4_1 : X_LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      ADR0 => fout_0_IBUF,
      ADR1 => fout_1_IBUF,
      ADR2 => fout_2_IBUF,
      ADR3 => fout_3_IBUF,
      O => U2_Mxor_cpar_0_Xo_4_GROM
    );
  U2_Mxor_cpar_0_Xo_4_YUSED : X_BUF
    port map (
      I => U2_Mxor_cpar_0_Xo_4_GROM,
      O => U2_Mxor_cpar_0_Xo(4)
    );
  U2_Mxor_cpar_0_Xo_5_1 : X_LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      ADR0 => fout_4_IBUF,
      ADR1 => fout_5_IBUF,
      ADR2 => fout_6_IBUF,
      ADR3 => fout_7_IBUF,
      O => U2_Mxor_cpar_0_Xo_5_GROM
    );
  U2_Mxor_cpar_0_Xo_5_YUSED : X_BUF
    port map (
      I => U2_Mxor_cpar_0_Xo_5_GROM,
      O => U2_Mxor_cpar_0_Xo(5)
    );
  ULED2_q1_LOGIC_ONE_918 : X_ONE
    port map (
      O => ULED2_q1_LOGIC_ONE
    );
  U2_Mxor_cpar_0_Xo_6_1 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => U2_Mxor_cpar_0_Xo(4),
      ADR1 => U2_Mxor_cpar_0_Xo(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_cpar_0_FROM
    );
  U2_parcheck1 : X_LUT4
    generic map(
      INIT => X"6FF6"
    )
    port map (
      ADR0 => par_1_IBUF,
      ADR1 => U2_cpar(1),
      ADR2 => par_0_IBUF,
      ADR3 => U2_cpar(0),
      O => U2_cpar_0_GROM
    );
  U2_cpar_0_XUSED : X_BUF
    port map (
      I => U2_cpar_0_FROM,
      O => U2_cpar(0)
    );
  U2_cpar_0_YUSED : X_BUF
    port map (
      I => U2_cpar_0_GROM,
      O => parcheck
    );
  U3_n0102_2_55 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd19,
      ADR1 => U3_header1_reg(2),
      ADR2 => U3_state_FFd16,
      ADR3 => U3_header2_reg(2),
      O => CHOICE909_FROM
    );
  U3_n0102_13_23 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(13),
      ADR2 => U3_state_FFd14,
      ADR3 => U3_trailer_reg_12_Q,
      O => CHOICE909_GROM
    );
  CHOICE909_XUSED : X_BUF
    port map (
      I => CHOICE909_FROM,
      O => CHOICE909
    );
  CHOICE909_YUSED : X_BUF
    port map (
      I => CHOICE909_GROM,
      O => CHOICE613
    );
  U3_n0102_15_24 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => fout_14_IBUF,
      ADR1 => U3_state_FFd9,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE831_FROM
    );
  U3_n0102_13_26 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd9,
      ADR1 => fout_12_IBUF,
      ADR2 => U3_state_FFd15,
      ADR3 => VCC,
      O => CHOICE831_GROM
    );
  CHOICE831_XUSED : X_BUF
    port map (
      I => CHOICE831_FROM,
      O => CHOICE831
    );
  CHOICE831_YUSED : X_BUF
    port map (
      I => CHOICE831_GROM,
      O => CHOICE615
    );
  U3_n0102_14_21 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd2,
      ADR1 => U1_resynch_to,
      ADR2 => U3_state_FFd1,
      ADR3 => U1_resynch_maxw,
      O => CHOICE875_FROM
    );
  U3_n0102_14_48_SW0 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U1_resynch_FF,
      ADR2 => CHOICE872,
      ADR3 => CHOICE875,
      O => CHOICE875_GROM
    );
  CHOICE875_XUSED : X_BUF
    port map (
      I => CHOICE875_FROM,
      O => CHOICE875
    );
  CHOICE875_YUSED : X_BUF
    port map (
      I => CHOICE875_GROM,
      O => N44506
    );
  U3_n0102_14_41 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => fout_13_IBUF,
      ADR1 => U3_state_FFd9,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE879_GROM
    );
  CHOICE879_YUSED : X_BUF
    port map (
      I => CHOICE879_GROM,
      O => CHOICE879
    );
  U3_n0102_15_10 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(15),
      ADR2 => U3_state_FFd14,
      ADR3 => U3_trailer_reg_14_Q,
      O => CHOICE827_FROM
    );
  U3_n0102_15_16 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE824,
      ADR1 => U3_state_FFd31,
      ADR2 => U3_state_FFd30,
      ADR3 => CHOICE827,
      O => CHOICE827_GROM
    );
  CHOICE827_XUSED : X_BUF
    port map (
      I => CHOICE827_FROM,
      O => CHOICE827
    );
  CHOICE827_YUSED : X_BUF
    port map (
      I => CHOICE827_GROM,
      O => CHOICE829
    );
  U3_n0102_14_6 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd30,
      ADR1 => U1_warn_PAF,
      ADR2 => U3_state_FFd17,
      ADR3 => U1_resynch_evidmis,
      O => CHOICE868_FROM
    );
  U3_n0102_14_48 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => N44506,
      ADR1 => CHOICE879,
      ADR2 => U3_this_ef23_2,
      ADR3 => CHOICE868,
      O => CHOICE868_GROM
    );
  CHOICE868_XUSED : X_BUF
    port map (
      I => CHOICE868_FROM,
      O => CHOICE868
    );
  CHOICE868_YUSED : X_BUF
    port map (
      I => CHOICE868_GROM,
      O => CHOICE881
    );
  U3_n0102_3_12 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd19,
      ADR1 => U3_header1_reg(3),
      ADR2 => U3_state_FFd16,
      ADR3 => U3_header2_reg(3),
      O => CHOICE777_FROM
    );
  U3_n0102_1_11 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(1),
      ADR2 => U3_state_FFd36,
      ADR3 => U3_dontread(1),
      O => CHOICE777_GROM
    );
  CHOICE777_XUSED : X_BUF
    port map (
      I => CHOICE777_FROM,
      O => CHOICE777
    );
  CHOICE777_YUSED : X_BUF
    port map (
      I => CHOICE777_GROM,
      O => CHOICE849
    );
  U3_n0102_0_43 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U1_ff_reg(3),
      ADR1 => U3_sel_read(3),
      ADR2 => U1_ff_reg(2),
      ADR3 => U3_sel_read(2),
      O => CHOICE937_FROM
    );
  U3_n0102_0_64_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => CHOICE934,
      ADR1 => CHOICE937,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE937_GROM
    );
  CHOICE937_XUSED : X_BUF
    port map (
      I => CHOICE937_FROM,
      O => CHOICE937
    );
  CHOICE937_YUSED : X_BUF
    port map (
      I => CHOICE937_GROM,
      O => N44375
    );
  U3_this_paf14 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => paf_1_IBUF,
      ADR1 => U3_sel_read(1),
      ADR2 => paf_0_IBUF,
      ADR3 => U3_sel_read(0),
      O => CHOICE515_FROM
    );
  U3_this_paf23 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE509,
      ADR1 => CHOICE512,
      ADR2 => CHOICE515,
      ADR3 => VCC,
      O => CHOICE515_GROM
    );
  CHOICE515_XUSED : X_BUF
    port map (
      I => CHOICE515_FROM,
      O => CHOICE515
    );
  CHOICE515_YUSED : X_BUF
    port map (
      I => CHOICE515_GROM,
      O => U3_this_paf
    );
  U3_n0102_4_25 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_rob_id(4),
      ADR1 => U3_N31548,
      ADR2 => CHOICE792,
      ADR3 => CHOICE795,
      O => U3_n0102_4_25_O_FROM
    );
  U3_n0102_4_47 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_trailer_reg_4_Q,
      ADR1 => U3_N31709,
      ADR2 => CHOICE789,
      ADR3 => U3_n0102_4_25_O,
      O => U3_n0102_4_25_O_GROM
    );
  U3_n0102_4_25_O_XUSED : X_BUF
    port map (
      I => U3_n0102_4_25_O_FROM,
      O => U3_n0102_4_25_O
    );
  U3_n0102_4_25_O_YUSED : X_BUF
    port map (
      I => U3_n0102_4_25_O_GROM,
      O => CHOICE801
    );
  U3_n0116_1_1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => enw_evid_mis,
      ADR1 => U3_evid_mis(1),
      ADR2 => U3_sel_read(1),
      ADR3 => VCC,
      O => U3_n0116(1)
    );
  U3_n0116_0_1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => enw_evid_mis,
      ADR1 => U3_evid_mis(0),
      ADR2 => U3_sel_read(0),
      ADR3 => VCC,
      O => U3_n0116(0)
    );
  U3_n0116_3_1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => enw_evid_mis,
      ADR1 => U3_evid_mis(3),
      ADR2 => U3_sel_read(3),
      ADR3 => VCC,
      O => U3_n0116(3)
    );
  U3_n0116_2_1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => enw_evid_mis,
      ADR1 => U3_evid_mis(2),
      ADR2 => U3_sel_read(2),
      ADR3 => VCC,
      O => U3_n0116(2)
    );
  U3_n0116_5_1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => enw_evid_mis,
      ADR1 => U3_evid_mis(5),
      ADR2 => U3_sel_read_5_1,
      ADR3 => VCC,
      O => U3_n0116(5)
    );
  U3_n0116_4_1 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => enw_evid_mis,
      ADR1 => U3_evid_mis(4),
      ADR2 => U3_sel_read(4),
      ADR3 => VCC,
      O => U3_n0116(4)
    );
  U3_state_FFd8_In1 : X_LUT4
    generic map(
      INIT => X"88A8"
    )
    port map (
      ADR0 => U3_this_ef23_1,
      ADR1 => U3_N31621,
      ADR2 => U3_state_FFd8,
      ADR3 => U3_time_out,
      O => U3_state_FFd8_In1_O
    );
  U3_state_FFd7_In1 : X_LUT4
    generic map(
      INIT => X"1010"
    )
    port map (
      ADR0 => U1_dis_maxw_mask,
      ADR1 => U3_n0050,
      ADR2 => U3_state_FFd10,
      ADR3 => VCC,
      O => U3_state_FFd7_In
    );
  U3_state_FFd8_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd8_SRMUX_OUTPUTNOT
    );
  U3_n02421 : X_LUT4
    generic map(
      INIT => X"5DFF"
    )
    port map (
      ADR0 => U3_time_start,
      ADR1 => U3_fmt_error_ff_2_1_Q,
      ADR2 => U1_dis_hul_mask,
      ADR3 => U3_time_out,
      O => U3_time_counter_12_FROM
    );
  U3_Mmux_n0117_Result_12_1 : X_LUT4
    generic map(
      INIT => X"B000"
    )
    port map (
      ADR0 => U1_dis_hul_mask,
      ADR1 => U3_fmt_error_ff_2_1_Q,
      ADR2 => U3_n0251(12),
      ADR3 => U3_time_start,
      O => U3_n0117(12)
    );
  U3_time_counter_12_XUSED : X_BUF
    port map (
      I => U3_time_counter_12_FROM,
      O => U3_n0242
    );
  U2_n00421 : X_LUT4
    generic map(
      INIT => X"2A2A"
    )
    port map (
      ADR0 => U2_q1a,
      ADR1 => U2_loadcnt(5),
      ADR2 => U2_q4,
      ADR3 => VCC,
      O => U2_n0042
    );
  U2_n00401 : X_LUT4
    generic map(
      INIT => X"7770"
    )
    port map (
      ADR0 => U2_q4,
      ADR1 => U2_loadcnt(5),
      ADR2 => U2_q1,
      ADR3 => load_paepaf_IBUF,
      O => U2_n0040
    );
  U2_n01331 : X_LUT4
    generic map(
      INIT => X"04FF"
    )
    port map (
      ADR0 => U2_q4,
      ADR1 => U2_q2,
      ADR2 => U2_q3,
      ADR3 => U2_loadcnt(5),
      O => U2_q4_FROM
    );
  U2_n00431 : X_LUT4
    generic map(
      INIT => X"2A2A"
    )
    port map (
      ADR0 => U2_q2,
      ADR1 => U2_loadcnt(5),
      ADR2 => U2_q4,
      ADR3 => VCC,
      O => U2_n0043
    );
  U2_q4_XUSED : X_BUF
    port map (
      I => U2_q4_FROM,
      O => U2_n0133
    );
  U2_loadcnt_Mmux_n0001_Result_1_1 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => U2_q4,
      ADR1 => U2_q2,
      ADR2 => U2_q3,
      ADR3 => U2_loadcnt_n0002(1),
      O => U2_loadcnt_n0001(1)
    );
  U2_loadcnt_Mmux_n0001_Result_0_1 : X_LUT4
    generic map(
      INIT => X"5551"
    )
    port map (
      ADR0 => U2_loadcnt(0),
      ADR1 => U2_q2,
      ADR2 => U2_q3,
      ADR3 => U2_q4,
      O => U2_loadcnt_n0001(0)
    );
  U2_loadcnt_Mmux_n0001_Result_3_1 : X_LUT4
    generic map(
      INIT => X"FF04"
    )
    port map (
      ADR0 => U2_q4,
      ADR1 => U2_q2,
      ADR2 => U2_q3,
      ADR3 => U2_loadcnt_n0002(3),
      O => U2_loadcnt_n0001(3)
    );
  U2_loadcnt_Mmux_n0001_Result_2_1 : X_LUT4
    generic map(
      INIT => X"AAA2"
    )
    port map (
      ADR0 => U2_loadcnt_n0002(2),
      ADR1 => U2_q2,
      ADR2 => U2_q3,
      ADR3 => U2_q4,
      O => U2_loadcnt_n0001(2)
    );
  U2_loadcnt_Mmux_n0001_Result_5_1 : X_LUT4
    generic map(
      INIT => X"AAA2"
    )
    port map (
      ADR0 => U2_loadcnt_n0002(5),
      ADR1 => U2_q2,
      ADR2 => U2_q3,
      ADR3 => U2_q4,
      O => U2_loadcnt_n0001(5)
    );
  U2_loadcnt_Mmux_n0001_Result_4_1 : X_LUT4
    generic map(
      INIT => X"AAA2"
    )
    port map (
      ADR0 => U2_loadcnt_n0002(4),
      ADR1 => U2_q2,
      ADR2 => U2_q3,
      ADR3 => U2_q4,
      O => U2_loadcnt_n0001(4)
    );
  U2_fld1 : X_LUT4
    generic map(
      INIT => X"EFAA"
    )
    port map (
      ADR0 => U2_fwrg1,
      ADR1 => U1_etr_paepaf_reg_1,
      ADR2 => U1_etr_paepaf_reg_2,
      ADR3 => U2_loadcnt(5),
      O => U1_per_paepaf_reg_FROM
    );
  U1_per_paepaf1 : X_LUT4
    generic map(
      INIT => X"DDDD"
    )
    port map (
      ADR0 => U1_etr_paepaf_reg_2,
      ADR1 => U1_etr_paepaf_reg_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_per_paepaf_reg_GROM
    );
  U1_per_paepaf_reg_XUSED : X_BUF
    port map (
      I => U1_per_paepaf_reg_FROM,
      O => fld_OBUF
    );
  U1_per_paepaf_reg_YUSED : X_BUF
    port map (
      I => U1_per_paepaf_reg_GROM,
      O => per_paepaf
    );
  U1_etr_paf_counter1 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => U1_N29944,
      ADR1 => etr_x_IBUF,
      ADR2 => add_3_IBUF,
      ADR3 => VCC,
      O => U1_per_fifo_aux_2_FROM
    );
  U1_per_fifo_aux1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => U1_etr_fifo_reg,
      ADR2 => U1_N29944,
      ADR3 => add_3_IBUF,
      O => U1_per_fifo_aux
    );
  U1_per_fifo_aux_2_XUSED : X_BUF
    port map (
      I => U1_per_fifo_aux_2_FROM,
      O => U1_etr_paf_counter
    );
  U3_n0102_9_10 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(9),
      ADR2 => U3_state_FFd14,
      ADR3 => U3_trailer_reg_9_Q,
      O => U3_state_FFd14_FROM
    );
  U3_state_FFd14_In1 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_trail,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_state_FFd14_In
    );
  U3_state_FFd14_XUSED : X_BUF
    port map (
      I => U3_state_FFd14_FROM,
      O => CHOICE726
    );
  U3_state_FFd14_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd14_SRMUX_OUTPUTNOT
    );
  U3_Ker316641_SW1_SW0 : X_LUT4
    generic map(
      INIT => X"5454"
    )
    port map (
      ADR0 => tp_2_OBUF,
      ADR1 => U3_state_FFd34,
      ADR2 => U3_state_FFd33,
      ADR3 => VCC,
      O => U3_state_FFd31_FROM
    );
  U3_state_FFd31_In1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => tp_2_OBUF,
      ADR1 => U3_state_FFd34,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_state_FFd31_In
    );
  U3_state_FFd31_XUSED : X_BUF
    port map (
      I => U3_state_FFd31_FROM,
      O => N44538
    );
  U3_state_FFd31_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd31_SRMUX_OUTPUTNOT
    );
  U3_n009721 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => U3_N31407,
      ADR2 => U3_state_FFd35,
      ADR3 => VCC,
      O => U3_state_FFd35_FROM
    );
  U3_state_FFd35_In1 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => U3_N31407,
      ADR2 => U3_state_FFd36,
      ADR3 => U3_state_FFd35,
      O => U3_state_FFd35_In
    );
  U3_state_FFd35_XUSED : X_BUF
    port map (
      I => U3_state_FFd35_FROM,
      O => CHOICE574
    );
  U3_state_FFd35_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd35_SRMUX_OUTPUTNOT
    );
  U3_Ker31534_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd39,
      ADR1 => U3_state_FFd25,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_state_FFd37_FROM
    );
  U3_state_FFd37_In1 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => U3_state_FFd39,
      ADR1 => CHOICE383,
      ADR2 => CHOICE386,
      ADR3 => CHOICE389,
      O => U3_state_FFd37_In
    );
  U3_state_FFd37_XUSED : X_BUF
    port map (
      I => U3_state_FFd37_FROM,
      O => N39677
    );
  U3_state_FFd37_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd37_SRMUX_OUTPUTNOT
    );
  U3_n010319 : X_LUT4
    generic map(
      INIT => X"FFAE"
    )
    port map (
      ADR0 => CHOICE268,
      ADR1 => U3_N31256,
      ADR2 => U3_lives_in,
      ADR3 => U3_N31509,
      O => U3_n0103
    );
  U3_lives_in_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_lives_in_SRMUX_OUTPUTNOT
    );
  U3_dontread_1_n00001 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_1_FROM
    );
  U3_n0120_1_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => U1_mask(1),
      ADR1 => soft_reset,
      ADR2 => U3_dontread(1),
      ADR3 => U3_sel_read(1),
      O => U3_n0120(1)
    );
  U3_dontread_1_XUSED : X_BUF
    port map (
      I => U3_dontread_1_FROM,
      O => U3_dontread_1_n0000
    );
  U3_dontread_2_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_dontread_2_n0000,
      I1 => GSR,
      O => U3_dontread_2_FFY_RST
    );
  U3_dontread_2_FFY_SETOR : X_BUF
    port map (
      I => U3_dontread_2_n0001,
      O => U3_dontread_2_FFY_SET
    );
  U3_dontread_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0120(2),
      CE => U3_n0243,
      CLK => CLK,
      SET => U3_dontread_2_FFY_SET,
      RST => U3_dontread_2_FFY_RST,
      O => U3_dontread(2)
    );
  U3_this_dontread9 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_dontread(3),
      ADR1 => U3_sel_read(3),
      ADR2 => U3_dontread(2),
      ADR3 => U3_sel_read(2),
      O => U3_dontread_2_FROM
    );
  U3_n0120_2_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => U1_mask(2),
      ADR1 => soft_reset,
      ADR2 => U3_dontread(2),
      ADR3 => U3_sel_read(2),
      O => U3_n0120(2)
    );
  U3_dontread_2_XUSED : X_BUF
    port map (
      I => U3_dontread_2_FROM,
      O => CHOICE386
    );
  U3_dontread_3_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_dontread_3_n0000,
      I1 => GSR,
      O => U3_dontread_3_FFY_RST
    );
  U3_dontread_3_FFY_SETOR : X_BUF
    port map (
      I => U3_dontread_3_n0001,
      O => U3_dontread_3_FFY_SET
    );
  U3_dontread_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0120(3),
      CE => U3_n0243,
      CLK => CLK,
      SET => U3_dontread_3_FFY_SET,
      RST => U3_dontread_3_FFY_RST,
      O => U3_dontread(3)
    );
  U3_dontread_3_n00001 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_3_FROM
    );
  U3_n0120_3_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => U1_mask(3),
      ADR1 => soft_reset,
      ADR2 => U3_dontread(3),
      ADR3 => U3_sel_read(3),
      O => U3_n0120(3)
    );
  U3_dontread_3_XUSED : X_BUF
    port map (
      I => U3_dontread_3_FROM,
      O => U3_dontread_3_n0000
    );
  U3_this_dontread4 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_dontread(5),
      ADR1 => U3_sel_read(5),
      ADR2 => U3_dontread(4),
      ADR3 => U3_sel_read(4),
      O => U3_dontread_4_FROM
    );
  U3_n0120_4_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => U1_mask(4),
      ADR1 => soft_reset,
      ADR2 => U3_dontread(4),
      ADR3 => U3_sel_read(4),
      O => U3_n0120(4)
    );
  U3_dontread_4_XUSED : X_BUF
    port map (
      I => U3_dontread_4_FROM,
      O => CHOICE383
    );
  U3_dontread_5_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_dontread_5_n0000,
      I1 => GSR,
      O => U3_dontread_5_FFY_RST
    );
  U3_dontread_5_FFY_SETOR : X_BUF
    port map (
      I => U3_dontread_5_n0001,
      O => U3_dontread_5_FFY_SET
    );
  U3_dontread_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0120(5),
      CE => U3_n0243,
      CLK => CLK,
      SET => U3_dontread_5_FFY_SET,
      RST => U3_dontread_5_FFY_RST,
      O => U3_dontread(5)
    );
  U3_dontread_5_n00001 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_5_FROM
    );
  U3_n0120_5_1 : X_LUT4
    generic map(
      INIT => X"BBB8"
    )
    port map (
      ADR0 => U1_mask(5),
      ADR1 => soft_reset,
      ADR2 => U3_dontread(5),
      ADR3 => U3_sel_read_5_1,
      O => U3_n0120(5)
    );
  U3_dontread_5_XUSED : X_BUF
    port map (
      I => U3_dontread_5_FROM,
      O => U3_dontread_5_n0000
    );
  U2_q1a_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_q1a_FFY_RST
    );
  U2_q1a_919 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_n0041,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_q1a_FFY_RST,
      O => U2_q1a
    );
  recoff_p1 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => U1_recoff,
      ADR1 => U2_q1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_q1a_FROM
    );
  U2_n00411 : X_LUT4
    generic map(
      INIT => X"2A2A"
    )
    port map (
      ADR0 => U2_q1,
      ADR1 => U2_loadcnt(5),
      ADR2 => U2_q4,
      ADR3 => VCC,
      O => U2_n0041
    );
  U2_q1a_XUSED : X_BUF
    port map (
      I => U2_q1a_FROM,
      O => recoff_p_OBUF
    );
  U1_Mmux_n0014_Result_1_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => U1_n0077,
      ADR1 => N44086,
      ADR2 => U1_paf_reg(1),
      ADR3 => paf_1_IBUF,
      O => U1_n0014(1)
    );
  U1_Mmux_n0014_Result_0_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => U1_n0077,
      ADR1 => N44084,
      ADR2 => U1_paf_reg(0),
      ADR3 => paf_0_IBUF,
      O => U1_n0014(0)
    );
  U1_Mmux_n0014_Result_3_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => U1_n0077,
      ADR1 => N44090,
      ADR2 => U1_paf_reg(3),
      ADR3 => paf_3_IBUF,
      O => U1_n0014(3)
    );
  U1_Mmux_n0014_Result_2_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => U1_n0077,
      ADR1 => N44088,
      ADR2 => U1_paf_reg(2),
      ADR3 => paf_2_IBUF,
      O => U1_n0014(2)
    );
  U3_this_paf4 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => paf_5_IBUF,
      ADR1 => U3_sel_read(5),
      ADR2 => paf_4_IBUF,
      ADR3 => U3_sel_read(4),
      O => U1_paf_reg_4_FROM
    );
  U1_Mmux_n0014_Result_4_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => U1_n0077,
      ADR1 => N44092,
      ADR2 => U1_paf_reg(4),
      ADR3 => paf_4_IBUF,
      O => U1_n0014(4)
    );
  U1_paf_reg_4_XUSED : X_BUF
    port map (
      I => U1_paf_reg_4_FROM,
      O => CHOICE509
    );
  U2_fsi1 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U2_pae_paf_reg(0),
      ADR1 => U2_fwrg1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => fsi_OBUF_GROM
    );
  fsi_OBUF_YUSED : X_BUF
    port map (
      I => fsi_OBUF_GROM,
      O => fsi_OBUF
    );
  U3_Ker317884 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd14,
      ADR1 => U3_state_FFd9,
      ADR2 => U3_state_FFd28,
      ADR3 => U3_state_FFd11,
      O => CHOICE1036_FROM
    );
  U3_n0102_7_26 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => N44344,
      ADR1 => U3_state_FFd13_In,
      ADR2 => U3_state_FFd14,
      ADR3 => U3_trailer_reg_7_Q,
      O => CHOICE1036_GROM
    );
  CHOICE1036_XUSED : X_BUF
    port map (
      I => CHOICE1036_FROM,
      O => CHOICE1036
    );
  CHOICE1036_YUSED : X_BUF
    port map (
      I => CHOICE1036_GROM,
      O => CHOICE703
    );
  U3_n0102_14_16 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(14),
      ADR2 => U3_state_FFd14,
      ADR3 => U3_trailer_reg_13_Q,
      O => CHOICE872_FROM
    );
  U3_n0102_8_10 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(8),
      ADR2 => U3_state_FFd14,
      ADR3 => U3_trailer_reg_8_Q,
      O => CHOICE872_GROM
    );
  CHOICE872_XUSED : X_BUF
    port map (
      I => CHOICE872_FROM,
      O => CHOICE872
    );
  CHOICE872_YUSED : X_BUF
    port map (
      I => CHOICE872_GROM,
      O => CHOICE712
    );
  U3_state_FFd28_In17 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => U3_state_FFd28,
      ADR1 => tp_2_OBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE277_FROM
    );
  U3_state_FFd11_In_SW0 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd28,
      ADR1 => tp_2_OBUF,
      ADR2 => U3_state_FFd6,
      ADR3 => VCC,
      O => CHOICE277_GROM
    );
  CHOICE277_XUSED : X_BUF
    port map (
      I => CHOICE277_FROM,
      O => CHOICE277
    );
  CHOICE277_YUSED : X_BUF
    port map (
      I => CHOICE277_GROM,
      O => N38705
    );
  U3_state_FFd19_In_SW0 : X_LUT4
    generic map(
      INIT => X"DDDD"
    )
    port map (
      ADR0 => U3_error_evid,
      ADR1 => U1_dis_evid_wrong,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_state_FFd19_FROM
    );
  U3_state_FFd19_In_920 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => U3_state_FFd22,
      ADR1 => U3_state_FFd17,
      ADR2 => tp_2_OBUF,
      ADR3 => N38242,
      O => U3_state_FFd19_In
    );
  U3_state_FFd19_XUSED : X_BUF
    port map (
      I => U3_state_FFd19_FROM,
      O => N38242
    );
  U3_state_FFd19_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd19_SRMUX_OUTPUTNOT
    );
  Q_n00681 : X_LUT4
    generic map(
      INIT => X"DDDD"
    )
    port map (
      ADR0 => ULED1_q2,
      ADR1 => U3_ros_done,
      ADR2 => VCC,
      ADR3 => VCC,
      O => led_0_OBUF_GROM
    );
  led_0_OBUF_YUSED : X_BUF
    port map (
      I => led_0_OBUF_GROM,
      O => led_0_OBUF
    );
  U3_Ker318251 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U3_state_FFd30,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N31827_FROM
    );
  U3_Ker3178819_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd6,
      ADR1 => U3_state_FFd30,
      ADR2 => U3_state_FFd22,
      ADR3 => U3_state_FFd15,
      O => U3_N31827_GROM
    );
  U3_N31827_XUSED : X_BUF
    port map (
      I => U3_N31827_FROM,
      O => U3_N31827
    );
  U3_N31827_YUSED : X_BUF
    port map (
      I => U3_N31827_GROM,
      O => N44666
    );
  U3_n024337_SW0 : X_LUT4
    generic map(
      INIT => X"CFDF"
    )
    port map (
      ADR0 => U3_state_FFd23,
      ADR1 => U1_dis_evid_bloq,
      ADR2 => U3_error_evid,
      ADR3 => U3_state_FFd22,
      O => N44502_FROM
    );
  U3_n024337 : X_LUT4
    generic map(
      INIT => X"BBFB"
    )
    port map (
      ADR0 => U3_N31940,
      ADR1 => N44502,
      ADR2 => U3_state_FFd7,
      ADR3 => U1_dis_maxw_mask,
      O => N44502_GROM
    );
  N44502_XUSED : X_BUF
    port map (
      I => N44502_FROM,
      O => N44502
    );
  N44502_YUSED : X_BUF
    port map (
      I => N44502_GROM,
      O => CHOICE428
    );
  U1_I46_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29992,
      ADR3 => U1_N30021,
      O => U1_I46_N1762_FROM
    );
  U1_I67_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29937,
      ADR3 => U1_N29992,
      O => U1_I46_N1762_GROM
    );
  U1_I46_N1762_XUSED : X_BUF
    port map (
      I => U1_I46_N1762_FROM,
      O => U1_I46_N1762
    );
  U1_I46_N1762_YUSED : X_BUF
    port map (
      I => U1_I46_N1762_GROM,
      O => U1_I67_N1762
    );
  U2_n0076_SW1 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_2_IBUF,
      ADR2 => add_0_IBUF,
      ADR3 => VCC,
      O => N44656_FROM
    );
  U2_n0074_SW1 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => add_2_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => add_0_IBUF,
      ADR3 => VCC,
      O => N44656_GROM
    );
  N44656_XUSED : X_BUF
    port map (
      I => N44656_FROM,
      O => N44656
    );
  N44656_YUSED : X_BUF
    port map (
      I => N44656_GROM,
      O => N44644
    );
  U1_n0180_SW0 : X_LUT4
    generic map(
      INIT => X"DFDF"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_2_IBUF,
      ADR2 => add_0_IBUF,
      ADR3 => VCC,
      O => N38423_FROM
    );
  U1_n0180_921 : X_LUT4
    generic map(
      INIT => X"2227"
    )
    port map (
      ADR0 => U1_enw_paf_counter,
      ADR1 => N38423,
      ADR2 => U1_paf_cnt_set(3),
      ADR3 => paf_3_IBUF,
      O => N38423_GROM
    );
  N38423_XUSED : X_BUF
    port map (
      I => N38423_FROM,
      O => N38423
    );
  N38423_YUSED : X_BUF
    port map (
      I => N38423_GROM,
      O => U1_n0180
    );
  U2_n0077_SW1 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => VCC,
      O => N44652_FROM
    );
  Q_n005119 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => add_0_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => add_3_IBUF,
      O => N44652_GROM
    );
  N44652_XUSED : X_BUF
    port map (
      I => N44652_FROM,
      O => N44652
    );
  N44652_YUSED : X_BUF
    port map (
      I => N44652_GROM,
      O => CHOICE260
    );
  soft_reset1_1_922 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => vspare_0_IBUF,
      ADR1 => reset2,
      ADR2 => reset_IBUF,
      ADR3 => reset1,
      O => soft_reset1_1_FROM
    );
  U3_dontread_0_n00001 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => soft_reset1_1_GROM
    );
  soft_reset1_1_XUSED : X_BUF
    port map (
      I => soft_reset1_1_FROM,
      O => soft_reset1_1
    );
  soft_reset1_1_YUSED : X_BUF
    port map (
      I => soft_reset1_1_GROM,
      O => U3_dontread_0_n0000
    );
  U2_n0078_SW1 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => add_0_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => VCC,
      O => N44648_FROM
    );
  U2_n0075_SW1 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => add_2_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => add_1_IBUF,
      ADR3 => VCC,
      O => N44648_GROM
    );
  N44648_XUSED : X_BUF
    port map (
      I => N44648_FROM,
      O => N44648
    );
  N44648_YUSED : X_BUF
    port map (
      I => N44648_GROM,
      O => N44631
    );
  notblocked_1_13 : X_LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      ADR0 => U1_ff_reg(1),
      ADR1 => lock_1_IBUF,
      ADR2 => U1_hasunlock(1),
      ADR3 => U1_dis_hul_mask,
      O => CHOICE301_FROM
    );
  notblocked_0_13 : X_LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      ADR0 => U1_ff_reg(0),
      ADR1 => lock_0_IBUF,
      ADR2 => U1_hasunlock(0),
      ADR3 => U1_dis_hul_mask,
      O => CHOICE301_GROM
    );
  CHOICE301_XUSED : X_BUF
    port map (
      I => CHOICE301_FROM,
      O => CHOICE301
    );
  CHOICE301_YUSED : X_BUF
    port map (
      I => CHOICE301_GROM,
      O => CHOICE284
    );
  U3_n0102_3_7 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_dontread(3),
      ADR2 => U3_state_FFd17,
      ADR3 => evid_3_IBUF,
      O => CHOICE774_FROM
    );
  Q_n006624 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => evid_0_IBUF,
      ADR1 => evid_1_IBUF,
      ADR2 => evid_2_IBUF,
      ADR3 => evid_3_IBUF,
      O => CHOICE774_GROM
    );
  CHOICE774_XUSED : X_BUF
    port map (
      I => CHOICE774_FROM,
      O => CHOICE774
    );
  CHOICE774_YUSED : X_BUF
    port map (
      I => CHOICE774_GROM,
      O => CHOICE91
    );
  notblocked_0_32 : X_LUT4
    generic map(
      INIT => X"B0BB"
    )
    port map (
      ADR0 => U1_dis_maxw_mask,
      ADR1 => U3_maxw_reached(0),
      ADR2 => U1_dis_evid_bloq,
      ADR3 => U3_evid_mis(0),
      O => CHOICE293_FROM
    );
  notblocked_0_37 : X_LUT4
    generic map(
      INIT => X"00A2"
    )
    port map (
      ADR0 => CHOICE293,
      ADR1 => U3_timed_out(0),
      ADR2 => U1_dis_timo_mask,
      ADR3 => U1_mask(0),
      O => CHOICE293_GROM
    );
  CHOICE293_XUSED : X_BUF
    port map (
      I => CHOICE293_FROM,
      O => CHOICE293
    );
  CHOICE293_YUSED : X_BUF
    port map (
      I => CHOICE293_GROM,
      O => CHOICE294
    );
  U1_n0182_SW0 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => VCC,
      O => N38375_FROM
    );
  U1_n0182_923 : X_LUT4
    generic map(
      INIT => X"CD01"
    )
    port map (
      ADR0 => U1_paf_cnt_set(5),
      ADR1 => U1_enw_paf_counter,
      ADR2 => paf_5_IBUF,
      ADR3 => N38375,
      O => N38375_GROM
    );
  N38375_XUSED : X_BUF
    port map (
      I => N38375_FROM,
      O => N38375
    );
  N38375_YUSED : X_BUF
    port map (
      I => N38375_GROM,
      O => U1_n0182
    );
  notblocked_0_43 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => CHOICE284,
      ADR1 => CHOICE294,
      ADR2 => VCC,
      ADR3 => VCC,
      O => blocked_0_FROM
    );
  Mmux_n0048_Result_0_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => Q_n0051,
      ADR1 => N44092,
      ADR2 => blocked(0),
      ADR3 => hasul_0_OBUF,
      O => Q_n0048(0)
    );
  blocked_0_XUSED : X_BUF
    port map (
      I => blocked_0_FROM,
      O => hasul_0_OBUF
    );
  U3_n0102_9_5 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_evid_mis(3),
      ADR2 => U3_state_FFd17,
      ADR3 => evid_9_IBUF,
      O => CHOICE723_FROM
    );
  Q_n006661 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => evid_8_IBUF,
      ADR1 => evid_9_IBUF,
      ADR2 => evid_10_IBUF,
      ADR3 => evid_11_IBUF,
      O => CHOICE723_GROM
    );
  CHOICE723_XUSED : X_BUF
    port map (
      I => CHOICE723_FROM,
      O => CHOICE723
    );
  CHOICE723_YUSED : X_BUF
    port map (
      I => CHOICE723_GROM,
      O => CHOICE106
    );
  U3_n0102_7_6 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd17,
      ADR1 => evid_7_IBUF,
      ADR2 => U3_state_FFd19,
      ADR3 => U3_header1_reg(7),
      O => CHOICE696_FROM
    );
  Q_n006648 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => evid_4_IBUF,
      ADR1 => evid_5_IBUF,
      ADR2 => evid_6_IBUF,
      ADR3 => evid_7_IBUF,
      O => CHOICE696_GROM
    );
  CHOICE696_XUSED : X_BUF
    port map (
      I => CHOICE696_FROM,
      O => CHOICE696
    );
  CHOICE696_YUSED : X_BUF
    port map (
      I => CHOICE696_GROM,
      O => CHOICE99
    );
  notblocked_1_32 : X_LUT4
    generic map(
      INIT => X"B0BB"
    )
    port map (
      ADR0 => U1_dis_maxw_mask,
      ADR1 => U3_maxw_reached(1),
      ADR2 => U1_dis_evid_bloq,
      ADR3 => U3_evid_mis(1),
      O => CHOICE310_FROM
    );
  notblocked_1_37 : X_LUT4
    generic map(
      INIT => X"00A2"
    )
    port map (
      ADR0 => CHOICE310,
      ADR1 => U3_timed_out(1),
      ADR2 => U1_dis_timo_mask,
      ADR3 => U1_mask(1),
      O => CHOICE310_GROM
    );
  CHOICE310_XUSED : X_BUF
    port map (
      I => CHOICE310_FROM,
      O => CHOICE310
    );
  CHOICE310_YUSED : X_BUF
    port map (
      I => CHOICE310_GROM,
      O => CHOICE311
    );
  notblocked_1_43 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => CHOICE301,
      ADR1 => CHOICE311,
      ADR2 => VCC,
      ADR3 => VCC,
      O => blocked_1_FROM
    );
  Mmux_n0048_Result_1_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => Q_n0051,
      ADR1 => N44094,
      ADR2 => blocked(1),
      ADR3 => hasul_1_OBUF,
      O => Q_n0048(1)
    );
  blocked_1_XUSED : X_BUF
    port map (
      I => blocked_1_FROM,
      O => hasul_1_OBUF
    );
  notblocked_5_13 : X_LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      ADR0 => U1_ff_reg(5),
      ADR1 => lock_5_IBUF,
      ADR2 => U1_hasunlock(5),
      ADR3 => U1_dis_hul_mask,
      O => CHOICE369_FROM
    );
  notblocked_2_13 : X_LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      ADR0 => U1_ff_reg(2),
      ADR1 => lock_2_IBUF,
      ADR2 => U1_hasunlock(2),
      ADR3 => U1_dis_hul_mask,
      O => CHOICE369_GROM
    );
  CHOICE369_XUSED : X_BUF
    port map (
      I => CHOICE369_FROM,
      O => CHOICE369
    );
  CHOICE369_YUSED : X_BUF
    port map (
      I => CHOICE369_GROM,
      O => CHOICE318
    );
  U1_I43_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29983,
      ADR3 => U1_N30021,
      O => U1_I43_N1762_FROM
    );
  U1_I47_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29930,
      ADR3 => U1_N29983,
      O => U1_I43_N1762_GROM
    );
  U1_I43_N1762_XUSED : X_BUF
    port map (
      I => U1_I43_N1762_FROM,
      O => U1_I43_N1762
    );
  U1_I43_N1762_YUSED : X_BUF
    port map (
      I => U1_I43_N1762_GROM,
      O => U1_I47_N1762
    );
  U1_I60_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => cs_IBUF,
      ADR1 => U1_etr_paf_counter,
      ADR2 => add_2_IBUF,
      ADR3 => U1_N29974,
      O => U1_I60_N1762_FROM
    );
  U1_I63_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => U1_etr_paf_counter,
      ADR1 => add_2_IBUF,
      ADR2 => U1_N29983,
      ADR3 => cs_IBUF,
      O => U1_I60_N1762_GROM
    );
  U1_I60_N1762_XUSED : X_BUF
    port map (
      I => U1_I60_N1762_FROM,
      O => U1_I60_N1762
    );
  U1_I60_N1762_YUSED : X_BUF
    port map (
      I => U1_I60_N1762_GROM,
      O => U1_I63_N1762
    );
  U3_dontread_0_n00011 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_0_n0001_FROM
    );
  U3_dontread_1_n00011 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_0_n0001_GROM
    );
  U3_dontread_0_n0001_XUSED : X_BUF
    port map (
      I => U3_dontread_0_n0001_FROM,
      O => U3_dontread_0_n0001
    );
  U3_dontread_0_n0001_YUSED : X_BUF
    port map (
      I => U3_dontread_0_n0001_GROM,
      O => U3_dontread_1_n0001
    );
  notblocked_2_32 : X_LUT4
    generic map(
      INIT => X"B0BB"
    )
    port map (
      ADR0 => U1_dis_maxw_mask,
      ADR1 => U3_maxw_reached(2),
      ADR2 => U1_dis_evid_bloq,
      ADR3 => U3_evid_mis(2),
      O => CHOICE327_FROM
    );
  notblocked_2_37 : X_LUT4
    generic map(
      INIT => X"00A2"
    )
    port map (
      ADR0 => CHOICE327,
      ADR1 => U3_timed_out(2),
      ADR2 => U1_dis_timo_mask,
      ADR3 => U1_mask(2),
      O => CHOICE327_GROM
    );
  CHOICE327_XUSED : X_BUF
    port map (
      I => CHOICE327_FROM,
      O => CHOICE327
    );
  CHOICE327_YUSED : X_BUF
    port map (
      I => CHOICE327_GROM,
      O => CHOICE328
    );
  notblocked_2_43 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => CHOICE318,
      ADR1 => CHOICE328,
      ADR2 => VCC,
      ADR3 => VCC,
      O => blocked_2_FROM
    );
  Mmux_n0048_Result_2_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => Q_n0051,
      ADR1 => N44096,
      ADR2 => blocked(2),
      ADR3 => hasul_2_OBUF,
      O => Q_n0048(2)
    );
  blocked_2_XUSED : X_BUF
    port map (
      I => blocked_2_FROM,
      O => hasul_2_OBUF
    );
  notblocked_3_13 : X_LUT4
    generic map(
      INIT => X"FF01"
    )
    port map (
      ADR0 => U1_ff_reg(3),
      ADR1 => lock_3_IBUF,
      ADR2 => U1_hasunlock(3),
      ADR3 => U1_dis_hul_mask,
      O => CHOICE352_GROM
    );
  CHOICE352_YUSED : X_BUF
    port map (
      I => CHOICE352_GROM,
      O => CHOICE352
    );
  U3_this_paf9 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => paf_3_IBUF,
      ADR1 => U3_sel_read(3),
      ADR2 => paf_2_IBUF,
      ADR3 => U3_sel_read(2),
      O => CHOICE512_FROM
    );
  U3_this_ff9 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => ff_3_IBUF,
      ADR1 => U3_sel_read(3),
      ADR2 => ff_2_IBUF,
      ADR3 => U3_sel_read(2),
      O => CHOICE512_GROM
    );
  CHOICE512_XUSED : X_BUF
    port map (
      I => CHOICE512_FROM,
      O => CHOICE512
    );
  CHOICE512_YUSED : X_BUF
    port map (
      I => CHOICE512_GROM,
      O => CHOICE397
    );
  U3_n01033 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd9,
      ADR1 => U3_state_FFd37,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE265_FROM
    );
  U3_n01039 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE265,
      ADR1 => U3_state_FFd29,
      ADR2 => U3_state_FFd25,
      ADR3 => U3_state_FFd15,
      O => CHOICE265_GROM
    );
  CHOICE265_XUSED : X_BUF
    port map (
      I => CHOICE265_FROM,
      O => CHOICE265
    );
  CHOICE265_YUSED : X_BUF
    port map (
      I => CHOICE265_GROM,
      O => CHOICE268
    );
  U3_Ker316491_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd27,
      ADR1 => U3_state_FFd25,
      ADR2 => U3_state_FFd39,
      ADR3 => U3_state_FFd10,
      O => N44336_FROM
    );
  U3_n01042 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd29,
      ADR1 => U3_state_FFd27,
      ADR2 => U3_state_FFd10,
      ADR3 => VCC,
      O => N44336_GROM
    );
  N44336_XUSED : X_BUF
    port map (
      I => N44336_FROM,
      O => N44336
    );
  N44336_YUSED : X_BUF
    port map (
      I => N44336_GROM,
      O => CHOICE530
    );
  notblocked_3_32 : X_LUT4
    generic map(
      INIT => X"B0BB"
    )
    port map (
      ADR0 => U1_dis_maxw_mask,
      ADR1 => U3_maxw_reached(3),
      ADR2 => U1_dis_evid_bloq,
      ADR3 => U3_evid_mis(3),
      O => CHOICE361_FROM
    );
  notblocked_3_37 : X_LUT4
    generic map(
      INIT => X"00A2"
    )
    port map (
      ADR0 => CHOICE361,
      ADR1 => U3_timed_out(3),
      ADR2 => U1_dis_timo_mask,
      ADR3 => U1_mask(3),
      O => CHOICE361_GROM
    );
  CHOICE361_XUSED : X_BUF
    port map (
      I => CHOICE361_FROM,
      O => CHOICE361
    );
  CHOICE361_YUSED : X_BUF
    port map (
      I => CHOICE361_GROM,
      O => CHOICE362
    );
  U3_n01052 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd25,
      ADR1 => U3_state_FFd18,
      ADR2 => U3_state_FFd39,
      ADR3 => VCC,
      O => U3_sel_read_5_1_FROM
    );
  U3_n010539_1 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE601,
      ADR1 => U3_N31572,
      ADR2 => CHOICE590,
      ADR3 => U3_sel_read(5),
      O => U3_n010539_1_O
    );
  U3_sel_read_5_1_XUSED : X_BUF
    port map (
      I => U3_sel_read_5_1_FROM,
      O => CHOICE590
    );
  U3_sel_read_5_1_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_sel_read_5_1_SRMUX_OUTPUTNOT
    );
  notblocked_3_43 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => CHOICE352,
      ADR1 => CHOICE362,
      ADR2 => VCC,
      ADR3 => VCC,
      O => blocked_3_FROM
    );
  Mmux_n0048_Result_3_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => Q_n0051,
      ADR1 => N44098,
      ADR2 => blocked(3),
      ADR3 => hasul_3_OBUF,
      O => Q_n0048(3)
    );
  blocked_3_XUSED : X_BUF
    port map (
      I => blocked_3_FROM,
      O => hasul_3_OBUF
    );
  U2_disparity_inst_lut3_01_SW0 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => enw1,
      ADR1 => cs_IBUF,
      ADR2 => U1_N30014,
      ADR3 => U1_N30000,
      O => N44542_FROM
    );
  U2_disparity_inst_lut3_01 : X_LUT4
    generic map(
      INIT => X"FB40"
    )
    port map (
      ADR0 => enw2,
      ADR1 => N44542,
      ADR2 => N44072,
      ADR3 => U2_disparity(0),
      O => N44542_GROM
    );
  N44542_XUSED : X_BUF
    port map (
      I => N44542_FROM,
      O => N44542
    );
  N44542_YUSED : X_BUF
    port map (
      I => N44542_GROM,
      O => U2_disparity_inst_lut3_0
    );
  U3_dontread_2_n00001 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_2_n0000_FROM
    );
  U3_dontread_5_n00011 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_2_n0000_GROM
    );
  U3_dontread_2_n0000_XUSED : X_BUF
    port map (
      I => U3_dontread_2_n0000_FROM,
      O => U3_dontread_2_n0000
    );
  U3_dontread_2_n0000_YUSED : X_BUF
    port map (
      I => U3_dontread_2_n0000_GROM,
      O => U3_dontread_5_n0001
    );
  notblocked_4_32 : X_LUT4
    generic map(
      INIT => X"B0BB"
    )
    port map (
      ADR0 => U1_dis_maxw_mask,
      ADR1 => U3_maxw_reached(4),
      ADR2 => U1_dis_evid_bloq,
      ADR3 => U3_evid_mis(4),
      O => CHOICE344_FROM
    );
  notblocked_4_37 : X_LUT4
    generic map(
      INIT => X"00A2"
    )
    port map (
      ADR0 => CHOICE344,
      ADR1 => U3_timed_out(4),
      ADR2 => U1_dis_timo_mask,
      ADR3 => U1_mask(4),
      O => CHOICE344_GROM
    );
  CHOICE344_XUSED : X_BUF
    port map (
      I => CHOICE344_FROM,
      O => CHOICE344
    );
  CHOICE344_YUSED : X_BUF
    port map (
      I => CHOICE344_GROM,
      O => CHOICE345
    );
  notblocked_4_43 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => CHOICE335,
      ADR1 => CHOICE345,
      ADR2 => VCC,
      ADR3 => VCC,
      O => blocked_4_FROM
    );
  Mmux_n0048_Result_4_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => Q_n0051,
      ADR1 => N44100,
      ADR2 => blocked(4),
      ADR3 => hasul_4_OBUF,
      O => Q_n0048(4)
    );
  blocked_4_XUSED : X_BUF
    port map (
      I => blocked_4_FROM,
      O => hasul_4_OBUF
    );
  Q_n006674_SW0 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => cspare_0_IBUF,
      ADR1 => CHOICE91,
      ADR2 => CHOICE99,
      ADR3 => CHOICE106,
      O => N44514_FROM
    );
  Q_n006674 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => CLK,
      ADR1 => vspare_1_IBUF,
      ADR2 => cspare_1_IBUF,
      ADR3 => N44514,
      O => N44514_GROM
    );
  N44514_XUSED : X_BUF
    port map (
      I => N44514_FROM,
      O => N44514
    );
  N44514_YUSED : X_BUF
    port map (
      I => N44514_GROM,
      O => tp_3_OBUF
    );
  notblocked_5_32 : X_LUT4
    generic map(
      INIT => X"B0BB"
    )
    port map (
      ADR0 => U1_dis_maxw_mask,
      ADR1 => U3_maxw_reached(5),
      ADR2 => U1_dis_evid_bloq,
      ADR3 => U3_evid_mis(5),
      O => CHOICE378_FROM
    );
  notblocked_5_37 : X_LUT4
    generic map(
      INIT => X"00A2"
    )
    port map (
      ADR0 => CHOICE378,
      ADR1 => U3_timed_out(5),
      ADR2 => U1_dis_timo_mask,
      ADR3 => U1_mask(5),
      O => CHOICE378_GROM
    );
  CHOICE378_XUSED : X_BUF
    port map (
      I => CHOICE378_FROM,
      O => CHOICE378
    );
  CHOICE378_YUSED : X_BUF
    port map (
      I => CHOICE378_GROM,
      O => CHOICE379
    );
  U3_n00491 : X_LUT4
    generic map(
      INIT => X"0002"
    )
    port map (
      ADR0 => fout_12_IBUF,
      ADR1 => fout_13_IBUF,
      ADR2 => fout_14_IBUF,
      ADR3 => fout_15_IBUF,
      O => U3_n0049_FROM
    );
  U3_Ker319171 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => U3_state_FFd9,
      ADR1 => U3_n0049,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_n0049_GROM
    );
  U3_n0049_XUSED : X_BUF
    port map (
      I => U3_n0049_FROM,
      O => U3_n0049
    );
  U3_n0049_YUSED : X_BUF
    port map (
      I => U3_n0049_GROM,
      O => U3_N31919
    );
  notblocked_5_43 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => CHOICE369,
      ADR1 => CHOICE379,
      ADR2 => VCC,
      ADR3 => VCC,
      O => blocked_5_FROM
    );
  Mmux_n0048_Result_5_1 : X_LUT4
    generic map(
      INIT => X"D8DD"
    )
    port map (
      ADR0 => Q_n0051,
      ADR1 => N44102,
      ADR2 => blocked(5),
      ADR3 => hasul_5_OBUF,
      O => Q_n0048(5)
    );
  blocked_5_XUSED : X_BUF
    port map (
      I => blocked_5_FROM,
      O => hasul_5_OBUF
    );
  U3_n011010 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd23,
      ADR1 => U3_state_FFd5,
      ADR2 => U3_sel_read(0),
      ADR3 => VCC,
      O => CHOICE661_FROM
    );
  U3_n02181 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd23,
      ADR1 => U3_state_FFd5,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE661_GROM
    );
  CHOICE661_XUSED : X_BUF
    port map (
      I => CHOICE661_FROM,
      O => CHOICE661
    );
  CHOICE661_YUSED : X_BUF
    port map (
      I => CHOICE661_GROM,
      O => U3_n0218
    );
  U1_n0010_SW1 : X_LUT4
    generic map(
      INIT => X"FFFB"
    )
    port map (
      ADR0 => add_4_IBUF,
      ADR1 => add_2_IBUF,
      ADR2 => add_1_IBUF,
      ADR3 => add_0_IBUF,
      O => N44622_FROM
    );
  U2_n0079_SW1 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => add_2_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => add_1_IBUF,
      ADR3 => VCC,
      O => N44622_GROM
    );
  N44622_XUSED : X_BUF
    port map (
      I => N44622_FROM,
      O => N44622
    );
  N44622_YUSED : X_BUF
    port map (
      I => N44622_GROM,
      O => N44640
    );
  U1_n0177_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => VCC,
      O => N38588_FROM
    );
  U1_n0177_924 : X_LUT4
    generic map(
      INIT => X"2227"
    )
    port map (
      ADR0 => U1_enw_paf_counter,
      ADR1 => N38588,
      ADR2 => U1_paf_cnt_set(0),
      ADR3 => paf_0_IBUF,
      O => N38588_GROM
    );
  N38588_XUSED : X_BUF
    port map (
      I => N38588_FROM,
      O => N38588
    );
  N38588_YUSED : X_BUF
    port map (
      I => N38588_GROM,
      O => U1_n0177
    );
  reset_IBUF_1_925 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => reset_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => reset_IBUF_1_FROM
    );
  reset_largo1 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => reset2,
      ADR1 => reset_IBUF,
      ADR2 => reset1,
      ADR3 => VCC,
      O => reset_IBUF_1_GROM
    );
  reset_IBUF_1_XUSED : X_BUF
    port map (
      I => reset_IBUF_1_FROM,
      O => reset_IBUF_1
    );
  reset_IBUF_1_YUSED : X_BUF
    port map (
      I => reset_IBUF_1_GROM,
      O => reset_largo
    );
  U2_n01321 : X_LUT4
    generic map(
      INIT => X"D555"
    )
    port map (
      ADR0 => U2_loadcnt(5),
      ADR1 => U1_N30000,
      ADR2 => U1_N29954,
      ADR3 => U1_N29930,
      O => U2_n0132_FROM
    );
  U3_n02391 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => U1_N30021,
      ADR1 => U3_state_FFd11,
      ADR2 => U1_N29954,
      ADR3 => U1_N30000,
      O => U2_n0132_GROM
    );
  U2_n0132_XUSED : X_BUF
    port map (
      I => U2_n0132_FROM,
      O => U2_n0132
    );
  U2_n0132_YUSED : X_BUF
    port map (
      I => U2_n0132_GROM,
      O => U3_n0239
    );
  U3_n00954 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_N31808,
      ADR2 => U3_n0216,
      ADR3 => U3_n0218,
      O => CHOICE578_FROM
    );
  U3_n00957 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd25,
      ADR1 => U3_this_ef23_2,
      ADR2 => CHOICE578,
      ADR3 => VCC,
      O => CHOICE578_GROM
    );
  CHOICE578_XUSED : X_BUF
    port map (
      I => CHOICE578_FROM,
      O => CHOICE578
    );
  CHOICE578_YUSED : X_BUF
    port map (
      I => CHOICE578_GROM,
      O => CHOICE580
    );
  U2_Mxor_cpar_1_Xo_4_1 : X_LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      ADR0 => fout_8_IBUF,
      ADR1 => fout_9_IBUF,
      ADR2 => fout_10_IBUF,
      ADR3 => fout_11_IBUF,
      O => U2_Mxor_cpar_1_Xo_4_GROM
    );
  U2_Mxor_cpar_1_Xo_4_YUSED : X_BUF
    port map (
      I => U2_Mxor_cpar_1_Xo_4_GROM,
      O => U2_Mxor_cpar_1_Xo(4)
    );
  U2_Mxor_cpar_1_Xo_5_1 : X_LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      ADR0 => fout_12_IBUF,
      ADR1 => fout_13_IBUF,
      ADR2 => fout_14_IBUF,
      ADR3 => fout_15_IBUF,
      O => U2_Mxor_cpar_1_Xo_5_FROM
    );
  U2_Mxor_cpar_1_Xo_6_1 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => U2_Mxor_cpar_1_Xo(4),
      ADR1 => U2_Mxor_cpar_1_Xo(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U2_Mxor_cpar_1_Xo_5_GROM
    );
  U2_Mxor_cpar_1_Xo_5_XUSED : X_BUF
    port map (
      I => U2_Mxor_cpar_1_Xo_5_FROM,
      O => U2_Mxor_cpar_1_Xo(5)
    );
  U2_Mxor_cpar_1_Xo_5_YUSED : X_BUF
    port map (
      I => U2_Mxor_cpar_1_Xo_5_GROM,
      O => U2_cpar(1)
    );
  U1_I52_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29974,
      ADR3 => U1_N30014,
      O => U1_I52_N1762_FROM
    );
  U1_I51_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29983,
      ADR3 => U1_N30014,
      O => U1_I52_N1762_GROM
    );
  U1_I52_N1762_XUSED : X_BUF
    port map (
      I => U1_I52_N1762_FROM,
      O => U1_I52_N1762
    );
  U1_I52_N1762_YUSED : X_BUF
    port map (
      I => U1_I52_N1762_GROM,
      O => U1_I51_N1762
    );
  U1_n0178_SW0 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => add_0_IBUF,
      ADR1 => add_1_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => VCC,
      O => N38533_FROM
    );
  U1_n0178_926 : X_LUT4
    generic map(
      INIT => X"2227"
    )
    port map (
      ADR0 => U1_enw_paf_counter,
      ADR1 => N38533,
      ADR2 => U1_paf_cnt_set(1),
      ADR3 => paf_1_IBUF,
      O => N38533_GROM
    );
  N38533_XUSED : X_BUF
    port map (
      I => N38533_FROM,
      O => N38533
    );
  N38533_YUSED : X_BUF
    port map (
      I => N38533_GROM,
      O => U1_n0178
    );
  U3_n00989 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => U1_dis_head_trail,
      ADR1 => U3_n0049,
      ADR2 => U3_state_FFd25,
      ADR3 => U3_N31694,
      O => CHOICE475_FROM
    );
  U3_n009825 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE475,
      ADR1 => CHOICE478,
      ADR2 => CHOICE480,
      ADR3 => VCC,
      O => CHOICE475_GROM
    );
  CHOICE475_XUSED : X_BUF
    port map (
      I => CHOICE475_FROM,
      O => CHOICE475
    );
  CHOICE475_YUSED : X_BUF
    port map (
      I => CHOICE475_GROM,
      O => CHOICE482
    );
  U3_Ker317071_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_evid_mis(1),
      ADR2 => U3_state_FFd7,
      ADR3 => VCC,
      O => N44510_FROM
    );
  U3_Ker317071_SW0 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd16,
      ADR1 => U3_header2_reg(7),
      ADR2 => CHOICE696,
      ADR3 => N44510,
      O => N44510_GROM
    );
  N44510_XUSED : X_BUF
    port map (
      I => N44510_FROM,
      O => N44510
    );
  N44510_YUSED : X_BUF
    port map (
      I => N44510_GROM,
      O => N44344
    );
  U1_n0179_SW0 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => add_1_IBUF,
      ADR1 => add_0_IBUF,
      ADR2 => add_2_IBUF,
      ADR3 => VCC,
      O => N38478_FROM
    );
  U1_n0179_927 : X_LUT4
    generic map(
      INIT => X"2227"
    )
    port map (
      ADR0 => U1_enw_paf_counter,
      ADR1 => N38478,
      ADR2 => U1_paf_cnt_set(2),
      ADR3 => paf_2_IBUF,
      O => N38478_GROM
    );
  N38478_XUSED : X_BUF
    port map (
      I => N38478_FROM,
      O => N38478
    );
  N38478_YUSED : X_BUF
    port map (
      I => N38478_GROM,
      O => U1_n0179
    );
  U3_state_FFd2_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd2_SRMUX_OUTPUTNOT
    );
  U2_fwrg1_LOGIC_ONE_928 : X_ONE
    port map (
      O => U2_fwrg1_LOGIC_ONE
    );
  U2_fwrg2_LOGIC_ONE_929 : X_ONE
    port map (
      O => U2_fwrg2_LOGIC_ONE
    );
  U2_fwrg3_FFY_RSTOR : X_OR2
    port map (
      I0 => U2_n0045,
      I1 => GSR,
      O => U2_fwrg3_FFY_RST
    );
  U2_fwrg3_930 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fwrg2,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_fwrg3_FFY_RST,
      O => U2_fwrg3
    );
  U3_this_dontread14 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_dontread(1),
      ADR1 => U3_sel_read(1),
      ADR2 => U3_dontread(0),
      ADR3 => U3_sel_read(0),
      O => CHOICE389_FROM
    );
  U3_this_dontread23 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE383,
      ADR1 => CHOICE386,
      ADR2 => CHOICE389,
      ADR3 => VCC,
      O => CHOICE389_GROM
    );
  CHOICE389_XUSED : X_BUF
    port map (
      I => CHOICE389_FROM,
      O => CHOICE389
    );
  CHOICE389_YUSED : X_BUF
    port map (
      I => CHOICE389_GROM,
      O => U3_this_dontread
    );
  U1_etr_paepaf_p_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => add_4_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U1_etr_paepaf_reg_2_FROM
    );
  U1_etr_paepaf_p : X_LUT4
    generic map(
      INIT => X"FDFF"
    )
    port map (
      ADR0 => add_5_IBUF,
      ADR1 => N37571,
      ADR2 => etr_x_IBUF,
      ADR3 => cs_IBUF,
      O => U1_etr_paepaf_reg_2_GROM
    );
  U1_etr_paepaf_reg_2_XUSED : X_BUF
    port map (
      I => U1_etr_paepaf_reg_2_FROM,
      O => N37571
    );
  U1_etr_paepaf_reg_2_YUSED : X_BUF
    port map (
      I => U1_etr_paepaf_reg_2_GROM,
      O => etr_paepaf
    );
  U1_enw_paf_counter1_4_931 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => enw2,
      ADR2 => enw1,
      ADR3 => U1_N29944,
      O => U1_enw_paf_counter1_4_FROM
    );
  U1_n0010_932 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_5_IBUF,
      ADR1 => N44622,
      ADR2 => U1_N29954,
      ADR3 => add_3_IBUF,
      O => U1_enw_paf_counter1_4_GROM
    );
  U1_enw_paf_counter1_4_XUSED : X_BUF
    port map (
      I => U1_enw_paf_counter1_4_FROM,
      O => U1_enw_paf_counter1_4
    );
  U1_enw_paf_counter1_4_YUSED : X_BUF
    port map (
      I => U1_enw_paf_counter1_4_GROM,
      O => U1_n0010
    );
  U3_this_ff14 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => ff_1_IBUF,
      ADR1 => U3_sel_read(1),
      ADR2 => ff_0_IBUF,
      ADR3 => U3_sel_read(0),
      O => CHOICE400_FROM
    );
  U3_this_ff23 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE394,
      ADR1 => CHOICE397,
      ADR2 => CHOICE400,
      ADR3 => VCC,
      O => CHOICE400_GROM
    );
  CHOICE400_XUSED : X_BUF
    port map (
      I => CHOICE400_FROM,
      O => CHOICE400
    );
  CHOICE400_YUSED : X_BUF
    port map (
      I => CHOICE400_GROM,
      O => U3_this_ff
    );
  U3_n0102_2_6 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => lock_1_IBUF,
      ADR1 => U3_sel_read(1),
      ADR2 => lock_0_IBUF,
      ADR3 => U3_sel_read(0),
      O => CHOICE894_FROM
    );
  U3_this_hasunlock14 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U1_hasunlock(1),
      ADR1 => U3_sel_read(1),
      ADR2 => U1_hasunlock(0),
      ADR3 => U3_sel_read(0),
      O => CHOICE894_GROM
    );
  CHOICE894_XUSED : X_BUF
    port map (
      I => CHOICE894_FROM,
      O => CHOICE894
    );
  CHOICE894_YUSED : X_BUF
    port map (
      I => CHOICE894_GROM,
      O => CHOICE526
    );
  U3_Ker31197_SW0 : X_LUT4
    generic map(
      INIT => X"E0E0"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U3_n0216,
      ADR2 => U3_sel_read(5),
      ADR3 => VCC,
      O => N39609_FROM
    );
  U3_n010517 : X_LUT4
    generic map(
      INIT => X"F8A8"
    )
    port map (
      ADR0 => U3_sel_read(4),
      ADR1 => U3_N31940,
      ADR2 => U3_n0216,
      ADR3 => U3_sel_read(5),
      O => N39609_GROM
    );
  N39609_XUSED : X_BUF
    port map (
      I => N39609_FROM,
      O => N39609
    );
  N39609_YUSED : X_BUF
    port map (
      I => N39609_GROM,
      O => CHOICE596
    );
  U3_Ker314771 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_N31548,
      ADR1 => U3_state_FFd36_In,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_N31479_FROM
    );
  U3_n0102_6_44_SW1 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd36_In,
      ADR1 => CHOICE808,
      ADR2 => U3_trailer_reg_6_Q,
      ADR3 => VCC,
      O => U3_N31479_GROM
    );
  U3_N31479_XUSED : X_BUF
    port map (
      I => U3_N31479_FROM,
      O => U3_N31479
    );
  U3_N31479_YUSED : X_BUF
    port map (
      I => U3_N31479_GROM,
      O => N44320
    );
  U3_n0102_0_33 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U1_ff_reg(1),
      ADR1 => U3_sel_read(1),
      ADR2 => U1_ff_reg(0),
      ADR3 => U3_sel_read(0),
      O => CHOICE931_FROM
    );
  U3_n010934 : X_LUT4
    generic map(
      INIT => X"A808"
    )
    port map (
      ADR0 => U3_n0218,
      ADR1 => U3_sel_read(0),
      ADR2 => U3_n0253,
      ADR3 => U3_sel_read(1),
      O => CHOICE931_GROM
    );
  CHOICE931_XUSED : X_BUF
    port map (
      I => CHOICE931_FROM,
      O => CHOICE931
    );
  CHOICE931_YUSED : X_BUF
    port map (
      I => CHOICE931_GROM,
      O => CHOICE986
    );
  U3_n0102_1_33 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => ceros_id_1_IBUF,
      ADR1 => tp_2_OBUF,
      ADR2 => U3_state_FFd38,
      ADR3 => VCC,
      O => CHOICE856_FROM
    );
  U3_Ker316641_SW0 : X_LUT4
    generic map(
      INIT => X"A0B3"
    )
    port map (
      ADR0 => U3_fmt_error_ff_2_3_Q,
      ADR1 => N44332,
      ADR2 => U3_state_FFd15,
      ADR3 => tp_2_OBUF,
      O => CHOICE856_GROM
    );
  CHOICE856_XUSED : X_BUF
    port map (
      I => CHOICE856_FROM,
      O => CHOICE856
    );
  CHOICE856_YUSED : X_BUF
    port map (
      I => CHOICE856_GROM,
      O => N44430
    );
  U3_Ker31659_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => U3_state_FFd34,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N39520_FROM
    );
  U3_Ker316641_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE676,
      ADR1 => U3_state_FFd38,
      ADR2 => U3_state_FFd15,
      ADR3 => N44538,
      O => N39520_GROM
    );
  N39520_XUSED : X_BUF
    port map (
      I => N39520_FROM,
      O => N39520
    );
  N39520_YUSED : X_BUF
    port map (
      I => N39520_GROM,
      O => N44486
    );
  U1_I44_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29974,
      ADR3 => U1_N30021,
      O => U1_I44_N1762_FROM
    );
  U1_I48_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29930,
      ADR3 => U1_N29974,
      O => U1_I44_N1762_GROM
    );
  U1_I44_N1762_XUSED : X_BUF
    port map (
      I => U1_I44_N1762_FROM,
      O => U1_I44_N1762
    );
  U1_I44_N1762_YUSED : X_BUF
    port map (
      I => U1_I44_N1762_GROM,
      O => U1_I48_N1762
    );
  U1_I65_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29937,
      ADR3 => U1_N29974,
      O => U1_I65_N1762_FROM
    );
  U1_I56_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"BFFF"
    )
    port map (
      ADR0 => etr_x_IBUF,
      ADR1 => cs_IBUF,
      ADR2 => U1_N29937,
      ADR3 => U1_N29983,
      O => U1_I65_N1762_GROM
    );
  U1_I65_N1762_XUSED : X_BUF
    port map (
      I => U1_I65_N1762_FROM,
      O => U1_I65_N1762
    );
  U1_I65_N1762_YUSED : X_BUF
    port map (
      I => U1_I65_N1762_GROM,
      O => U1_I56_N1762
    );
  U3_dontread_3_n00011 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_3_n0001_FROM
    );
  U3_dontread_2_n00011 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => soft_reset1_1,
      ADR1 => U1_mask(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_dontread_3_n0001_GROM
    );
  U3_dontread_3_n0001_XUSED : X_BUF
    port map (
      I => U3_dontread_3_n0001_FROM,
      O => U3_dontread_3_n0001
    );
  U3_dontread_3_n0001_YUSED : X_BUF
    port map (
      I => U3_dontread_3_n0001_GROM,
      O => U3_dontread_2_n0001
    );
  U3_Ker312541_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => U3_state_FFd32,
      ADR1 => U3_state_FFd26,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N44290_FROM
    );
  U3_n009814 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd32,
      ADR1 => U3_state_FFd15,
      ADR2 => U3_state_FFd9,
      ADR3 => U3_state_FFd26,
      O => N44290_GROM
    );
  N44290_XUSED : X_BUF
    port map (
      I => N44290_FROM,
      O => N44290
    );
  N44290_YUSED : X_BUF
    port map (
      I => N44290_GROM,
      O => CHOICE478
    );
  U3_Ker312171_SW1 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U1_dis_ffreg_mask,
      ADR2 => U3_state_FFd38,
      ADR3 => U3_state_FFd35,
      O => N44328_FROM
    );
  U3_state_FFd32_In30_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U1_dis_ffreg_mask,
      ADR2 => U3_state_FFd30,
      ADR3 => VCC,
      O => N44328_GROM
    );
  N44328_XUSED : X_BUF
    port map (
      I => N44328_FROM,
      O => N44328
    );
  N44328_YUSED : X_BUF
    port map (
      I => N44328_GROM,
      O => N44662
    );
  U3_n009934 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE457,
      ADR1 => U3_state_FFd33,
      ADR2 => U3_state_FFd26,
      ADR3 => U3_N31694,
      O => CHOICE460_FROM
    );
  U3_n009952 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => U3_state_FFd36_In,
      ADR1 => U3_N31564,
      ADR2 => CHOICE460,
      ADR3 => U3_txena_dir,
      O => CHOICE460_GROM
    );
  CHOICE460_XUSED : X_BUF
    port map (
      I => CHOICE460_FROM,
      O => CHOICE460
    );
  CHOICE460_YUSED : X_BUF
    port map (
      I => CHOICE460_GROM,
      O => CHOICE463
    );
  U3_n0102_15_5 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => U3_state_FFd36,
      ADR1 => U3_state_FFd17,
      ADR2 => U3_state_FFd2,
      ADR3 => U3_state_FFd1,
      O => CHOICE824_FROM
    );
  U3_n009928 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd34,
      ADR1 => U3_state_FFd2,
      ADR2 => U3_state_FFd1,
      ADR3 => VCC,
      O => CHOICE824_GROM
    );
  CHOICE824_XUSED : X_BUF
    port map (
      I => CHOICE824_FROM,
      O => CHOICE824
    );
  CHOICE824_YUSED : X_BUF
    port map (
      I => CHOICE824_GROM,
      O => CHOICE457
    );
  U3_n009910_SW0 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => N44590,
      ADR1 => U3_state_FFd34,
      ADR2 => U3_state_FFd33,
      ADR3 => tp_2_OBUF,
      O => N44482_FROM
    );
  U3_n009920_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd13_In,
      ADR1 => U3_N31509,
      ADR2 => N44482,
      ADR3 => VCC,
      O => N44482_GROM
    );
  N44482_XUSED : X_BUF
    port map (
      I => N44482_FROM,
      O => N44482
    );
  N44482_YUSED : X_BUF
    port map (
      I => N44482_GROM,
      O => N44490
    );
  U3_state_FFd38_In_SW0 : X_LUT4
    generic map(
      INIT => X"DDDD"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => tp_2_OBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => U3_state_FFd38_FROM
    );
  U3_state_FFd38_In : X_LUT4
    generic map(
      INIT => X"A0B3"
    )
    port map (
      ADR0 => U3_N31235,
      ADR1 => U3_N31407,
      ADR2 => U3_sel_read_5_1,
      ADR3 => N39166,
      O => U3_state_FFd38_In_O
    );
  U3_state_FFd38_XUSED : X_BUF
    port map (
      I => U3_state_FFd38_FROM,
      O => N39166
    );
  U3_state_FFd38_SRMUX : X_INV
    port map (
      I => valen_IBUF,
      O => U3_state_FFd38_SRMUX_OUTPUTNOT
    );
  U1_enw_paf_counter1_2_933 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => enw2,
      ADR2 => enw1,
      ADR3 => U1_N29944,
      O => U1_enw_paf_counter1_2_FROM
    );
  U1_enw_paf_counter1 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => add_3_IBUF,
      ADR1 => enw2,
      ADR2 => enw1,
      ADR3 => U1_N29944,
      O => U1_enw_paf_counter1_2_GROM
    );
  U1_enw_paf_counter1_2_XUSED : X_BUF
    port map (
      I => U1_enw_paf_counter1_2_FROM,
      O => U1_enw_paf_counter1_2
    );
  U1_enw_paf_counter1_2_YUSED : X_BUF
    port map (
      I => U1_enw_paf_counter1_2_GROM,
      O => U1_enw_paf_counter
    );
  U1_paf_cnt_set_0_BYMUX : X_INV
    port map (
      I => paf_0_IBUF,
      O => U1_paf_cnt_set_0_BYMUXNOT
    );
  U1_paf_cnt_set_1_BYMUX : X_INV
    port map (
      I => paf_1_IBUF,
      O => U1_paf_cnt_set_1_BYMUXNOT
    );
  U1_paf_cnt_set_2_BYMUX : X_INV
    port map (
      I => paf_2_IBUF,
      O => U1_paf_cnt_set_2_BYMUXNOT
    );
  U1_paf_cnt_set_3_BYMUX : X_INV
    port map (
      I => paf_3_IBUF,
      O => U1_paf_cnt_set_3_BYMUXNOT
    );
  U2_n0074 : X_LUT4
    generic map(
      INIT => X"7F40"
    )
    port map (
      ADR0 => U3_sel_read_5_1,
      ADR1 => etr_fifo,
      ADR2 => etr_paepaf,
      ADR3 => N44644,
      O => oe_5_OBUF_FROM
    );
  U2_ren_5_1 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => read,
      ADR1 => per_paepaf,
      ADR2 => U1_per_fifo,
      ADR3 => oe_5_OBUF,
      O => oe_5_OBUF_GROM
    );
  oe_5_OBUF_XUSED : X_BUF
    port map (
      I => oe_5_OBUF_FROM,
      O => oe_5_OBUF
    );
  oe_5_OBUF_YUSED : X_BUF
    port map (
      I => oe_5_OBUF_GROM,
      O => ren_5_OBUF
    );
  U1_paf_cnt_set_4_BYMUX : X_INV
    port map (
      I => paf_4_IBUF,
      O => U1_paf_cnt_set_4_BYMUXNOT
    );
  U2_n0075 : X_LUT4
    generic map(
      INIT => X"7F40"
    )
    port map (
      ADR0 => U3_sel_read(4),
      ADR1 => etr_fifo,
      ADR2 => etr_paepaf,
      ADR3 => N44631,
      O => oe_4_OBUF_FROM
    );
  U2_ren_4_1 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => read,
      ADR1 => per_paepaf,
      ADR2 => U1_per_fifo,
      ADR3 => oe_4_OBUF,
      O => oe_4_OBUF_GROM
    );
  oe_4_OBUF_XUSED : X_BUF
    port map (
      I => oe_4_OBUF_FROM,
      O => oe_4_OBUF
    );
  oe_4_OBUF_YUSED : X_BUF
    port map (
      I => oe_4_OBUF_GROM,
      O => ren_4_OBUF
    );
  U1_paf_cnt_set_5_BYMUX : X_INV
    port map (
      I => paf_5_IBUF,
      O => U1_paf_cnt_set_5_BYMUXNOT
    );
  U2_n0076 : X_LUT4
    generic map(
      INIT => X"7F40"
    )
    port map (
      ADR0 => U3_sel_read(3),
      ADR1 => etr_fifo,
      ADR2 => etr_paepaf,
      ADR3 => N44656,
      O => oe_3_OBUF_FROM
    );
  U2_ren_3_1 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => read,
      ADR1 => per_paepaf,
      ADR2 => U1_per_fifo,
      ADR3 => oe_3_OBUF,
      O => oe_3_OBUF_GROM
    );
  oe_3_OBUF_XUSED : X_BUF
    port map (
      I => oe_3_OBUF_FROM,
      O => oe_3_OBUF
    );
  oe_3_OBUF_YUSED : X_BUF
    port map (
      I => oe_3_OBUF_GROM,
      O => ren_3_OBUF
    );
  U2_n0077 : X_LUT4
    generic map(
      INIT => X"7F40"
    )
    port map (
      ADR0 => U3_sel_read(2),
      ADR1 => etr_fifo,
      ADR2 => etr_paepaf,
      ADR3 => N44652,
      O => oe_2_OBUF_FROM
    );
  U2_ren_2_1 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => read,
      ADR1 => per_paepaf,
      ADR2 => U1_per_fifo,
      ADR3 => oe_2_OBUF,
      O => oe_2_OBUF_GROM
    );
  oe_2_OBUF_XUSED : X_BUF
    port map (
      I => oe_2_OBUF_FROM,
      O => oe_2_OBUF
    );
  oe_2_OBUF_YUSED : X_BUF
    port map (
      I => oe_2_OBUF_GROM,
      O => ren_2_OBUF
    );
  U2_n0078 : X_LUT4
    generic map(
      INIT => X"7F40"
    )
    port map (
      ADR0 => U3_sel_read(1),
      ADR1 => etr_fifo,
      ADR2 => etr_paepaf,
      ADR3 => N44648,
      O => oe_1_OBUF_FROM
    );
  U2_ren_1_1 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => read,
      ADR1 => per_paepaf,
      ADR2 => U1_per_fifo,
      ADR3 => oe_1_OBUF,
      O => oe_1_OBUF_GROM
    );
  oe_1_OBUF_XUSED : X_BUF
    port map (
      I => oe_1_OBUF_FROM,
      O => oe_1_OBUF
    );
  oe_1_OBUF_YUSED : X_BUF
    port map (
      I => oe_1_OBUF_GROM,
      O => ren_1_OBUF
    );
  U2_n0079 : X_LUT4
    generic map(
      INIT => X"7F40"
    )
    port map (
      ADR0 => U3_sel_read(0),
      ADR1 => etr_fifo,
      ADR2 => etr_paepaf,
      ADR3 => N44640,
      O => oe_0_OBUF_FROM
    );
  U2_ren_0_1 : X_LUT4
    generic map(
      INIT => X"FF40"
    )
    port map (
      ADR0 => read,
      ADR1 => per_paepaf,
      ADR2 => U1_per_fifo,
      ADR3 => oe_0_OBUF,
      O => oe_0_OBUF_GROM
    );
  oe_0_OBUF_XUSED : X_BUF
    port map (
      I => oe_0_OBUF_FROM,
      O => oe_0_OBUF
    );
  oe_0_OBUF_YUSED : X_BUF
    port map (
      I => oe_0_OBUF_GROM,
      O => ren_0_OBUF
    );
  sff_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => ff_2_IBUF,
      ADR1 => ff_1_IBUF,
      ADR2 => ff_0_IBUF,
      ADR3 => VCC,
      O => N37993_FROM
    );
  sff_934 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => ff_5_IBUF,
      ADR1 => ff_4_IBUF,
      ADR2 => ff_3_IBUF,
      ADR3 => N37993,
      O => N37993_GROM
    );
  N37993_XUSED : X_BUF
    port map (
      I => N37993_FROM,
      O => N37993
    );
  N37993_YUSED : X_BUF
    port map (
      I => N37993_GROM,
      O => sff_OBUF
    );
  U3_n0102_1_6 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd17,
      ADR1 => evid_1_IBUF,
      ADR2 => U3_state_FFd19,
      ADR3 => U3_header1_reg(1),
      O => CHOICE846_FROM
    );
  U3_n0102_0_6 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd17,
      ADR1 => evid_0_IBUF,
      ADR2 => U3_state_FFd19,
      ADR3 => U3_header1_reg(0),
      O => CHOICE846_GROM
    );
  CHOICE846_XUSED : X_BUF
    port map (
      I => CHOICE846_FROM,
      O => CHOICE846
    );
  CHOICE846_YUSED : X_BUF
    port map (
      I => CHOICE846_GROM,
      O => CHOICE922
    );
  U3_n0102_2_11 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => lock_5_IBUF,
      ADR1 => U3_sel_read(5),
      ADR2 => lock_4_IBUF,
      ADR3 => U3_sel_read(4),
      O => CHOICE897_GROM
    );
  CHOICE897_YUSED : X_BUF
    port map (
      I => CHOICE897_GROM,
      O => CHOICE897
    );
  U3_n0102_2_16 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => lock_3_IBUF,
      ADR1 => U3_sel_read(3),
      ADR2 => lock_2_IBUF,
      ADR3 => U3_sel_read(2),
      O => CHOICE900_FROM
    );
  U3_n0102_2_37 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => U3_N31636,
      ADR1 => CHOICE894,
      ADR2 => CHOICE897,
      ADR3 => CHOICE900,
      O => CHOICE900_GROM
    );
  CHOICE900_XUSED : X_BUF
    port map (
      I => CHOICE900_FROM,
      O => CHOICE900
    );
  CHOICE900_YUSED : X_BUF
    port map (
      I => CHOICE900_GROM,
      O => CHOICE903
    );
  U3_n00975_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd31,
      ADR1 => U3_state_FFd23,
      ADR2 => U3_state_FFd5,
      ADR3 => VCC,
      O => N44598_FROM
    );
  U3_n00975 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => tp_2_OBUF,
      ADR2 => U3_n0216,
      ADR3 => N44598,
      O => N44598_GROM
    );
  N44598_XUSED : X_BUF
    port map (
      I => N44598_FROM,
      O => N44598
    );
  N44598_YUSED : X_BUF
    port map (
      I => N44598_GROM,
      O => CHOICE570
    );
  U3_n0102_5_20 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd19,
      ADR1 => U3_header1_reg(5),
      ADR2 => U3_state_FFd16,
      ADR3 => U3_header2_reg(5),
      O => CHOICE632_FROM
    );
  U3_n0102_4_14 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd19,
      ADR1 => U3_header1_reg(4),
      ADR2 => U3_state_FFd16,
      ADR3 => U3_header2_reg(4),
      O => CHOICE632_GROM
    );
  CHOICE632_XUSED : X_BUF
    port map (
      I => CHOICE632_FROM,
      O => CHOICE632
    );
  CHOICE632_YUSED : X_BUF
    port map (
      I => CHOICE632_GROM,
      O => CHOICE795
    );
  U3_Ker31659_SW2 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => U3_state_FFd38,
      ADR1 => U3_state_FFd34,
      ADR2 => U3_state_FFd33,
      ADR3 => VCC,
      O => N44390_FROM
    );
  U3_Ker311701 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE679,
      ADR1 => CHOICE676,
      ADR2 => N44314,
      ADR3 => N44390,
      O => N44390_GROM
    );
  N44390_XUSED : X_BUF
    port map (
      I => N44390_FROM,
      O => N44390
    );
  N44390_YUSED : X_BUF
    port map (
      I => N44390_GROM,
      O => U3_N31172
    );
  U3_n0102_5_34 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE629,
      ADR1 => CHOICE632,
      ADR2 => CHOICE635,
      ADR3 => VCC,
      O => CHOICE637_FROM
    );
  U3_n0102_5_100 : X_LUT4
    generic map(
      INIT => X"FFF8"
    )
    port map (
      ADR0 => U3_N31636,
      ADR1 => N44384,
      ADR2 => U3_state_FFd36_In,
      ADR3 => CHOICE637,
      O => CHOICE637_GROM
    );
  CHOICE637_XUSED : X_BUF
    port map (
      I => CHOICE637_FROM,
      O => CHOICE637
    );
  CHOICE637_YUSED : X_BUF
    port map (
      I => CHOICE637_GROM,
      O => CHOICE651
    );
  U3_n0102_6_14 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_state_FFd19,
      ADR1 => U3_header1_reg(6),
      ADR2 => U3_state_FFd16,
      ADR3 => U3_header2_reg(6),
      O => CHOICE813_FROM
    );
  U3_n0102_6_17 : X_LUT4
    generic map(
      INIT => X"FEAA"
    )
    port map (
      ADR0 => CHOICE813,
      ADR1 => U3_state_FFd34,
      ADR2 => U3_state_FFd33,
      ADR3 => tp_2_OBUF,
      O => CHOICE813_GROM
    );
  CHOICE813_XUSED : X_BUF
    port map (
      I => CHOICE813_FROM,
      O => CHOICE813
    );
  CHOICE813_YUSED : X_BUF
    port map (
      I => CHOICE813_GROM,
      O => CHOICE814
    );
  U3_n0102_5_48 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_evid_mis(1),
      ADR1 => U3_sel_read(1),
      ADR2 => U3_evid_mis(0),
      ADR3 => U3_sel_read(0),
      O => CHOICE640_GROM
    );
  CHOICE640_YUSED : X_BUF
    port map (
      I => CHOICE640_GROM,
      O => CHOICE640
    );
  U3_n0102_5_58 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => U3_evid_mis(3),
      ADR1 => U3_sel_read(3),
      ADR2 => U3_evid_mis(2),
      ADR3 => U3_sel_read(2),
      O => CHOICE646_FROM
    );
  U3_n0102_5_79_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => CHOICE640,
      ADR1 => CHOICE643,
      ADR2 => CHOICE646,
      ADR3 => VCC,
      O => CHOICE646_GROM
    );
  CHOICE646_XUSED : X_BUF
    port map (
      I => CHOICE646_FROM,
      O => CHOICE646
    );
  CHOICE646_YUSED : X_BUF
    port map (
      I => CHOICE646_GROM,
      O => N44384
    );
  evid_0_IMUX : X_BUF
    port map (
      I => evid_0_IBUF_24,
      O => evid_0_IBUF
    );
  evid_0_IBUF_935 : X_BUF
    port map (
      I => evid(0),
      O => evid_0_IBUF_24
    );
  doneout_LOGIC_ONE_936 : X_ONE
    port map (
      O => doneout_LOGIC_ONE
    );
  doneout_OBUF_937 : X_TRI
    port map (
      I => doneout_OUTMUX,
      CTL => doneout_ENABLE,
      O => doneout
    );
  doneout_ENABLEINV : X_INV
    port map (
      I => doneout_TORGTS,
      O => doneout_ENABLE
    );
  doneout_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => doneout_TORGTS
    );
  doneout_OUTMUX_938 : X_BUF
    port map (
      I => doneout_OBUF,
      O => doneout_OUTMUX
    );
  evid_1_IMUX : X_BUF
    port map (
      I => evid_1_IBUF_25,
      O => evid_1_IBUF
    );
  evid_1_IBUF_939 : X_BUF
    port map (
      I => evid(1),
      O => evid_1_IBUF_25
    );
  evid_2_IMUX : X_BUF
    port map (
      I => evid_2_IBUF_26,
      O => evid_2_IBUF
    );
  evid_2_IBUF_940 : X_BUF
    port map (
      I => evid(2),
      O => evid_2_IBUF_26
    );
  evid_3_IMUX : X_BUF
    port map (
      I => evid_3_IBUF_27,
      O => evid_3_IBUF
    );
  evid_3_IBUF_941 : X_BUF
    port map (
      I => evid(3),
      O => evid_3_IBUF_27
    );
  evid_4_IMUX : X_BUF
    port map (
      I => evid_4_IBUF_28,
      O => evid_4_IBUF
    );
  evid_4_IBUF_942 : X_BUF
    port map (
      I => evid(4),
      O => evid_4_IBUF_28
    );
  evid_5_IMUX : X_BUF
    port map (
      I => evid_5_IBUF_29,
      O => evid_5_IBUF
    );
  evid_5_IBUF_943 : X_BUF
    port map (
      I => evid(5),
      O => evid_5_IBUF_29
    );
  evid_6_IMUX : X_BUF
    port map (
      I => evid_6_IBUF_30,
      O => evid_6_IBUF
    );
  evid_6_IBUF_944 : X_BUF
    port map (
      I => evid(6),
      O => evid_6_IBUF_30
    );
  evid_7_IMUX : X_BUF
    port map (
      I => evid_7_IBUF_31,
      O => evid_7_IBUF
    );
  evid_7_IBUF_945 : X_BUF
    port map (
      I => evid(7),
      O => evid_7_IBUF_31
    );
  evid_8_IMUX : X_BUF
    port map (
      I => evid_8_IBUF_32,
      O => evid_8_IBUF
    );
  evid_8_IBUF_946 : X_BUF
    port map (
      I => evid(8),
      O => evid_8_IBUF_32
    );
  evid_9_IMUX : X_BUF
    port map (
      I => evid_9_IBUF_33,
      O => evid_9_IBUF
    );
  evid_9_IBUF_947 : X_BUF
    port map (
      I => evid(9),
      O => evid_9_IBUF_33
    );
  sff_OBUF_948 : X_TRI
    port map (
      I => sff_OUTMUX,
      CTL => sff_ENABLE,
      O => sff
    );
  sff_ENABLEINV : X_INV
    port map (
      I => sff_TORGTS,
      O => sff_ENABLE
    );
  sff_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => sff_TORGTS
    );
  sff_OUTMUX_949 : X_BUF
    port map (
      I => sff_OBUF,
      O => sff_OUTMUX
    );
  dout_0_OBUFT : X_TRI
    port map (
      I => dout_0_OUTMUX,
      CTL => dout_0_ENABLE,
      O => dout(0)
    );
  dout_0_ENABLEINV : X_INV
    port map (
      I => dout_0_TORGTS,
      O => dout_0_ENABLE
    );
  dout_0_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_0_TDATANOT,
      O => dout_0_TORGTS
    );
  dout_0_OUTMUX_950 : X_BUF
    port map (
      I => s_data_reg(0),
      O => dout_0_OUTMUX
    );
  dout_0_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_0_TDATANOT
    );
  dout_0_OMUX : X_BUF
    port map (
      I => U3_s_data(0),
      O => dout_0_OD
    );
  dout_1_OBUFT : X_TRI
    port map (
      I => dout_1_OUTMUX,
      CTL => dout_1_ENABLE,
      O => dout(1)
    );
  dout_1_ENABLEINV : X_INV
    port map (
      I => dout_1_TORGTS,
      O => dout_1_ENABLE
    );
  dout_1_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_1_TDATANOT,
      O => dout_1_TORGTS
    );
  dout_1_OUTMUX_951 : X_BUF
    port map (
      I => s_data_reg(1),
      O => dout_1_OUTMUX
    );
  dout_1_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_1_TDATANOT
    );
  dout_1_OMUX : X_BUF
    port map (
      I => U3_s_data(1),
      O => dout_1_OD
    );
  dout_2_OBUFT : X_TRI
    port map (
      I => dout_2_OUTMUX,
      CTL => dout_2_ENABLE,
      O => dout(2)
    );
  dout_2_ENABLEINV : X_INV
    port map (
      I => dout_2_TORGTS,
      O => dout_2_ENABLE
    );
  dout_2_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_2_TDATANOT,
      O => dout_2_TORGTS
    );
  dout_2_OUTMUX_952 : X_BUF
    port map (
      I => s_data_reg(2),
      O => dout_2_OUTMUX
    );
  dout_2_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_2_TDATANOT
    );
  dout_2_OMUX : X_BUF
    port map (
      I => U3_s_data(2),
      O => dout_2_OD
    );
  dout_3_OBUFT : X_TRI
    port map (
      I => dout_3_OUTMUX,
      CTL => dout_3_ENABLE,
      O => dout(3)
    );
  dout_3_ENABLEINV : X_INV
    port map (
      I => dout_3_TORGTS,
      O => dout_3_ENABLE
    );
  dout_3_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_3_TDATANOT,
      O => dout_3_TORGTS
    );
  dout_3_OUTMUX_953 : X_BUF
    port map (
      I => s_data_reg(3),
      O => dout_3_OUTMUX
    );
  dout_3_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_3_TDATANOT
    );
  dout_3_OMUX : X_BUF
    port map (
      I => U3_s_data(3),
      O => dout_3_OD
    );
  evid_10_IMUX : X_BUF
    port map (
      I => evid_10_IBUF_34,
      O => evid_10_IBUF
    );
  evid_10_IBUF_954 : X_BUF
    port map (
      I => evid(10),
      O => evid_10_IBUF_34
    );
  dout_4_OBUFT : X_TRI
    port map (
      I => dout_4_OUTMUX,
      CTL => dout_4_ENABLE,
      O => dout(4)
    );
  dout_4_ENABLEINV : X_INV
    port map (
      I => dout_4_TORGTS,
      O => dout_4_ENABLE
    );
  dout_4_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_4_TDATANOT,
      O => dout_4_TORGTS
    );
  dout_4_OUTMUX_955 : X_BUF
    port map (
      I => s_data_reg(4),
      O => dout_4_OUTMUX
    );
  dout_4_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_4_TDATANOT
    );
  dout_4_OMUX : X_BUF
    port map (
      I => U3_s_data(4),
      O => dout_4_OD
    );
  evid_11_IMUX : X_BUF
    port map (
      I => evid_11_IBUF_35,
      O => evid_11_IBUF
    );
  evid_11_IBUF_956 : X_BUF
    port map (
      I => evid(11),
      O => evid_11_IBUF_35
    );
  dout_5_OBUFT : X_TRI
    port map (
      I => dout_5_OUTMUX,
      CTL => dout_5_ENABLE,
      O => dout(5)
    );
  dout_5_ENABLEINV : X_INV
    port map (
      I => dout_5_TORGTS,
      O => dout_5_ENABLE
    );
  dout_5_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_5_TDATANOT,
      O => dout_5_TORGTS
    );
  dout_5_OUTMUX_957 : X_BUF
    port map (
      I => s_data_reg(5),
      O => dout_5_OUTMUX
    );
  dout_5_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_5_TDATANOT
    );
  dout_5_OMUX : X_BUF
    port map (
      I => U3_s_data(5),
      O => dout_5_OD
    );
  dout_6_OBUFT : X_TRI
    port map (
      I => dout_6_OUTMUX,
      CTL => dout_6_ENABLE,
      O => dout(6)
    );
  dout_6_ENABLEINV : X_INV
    port map (
      I => dout_6_TORGTS,
      O => dout_6_ENABLE
    );
  dout_6_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_6_TDATANOT,
      O => dout_6_TORGTS
    );
  dout_6_OUTMUX_958 : X_BUF
    port map (
      I => s_data_reg(6),
      O => dout_6_OUTMUX
    );
  dout_6_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_6_TDATANOT
    );
  dout_6_OMUX : X_BUF
    port map (
      I => U3_s_data(6),
      O => dout_6_OD
    );
  dout_7_OBUFT : X_TRI
    port map (
      I => dout_7_OUTMUX,
      CTL => dout_7_ENABLE,
      O => dout(7)
    );
  dout_7_ENABLEINV : X_INV
    port map (
      I => dout_7_TORGTS,
      O => dout_7_ENABLE
    );
  dout_7_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_7_TDATANOT,
      O => dout_7_TORGTS
    );
  dout_7_OUTMUX_959 : X_BUF
    port map (
      I => s_data_reg(7),
      O => dout_7_OUTMUX
    );
  dout_7_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_7_TDATANOT
    );
  dout_7_OMUX : X_BUF
    port map (
      I => U3_s_data(7),
      O => dout_7_OD
    );
  dout_8_OBUFT : X_TRI
    port map (
      I => dout_8_OUTMUX,
      CTL => dout_8_ENABLE,
      O => dout(8)
    );
  dout_8_ENABLEINV : X_INV
    port map (
      I => dout_8_TORGTS,
      O => dout_8_ENABLE
    );
  dout_8_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_8_TDATANOT,
      O => dout_8_TORGTS
    );
  dout_8_OUTMUX_960 : X_BUF
    port map (
      I => s_data_reg(8),
      O => dout_8_OUTMUX
    );
  dout_8_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_8_TDATANOT
    );
  dout_8_OMUX : X_BUF
    port map (
      I => U3_s_data(8),
      O => dout_8_OD
    );
  dout_9_OBUFT : X_TRI
    port map (
      I => dout_9_OUTMUX,
      CTL => dout_9_ENABLE,
      O => dout(9)
    );
  dout_9_ENABLEINV : X_INV
    port map (
      I => dout_9_TORGTS,
      O => dout_9_ENABLE
    );
  dout_9_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_9_TDATANOT,
      O => dout_9_TORGTS
    );
  dout_9_OUTMUX_961 : X_BUF
    port map (
      I => s_data_reg(9),
      O => dout_9_OUTMUX
    );
  dout_9_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_9_TDATANOT
    );
  dout_9_OMUX : X_BUF
    port map (
      I => U3_s_data(9),
      O => dout_9_OD
    );
  UDDL5 : X_TRI
    port map (
      I => locked_p_OUTMUX,
      CTL => locked_p_ENABLE,
      O => locked_p
    );
  locked_p_ENABLEINV : X_INV
    port map (
      I => locked_p_TORGTS,
      O => locked_p_ENABLE
    );
  locked_p_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => locked_p_TORGTS
    );
  locked_p_OUTMUX_962 : X_BUF
    port map (
      I => LOCKED,
      O => locked_p_OUTMUX
    );
  hasul_0_OBUF_963 : X_TRI
    port map (
      I => hasul_0_OUTMUX,
      CTL => hasul_0_ENABLE,
      O => hasul(0)
    );
  hasul_0_ENABLEINV : X_INV
    port map (
      I => hasul_0_TORGTS,
      O => hasul_0_ENABLE
    );
  hasul_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hasul_0_TORGTS
    );
  hasul_0_OUTMUX_964 : X_BUF
    port map (
      I => hasul_0_OBUF,
      O => hasul_0_OUTMUX
    );
  hasul_1_OBUF_965 : X_TRI
    port map (
      I => hasul_1_OUTMUX,
      CTL => hasul_1_ENABLE,
      O => hasul(1)
    );
  hasul_1_ENABLEINV : X_INV
    port map (
      I => hasul_1_TORGTS,
      O => hasul_1_ENABLE
    );
  hasul_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hasul_1_TORGTS
    );
  hasul_1_OUTMUX_966 : X_BUF
    port map (
      I => hasul_1_OBUF,
      O => hasul_1_OUTMUX
    );
  hasul_2_OBUF_967 : X_TRI
    port map (
      I => hasul_2_OUTMUX,
      CTL => hasul_2_ENABLE,
      O => hasul(2)
    );
  hasul_2_ENABLEINV : X_INV
    port map (
      I => hasul_2_TORGTS,
      O => hasul_2_ENABLE
    );
  hasul_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hasul_2_TORGTS
    );
  hasul_2_OUTMUX_968 : X_BUF
    port map (
      I => hasul_2_OBUF,
      O => hasul_2_OUTMUX
    );
  dout_10_OBUFT : X_TRI
    port map (
      I => dout_10_OUTMUX,
      CTL => dout_10_ENABLE,
      O => dout(10)
    );
  dout_10_ENABLEINV : X_INV
    port map (
      I => dout_10_TORGTS,
      O => dout_10_ENABLE
    );
  dout_10_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_10_TDATANOT,
      O => dout_10_TORGTS
    );
  dout_10_OUTMUX_969 : X_BUF
    port map (
      I => s_data_reg(10),
      O => dout_10_OUTMUX
    );
  dout_10_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_10_TDATANOT
    );
  dout_10_OMUX : X_BUF
    port map (
      I => U3_s_data(10),
      O => dout_10_OD
    );
  hasul_3_OBUF_970 : X_TRI
    port map (
      I => hasul_3_OUTMUX,
      CTL => hasul_3_ENABLE,
      O => hasul(3)
    );
  hasul_3_ENABLEINV : X_INV
    port map (
      I => hasul_3_TORGTS,
      O => hasul_3_ENABLE
    );
  hasul_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hasul_3_TORGTS
    );
  hasul_3_OUTMUX_971 : X_BUF
    port map (
      I => hasul_3_OBUF,
      O => hasul_3_OUTMUX
    );
  dout_11_OBUFT : X_TRI
    port map (
      I => dout_11_OUTMUX,
      CTL => dout_11_ENABLE,
      O => dout(11)
    );
  dout_11_ENABLEINV : X_INV
    port map (
      I => dout_11_TORGTS,
      O => dout_11_ENABLE
    );
  dout_11_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_11_TDATANOT,
      O => dout_11_TORGTS
    );
  dout_11_OUTMUX_972 : X_BUF
    port map (
      I => s_data_reg(11),
      O => dout_11_OUTMUX
    );
  dout_11_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_11_TDATANOT
    );
  dout_11_OMUX : X_BUF
    port map (
      I => U3_s_data(11),
      O => dout_11_OD
    );
  hasul_4_OBUF_973 : X_TRI
    port map (
      I => hasul_4_OUTMUX,
      CTL => hasul_4_ENABLE,
      O => hasul(4)
    );
  hasul_4_ENABLEINV : X_INV
    port map (
      I => hasul_4_TORGTS,
      O => hasul_4_ENABLE
    );
  hasul_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hasul_4_TORGTS
    );
  hasul_4_OUTMUX_974 : X_BUF
    port map (
      I => hasul_4_OBUF,
      O => hasul_4_OUTMUX
    );
  dout_12_OBUFT : X_TRI
    port map (
      I => dout_12_OUTMUX,
      CTL => dout_12_ENABLE,
      O => dout(12)
    );
  dout_12_ENABLEINV : X_INV
    port map (
      I => dout_12_TORGTS,
      O => dout_12_ENABLE
    );
  dout_12_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_12_TDATANOT,
      O => dout_12_TORGTS
    );
  dout_12_OUTMUX_975 : X_BUF
    port map (
      I => s_data_reg(12),
      O => dout_12_OUTMUX
    );
  dout_12_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_12_TDATANOT
    );
  dout_12_OMUX : X_BUF
    port map (
      I => U3_s_data(12),
      O => dout_12_OD
    );
  hasul_5_OBUF_976 : X_TRI
    port map (
      I => hasul_5_OUTMUX,
      CTL => hasul_5_ENABLE,
      O => hasul(5)
    );
  hasul_5_ENABLEINV : X_INV
    port map (
      I => hasul_5_TORGTS,
      O => hasul_5_ENABLE
    );
  hasul_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => hasul_5_TORGTS
    );
  hasul_5_OUTMUX_977 : X_BUF
    port map (
      I => hasul_5_OBUF,
      O => hasul_5_OUTMUX
    );
  dout_13_OBUFT : X_TRI
    port map (
      I => dout_13_OUTMUX,
      CTL => dout_13_ENABLE,
      O => dout(13)
    );
  dout_13_ENABLEINV : X_INV
    port map (
      I => dout_13_TORGTS,
      O => dout_13_ENABLE
    );
  dout_13_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_13_TDATANOT,
      O => dout_13_TORGTS
    );
  dout_13_OUTMUX_978 : X_BUF
    port map (
      I => s_data_reg(13),
      O => dout_13_OUTMUX
    );
  dout_13_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_13_TDATANOT
    );
  dout_13_OMUX : X_BUF
    port map (
      I => U3_s_data(13),
      O => dout_13_OD
    );
  dout_14_OBUFT : X_TRI
    port map (
      I => dout_14_OUTMUX,
      CTL => dout_14_ENABLE,
      O => dout(14)
    );
  dout_14_ENABLEINV : X_INV
    port map (
      I => dout_14_TORGTS,
      O => dout_14_ENABLE
    );
  dout_14_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_14_TDATANOT,
      O => dout_14_TORGTS
    );
  dout_14_OUTMUX_979 : X_BUF
    port map (
      I => s_data_reg(14),
      O => dout_14_OUTMUX
    );
  dout_14_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_14_TDATANOT
    );
  dout_14_OMUX : X_BUF
    port map (
      I => U3_s_data(14),
      O => dout_14_OD
    );
  dout_15_OBUFT : X_TRI
    port map (
      I => dout_15_OUTMUX,
      CTL => dout_15_ENABLE,
      O => dout(15)
    );
  dout_15_ENABLEINV : X_INV
    port map (
      I => dout_15_TORGTS,
      O => dout_15_ENABLE
    );
  dout_15_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => dout_15_TDATANOT,
      O => dout_15_TORGTS
    );
  dout_15_OUTMUX_980 : X_BUF
    port map (
      I => s_data_reg(15),
      O => dout_15_OUTMUX
    );
  dout_15_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => dout_15_TDATANOT
    );
  dout_15_OMUX : X_BUF
    port map (
      I => U3_s_data(15),
      O => dout_15_OD
    );
  tp_0_OBUF : X_TRI
    port map (
      I => tp_0_OUTMUX,
      CTL => tp_0_ENABLE,
      O => tp(0)
    );
  tp_0_ENABLEINV : X_INV
    port map (
      I => tp_0_TORGTS,
      O => tp_0_ENABLE
    );
  tp_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => tp_0_TORGTS
    );
  tp_0_OUTMUX_981 : X_BUF
    port map (
      I => U3_lives_in,
      O => tp_0_OUTMUX
    );
  tp_1_OBUF : X_TRI
    port map (
      I => tp_1_OUTMUX,
      CTL => tp_1_ENABLE,
      O => tp(1)
    );
  tp_1_ENABLEINV : X_INV
    port map (
      I => tp_1_TORGTS,
      O => tp_1_ENABLE
    );
  tp_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => tp_1_TORGTS
    );
  tp_1_OUTMUX_982 : X_BUF
    port map (
      I => U3_ros_done,
      O => tp_1_OUTMUX
    );
  tp_2_OBUF_983 : X_TRI
    port map (
      I => tp_2_OUTMUX,
      CTL => tp_2_ENABLE,
      O => tp(2)
    );
  tp_2_ENABLEINV : X_INV
    port map (
      I => tp_2_TORGTS,
      O => tp_2_ENABLE
    );
  tp_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => tp_2_TORGTS
    );
  tp_2_OUTMUX_984 : X_BUF
    port map (
      I => tp_2_OBUF,
      O => tp_2_OUTMUX
    );
  tp_3_OBUF_985 : X_TRI
    port map (
      I => tp_3_OUTMUX,
      CTL => tp_3_ENABLE,
      O => tp(3)
    );
  tp_3_ENABLEINV : X_INV
    port map (
      I => tp_3_TORGTS,
      O => tp_3_ENABLE
    );
  tp_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => tp_3_TORGTS
    );
  tp_3_OUTMUX_986 : X_BUF
    port map (
      I => tp_3_OBUF,
      O => tp_3_OUTMUX
    );
  wclkena_p_OBUF : X_TRI
    port map (
      I => wclkena_p_OUTMUX,
      CTL => wclkena_p_ENABLE,
      O => wclkena_p
    );
  wclkena_p_ENABLEINV : X_INV
    port map (
      I => wclkena_p_TORGTS,
      O => wclkena_p_ENABLE
    );
  wclkena_p_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => wclkena_p_TORGTS
    );
  wclkena_p_OUTMUX_987 : X_BUF
    port map (
      I => U2_q1,
      O => wclkena_p_OUTMUX
    );
  fout_0_IMUX : X_BUF
    port map (
      I => fout_0_IBUF_36,
      O => fout_0_IBUF
    );
  fout_0_IBUF_988 : X_BUF
    port map (
      I => fout(0),
      O => fout_0_IBUF_36
    );
  fout_1_IMUX : X_BUF
    port map (
      I => fout_1_IBUF_37,
      O => fout_1_IBUF
    );
  fout_1_IBUF_989 : X_BUF
    port map (
      I => fout(1),
      O => fout_1_IBUF_37
    );
  fout_2_IMUX : X_BUF
    port map (
      I => fout_2_IBUF_38,
      O => fout_2_IBUF
    );
  fout_2_IBUF_990 : X_BUF
    port map (
      I => fout(2),
      O => fout_2_IBUF_38
    );
  fout_3_IMUX : X_BUF
    port map (
      I => fout_3_IBUF_39,
      O => fout_3_IBUF
    );
  fout_3_IBUF_991 : X_BUF
    port map (
      I => fout(3),
      O => fout_3_IBUF_39
    );
  fout_4_IMUX : X_BUF
    port map (
      I => fout_4_IBUF_40,
      O => fout_4_IBUF
    );
  fout_4_IBUF_992 : X_BUF
    port map (
      I => fout(4),
      O => fout_4_IBUF_40
    );
  fout_5_IMUX : X_BUF
    port map (
      I => fout_5_IBUF_41,
      O => fout_5_IBUF
    );
  fout_5_IBUF_993 : X_BUF
    port map (
      I => fout(5),
      O => fout_5_IBUF_41
    );
  fout_6_IMUX : X_BUF
    port map (
      I => fout_6_IBUF_42,
      O => fout_6_IBUF
    );
  fout_6_IBUF_994 : X_BUF
    port map (
      I => fout(6),
      O => fout_6_IBUF_42
    );
  fout_7_IMUX : X_BUF
    port map (
      I => fout_7_IBUF_43,
      O => fout_7_IBUF
    );
  fout_7_IBUF_995 : X_BUF
    port map (
      I => fout(7),
      O => fout_7_IBUF_43
    );
  fout_8_IMUX : X_BUF
    port map (
      I => fout_8_IBUF_44,
      O => fout_8_IBUF
    );
  fout_8_IBUF_996 : X_BUF
    port map (
      I => fout(8),
      O => fout_8_IBUF_44
    );
  fout_9_IMUX : X_BUF
    port map (
      I => fout_9_IBUF_45,
      O => fout_9_IBUF
    );
  fout_9_IBUF_997 : X_BUF
    port map (
      I => fout(9),
      O => fout_9_IBUF_45
    );
  lock_0_IMUX : X_BUF
    port map (
      I => lock_0_IBUF_46,
      O => lock_0_IBUF
    );
  lock_0_IBUF_998 : X_BUF
    port map (
      I => lock(0),
      O => lock_0_IBUF_46
    );
  lock_1_IMUX : X_BUF
    port map (
      I => lock_1_IBUF_47,
      O => lock_1_IBUF
    );
  lock_1_IBUF_999 : X_BUF
    port map (
      I => lock(1),
      O => lock_1_IBUF_47
    );
  lock_2_IMUX : X_BUF
    port map (
      I => lock_2_IBUF_48,
      O => lock_2_IBUF
    );
  lock_2_IBUF_1000 : X_BUF
    port map (
      I => lock(2),
      O => lock_2_IBUF_48
    );
  lock_3_IMUX : X_BUF
    port map (
      I => lock_3_IBUF_49,
      O => lock_3_IBUF
    );
  lock_3_IBUF_1001 : X_BUF
    port map (
      I => lock(3),
      O => lock_3_IBUF_49
    );
  lock_4_IMUX : X_BUF
    port map (
      I => lock_4_IBUF_50,
      O => lock_4_IBUF
    );
  lock_4_IBUF_1002 : X_BUF
    port map (
      I => lock(4),
      O => lock_4_IBUF_50
    );
  lock_5_IMUX : X_BUF
    port map (
      I => lock_5_IBUF_51,
      O => lock_5_IBUF
    );
  lock_5_IBUF_1003 : X_BUF
    port map (
      I => lock(5),
      O => lock_5_IBUF_51
    );
  led_0_OBUF_1004 : X_TRI
    port map (
      I => led_0_OUTMUX,
      CTL => led_0_ENABLE,
      O => led(0)
    );
  led_0_ENABLEINV : X_INV
    port map (
      I => led_0_TORGTS,
      O => led_0_ENABLE
    );
  led_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => led_0_TORGTS
    );
  led_0_OUTMUX_1005 : X_BUF
    port map (
      I => led_0_OBUF,
      O => led_0_OUTMUX
    );
  led_1_OBUF : X_TRI
    port map (
      I => led_1_OUTMUX,
      CTL => led_1_ENABLE,
      O => led(1)
    );
  led_1_ENABLEINV : X_INV
    port map (
      I => led_1_TORGTS,
      O => led_1_ENABLE
    );
  led_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => led_1_TORGTS
    );
  led_1_OUTMUX_1006 : X_BUF
    port map (
      I => led_1_ODNOT,
      O => led_1_OUTMUX
    );
  led_1_OMUX : X_INV
    port map (
      I => ULED2_q2,
      O => led_1_ODNOT
    );
  recoff_p_OBUF_1007 : X_TRI
    port map (
      I => recoff_p_OUTMUX,
      CTL => recoff_p_ENABLE,
      O => recoff_p
    );
  recoff_p_ENABLEINV : X_INV
    port map (
      I => recoff_p_TORGTS,
      O => recoff_p_ENABLE
    );
  recoff_p_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => recoff_p_TORGTS
    );
  recoff_p_OUTMUX_1008 : X_BUF
    port map (
      I => recoff_p_OBUF,
      O => recoff_p_OUTMUX
    );
  etr_x_IMUX : X_BUF
    port map (
      I => etr_x_IBUF_52,
      O => etr_x_IBUF
    );
  etr_x_IBUF_1009 : X_BUF
    port map (
      I => etr_x,
      O => etr_x_IBUF_52
    );
  UDDL4 : X_TRI
    port map (
      I => clk20_p_OUTMUX,
      CTL => clk20_p_ENABLE,
      O => clk20_p
    );
  clk20_p_ENABLEINV : X_INV
    port map (
      I => clk20_p_TORGTS,
      O => clk20_p_ENABLE
    );
  clk20_p_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => clk20_p_TORGTS
    );
  clk20_p_OUTMUX_1010 : X_BUF
    port map (
      I => CLK20,
      O => clk20_p_OUTMUX
    );
  paf_0_IMUX : X_BUF
    port map (
      I => paf_0_IBUF_53,
      O => paf_0_IBUF
    );
  paf_0_IBUF_1011 : X_BUF
    port map (
      I => paf(0),
      O => paf_0_IBUF_53
    );
  paf_1_IMUX : X_BUF
    port map (
      I => paf_1_IBUF_54,
      O => paf_1_IBUF
    );
  paf_1_IBUF_1012 : X_BUF
    port map (
      I => paf(1),
      O => paf_1_IBUF_54
    );
  paf_2_IMUX : X_BUF
    port map (
      I => paf_2_IBUF_55,
      O => paf_2_IBUF
    );
  paf_2_IBUF_1013 : X_BUF
    port map (
      I => paf(2),
      O => paf_2_IBUF_55
    );
  paf_3_IMUX : X_BUF
    port map (
      I => paf_3_IBUF_56,
      O => paf_3_IBUF
    );
  paf_3_IBUF_1014 : X_BUF
    port map (
      I => paf(3),
      O => paf_3_IBUF_56
    );
  paf_4_IMUX : X_BUF
    port map (
      I => paf_4_IBUF_57,
      O => paf_4_IBUF
    );
  paf_4_IBUF_1015 : X_BUF
    port map (
      I => paf(4),
      O => paf_4_IBUF_57
    );
  paf_5_IMUX : X_BUF
    port map (
      I => paf_5_IBUF_58,
      O => paf_5_IBUF
    );
  paf_5_IBUF_1016 : X_BUF
    port map (
      I => paf(5),
      O => paf_5_IBUF_58
    );
  cs_IMUX : X_BUF
    port map (
      I => cs_IBUF_59,
      O => cs_IBUF
    );
  cs_IBUF_1017 : X_BUF
    port map (
      I => cs,
      O => cs_IBUF_59
    );
  txena_p_OBUFT : X_TRI
    port map (
      I => txena_p_OUTMUX,
      CTL => txena_p_ENABLE,
      O => txena_p
    );
  txena_p_ENABLEINV : X_INV
    port map (
      I => txena_p_TORGTS,
      O => txena_p_ENABLE
    );
  txena_p_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => txena_p_TDATANOT,
      O => txena_p_TORGTS
    );
  txena_p_OUTMUX_1018 : X_BUF
    port map (
      I => txena_reg,
      O => txena_p_OUTMUX
    );
  txena_p_TRIMUX : X_INV
    port map (
      I => tp_2_OBUF,
      O => txena_p_TDATANOT
    );
  txena_p_OMUX : X_BUF
    port map (
      I => U3_txena_dir,
      O => txena_p_OD
    );
  fout_10_IMUX : X_BUF
    port map (
      I => fout_10_IBUF_60,
      O => fout_10_IBUF
    );
  fout_10_IBUF_1019 : X_BUF
    port map (
      I => fout(10),
      O => fout_10_IBUF_60
    );
  fout_11_IMUX : X_BUF
    port map (
      I => fout_11_IBUF_61,
      O => fout_11_IBUF
    );
  fout_11_IBUF_1020 : X_BUF
    port map (
      I => fout(11),
      O => fout_11_IBUF_61
    );
  fout_12_IMUX : X_BUF
    port map (
      I => fout_12_IBUF_62,
      O => fout_12_IBUF
    );
  fout_12_IBUF_1021 : X_BUF
    port map (
      I => fout(12),
      O => fout_12_IBUF_62
    );
  fout_13_IMUX : X_BUF
    port map (
      I => fout_13_IBUF_63,
      O => fout_13_IBUF
    );
  fout_13_IBUF_1022 : X_BUF
    port map (
      I => fout(13),
      O => fout_13_IBUF_63
    );
  fout_14_IMUX : X_BUF
    port map (
      I => fout_14_IBUF_64,
      O => fout_14_IBUF
    );
  fout_14_IBUF_1023 : X_BUF
    port map (
      I => fout(14),
      O => fout_14_IBUF_64
    );
  fout_15_IMUX : X_BUF
    port map (
      I => fout_15_IBUF_65,
      O => fout_15_IBUF
    );
  fout_15_IBUF_1024 : X_BUF
    port map (
      I => fout(15),
      O => fout_15_IBUF_65
    );
  valen_IMUX : X_BUF
    port map (
      I => valen_IBUF_66,
      O => valen_IBUF
    );
  valen_IBUF_1025 : X_BUF
    port map (
      I => valen,
      O => valen_IBUF_66
    );
  reset_IMUX : X_BUF
    port map (
      I => reset_IBUF_67,
      O => reset_IBUF
    );
  reset_IBUF_1026 : X_BUF
    port map (
      I => reset,
      O => reset_IBUF_67
    );
  par_0_IMUX : X_BUF
    port map (
      I => par_0_IBUF_68,
      O => par_0_IBUF
    );
  par_0_IBUF_1027 : X_BUF
    port map (
      I => par(0),
      O => par_0_IBUF_68
    );
  par_1_IMUX : X_BUF
    port map (
      I => par_1_IBUF_69,
      O => par_1_IBUF
    );
  par_1_IBUF_1028 : X_BUF
    port map (
      I => par(1),
      O => par_1_IBUF_69
    );
  token_IMUX : X_BUF
    port map (
      I => token_IBUF,
      O => tp_2_OBUF
    );
  token_IBUF_1029 : X_BUF
    port map (
      I => token,
      O => token_IBUF
    );
  cspare_0_IMUX : X_BUF
    port map (
      I => cspare_0_IBUF_70,
      O => cspare_0_IBUF
    );
  cspare_0_IBUF_1030 : X_BUF
    port map (
      I => cspare_0,
      O => cspare_0_IBUF_70
    );
  ren_0_OBUF_1031 : X_TRI
    port map (
      I => ren_0_OUTMUX,
      CTL => ren_0_ENABLE,
      O => ren(0)
    );
  ren_0_ENABLEINV : X_INV
    port map (
      I => ren_0_TORGTS,
      O => ren_0_ENABLE
    );
  ren_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ren_0_TORGTS
    );
  ren_0_OUTMUX_1032 : X_BUF
    port map (
      I => ren_0_OBUF,
      O => ren_0_OUTMUX
    );
  cspare_1_IMUX : X_BUF
    port map (
      I => cspare_1_IBUF_71,
      O => cspare_1_IBUF
    );
  cspare_1_IBUF_1033 : X_BUF
    port map (
      I => cspare_1,
      O => cspare_1_IBUF_71
    );
  ren_1_OBUF_1034 : X_TRI
    port map (
      I => ren_1_OUTMUX,
      CTL => ren_1_ENABLE,
      O => ren(1)
    );
  ren_1_ENABLEINV : X_INV
    port map (
      I => ren_1_TORGTS,
      O => ren_1_ENABLE
    );
  ren_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ren_1_TORGTS
    );
  ren_1_OUTMUX_1035 : X_BUF
    port map (
      I => ren_1_OBUF,
      O => ren_1_OUTMUX
    );
  ren_2_OBUF_1036 : X_TRI
    port map (
      I => ren_2_OUTMUX,
      CTL => ren_2_ENABLE,
      O => ren(2)
    );
  ren_2_ENABLEINV : X_INV
    port map (
      I => ren_2_TORGTS,
      O => ren_2_ENABLE
    );
  ren_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ren_2_TORGTS
    );
  ren_2_OUTMUX_1037 : X_BUF
    port map (
      I => ren_2_OBUF,
      O => ren_2_OUTMUX
    );
  ren_3_OBUF_1038 : X_TRI
    port map (
      I => ren_3_OUTMUX,
      CTL => ren_3_ENABLE,
      O => ren(3)
    );
  ren_3_ENABLEINV : X_INV
    port map (
      I => ren_3_TORGTS,
      O => ren_3_ENABLE
    );
  ren_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ren_3_TORGTS
    );
  ren_3_OUTMUX_1039 : X_BUF
    port map (
      I => ren_3_OBUF,
      O => ren_3_OUTMUX
    );
  ren_4_OBUF_1040 : X_TRI
    port map (
      I => ren_4_OUTMUX,
      CTL => ren_4_ENABLE,
      O => ren(4)
    );
  ren_4_ENABLEINV : X_INV
    port map (
      I => ren_4_TORGTS,
      O => ren_4_ENABLE
    );
  ren_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ren_4_TORGTS
    );
  ren_4_OUTMUX_1041 : X_BUF
    port map (
      I => ren_4_OBUF,
      O => ren_4_OUTMUX
    );
  ren_5_OBUF_1042 : X_TRI
    port map (
      I => ren_5_OUTMUX,
      CTL => ren_5_ENABLE,
      O => ren(5)
    );
  ren_5_ENABLEINV : X_INV
    port map (
      I => ren_5_TORGTS,
      O => ren_5_ENABLE
    );
  ren_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ren_5_TORGTS
    );
  ren_5_OUTMUX_1043 : X_BUF
    port map (
      I => ren_5_OBUF,
      O => ren_5_OUTMUX
    );
  donein_IMUX : X_BUF
    port map (
      I => donein_IBUF_72,
      O => donein_IBUF
    );
  donein_IBUF_1044 : X_BUF
    port map (
      I => donein,
      O => donein_IBUF_72
    );
  db_10_IOBUF_OBUFT : X_TRI
    port map (
      I => db_10_OUTMUX,
      CTL => db_10_ENABLE,
      O => db(10)
    );
  db_10_ENABLEINV : X_INV
    port map (
      I => db_10_TORGTS,
      O => db_10_ENABLE
    );
  db_10_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_10_TORGTS
    );
  db_10_OUTMUX_1045 : X_BUF
    port map (
      I => db_out(10),
      O => db_10_OUTMUX
    );
  db_10_IMUX : X_BUF
    port map (
      I => db_10_IBUF,
      O => N44092
    );
  db_10_IOBUF_IBUF : X_BUF
    port map (
      I => db(10),
      O => db_10_IBUF
    );
  db_11_IOBUF_OBUFT : X_TRI
    port map (
      I => db_11_OUTMUX,
      CTL => db_11_ENABLE,
      O => db(11)
    );
  db_11_ENABLEINV : X_INV
    port map (
      I => db_11_TORGTS,
      O => db_11_ENABLE
    );
  db_11_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_11_TORGTS
    );
  db_11_OUTMUX_1046 : X_BUF
    port map (
      I => db_out(11),
      O => db_11_OUTMUX
    );
  db_11_IMUX : X_BUF
    port map (
      I => db_11_IBUF,
      O => N44094
    );
  db_11_IOBUF_IBUF : X_BUF
    port map (
      I => db(11),
      O => db_11_IBUF
    );
  db_12_IOBUF_OBUFT : X_TRI
    port map (
      I => db_12_OUTMUX,
      CTL => db_12_ENABLE,
      O => db(12)
    );
  db_12_ENABLEINV : X_INV
    port map (
      I => db_12_TORGTS,
      O => db_12_ENABLE
    );
  db_12_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_12_TORGTS
    );
  db_12_OUTMUX_1047 : X_BUF
    port map (
      I => db_out(12),
      O => db_12_OUTMUX
    );
  db_12_IMUX : X_BUF
    port map (
      I => db_12_IBUF,
      O => N44096
    );
  db_12_IOBUF_IBUF : X_BUF
    port map (
      I => db(12),
      O => db_12_IBUF
    );
  db_13_IOBUF_OBUFT : X_TRI
    port map (
      I => db_13_OUTMUX,
      CTL => db_13_ENABLE,
      O => db(13)
    );
  db_13_ENABLEINV : X_INV
    port map (
      I => db_13_TORGTS,
      O => db_13_ENABLE
    );
  db_13_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_13_TORGTS
    );
  db_13_OUTMUX_1048 : X_BUF
    port map (
      I => db_out(13),
      O => db_13_OUTMUX
    );
  db_13_IMUX : X_BUF
    port map (
      I => db_13_IBUF,
      O => N44098
    );
  db_13_IOBUF_IBUF : X_BUF
    port map (
      I => db(13),
      O => db_13_IBUF
    );
  db_14_IOBUF_OBUFT : X_TRI
    port map (
      I => db_14_OUTMUX,
      CTL => db_14_ENABLE,
      O => db(14)
    );
  db_14_ENABLEINV : X_INV
    port map (
      I => db_14_TORGTS,
      O => db_14_ENABLE
    );
  db_14_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_14_TORGTS
    );
  db_14_OUTMUX_1049 : X_BUF
    port map (
      I => db_out(14),
      O => db_14_OUTMUX
    );
  db_14_IMUX : X_BUF
    port map (
      I => db_14_IBUF,
      O => N44100
    );
  db_14_IOBUF_IBUF : X_BUF
    port map (
      I => db(14),
      O => db_14_IBUF
    );
  db_15_IOBUF_OBUFT : X_TRI
    port map (
      I => db_15_OUTMUX,
      CTL => db_15_ENABLE,
      O => db(15)
    );
  db_15_ENABLEINV : X_INV
    port map (
      I => db_15_TORGTS,
      O => db_15_ENABLE
    );
  db_15_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I18_N1762,
      O => db_15_TORGTS
    );
  db_15_OUTMUX_1050 : X_BUF
    port map (
      I => db_out(15),
      O => db_15_OUTMUX
    );
  db_15_IMUX : X_BUF
    port map (
      I => db_15_IBUF,
      O => N44102
    );
  db_15_IOBUF_IBUF : X_BUF
    port map (
      I => db(15),
      O => db_15_IBUF
    );
  ceros_done_p_OBUF : X_TRI
    port map (
      I => ceros_done_p_OUTMUX,
      CTL => ceros_done_p_ENABLE,
      O => ceros_done_p
    );
  ceros_done_p_ENABLEINV : X_INV
    port map (
      I => ceros_done_p_TORGTS,
      O => ceros_done_p_ENABLE
    );
  ceros_done_p_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => ceros_done_p_TORGTS
    );
  ceros_done_p_OUTMUX_1051 : X_BUF
    port map (
      I => U3_ros_done,
      O => ceros_done_p_OUTMUX
    );
  fsen_OBUF : X_TRI
    port map (
      I => fsen_OUTMUX,
      CTL => fsen_ENABLE,
      O => fsen
    );
  fsen_ENABLEINV : X_INV
    port map (
      I => fsen_TORGTS,
      O => fsen_ENABLE
    );
  fsen_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => fsen_TORGTS
    );
  fsen_OUTMUX_1052 : X_BUF
    port map (
      I => U2_loadcnt(5),
      O => fsen_OUTMUX
    );
  fmrs_OBUF : X_TRI
    port map (
      I => fmrs_OUTMUX,
      CTL => fmrs_ENABLE,
      O => fmrs
    );
  fmrs_ENABLEINV : X_INV
    port map (
      I => fmrs_TORGTS,
      O => fmrs_ENABLE
    );
  fmrs_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => fmrs_TORGTS
    );
  fmrs_OUTMUX_1053 : X_BUF
    port map (
      I => fmrs_ODNOT,
      O => fmrs_OUTMUX
    );
  fmrs_OMUX : X_INV
    port map (
      I => U2_fwrg2,
      O => fmrs_ODNOT
    );
  lives_p_OBUF : X_TRI
    port map (
      I => lives_p_OUTMUX,
      CTL => lives_p_ENABLE,
      O => lives_p
    );
  lives_p_ENABLEINV : X_INV
    port map (
      I => lives_p_TORGTS,
      O => lives_p_ENABLE
    );
  lives_p_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => lives_p_TORGTS
    );
  lives_p_OUTMUX_1054 : X_BUF
    port map (
      I => U3_lives_in,
      O => lives_p_OUTMUX
    );
  fld_OBUF_1055 : X_TRI
    port map (
      I => fld_OUTMUX,
      CTL => fld_ENABLE,
      O => fld
    );
  fld_ENABLEINV : X_INV
    port map (
      I => fld_TORGTS,
      O => fld_ENABLE
    );
  fld_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => fld_TORGTS
    );
  fld_OUTMUX_1056 : X_BUF
    port map (
      I => fld_OBUF,
      O => fld_OUTMUX
    );
  fsi_OBUF_1057 : X_TRI
    port map (
      I => fsi_OUTMUX,
      CTL => fsi_ENABLE,
      O => fsi
    );
  fsi_ENABLEINV : X_INV
    port map (
      I => fsi_TORGTS,
      O => fsi_ENABLE
    );
  fsi_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => fsi_TORGTS
    );
  fsi_OUTMUX_1058 : X_BUF
    port map (
      I => fsi_OBUF,
      O => fsi_OUTMUX
    );
  U1_paf_counter_3_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_13,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_13_FFX_RST,
      O => U1_paf_counter_3(13)
    );
  U1_paf_counter_3_13_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_13_FFX_RST
    );
  U1_paf_counter_4_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_0,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_0_FFY_RST,
      O => U1_paf_counter_4(0)
    );
  U1_paf_counter_4_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_0_FFY_RST
    );
  U1_paf_counter_3_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_15,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_15_FFX_RST,
      O => U1_paf_counter_3(15)
    );
  U1_paf_counter_3_15_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_15_FFX_RST
    );
  U1_paf_counter_4_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_2,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_1_FFY_RST,
      O => U1_paf_counter_4(2)
    );
  U1_paf_counter_4_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_1_FFY_RST
    );
  U1_paf_counter_4_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_6,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_5_FFY_RST,
      O => U1_paf_counter_4(6)
    );
  U1_paf_counter_4_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_5_FFY_RST
    );
  U1_paf_counter_4_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_1,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_1_FFX_RST,
      O => U1_paf_counter_4(1)
    );
  U1_paf_counter_4_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_1_FFX_RST
    );
  U1_paf_counter_4_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_4,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_3_FFY_RST,
      O => U1_paf_counter_4(4)
    );
  U1_paf_counter_4_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_3_FFY_RST
    );
  U3_header1_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_1_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header1_reg_1_FFY_RST,
      O => U3_header1_reg(1)
    );
  U3_header1_reg_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header1_reg_1_FFY_RST
    );
  U3_header2_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_1_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_1_FFY_RST,
      O => U3_header2_reg(1)
    );
  U3_header2_reg_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_1_FFY_RST
    );
  U3_state_FFd11_1059 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd11_In_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd12_FFY_RST,
      O => U3_state_FFd11
    );
  U3_state_FFd12_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd12_FFY_RST
    );
  U3_state_FFd21_1060 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd21_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd22_FFY_RST,
      O => U3_state_FFd21
    );
  U3_state_FFd22_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd22_FFY_RST
    );
  U3_state_FFd12_1061 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd12_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd12_FFX_RST,
      O => U3_state_FFd12
    );
  U3_state_FFd12_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd12_FFX_RST
    );
  U3_state_FFd20_1062 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd20_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd24_FFY_RST,
      O => U3_state_FFd20
    );
  U3_state_FFd24_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd24_FFY_RST
    );
  U3_state_FFd24_1063 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd24_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd24_FFX_RST,
      O => U3_state_FFd24
    );
  U3_state_FFd24_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd24_FFX_RST
    );
  U1_timeout_value_11 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44094,
      CE => U1_n0009,
      CLK => CLK,
      SET => U1_timeout_value_11_FFY_SET,
      RST => GND,
      O => U1_timeout_value(11)
    );
  U1_timeout_value_11_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_timeout_value_11_FFY_SET
    );
  U3_time_out_1064 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0118,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_out_FFY_RST,
      O => U3_time_out
    );
  U3_time_out_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_out_FFY_RST
    );
  U1_fout_reg_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_10_IBUF_60,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_10_IFF_RST,
      O => U1_fout_reg(10)
    );
  fout_10_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_10_IFF_RST
    );
  U1_fout_reg_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_11_IBUF_61,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_11_IFF_RST,
      O => U1_fout_reg(11)
    );
  fout_11_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_11_IFF_RST
    );
  U1_fout_reg_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_12_IBUF_62,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_12_IFF_RST,
      O => U1_fout_reg(12)
    );
  fout_12_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_12_IFF_RST
    );
  U1_fout_reg_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_13_IBUF_63,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_13_IFF_RST,
      O => U1_fout_reg(13)
    );
  fout_13_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_13_IFF_RST
    );
  U1_fout_reg_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_14_IBUF_64,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_14_IFF_RST,
      O => U1_fout_reg(14)
    );
  fout_14_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_14_IFF_RST
    );
  U1_fout_reg_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_15_IBUF_65,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_15_IFF_RST,
      O => U1_fout_reg(15)
    );
  fout_15_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_15_IFF_RST
    );
  reset1_1065 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => reset_IBUF_67,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => reset_IFF_RST,
      O => reset1
    );
  reset_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => reset_IFF_RST
    );
  U2_byte_par_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0031_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_5_FFX_RST,
      O => U2_byte_par(5)
    );
  U2_byte_par_5_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_5_FFX_RST
    );
  U2_byte_par_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0035_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_1_FFX_RST,
      O => U2_byte_par(1)
    );
  U2_byte_par_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_1_FFX_RST
    );
  U2_byte_par_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0034_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_3_FFY_RST,
      O => U2_byte_par(2)
    );
  U2_byte_par_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_3_FFY_RST
    );
  U2_byte_par_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0033_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_3_FFX_RST,
      O => U2_byte_par(3)
    );
  U2_byte_par_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_3_FFX_RST
    );
  U2_byte_par_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0032_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_5_FFY_RST,
      O => U2_byte_par(4)
    );
  U2_byte_par_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_5_FFY_RST
    );
  U2_byte_par_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0030_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_7_FFY_RST,
      O => U2_byte_par(6)
    );
  U2_byte_par_7_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_byte_par_7_FFY_RST
    );
  U2_byte_par_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0029_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_7_FFX_RST,
      O => U2_byte_par(7)
    );
  U2_byte_par_7_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_byte_par_7_FFX_RST
    );
  U2_byte_par_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0027_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_9_FFX_RST,
      O => U2_byte_par(9)
    );
  U2_byte_par_9_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_byte_par_9_FFX_RST
    );
  U2_byte_par_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0028_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_9_FFY_RST,
      O => U2_byte_par(8)
    );
  U2_byte_par_9_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_byte_par_9_FFY_RST
    );
  blocked_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0048(0),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => blocked_0_FFY_RST,
      O => blocked(0)
    );
  blocked_0_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => blocked_0_FFY_RST
    );
  U1_warn_PAF_1066 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44076,
      CE => U1_n0016,
      CLK => CLK,
      SET => U1_warn_PAF_FFY_SET,
      RST => GND,
      O => U1_warn_PAF
    );
  U1_warn_PAF_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_warn_PAF_FFY_SET
    );
  blocked_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0048(1),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => blocked_1_FFY_RST,
      O => blocked(1)
    );
  blocked_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => blocked_1_FFY_RST
    );
  U1_paf_counter_1_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_11,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_11_FFX_RST,
      O => U1_paf_counter_1(11)
    );
  U1_paf_counter_1_11_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_11_FFX_RST
    );
  U1_paf_counter_2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_0,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_0_FFY_RST,
      O => U1_paf_counter_2(0)
    );
  U1_paf_counter_2_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_0_FFY_RST
    );
  U1_paf_counter_1_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_13,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_13_FFX_RST,
      O => U1_paf_counter_1(13)
    );
  U1_paf_counter_1_13_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_13_FFX_RST
    );
  U1_paf_counter_1_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_15,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_15_FFX_RST,
      O => U1_paf_counter_1(15)
    );
  U1_paf_counter_1_15_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_15_FFX_RST
    );
  U1_paf_counter_2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_2,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_1_FFY_RST,
      O => U1_paf_counter_2(2)
    );
  U1_paf_counter_2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_1_FFY_RST
    );
  U1_paf_counter_1_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_0,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_0_FFY_RST,
      O => U1_paf_counter_1(0)
    );
  U1_paf_counter_1_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_0_FFY_RST
    );
  U1_paf_counter_0_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_9,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_9_FFX_RST,
      O => U1_paf_counter_0(9)
    );
  U1_paf_counter_0_9_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_9_FFX_RST
    );
  U1_paf_counter_0_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_11,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_11_FFX_RST,
      O => U1_paf_counter_0(11)
    );
  U1_paf_counter_0_11_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_11_FFX_RST
    );
  U1_paf_counter_0_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_14,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_13_FFY_RST,
      O => U1_paf_counter_0(14)
    );
  U1_paf_counter_0_13_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_13_FFY_RST
    );
  U1_paf_counter_0_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_15,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_15_FFX_RST,
      O => U1_paf_counter_0(15)
    );
  U1_paf_counter_0_15_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_15_FFX_RST
    );
  U1_paf_counter_0_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_13,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_13_FFX_RST,
      O => U1_paf_counter_0(13)
    );
  U1_paf_counter_0_13_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_13_FFX_RST
    );
  U2_disparity_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_8,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_7_FFY_RST,
      O => U2_disparity(8)
    );
  U2_disparity_7_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_7_FFY_RST
    );
  U2_disparity_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_1,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_1_FFX_RST,
      O => U2_disparity(1)
    );
  U2_disparity_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_1_FFX_RST
    );
  U2_disparity_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_4,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_3_FFY_RST,
      O => U2_disparity(4)
    );
  U2_disparity_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_3_FFY_RST
    );
  U2_disparity_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_6,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_5_FFY_RST,
      O => U2_disparity(6)
    );
  U2_disparity_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_5_FFY_RST
    );
  U2_disparity_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_3,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_3_FFX_RST,
      O => U2_disparity(3)
    );
  U2_disparity_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_3_FFX_RST
    );
  U2_disparity_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_11,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_11_FFX_RST,
      O => U2_disparity(11)
    );
  U2_disparity_11_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_11_FFX_RST
    );
  U2_disparity_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_13,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_13_FFX_RST,
      O => U2_disparity(13)
    );
  U2_disparity_13_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_13_FFX_RST
    );
  U2_disparity_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_disparity_inst_sum_15,
      CE => U2_n0131,
      CLK => CLK,
      SET => GND,
      RST => U2_disparity_15_FFX_RST,
      O => U2_disparity(15)
    );
  U2_disparity_15_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_disparity_15_FFX_RST
    );
  U1_paf_counter_1_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_14,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_13_FFY_RST,
      O => U1_paf_counter_1(14)
    );
  U1_paf_counter_1_13_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_13_FFY_RST
    );
  U1_paf_counter_1_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_5,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_5_FFX_RST,
      O => U1_paf_counter_1(5)
    );
  U1_paf_counter_1_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_5_FFX_RST
    );
  U1_paf_counter_1_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_7,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_7_FFX_RST,
      O => U1_paf_counter_1(7)
    );
  U1_paf_counter_1_7_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_7_FFX_RST
    );
  U1_paf_counter_1_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_10,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_9_FFY_RST,
      O => U1_paf_counter_1(10)
    );
  U1_paf_counter_1_9_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_9_FFY_RST
    );
  U1_paf_counter_1_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_12,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_11_FFY_RST,
      O => U1_paf_counter_1(12)
    );
  U1_paf_counter_1_11_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_11_FFY_RST
    );
  U1_paf_counter_1_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_9,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_9_FFX_RST,
      O => U1_paf_counter_1(9)
    );
  U1_paf_counter_1_9_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_9_FFX_RST
    );
  U1_paf_counter_1_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_2,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_1_FFY_RST,
      O => U1_paf_counter_1(2)
    );
  U1_paf_counter_1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_1_FFY_RST
    );
  U1_paf_counter_1_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_8,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_7_FFY_RST,
      O => U1_paf_counter_1(8)
    );
  U1_paf_counter_1_7_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_7_FFY_RST
    );
  U1_paf_counter_1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_1,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_1_FFX_RST,
      O => U1_paf_counter_1(1)
    );
  U1_paf_counter_1_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_1_FFX_RST
    );
  U1_paf_counter_1_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_4,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_3_FFY_RST,
      O => U1_paf_counter_1(4)
    );
  U1_paf_counter_1_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_3_FFY_RST
    );
  U1_paf_counter_1_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_6,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_5_FFY_RST,
      O => U1_paf_counter_1(6)
    );
  U1_paf_counter_1_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_5_FFY_RST
    );
  U1_paf_counter_1_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_1_inst_sum_3,
      CE => U1_n0178,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_1_3_FFX_RST,
      O => U1_paf_counter_1(3)
    );
  U1_paf_counter_1_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_1_3_FFX_RST
    );
  U1_paf_counter_0_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_3,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_3_FFX_RST,
      O => U1_paf_counter_0(3)
    );
  U1_paf_counter_0_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_3_FFX_RST
    );
  U1_paf_counter_0_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_5,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_5_FFX_RST,
      O => U1_paf_counter_0(5)
    );
  U1_paf_counter_0_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_5_FFX_RST
    );
  U1_paf_counter_0_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_8,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_7_FFY_RST,
      O => U1_paf_counter_0(8)
    );
  U1_paf_counter_0_7_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_7_FFY_RST
    );
  U1_paf_counter_0_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_7,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_7_FFX_RST,
      O => U1_paf_counter_0(7)
    );
  U1_paf_counter_0_7_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_7_FFX_RST
    );
  U1_paf_counter_0_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_10,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_9_FFY_RST,
      O => U1_paf_counter_0(10)
    );
  U1_paf_counter_0_9_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_9_FFY_RST
    );
  U1_paf_counter_0_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_0_inst_sum_12,
      CE => U1_n0177,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_0_11_FFY_RST,
      O => U1_paf_counter_0(12)
    );
  U1_paf_counter_0_11_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_0_11_FFY_RST
    );
  U1_paf_counter_2_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_10,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_9_FFY_RST,
      O => U1_paf_counter_2(10)
    );
  U1_paf_counter_2_9_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_9_FFY_RST
    );
  U1_paf_counter_2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_1,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_1_FFX_RST,
      O => U1_paf_counter_2(1)
    );
  U1_paf_counter_2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_1_FFX_RST
    );
  U1_paf_counter_2_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_4,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_3_FFY_RST,
      O => U1_paf_counter_2(4)
    );
  U1_paf_counter_2_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_3_FFY_RST
    );
  U1_paf_counter_2_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_3,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_3_FFX_RST,
      O => U1_paf_counter_2(3)
    );
  U1_paf_counter_2_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_3_FFX_RST
    );
  U1_paf_counter_2_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_6,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_5_FFY_RST,
      O => U1_paf_counter_2(6)
    );
  U1_paf_counter_2_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_5_FFY_RST
    );
  U1_paf_counter_2_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_8,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_7_FFY_RST,
      O => U1_paf_counter_2(8)
    );
  U1_paf_counter_2_7_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_7_FFY_RST
    );
  U1_paf_counter_2_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_5,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_5_FFX_RST,
      O => U1_paf_counter_2(5)
    );
  U1_paf_counter_2_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_5_FFX_RST
    );
  U1_paf_counter_2_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_7,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_7_FFX_RST,
      O => U1_paf_counter_2(7)
    );
  U1_paf_counter_2_7_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_7_FFX_RST
    );
  U1_paf_counter_2_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_9,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_9_FFX_RST,
      O => U1_paf_counter_2(9)
    );
  U1_paf_counter_2_9_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_9_FFX_RST
    );
  U1_paf_counter_2_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_12,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_11_FFY_RST,
      O => U1_paf_counter_2(12)
    );
  U1_paf_counter_2_11_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_11_FFY_RST
    );
  U1_paf_counter_2_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_14,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_13_FFY_RST,
      O => U1_paf_counter_2(14)
    );
  U1_paf_counter_2_13_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_13_FFY_RST
    );
  U2_word_par_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_5_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_5_FFX_RST,
      O => U2_word_par(5)
    );
  U2_word_par_5_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_5_FFX_RST
    );
  U2_byte_par_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0008_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_27_FFX_RST,
      O => U2_byte_par(27)
    );
  U2_byte_par_27_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_27_FFX_RST
    );
  U2_byte_par_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0016_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_19_FFX_RST,
      O => U2_byte_par(19)
    );
  U2_byte_par_19_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_19_FFX_RST
    );
  U2_byte_par_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0017_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_19_FFY_RST,
      O => U2_byte_par(18)
    );
  U2_byte_par_19_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_19_FFY_RST
    );
  U2_word_par_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_7_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_7_FFX_RST,
      O => U2_word_par(7)
    );
  U2_word_par_7_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_7_FFX_RST
    );
  U2_word_par_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_6_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_7_FFY_RST,
      O => U2_word_par(6)
    );
  U2_word_par_7_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_7_FFY_RST
    );
  U2_byte_par_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0006_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_29_FFX_RST,
      O => U2_byte_par(29)
    );
  U2_byte_par_29_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_29_FFX_RST
    );
  U2_byte_par_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0007_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_29_FFY_RST,
      O => U2_byte_par(28)
    );
  U2_byte_par_29_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_29_FFY_RST
    );
  U2_word_par_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_9_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_9_FFX_RST,
      O => U2_word_par(9)
    );
  U2_word_par_9_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_9_FFX_RST
    );
  U2_word_par_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_8_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_9_FFY_RST,
      O => U2_word_par(8)
    );
  U2_word_par_9_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_9_FFY_RST
    );
  U3_header2_reg_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0112_10_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header2_reg_11_FFY_RST,
      O => U3_header2_reg(10)
    );
  U3_header2_reg_11_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header2_reg_11_FFY_RST
    );
  U1_paf_counter_3_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_7,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_7_FFX_RST,
      O => U1_paf_counter_3(7)
    );
  U1_paf_counter_3_7_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_3_7_FFX_RST
    );
  U1_paf_counter_3_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_12,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_11_FFY_RST,
      O => U1_paf_counter_3(12)
    );
  U1_paf_counter_3_11_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_11_FFY_RST
    );
  U1_paf_counter_3_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_11,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_11_FFX_RST,
      O => U1_paf_counter_3(11)
    );
  U1_paf_counter_3_11_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_11_FFX_RST
    );
  U1_paf_counter_3_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_14,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_13_FFY_RST,
      O => U1_paf_counter_3(14)
    );
  U1_paf_counter_3_13_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_13_FFY_RST
    );
  U1_paf_counter_2_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_11,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_11_FFX_RST,
      O => U1_paf_counter_2(11)
    );
  U1_paf_counter_2_11_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_11_FFX_RST
    );
  U1_paf_counter_3_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_0,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_0_FFY_RST,
      O => U1_paf_counter_3(0)
    );
  U1_paf_counter_3_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_0_FFY_RST
    );
  U1_paf_counter_2_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_13,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_13_FFX_RST,
      O => U1_paf_counter_2(13)
    );
  U1_paf_counter_2_13_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_13_FFX_RST
    );
  U1_paf_counter_2_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_2_inst_sum_15,
      CE => U1_n0179,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_2_15_FFX_RST,
      O => U1_paf_counter_2(15)
    );
  U1_paf_counter_2_15_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_2_15_FFX_RST
    );
  U1_paf_counter_3_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_2,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_1_FFY_RST,
      O => U1_paf_counter_3(2)
    );
  U1_paf_counter_3_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_1_FFY_RST
    );
  U1_paf_counter_3_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_4,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_3_FFY_RST,
      O => U1_paf_counter_3(4)
    );
  U1_paf_counter_3_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_3_FFY_RST
    );
  U3_read_fifo_dir_1067 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0098111_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_read_fifo_dir_FFY_RST,
      O => U3_read_fifo_dir
    );
  U3_read_fifo_dir_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_read_fifo_dir_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_read_fifo_dir_FFY_RST
    );
  U3_s_data_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_6_67_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_6_FFY_RST,
      O => U3_s_data(6)
    );
  U3_s_data_6_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_6_FFY_RST
    );
  U3_state_FFd27_1_1068 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd27_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd27_1_FFX_RST,
      O => U3_state_FFd27_1
    );
  U3_state_FFd27_1_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd27_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd27_1_FFX_RST
    );
  U3_state_FFd29_1069 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd29_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd30_FFY_RST,
      O => U3_state_FFd29
    );
  U3_state_FFd30_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd30_FFY_RST
    );
  U3_state_FFd39_1070 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd39_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd40_FFY_RST,
      O => U3_state_FFd39
    );
  U3_state_FFd40_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd40_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd40_FFY_RST
    );
  U3_state_FFd30_1071 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd30_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd30_FFX_RST,
      O => U3_state_FFd30
    );
  U3_state_FFd30_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd30_FFX_RST
    );
  U3_state_FFd40_1072 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U3_state_FFd40_LOGIC_ZERO,
      CE => VCC,
      CLK => CLK,
      SET => U3_state_FFd40_FFX_SET,
      RST => GND,
      O => U3_state_FFd40
    );
  U3_state_FFd40_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => U3_state_FFd40_SRMUX_OUTPUTNOT,
      O => U3_state_FFd40_FFX_SET
    );
  U3_rob_id_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0096_2_28_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_rob_id_2_FFY_RST,
      O => U3_rob_id(2)
    );
  U3_rob_id_2_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_rob_id_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_rob_id_2_FFY_RST
    );
  U3_rob_id_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0096_3_14_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_rob_id_3_FFY_RST,
      O => U3_rob_id(3)
    );
  U3_rob_id_3_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_rob_id_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_rob_id_3_FFY_RST
    );
  U2_byte_par_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0026_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_11_FFY_RST,
      O => U2_byte_par(10)
    );
  U2_byte_par_11_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_11_FFY_RST
    );
  U1_paf_counter_3_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_1,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_1_FFX_RST,
      O => U1_paf_counter_3(1)
    );
  U1_paf_counter_3_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_1_FFX_RST
    );
  U1_paf_counter_3_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_3,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_3_FFX_RST,
      O => U1_paf_counter_3(3)
    );
  U1_paf_counter_3_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_3_FFX_RST
    );
  U1_paf_counter_3_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_6,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_5_FFY_RST,
      O => U1_paf_counter_3(6)
    );
  U1_paf_counter_3_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_5_FFY_RST
    );
  U1_paf_counter_3_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_5,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_5_FFX_RST,
      O => U1_paf_counter_3(5)
    );
  U1_paf_counter_3_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_5_FFX_RST
    );
  U1_paf_counter_3_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_8,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_7_FFY_RST,
      O => U1_paf_counter_3(8)
    );
  U1_paf_counter_3_7_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_3_7_FFY_RST
    );
  U1_paf_counter_3_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_10,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_10_FFY_RST,
      O => U1_paf_counter_3(10)
    );
  U1_paf_counter_3_10_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_counter_3_10_FFY_RST
    );
  U1_paf_counter_4_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_3,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_3_FFX_RST,
      O => U1_paf_counter_4(3)
    );
  U1_paf_counter_4_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_3_FFX_RST
    );
  U1_paf_counter_4_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_5,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_5_FFX_RST,
      O => U1_paf_counter_4(5)
    );
  U1_paf_counter_4_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_5_FFX_RST
    );
  U1_paf_counter_4_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_8,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_7_FFY_RST,
      O => U1_paf_counter_4(8)
    );
  U1_paf_counter_4_7_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_7_FFY_RST
    );
  U1_paf_counter_4_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_12,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_11_FFY_RST,
      O => U1_paf_counter_4(12)
    );
  U1_paf_counter_4_11_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_11_FFY_RST
    );
  U1_paf_counter_4_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_7,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_7_FFX_RST,
      O => U1_paf_counter_4(7)
    );
  U1_paf_counter_4_7_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_7_FFX_RST
    );
  U1_paf_counter_4_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_10,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_9_FFY_RST,
      O => U1_paf_counter_4(10)
    );
  U1_paf_counter_4_9_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_9_FFY_RST
    );
  U3_sel_read_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0109,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_sel_read_1_FFY_RST,
      O => U3_sel_read(1)
    );
  U3_sel_read_1_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_sel_read_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_sel_read_1_FFY_RST
    );
  U2_pae_paf_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_0_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_1_FFY_RST,
      O => U2_pae_paf_reg(0)
    );
  U2_pae_paf_reg_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_1_FFY_RST
    );
  U2_pae_paf_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_2_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_3_FFY_RST,
      O => U2_pae_paf_reg(2)
    );
  U2_pae_paf_reg_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_3_FFY_RST
    );
  U2_pae_paf_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_1_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_1_FFX_RST,
      O => U2_pae_paf_reg(1)
    );
  U2_pae_paf_reg_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_1_FFX_RST
    );
  U2_pae_paf_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_3_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_3_FFX_RST,
      O => U2_pae_paf_reg(3)
    );
  U2_pae_paf_reg_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_3_FFX_RST
    );
  U2_pae_paf_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_5_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_5_FFX_RST,
      O => U2_pae_paf_reg(5)
    );
  U2_pae_paf_reg_5_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_5_FFX_RST
    );
  U2_pae_paf_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_4_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_5_FFY_RST,
      O => U2_pae_paf_reg(4)
    );
  U2_pae_paf_reg_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_5_FFY_RST
    );
  U1_db_error2_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_11_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_11_FFY_RST,
      O => U1_db_error2(11)
    );
  U1_db_error2_11_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_11_FFY_RST
    );
  U2_pae_paf_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_6_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_7_FFY_RST,
      O => U2_pae_paf_reg(6)
    );
  U2_pae_paf_reg_7_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_7_FFY_RST
    );
  U1_paf_counter_5_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_2,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_1_FFY_RST,
      O => U1_paf_counter_5(2)
    );
  U1_paf_counter_5_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_1_FFY_RST
    );
  U1_paf_counter_5_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_8,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_7_FFY_RST,
      O => U1_paf_counter_5(8)
    );
  U1_paf_counter_5_7_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_7_FFY_RST
    );
  U1_paf_counter_5_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_1,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_1_FFX_RST,
      O => U1_paf_counter_5(1)
    );
  U1_paf_counter_5_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_1_FFX_RST
    );
  U1_paf_counter_5_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_4,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_3_FFY_RST,
      O => U1_paf_counter_5(4)
    );
  U1_paf_counter_5_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_3_FFY_RST
    );
  U1_paf_counter_5_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_6,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_5_FFY_RST,
      O => U1_paf_counter_5(6)
    );
  U1_paf_counter_5_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_5_FFY_RST
    );
  U3_maxw_reached_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0115_Result_1_1_O,
      CE => U3_n0240,
      CLK => CLK,
      SET => GND,
      RST => U3_maxw_reached_1_FFX_RST,
      O => U3_maxw_reached(1)
    );
  U3_maxw_reached_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_maxw_reached_1_FFX_RST
    );
  U3_s_data_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_2_109_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_2_FFY_RST,
      O => U3_s_data(2)
    );
  U3_s_data_2_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_2_FFY_RST
    );
  U3_s_data_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_3_66_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_3_FFY_RST,
      O => U3_s_data(3)
    );
  U3_s_data_3_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_3_FFY_RST
    );
  U3_s_data_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_4_71_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_4_FFY_RST,
      O => U3_s_data(4)
    );
  U3_s_data_4_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_4_FFY_RST
    );
  U3_maxw_reached_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0115_Result_0_1_O,
      CE => U3_n0240,
      CLK => CLK,
      SET => GND,
      RST => U3_maxw_reached_1_FFY_RST,
      O => U3_maxw_reached(0)
    );
  U3_maxw_reached_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_maxw_reached_1_FFY_RST
    );
  U3_maxw_reached_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0115_Result_2_1_O,
      CE => U3_n0240,
      CLK => CLK,
      SET => GND,
      RST => U3_maxw_reached_3_FFY_RST,
      O => U3_maxw_reached(2)
    );
  U3_maxw_reached_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_maxw_reached_3_FFY_RST
    );
  U3_maxw_reached_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0115_Result_3_1_O,
      CE => U3_n0240,
      CLK => CLK,
      SET => GND,
      RST => U3_maxw_reached_3_FFX_RST,
      O => U3_maxw_reached(3)
    );
  U3_maxw_reached_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_maxw_reached_3_FFX_RST
    );
  U3_maxw_reached_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0115_Result_4_1_O,
      CE => U3_n0240,
      CLK => CLK,
      SET => GND,
      RST => U3_maxw_reached_5_FFY_RST,
      O => U3_maxw_reached(4)
    );
  U3_maxw_reached_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_maxw_reached_5_FFY_RST
    );
  U1_hasunlock_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0013_Result_5_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_hasunlock_5_FFY_RST,
      O => U1_hasunlock(5)
    );
  U1_hasunlock_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_hasunlock_5_FFY_RST
    );
  U1_paf_counter_4_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_15,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_15_FFX_RST,
      O => U1_paf_counter_4(15)
    );
  U1_paf_counter_4_15_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_15_FFX_RST
    );
  U1_paf_counter_4_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_9,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_9_FFX_RST,
      O => U1_paf_counter_4(9)
    );
  U1_paf_counter_4_9_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_9_FFX_RST
    );
  U1_paf_counter_4_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_11,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_11_FFX_RST,
      O => U1_paf_counter_4(11)
    );
  U1_paf_counter_4_11_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_11_FFX_RST
    );
  U1_paf_counter_4_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_14,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_13_FFY_RST,
      O => U1_paf_counter_4(14)
    );
  U1_paf_counter_4_13_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_13_FFY_RST
    );
  U1_paf_counter_5_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_0,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_0_FFY_RST,
      O => U1_paf_counter_5(0)
    );
  U1_paf_counter_5_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_0_FFY_RST
    );
  U1_paf_counter_4_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_4_inst_sum_13,
      CE => U1_n0181,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_4_13_FFX_RST,
      O => U1_paf_counter_4(13)
    );
  U1_paf_counter_4_13_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_4_13_FFX_RST
    );
  U1_paf_counter_5_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_3,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_3_FFX_RST,
      O => U1_paf_counter_5(3)
    );
  U1_paf_counter_5_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_3_FFX_RST
    );
  U1_paf_counter_5_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_14,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_13_FFY_RST,
      O => U1_paf_counter_5(14)
    );
  U1_paf_counter_5_13_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_13_FFY_RST
    );
  U1_paf_counter_5_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_5,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_5_FFX_RST,
      O => U1_paf_counter_5(5)
    );
  U1_paf_counter_5_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_5_FFX_RST
    );
  U1_paf_counter_5_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_7,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_7_FFX_RST,
      O => U1_paf_counter_5(7)
    );
  U1_paf_counter_5_7_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_7_FFX_RST
    );
  U1_paf_counter_5_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_10,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_9_FFY_RST,
      O => U1_paf_counter_5(10)
    );
  U1_paf_counter_5_9_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_9_FFY_RST
    );
  U1_paf_counter_5_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_5_inst_sum_12,
      CE => U1_n0182,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_5_11_FFY_RST,
      O => U1_paf_counter_5(12)
    );
  U1_paf_counter_5_11_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_5_11_FFY_RST
    );
  U3_s_data_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_7_47_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_7_FFY_RST,
      O => U3_s_data(7)
    );
  U3_s_data_7_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_7_FFY_RST
    );
  U3_s_data_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_8_44_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_8_FFY_RST,
      O => U3_s_data(8)
    );
  U3_s_data_8_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_8_FFY_RST
    );
  U3_s_data_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_5_133_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_5_FFY_RST,
      O => U3_s_data(5)
    );
  U3_s_data_5_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_5_FFY_RST
    );
  U3_s_data_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_9_44_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_9_FFY_RST,
      O => U3_s_data(9)
    );
  U3_s_data_9_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_9_FFY_RST
    );
  U3_txena_dir_1073 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n009986_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_txena_dir_FFY_RST,
      O => U3_txena_dir
    );
  U3_txena_dir_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_txena_dir_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_txena_dir_FFY_RST
    );
  U3_s_data_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_1_83_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_1_FFY_RST,
      O => U3_s_data(1)
    );
  U3_s_data_1_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_1_FFY_RST
    );
  U3_s_data_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_0_129_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_0_FFY_RST,
      O => U3_s_data(0)
    );
  U3_s_data_0_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_0_FFY_RST
    );
  U3_evid_mis_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0116(5),
      CE => U3_n0241,
      CLK => CLK,
      SET => GND,
      RST => U3_evid_mis_5_FFX_RST,
      O => U3_evid_mis(5)
    );
  U3_evid_mis_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_evid_mis_5_FFX_RST
    );
  U3_state_FFd7_1074 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd7_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd8_FFY_RST,
      O => U3_state_FFd7
    );
  U3_state_FFd8_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd8_FFY_RST
    );
  U3_state_FFd8_1075 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd8_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd8_FFX_RST,
      O => U3_state_FFd8
    );
  U3_state_FFd8_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd8_FFX_RST
    );
  U3_time_counter_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0117(12),
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_12_FFY_RST,
      O => U3_time_counter(12)
    );
  U3_time_counter_12_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_12_FFY_RST
    );
  U2_q1_1076 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_n0040,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_q2_FFY_RST,
      O => U2_q1
    );
  U2_q2_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_q2_FFY_RST
    );
  U2_q3_1077 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_n0043,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_q4_FFY_RST,
      O => U2_q3
    );
  U2_q4_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_q4_FFY_RST
    );
  U2_q2_1078 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_n0042,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_q2_FFX_RST,
      O => U2_q2
    );
  U2_q2_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_q2_FFX_RST
    );
  U2_q4_1079 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_q3,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_q4_FFX_RST,
      O => U2_q4
    );
  U2_q4_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_q4_FFX_RST
    );
  U2_loadcnt_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_loadcnt_n0001(0),
      CE => U2_n0133,
      CLK => CLK,
      SET => GND,
      RST => U2_loadcnt_1_FFY_RST,
      O => U2_loadcnt(0)
    );
  U2_loadcnt_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_loadcnt_1_FFY_RST
    );
  U2_loadcnt_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_loadcnt_n0001(2),
      CE => U2_n0133,
      CLK => CLK,
      SET => GND,
      RST => U2_loadcnt_3_FFY_RST,
      O => U2_loadcnt(2)
    );
  U2_loadcnt_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_loadcnt_3_FFY_RST
    );
  U2_pae_paf_reg_9 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U2_Mmux_n0038_Result_9_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => U2_pae_paf_reg_9_FFX_SET,
      RST => GND,
      O => U2_pae_paf_reg(9)
    );
  U2_pae_paf_reg_9_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF_1,
      O => U2_pae_paf_reg_9_FFX_SET
    );
  U2_pae_paf_reg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_7_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_7_FFX_RST,
      O => U2_pae_paf_reg(7)
    );
  U2_pae_paf_reg_7_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_7_FFX_RST
    );
  U2_pae_paf_reg_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_8_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_9_FFY_RST,
      O => U2_pae_paf_reg(8)
    );
  U2_pae_paf_reg_9_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_9_FFY_RST
    );
  U3_error_evid_1080 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n009539_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_error_evid_FFY_RST,
      O => U3_error_evid
    );
  U3_error_evid_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_error_evid_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_error_evid_FFY_RST
    );
  U3_time_counter_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_10_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_11_FFY_RST,
      O => U3_time_counter(10)
    );
  U3_time_counter_11_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_11_FFY_RST
    );
  U3_maxw_reached_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0115_Result_5_1_O,
      CE => U3_n0240,
      CLK => CLK,
      SET => GND,
      RST => U3_maxw_reached_5_FFX_RST,
      O => U3_maxw_reached(5)
    );
  U3_maxw_reached_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_maxw_reached_5_FFX_RST
    );
  U2_word_par_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_10_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_11_FFY_RST,
      O => U2_word_par(10)
    );
  U2_word_par_11_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_11_FFY_RST
    );
  U2_word_par_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_12_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_13_FFY_RST,
      O => U2_word_par(12)
    );
  U2_word_par_13_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_13_FFY_RST
    );
  U2_word_par_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_13_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_13_FFX_RST,
      O => U2_word_par(13)
    );
  U2_word_par_13_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_13_FFX_RST
    );
  U2_word_par_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_11_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_11_FFX_RST,
      O => U2_word_par(11)
    );
  U2_word_par_11_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_11_FFX_RST
    );
  U2_word_par_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_15_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_15_FFX_RST,
      O => U2_word_par(15)
    );
  U2_word_par_15_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_15_FFX_RST
    );
  U2_word_par_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_14_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_15_FFY_RST,
      O => U2_word_par(14)
    );
  U2_word_par_15_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_15_FFY_RST
    );
  U3_time_counter_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_0_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_0_FFY_RST,
      O => U3_time_counter(0)
    );
  U3_time_counter_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_0_FFY_RST
    );
  U3_time_counter_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_2_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_3_FFY_RST,
      O => U3_time_counter(2)
    );
  U3_time_counter_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_3_FFY_RST
    );
  U3_time_counter_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_1_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_1_FFY_RST,
      O => U3_time_counter(1)
    );
  U3_time_counter_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_1_FFY_RST
    );
  U3_sel_read_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0110,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_sel_read_0_FFY_RST,
      O => U3_sel_read(0)
    );
  U3_sel_read_0_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_sel_read_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_sel_read_0_FFY_RST
    );
  U3_trail_1081 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n010420_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_trail_FFY_RST,
      O => U3_trail
    );
  U3_trail_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_trail_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_trail_FFY_RST
    );
  U3_sel_read_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n010539_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_sel_read_5_FFY_RST,
      O => U3_sel_read(5)
    );
  U3_sel_read_5_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_sel_read_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_sel_read_5_FFY_RST
    );
  U3_sel_read_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0106,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_sel_read_4_FFY_RST,
      O => U3_sel_read(4)
    );
  U3_sel_read_4_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_sel_read_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_sel_read_4_FFY_RST
    );
  U3_sel_read_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0108,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_sel_read_2_FFY_RST,
      O => U3_sel_read(2)
    );
  U3_sel_read_2_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_sel_read_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_sel_read_2_FFY_RST
    );
  U3_sel_read_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0107,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_sel_read_3_FFY_RST,
      O => U3_sel_read(3)
    );
  U3_sel_read_3_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_sel_read_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_sel_read_3_FFY_RST
    );
  U3_state_FFd3_1082 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd3_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd4_FFY_RST,
      O => U3_state_FFd3
    );
  U3_state_FFd4_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd4_FFY_RST
    );
  U3_timed_out_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0114_Result_3_1_O,
      CE => U3_n0239,
      CLK => CLK,
      SET => GND,
      RST => U3_timed_out_3_FFX_RST,
      O => U3_timed_out(3)
    );
  U3_timed_out_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_timed_out_3_FFX_RST
    );
  U3_timed_out_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0114_Result_4_1_O,
      CE => U3_n0239,
      CLK => CLK,
      SET => GND,
      RST => U3_timed_out_5_FFY_RST,
      O => U3_timed_out(4)
    );
  U3_timed_out_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_timed_out_5_FFY_RST
    );
  U3_timed_out_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0114_Result_5_1_O,
      CE => U3_n0239,
      CLK => CLK,
      SET => GND,
      RST => U3_timed_out_5_FFX_RST,
      O => U3_timed_out(5)
    );
  U3_timed_out_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_timed_out_5_FFX_RST
    );
  U1_ff_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0015_Result_5_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_ff_reg_5_FFY_RST,
      O => U1_ff_reg(5)
    );
  U1_ff_reg_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_ff_reg_5_FFY_RST
    );
  U3_state_FFd4_1083 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd4_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd4_FFX_RST,
      O => U3_state_FFd4
    );
  U3_state_FFd4_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd4_FFX_RST
    );
  U3_trailer_reg_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_12_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_13_FFY_RST,
      O => U3_trailer_reg_12_Q
    );
  U3_trailer_reg_13_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_13_FFY_RST
    );
  U3_trailer_reg_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_13_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_13_FFX_RST,
      O => U3_trailer_reg_13_Q
    );
  U3_trailer_reg_13_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_13_FFX_RST
    );
  U3_state_FFd5_1084 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd5_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd6_FFY_RST,
      O => U3_state_FFd5
    );
  U3_state_FFd6_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd6_FFY_RST
    );
  U3_trailer_reg_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_14_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_1_FFY_RST,
      O => U3_trailer_reg_14_Q
    );
  U3_trailer_reg_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_1_FFY_RST
    );
  U3_state_FFd6_1085 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd6_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd6_FFX_RST,
      O => U3_state_FFd6
    );
  U3_state_FFd6_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd6_FFX_RST
    );
  U3_time_counter_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_3_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_3_FFX_RST,
      O => U3_time_counter(3)
    );
  U3_time_counter_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_3_FFX_RST
    );
  U3_time_counter_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_5_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_5_FFX_RST,
      O => U3_time_counter(5)
    );
  U3_time_counter_5_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_5_FFX_RST
    );
  U3_time_counter_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_4_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_5_FFY_RST,
      O => U3_time_counter(4)
    );
  U3_time_counter_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_5_FFY_RST
    );
  U3_time_counter_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_7_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_7_FFX_RST,
      O => U3_time_counter(7)
    );
  U3_time_counter_7_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_7_FFX_RST
    );
  U3_time_counter_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_6_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_7_FFY_RST,
      O => U3_time_counter(6)
    );
  U3_time_counter_7_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_7_FFY_RST
    );
  U3_time_counter_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_9_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_9_FFX_RST,
      O => U3_time_counter(9)
    );
  U3_time_counter_9_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_9_FFX_RST
    );
  U3_time_counter_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_8_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_9_FFY_RST,
      O => U3_time_counter(8)
    );
  U3_time_counter_9_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_9_FFY_RST
    );
  U3_timed_out_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0114_Result_1_1_O,
      CE => U3_n0239,
      CLK => CLK,
      SET => GND,
      RST => U3_timed_out_1_FFX_RST,
      O => U3_timed_out(1)
    );
  U3_timed_out_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_timed_out_1_FFX_RST
    );
  U3_timed_out_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0114_Result_0_1_O,
      CE => U3_n0239,
      CLK => CLK,
      SET => GND,
      RST => U3_timed_out_1_FFY_RST,
      O => U3_timed_out(0)
    );
  U3_timed_out_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_timed_out_1_FFY_RST
    );
  U3_timed_out_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0114_Result_2_1_O,
      CE => U3_n0239,
      CLK => CLK,
      SET => GND,
      RST => U3_timed_out_3_FFY_RST,
      O => U3_timed_out(2)
    );
  U3_timed_out_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_timed_out_3_FFY_RST
    );
  U3_state_FFd22_1086 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd22_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd22_FFX_RST,
      O => U3_state_FFd22
    );
  U3_state_FFd22_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd22_FFX_RST
    );
  U3_state_FFd15_1087 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd15_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd16_FFY_RST,
      O => U3_state_FFd15
    );
  U3_state_FFd16_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd16_FFY_RST
    );
  U3_state_FFd16_1088 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd19,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd16_FFX_RST,
      O => U3_state_FFd16
    );
  U3_state_FFd16_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd16_FFX_RST
    );
  U3_trailer_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_0_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_0_FFY_RST,
      O => U3_trailer_reg_0_Q
    );
  U3_trailer_reg_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_0_FFY_RST
    );
  U3_state_FFd32_1089 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd32_In30_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd32_FFY_RST,
      O => U3_state_FFd32
    );
  U3_state_FFd32_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd32_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd32_FFY_RST
    );
  U3_state_FFd25_1090 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd25_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd26_FFY_RST,
      O => U3_state_FFd25
    );
  U3_state_FFd26_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd26_FFY_RST
    );
  U3_state_FFd26_1091 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd26_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd26_FFX_RST,
      O => U3_state_FFd26
    );
  U3_state_FFd26_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd26_FFX_RST
    );
  U3_state_FFd27_1092 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd27_1_GROM,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd27_1_FFY_RST,
      O => U3_state_FFd27
    );
  U3_state_FFd27_1_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd27_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd27_1_FFY_RST
    );
  U3_state_FFd28_1093 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd28_In20_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd28_FFY_RST,
      O => U3_state_FFd28
    );
  U3_state_FFd28_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd28_FFY_RST
    );
  U3_time_counter_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_Mmux_n0117_Result_11_1_O,
      CE => U3_n0242,
      CLK => CLK,
      SET => GND,
      RST => U3_time_counter_11_FFX_RST,
      O => U3_time_counter(11)
    );
  U3_time_counter_11_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_time_counter_11_FFX_RST
    );
  U3_ros_done_1094 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n009724_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_ros_done_FFY_RST,
      O => U3_ros_done
    );
  U3_ros_done_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_ros_done_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_ros_done_FFY_RST
    );
  U1_db_error3_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_11_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_11_FFY_RST,
      O => U1_db_error3(11)
    );
  U1_db_error3_11_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_11_FFY_RST
    );
  U3_word_count_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_0_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_0_FFY_RST,
      O => U3_word_count(0)
    );
  U3_word_count_0_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_0_FFY_RST
    );
  U3_word_count_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_1_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_1_FFY_RST,
      O => U3_word_count(1)
    );
  U3_word_count_1_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_1_FFY_RST
    );
  U3_trailer_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_1_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_1_FFX_RST,
      O => U3_trailer_reg_1_Q
    );
  U3_trailer_reg_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_1_FFX_RST
    );
  U3_state_FFd9_1095 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd9_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd10_FFY_RST,
      O => U3_state_FFd9
    );
  U3_state_FFd10_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd10_FFY_RST
    );
  U3_state_FFd10_1096 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd10_In1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd10_FFX_RST,
      O => U3_state_FFd10
    );
  U3_state_FFd10_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd10_FFX_RST
    );
  U1_hasunlock_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0013_Result_0_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_hasunlock_1_FFY_RST,
      O => U1_hasunlock(0)
    );
  U1_hasunlock_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_hasunlock_1_FFY_RST
    );
  U1_hasunlock_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0013_Result_1_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_hasunlock_1_FFX_RST,
      O => U1_hasunlock(1)
    );
  U1_hasunlock_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_hasunlock_1_FFX_RST
    );
  U1_hasunlock_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0013_Result_2_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_hasunlock_3_FFY_RST,
      O => U1_hasunlock(2)
    );
  U1_hasunlock_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_hasunlock_3_FFY_RST
    );
  U1_hasunlock_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0013_Result_3_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_hasunlock_3_FFX_RST,
      O => U1_hasunlock(3)
    );
  U1_hasunlock_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_hasunlock_3_FFX_RST
    );
  U1_hasunlock_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0013_Result_4_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_hasunlock_4_FFY_RST,
      O => U1_hasunlock(4)
    );
  U1_hasunlock_4_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_hasunlock_4_FFY_RST
    );
  U3_s_data_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_10_62_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_10_FFY_RST,
      O => U3_s_data(10)
    );
  U3_s_data_10_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_10_FFY_RST
    );
  U3_s_data_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0102_11_58_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_s_data_11_FFY_RST,
      O => U3_s_data(11)
    );
  U3_s_data_11_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_s_data_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_s_data_11_FFY_RST
    );
  U2_byte_par_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0024_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_13_FFY_RST,
      O => U2_byte_par(12)
    );
  U2_byte_par_13_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_13_FFY_RST
    );
  U2_byte_par_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0025_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_11_FFX_RST,
      O => U2_byte_par(11)
    );
  U2_byte_par_11_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_11_FFX_RST
    );
  U2_byte_par_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0023_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_13_FFX_RST,
      O => U2_byte_par(13)
    );
  U2_byte_par_13_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_13_FFX_RST
    );
  U2_byte_par_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0014_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_21_FFX_RST,
      O => U2_byte_par(21)
    );
  U2_byte_par_21_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_21_FFX_RST
    );
  U2_byte_par_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0015_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_21_FFY_RST,
      O => U2_byte_par(20)
    );
  U2_byte_par_21_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_21_FFY_RST
    );
  U2_word_par_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_0_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_1_FFY_RST,
      O => U2_word_par(0)
    );
  U2_word_par_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_1_FFY_RST
    );
  U2_word_par_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_1_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_1_FFX_RST,
      O => U2_word_par(1)
    );
  U2_word_par_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_1_FFX_RST
    );
  U2_byte_par_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0004_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_31_FFX_RST,
      O => U2_byte_par(31)
    );
  U2_byte_par_31_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_31_FFX_RST
    );
  U2_byte_par_30 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0005_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_31_FFY_RST,
      O => U2_byte_par(30)
    );
  U2_byte_par_31_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_31_FFY_RST
    );
  U2_byte_par_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0013_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_23_FFY_RST,
      O => U2_byte_par(22)
    );
  U2_byte_par_23_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_23_FFY_RST
    );
  U2_byte_par_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0022_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_15_FFY_RST,
      O => U2_byte_par(14)
    );
  U2_byte_par_15_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_15_FFY_RST
    );
  U2_byte_par_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0021_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_15_FFX_RST,
      O => U2_byte_par(15)
    );
  U2_byte_par_15_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_15_FFX_RST
    );
  U2_byte_par_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0012_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_23_FFX_RST,
      O => U2_byte_par(23)
    );
  U2_byte_par_23_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_23_FFX_RST
    );
  U2_word_par_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_3_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_3_FFX_RST,
      O => U2_word_par(3)
    );
  U2_word_par_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_3_FFX_RST
    );
  U2_word_par_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_2_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_3_FFY_RST,
      O => U2_word_par(2)
    );
  U2_word_par_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_3_FFY_RST
    );
  U2_byte_par_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0010_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_25_FFX_RST,
      O => U2_byte_par(25)
    );
  U2_byte_par_25_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_25_FFX_RST
    );
  U2_byte_par_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0011_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_25_FFY_RST,
      O => U2_byte_par(24)
    );
  U2_byte_par_25_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_25_FFY_RST
    );
  U2_byte_par_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0018_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_17_FFX_RST,
      O => U2_byte_par(17)
    );
  U2_byte_par_17_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_17_FFX_RST
    );
  U2_byte_par_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0019_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_17_FFY_RST,
      O => U2_byte_par(16)
    );
  U2_byte_par_17_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_17_FFY_RST
    );
  U2_word_par_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0002_Result_4_1_O,
      CE => U2_n0096,
      CLK => CLK,
      SET => GND,
      RST => U2_word_par_5_FFY_RST,
      O => U2_word_par(4)
    );
  U2_word_par_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_word_par_5_FFY_RST
    );
  U2_byte_par_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0009_Result1_O,
      CE => U2_n0097,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_27_FFY_RST,
      O => U2_byte_par(26)
    );
  U2_byte_par_27_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_27_FFY_RST
    );
  U3_trailer_reg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_7_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_7_FFX_RST,
      O => U3_trailer_reg_7_Q
    );
  U3_trailer_reg_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_7_FFX_RST
    );
  U3_trailer_reg_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0113_9_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_trailer_reg_9_FFX_RST,
      O => U3_trailer_reg_9_Q
    );
  U3_trailer_reg_9_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_trailer_reg_9_FFX_RST
    );
  U3_word_count_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_2_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_3_FFY_RST,
      O => U3_word_count(2)
    );
  U3_word_count_3_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_3_FFY_RST
    );
  U3_word_count_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_3_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_3_FFX_RST,
      O => U3_word_count(3)
    );
  U3_word_count_3_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_3_FFX_RST
    );
  U3_word_count_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_4_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_5_FFY_RST,
      O => U3_word_count(4)
    );
  U3_word_count_5_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_5_FFY_RST
    );
  U3_word_count_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_5_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_5_FFX_RST,
      O => U3_word_count(5)
    );
  U3_word_count_5_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_5_FFX_RST
    );
  U3_word_count_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_6_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_7_FFY_RST,
      O => U3_word_count(6)
    );
  U3_word_count_7_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_7_FFY_RST
    );
  U3_word_count_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_7_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_7_FFX_RST,
      O => U3_word_count(7)
    );
  U3_word_count_7_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_7_FFX_RST
    );
  U3_word_count_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0100_8_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_word_count_9_FFY_RST,
      O => U3_word_count(8)
    );
  U3_word_count_9_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_word_count_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_word_count_9_FFY_RST
    );
  U2_loadcnt_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U2_loadcnt_n0001(1),
      CE => U2_n0133,
      CLK => CLK,
      SET => U2_loadcnt_1_FFX_SET,
      RST => GND,
      O => U2_loadcnt(1)
    );
  U2_loadcnt_1_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF_1,
      O => U2_loadcnt_1_FFX_SET
    );
  U2_loadcnt_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U2_loadcnt_n0001(3),
      CE => U2_n0133,
      CLK => CLK,
      SET => U2_loadcnt_3_FFX_SET,
      RST => GND,
      O => U2_loadcnt(3)
    );
  U2_loadcnt_3_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF_1,
      O => U2_loadcnt_3_FFX_SET
    );
  U2_loadcnt_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_loadcnt_n0001(4),
      CE => U2_n0133,
      CLK => CLK,
      SET => GND,
      RST => U2_loadcnt_5_FFY_RST,
      O => U2_loadcnt(4)
    );
  U2_loadcnt_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_loadcnt_5_FFY_RST
    );
  U2_loadcnt_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U2_loadcnt_n0001(5),
      CE => U2_n0133,
      CLK => CLK,
      SET => U2_loadcnt_5_FFX_SET,
      RST => GND,
      O => U2_loadcnt(5)
    );
  U2_loadcnt_5_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF_1,
      O => U2_loadcnt_5_FFX_SET
    );
  U1_per_fifo_aux_2_1097 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U1_per_fifo_aux,
      CE => VCC,
      CLK => CLK,
      SET => U1_per_fifo_aux_2_FFY_SET,
      RST => GND,
      O => U1_per_fifo_aux_2
    );
  U1_per_fifo_aux_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF,
      O => U1_per_fifo_aux_2_FFY_SET
    );
  U1_per_paepaf_reg_1098 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U1_per_paepaf_reg_GROM,
      CE => VCC,
      CLK => CLK,
      SET => U1_per_paepaf_reg_FFY_SET,
      RST => GND,
      O => U1_per_paepaf_reg
    );
  U1_per_paepaf_reg_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF,
      O => U1_per_paepaf_reg_FFY_SET
    );
  U3_state_FFd14_1099 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd14_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd14_FFY_RST,
      O => U3_state_FFd14
    );
  U3_state_FFd14_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd14_FFY_RST
    );
  U3_state_FFd31_1100 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd31_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd31_FFY_RST,
      O => U3_state_FFd31
    );
  U3_state_FFd31_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd31_FFY_RST
    );
  U3_state_FFd35_1101 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd35_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd35_FFY_RST,
      O => U3_state_FFd35
    );
  U3_state_FFd35_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd35_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd35_FFY_RST
    );
  U2_pae_paf_reg_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_15_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_15_FFX_RST,
      O => U2_pae_paf_reg(15)
    );
  U2_pae_paf_reg_15_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_15_FFX_RST
    );
  U2_pae_paf_reg_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_17_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_17_FFX_RST,
      O => U2_pae_paf_reg(17)
    );
  U2_pae_paf_reg_17_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_17_FFX_RST
    );
  U2_pae_paf_reg_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_18_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_18_FFY_RST,
      O => U2_pae_paf_reg(18)
    );
  U2_pae_paf_reg_18_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_18_FFY_RST
    );
  U2_pae_paf_reg_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_19_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_19_FFY_RST,
      O => U2_pae_paf_reg(19)
    );
  U2_pae_paf_reg_19_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_19_FFY_RST
    );
  U3_rob_id_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0096_0_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_rob_id_0_FFY_RST,
      O => U3_rob_id(0)
    );
  U3_rob_id_0_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_rob_id_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_rob_id_0_FFY_RST
    );
  U3_state_FFd13_1102 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd13_FROM,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd13_FFX_RST,
      O => U3_state_FFd13
    );
  U3_state_FFd13_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd13_FFX_RST
    );
  U2_byte_par_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0036_Result1_O,
      CE => U2_n0114,
      CLK => CLK,
      SET => GND,
      RST => U2_byte_par_1_FFY_RST,
      O => U2_byte_par(0)
    );
  U2_byte_par_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => U2_byte_par_1_FFY_RST
    );
  U3_header1_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_5_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header1_reg_5_FFX_RST,
      O => U3_header1_reg(5)
    );
  U3_header1_reg_5_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header1_reg_5_FFX_RST
    );
  U2_pae_paf_reg_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_13_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_13_FFX_RST,
      O => U2_pae_paf_reg(13)
    );
  U2_pae_paf_reg_13_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_13_FFX_RST
    );
  U3_header1_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_6_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header1_reg_7_FFY_RST,
      O => U3_header1_reg(6)
    );
  U3_header1_reg_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header1_reg_7_FFY_RST
    );
  U3_header1_reg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0111_7_1_O,
      CE => valen_IBUF,
      CLK => CLK,
      SET => GND,
      RST => U3_header1_reg_7_FFX_RST,
      O => U3_header1_reg(7)
    );
  U3_header1_reg_7_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => U3_header1_reg_7_FFX_RST
    );
  U2_pae_paf_reg_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_11_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_11_FFX_RST,
      O => U2_pae_paf_reg(11)
    );
  U2_pae_paf_reg_11_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_11_FFX_RST
    );
  U2_pae_paf_reg_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_10_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_11_FFY_RST,
      O => U2_pae_paf_reg(10)
    );
  U2_pae_paf_reg_11_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_11_FFY_RST
    );
  U2_pae_paf_reg_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_12_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_13_FFY_RST,
      O => U2_pae_paf_reg(12)
    );
  U2_pae_paf_reg_13_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_13_FFY_RST
    );
  U2_pae_paf_reg_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_16_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_17_FFY_RST,
      O => U2_pae_paf_reg(16)
    );
  U2_pae_paf_reg_17_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_17_FFY_RST
    );
  U2_pae_paf_reg_20 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U2_Mmux_n0038_Result_20_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => U2_pae_paf_reg_21_FFY_SET,
      RST => GND,
      O => U2_pae_paf_reg(20)
    );
  U2_pae_paf_reg_21_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF_1,
      O => U2_pae_paf_reg_21_FFY_SET
    );
  U2_pae_paf_reg_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_21_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_21_FFX_RST,
      O => U2_pae_paf_reg(21)
    );
  U2_pae_paf_reg_21_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_21_FFX_RST
    );
  U2_pae_paf_reg_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_Mmux_n0038_Result_14_1_O,
      CE => U2_n0132,
      CLK => CLK,
      SET => GND,
      RST => U2_pae_paf_reg_15_FFY_RST,
      O => U2_pae_paf_reg(14)
    );
  U2_pae_paf_reg_15_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_pae_paf_reg_15_FFY_RST
    );
  blocked_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0048(2),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => blocked_2_FFY_RST,
      O => blocked(2)
    );
  blocked_2_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => blocked_2_FFY_RST
    );
  U1_resynch_FF_1103 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44078,
      CE => U1_n0016,
      CLK => CLK,
      SET => U1_resynch_FF_FFY_SET,
      RST => GND,
      O => U1_resynch_FF
    );
  U1_resynch_FF_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_resynch_FF_FFY_SET
    );
  U1_paf_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_n0014(0),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_reg_1_FFY_RST,
      O => U1_paf_reg(0)
    );
  U1_paf_reg_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_reg_1_FFY_RST
    );
  U1_paf_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_n0014(1),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_reg_1_FFX_RST,
      O => U1_paf_reg(1)
    );
  U1_paf_reg_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_reg_1_FFX_RST
    );
  U1_paf_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_n0014(2),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_reg_3_FFY_RST,
      O => U1_paf_reg(2)
    );
  U1_paf_reg_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_reg_3_FFY_RST
    );
  U1_paf_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_n0014(3),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_reg_3_FFX_RST,
      O => U1_paf_reg(3)
    );
  U1_paf_reg_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_reg_3_FFX_RST
    );
  U1_paf_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_n0014(4),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_reg_4_FFY_RST,
      O => U1_paf_reg(4)
    );
  U1_paf_reg_4_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_reg_4_FFY_RST
    );
  U3_state_FFd19_1104 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd19_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd19_FFY_RST,
      O => U3_state_FFd19
    );
  U3_state_FFd19_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd19_FFY_RST
    );
  U1_db_error1_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_10_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_10_FFY_RST,
      O => U1_db_error1(10)
    );
  U1_db_error3_10_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_10_FFY_RST
    );
  U1_db_error3_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_10_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_10_FFX_RST,
      O => U1_db_error3(10)
    );
  U1_db_error3_10_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_10_FFX_RST
    );
  U1_db_error2_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_10_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_10_FFY_RST,
      O => U1_db_error2(10)
    );
  U1_db_error2_10_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_10_FFY_RST
    );
  U3_state_FFd36_1105 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd36_GROM,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd36_FFY_RST,
      O => U3_state_FFd36
    );
  U3_state_FFd36_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd36_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd36_FFY_RST
    );
  U1_db_error3_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_9_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_9_FFX_RST,
      O => U1_db_error3(9)
    );
  U1_db_error3_9_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_9_FFX_RST
    );
  U3_evid_mis_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0116(2),
      CE => U3_n0241,
      CLK => CLK,
      SET => GND,
      RST => U3_evid_mis_3_FFY_RST,
      O => U3_evid_mis(2)
    );
  U3_evid_mis_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_evid_mis_3_FFY_RST
    );
  U3_evid_mis_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0116(0),
      CE => U3_n0241,
      CLK => CLK,
      SET => GND,
      RST => U3_evid_mis_1_FFY_RST,
      O => U3_evid_mis(0)
    );
  U3_evid_mis_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_evid_mis_1_FFY_RST
    );
  U3_evid_mis_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0116(3),
      CE => U3_n0241,
      CLK => CLK,
      SET => GND,
      RST => U3_evid_mis_3_FFX_RST,
      O => U3_evid_mis(3)
    );
  U3_evid_mis_3_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_evid_mis_3_FFX_RST
    );
  U3_evid_mis_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0116(1),
      CE => U3_n0241,
      CLK => CLK,
      SET => GND,
      RST => U3_evid_mis_1_FFX_RST,
      O => U3_evid_mis(1)
    );
  U3_evid_mis_1_FFX_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_evid_mis_1_FFX_RST
    );
  U3_evid_mis_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0116(4),
      CE => U3_n0241,
      CLK => CLK,
      SET => GND,
      RST => U3_evid_mis_5_FFY_RST,
      O => U3_evid_mis(4)
    );
  U3_evid_mis_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U3_evid_mis_5_FFY_RST
    );
  U1_db_error3_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_1_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_1_FFX_RST,
      O => U1_db_error3(1)
    );
  U1_db_error3_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_1_FFX_RST
    );
  U1_db_error2_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_6_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_7_FFY_RST,
      O => U1_db_error2(6)
    );
  U1_db_error2_7_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_7_FFY_RST
    );
  U1_db_error2_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_7_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_7_FFX_RST,
      O => U1_db_error2(7)
    );
  U1_db_error2_7_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_7_FFX_RST
    );
  U1_db_error3_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_2_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_3_FFY_RST,
      O => U1_db_error3(2)
    );
  U1_db_error3_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_3_FFY_RST
    );
  U1_db_error3_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_3_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_3_FFX_RST,
      O => U1_db_error3(3)
    );
  U1_db_error3_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_3_FFX_RST
    );
  U1_db_error3_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_4_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_5_FFY_RST,
      O => U1_db_error3(4)
    );
  U1_db_error3_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_5_FFY_RST
    );
  U1_db_error3_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_5_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_5_FFX_RST,
      O => U1_db_error3(5)
    );
  U1_db_error3_5_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_5_FFX_RST
    );
  U1_db_error2_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_8_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_9_FFY_RST,
      O => U1_db_error2(8)
    );
  U1_db_error2_9_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_9_FFY_RST
    );
  U1_db_error2_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_9_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_9_FFX_RST,
      O => U1_db_error2(9)
    );
  U1_db_error2_9_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_9_FFX_RST
    );
  U1_db_error3_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_6_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_7_FFY_RST,
      O => U1_db_error3(6)
    );
  U1_db_error3_7_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_7_FFY_RST
    );
  U1_db_error3_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_8_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_9_FFY_RST,
      O => U1_db_error3(8)
    );
  U1_db_error3_9_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_9_FFY_RST
    );
  U1_db_error3_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_7_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_7_FFX_RST,
      O => U1_db_error3(7)
    );
  U1_db_error3_7_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_7_FFX_RST
    );
  U1_recoff_1106 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44094,
      CE => enw_paf_value,
      CLK => CLK,
      SET => GND,
      RST => U1_recoff_FFY_RST,
      O => U1_recoff
    );
  U1_recoff_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_recoff_FFY_RST
    );
  U1_dis_errorw_1107 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44088,
      CE => U1_n0012,
      CLK => CLK,
      SET => U1_dis_errorw_FFY_SET,
      RST => GND,
      O => U1_dis_errorw
    );
  U1_dis_errorw_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_dis_errorw_FFY_SET
    );
  U1_dis_ffreg_mask_1108 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44078,
      CE => U1_n0012,
      CLK => CLK,
      SET => GND,
      RST => U1_dis_ffreg_mask_FFY_RST,
      O => U1_dis_ffreg_mask
    );
  U1_dis_ffreg_mask_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_dis_ffreg_mask_FFY_RST
    );
  U1_paf_counter_3_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_counter_3_inst_sum_9,
      CE => U1_n0180,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_counter_3_9_FFY_RST,
      O => U1_paf_counter_3(9)
    );
  U1_paf_counter_3_9_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_counter_3_9_FFY_RST
    );
  U1_db_error2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_1_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_1_FFX_RST,
      O => U1_db_error2(1)
    );
  U1_db_error2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_1_FFX_RST
    );
  U1_db_error1_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_4_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_5_FFY_RST,
      O => U1_db_error1(4)
    );
  U1_db_error1_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_5_FFY_RST
    );
  U1_db_error1_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_5_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_5_FFX_RST,
      O => U1_db_error1(5)
    );
  U1_db_error1_5_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_5_FFX_RST
    );
  U1_db_error2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_2_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_3_FFY_RST,
      O => U1_db_error2(2)
    );
  U1_db_error2_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_3_FFY_RST
    );
  U1_db_error2_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_3_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_3_FFX_RST,
      O => U1_db_error2(3)
    );
  U1_db_error2_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_3_FFX_RST
    );
  U1_db_error1_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_6_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_7_FFY_RST,
      O => U1_db_error1(6)
    );
  U1_db_error1_7_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_7_FFY_RST
    );
  U1_db_error1_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_7_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_7_FFX_RST,
      O => U1_db_error1(7)
    );
  U1_db_error1_7_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_7_FFX_RST
    );
  U1_db_error2_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_4_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_5_FFY_RST,
      O => U1_db_error2(4)
    );
  U1_db_error2_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_5_FFY_RST
    );
  U1_db_error2_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0037_Result_5_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error2_5_FFX_RST,
      O => U1_db_error2(5)
    );
  U1_db_error2_5_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error2_5_FFX_RST
    );
  U1_db_error1_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_8_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_9_FFY_RST,
      O => U1_db_error1(8)
    );
  U1_db_error1_9_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_9_FFY_RST
    );
  U1_db_error3_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0038_Result_0_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error3_1_FFY_RST,
      O => U1_db_error3(0)
    );
  U1_db_error3_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error3_1_FFY_RST
    );
  U1_db_error1_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_Mmux_n0036_Result_9_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_db_error1_9_FFX_RST,
      O => U1_db_error1(9)
    );
  U1_db_error1_9_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_db_error1_9_FFX_RST
    );
  U3_sel_read_5_1_1109 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n010539_1_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_sel_read_5_1_FFY_RST,
      O => U3_sel_read_5_1
    );
  U3_sel_read_5_1_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_sel_read_5_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_sel_read_5_1_FFY_RST
    );
  blocked_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0048(3),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => blocked_3_FFY_RST,
      O => blocked(3)
    );
  blocked_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => blocked_3_FFY_RST
    );
  blocked_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0048(4),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => blocked_4_FFY_RST,
      O => blocked(4)
    );
  blocked_4_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => blocked_4_FFY_RST
    );
  U3_time_start_1110 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0101,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_time_start_FFY_RST,
      O => U3_time_start
    );
  U3_time_start_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_time_start_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_time_start_FFY_RST
    );
  U3_state_FFd34_1111 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd34_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd34_FFY_RST,
      O => U3_state_FFd34
    );
  U3_state_FFd34_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd34_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd34_FFY_RST
    );
  U3_state_FFd37_1112 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd37_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd37_FFY_RST,
      O => U3_state_FFd37
    );
  U3_state_FFd37_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd37_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd37_FFY_RST
    );
  U3_lives_in_1113 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0103,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_lives_in_FFY_RST,
      O => U3_lives_in
    );
  U3_lives_in_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_lives_in_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_lives_in_FFY_RST
    );
  U3_dontread_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0120(1),
      CE => U3_n0243,
      CLK => CLK,
      SET => U3_dontread_1_FFY_SET,
      RST => U3_dontread_1_FFY_RST,
      O => U3_dontread(1)
    );
  U3_dontread_1_FFY_SETOR : X_BUF
    port map (
      I => U3_dontread_1_n0001,
      O => U3_dontread_1_FFY_SET
    );
  U3_dontread_1_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_dontread_1_n0000,
      I1 => GSR,
      O => U3_dontread_1_FFY_RST
    );
  U3_dontread_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0120(4),
      CE => U3_n0243,
      CLK => CLK,
      SET => U3_dontread_4_FFY_SET,
      RST => U3_dontread_4_FFY_RST,
      O => U3_dontread(4)
    );
  U3_dontread_4_FFY_SETOR : X_BUF
    port map (
      I => U3_dontread_4_n0001,
      O => U3_dontread_4_FFY_SET
    );
  U3_dontread_4_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_dontread_4_n0000,
      I1 => GSR,
      O => U3_dontread_4_FFY_RST
    );
  blocked_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0048(5),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => blocked_5_FFY_RST,
      O => blocked(5)
    );
  blocked_5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => blocked_5_FFY_RST
    );
  U1_dis_evid_wrong_1114 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44082,
      CE => U1_n0012,
      CLK => CLK,
      SET => GND,
      RST => U1_dis_evid_wrong_FFY_RST,
      O => U1_dis_evid_wrong
    );
  U1_dis_evid_wrong_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_dis_evid_wrong_FFY_RST
    );
  U1_mask_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44084,
      CE => U1_n0008,
      CLK => CLK,
      SET => GND,
      RST => U1_mask_1_FFY_RST,
      O => U1_mask(0)
    );
  U1_mask_1_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_mask_1_FFY_RST
    );
  U1_mask_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44088,
      CE => U1_n0008,
      CLK => CLK,
      SET => GND,
      RST => U1_mask_3_FFY_RST,
      O => U1_mask(2)
    );
  U1_mask_3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_mask_3_FFY_RST
    );
  U1_mask_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44086,
      CE => U1_n0008,
      CLK => CLK,
      SET => GND,
      RST => U1_mask_1_FFX_RST,
      O => U1_mask(1)
    );
  U1_mask_1_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_mask_1_FFX_RST
    );
  U1_mask_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44090,
      CE => U1_n0008,
      CLK => CLK,
      SET => GND,
      RST => U1_mask_3_FFX_RST,
      O => U1_mask(3)
    );
  U1_mask_3_FFX_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_mask_3_FFX_RST
    );
  U1_mask_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44092,
      CE => U1_n0008,
      CLK => CLK,
      SET => GND,
      RST => U1_mask_4_FFY_RST,
      O => U1_mask(4)
    );
  U1_mask_4_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_mask_4_FFY_RST
    );
  U1_paf_cnt_set_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_cnt_set_5_BYMUXNOT,
      CE => U1_n0183,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_cnt_set_5_FFY_RST,
      O => U1_paf_cnt_set(5)
    );
  U1_paf_cnt_set_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_cnt_set_5_FFY_RST
    );
  U1_dis_paf_warn_1115 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44080,
      CE => U1_n0012,
      CLK => CLK,
      SET => GND,
      RST => U1_dis_paf_warn_FFY_RST,
      O => U1_dis_paf_warn
    );
  U1_dis_paf_warn_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_dis_paf_warn_FFY_RST
    );
  U1_timeout_value_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44072,
      CE => U1_n0009,
      CLK => CLK,
      SET => U1_timeout_value_1_FFY_SET,
      RST => GND,
      O => U1_timeout_value(0)
    );
  U1_timeout_value_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_timeout_value_1_FFY_SET
    );
  U1_timeout_value_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44074,
      CE => U1_n0009,
      CLK => CLK,
      SET => U1_timeout_value_1_FFX_SET,
      RST => GND,
      O => U1_timeout_value(1)
    );
  U1_timeout_value_1_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_timeout_value_1_FFX_SET
    );
  U1_timeout_value_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44076,
      CE => U1_n0009,
      CLK => CLK,
      SET => U1_timeout_value_3_FFY_SET,
      RST => GND,
      O => U1_timeout_value(2)
    );
  U1_timeout_value_3_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_timeout_value_3_FFY_SET
    );
  U3_dontread_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_n0120(0),
      CE => U3_n0243,
      CLK => CLK,
      SET => U3_dontread_0_FFY_SET,
      RST => U3_dontread_0_FFY_RST,
      O => U3_dontread(0)
    );
  U3_dontread_0_FFY_SETOR : X_BUF
    port map (
      I => U3_dontread_0_n0001,
      O => U3_dontread_0_FFY_SET
    );
  U3_dontread_0_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_dontread_0_n0000,
      I1 => GSR,
      O => U3_dontread_0_FFY_RST
    );
  U3_state_FFd1_1116 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd7,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd2_FFY_RST,
      O => U3_state_FFd1
    );
  U3_state_FFd2_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd2_FFY_RST
    );
  U2_fwrg2_1117 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fwrg2_LOGIC_ONE,
      CE => U2_fwrg1,
      CLK => CLK,
      SET => GND,
      RST => U2_fwrg2_FFY_RST,
      O => U2_fwrg2
    );
  U2_fwrg2_FFY_RSTOR : X_OR2
    port map (
      I0 => U2_n0045,
      I1 => GSR,
      O => U2_fwrg2_FFY_RST
    );
  U3_state_FFd2_1118 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd11,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd2_FFX_RST,
      O => U3_state_FFd2
    );
  U3_state_FFd2_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd2_FFX_RST
    );
  U2_fwrg1_1119 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fwrg1_LOGIC_ONE,
      CE => mrs_IBUF,
      CLK => CLK,
      SET => U2_fwrg1_FFX_SET,
      RST => U2_fwrg1_FFX_RST,
      O => U2_fwrg1
    );
  U2_fwrg1_FFX_SETOR : X_BUF
    port map (
      I => reset_IBUF_1,
      O => U2_fwrg1_FFX_SET
    );
  U2_fwrg1_FFX_RSTOR : X_OR2
    port map (
      I0 => U2_n0044,
      I1 => GSR,
      O => U2_fwrg1_FFX_RST
    );
  U2_fwrg4_1120 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fwrg3,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_fwrg4_FFY_RST,
      O => U2_fwrg4
    );
  U2_fwrg4_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_fwrg4_FFY_RST
    );
  U2_fwrg5_1121 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U2_fwrg4,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U2_fwrg5_FFY_RST,
      O => U2_fwrg5
    );
  U2_fwrg5_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => U2_fwrg5_FFY_RST
    );
  U1_dis_evid_bloq_1122 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44086,
      CE => U1_n0012,
      CLK => CLK,
      SET => U1_dis_evid_bloq_FFY_SET,
      RST => GND,
      O => U1_dis_evid_bloq
    );
  U1_dis_evid_bloq_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_dis_evid_bloq_FFY_SET
    );
  U3_state_FFd38_1123 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd38_In_O,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd38_FFY_RST,
      O => U3_state_FFd38
    );
  U3_state_FFd38_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd38_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd38_FFY_RST
    );
  U1_paf_cnt_set_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_cnt_set_0_BYMUXNOT,
      CE => U1_n0193,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_cnt_set_0_FFY_RST,
      O => U1_paf_cnt_set(0)
    );
  U1_paf_cnt_set_0_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_cnt_set_0_FFY_RST
    );
  U1_paf_cnt_set_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_cnt_set_1_BYMUXNOT,
      CE => U1_n0191,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_cnt_set_1_FFY_RST,
      O => U1_paf_cnt_set(1)
    );
  U1_paf_cnt_set_1_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_cnt_set_1_FFY_RST
    );
  U1_paf_cnt_set_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_cnt_set_2_BYMUXNOT,
      CE => U1_n0189,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_cnt_set_2_FFY_RST,
      O => U1_paf_cnt_set(2)
    );
  U1_paf_cnt_set_2_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_cnt_set_2_FFY_RST
    );
  U1_paf_cnt_set_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_cnt_set_3_BYMUXNOT,
      CE => U1_n0187,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_cnt_set_3_FFY_RST,
      O => U1_paf_cnt_set(3)
    );
  U1_paf_cnt_set_3_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_cnt_set_3_FFY_RST
    );
  U1_paf_cnt_set_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_paf_cnt_set_4_BYMUXNOT,
      CE => U1_n0185,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_cnt_set_4_FFY_RST,
      O => U1_paf_cnt_set(4)
    );
  U1_paf_cnt_set_4_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset,
      I1 => GSR,
      O => U1_paf_cnt_set_4_FFY_RST
    );
  U1_fout_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_5_IBUF_41,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_5_IFF_RST,
      O => U1_fout_reg(5)
    );
  fout_5_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_5_IFF_RST
    );
  U1_fout_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_6_IBUF_42,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_6_IFF_RST,
      O => U1_fout_reg(6)
    );
  fout_6_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_6_IFF_RST
    );
  U1_fout_reg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_7_IBUF_43,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_7_IFF_RST,
      O => U1_fout_reg(7)
    );
  fout_7_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_7_IFF_RST
    );
  U1_fout_reg_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_8_IBUF_44,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_8_IFF_RST,
      O => U1_fout_reg(8)
    );
  fout_8_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_8_IFF_RST
    );
  U1_fout_reg_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_9_IBUF_45,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_9_IFF_RST,
      O => U1_fout_reg(9)
    );
  fout_9_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_9_IFF_RST
    );
  U1_dis_head_trail_1124 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44084,
      CE => U1_n0012,
      CLK => CLK,
      SET => GND,
      RST => U1_dis_head_trail_FFY_RST,
      O => U1_dis_head_trail
    );
  U1_dis_head_trail_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_dis_head_trail_FFY_RST
    );
  U1_resynch_to_1125 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44072,
      CE => U1_n0016,
      CLK => CLK,
      SET => U1_resynch_to_FFY_SET,
      RST => GND,
      O => U1_resynch_to
    );
  U1_resynch_to_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_resynch_to_FFY_SET
    );
  U1_etr_paepaf_reg_1_1126 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U1_etr_paepaf_reg_2_GROM,
      CE => VCC,
      CLK => CLK,
      SET => U1_etr_paepaf_reg_2_FFY_SET,
      RST => GND,
      O => U1_etr_paepaf_reg_1
    );
  U1_etr_paepaf_reg_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF,
      O => U1_etr_paepaf_reg_2_FFY_SET
    );
  U1_etr_paepaf_reg_2_1127 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U1_etr_paepaf_reg_1,
      CE => VCC,
      CLK => CLK,
      SET => U1_etr_paepaf_reg_2_FFX_SET,
      RST => GND,
      O => U1_etr_paepaf_reg_2
    );
  U1_etr_paepaf_reg_2_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF,
      O => U1_etr_paepaf_reg_2_FFX_SET
    );
  U1_resynch_maxw_1128 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44080,
      CE => U1_n0016,
      CLK => CLK,
      SET => U1_resynch_maxw_FFY_SET,
      RST => GND,
      O => U1_resynch_maxw
    );
  U1_resynch_maxw_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_resynch_maxw_FFY_SET
    );
  s_data_reg_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_10_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_10_OFF_RST,
      O => s_data_reg(10)
    );
  dout_10_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_10_OFF_RST
    );
  s_data_reg_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_11_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_11_OFF_RST,
      O => s_data_reg(11)
    );
  dout_11_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_11_OFF_RST
    );
  s_data_reg_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_12_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_12_OFF_RST,
      O => s_data_reg(12)
    );
  dout_12_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_12_OFF_RST
    );
  s_data_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_3_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_3_OFF_RST,
      O => s_data_reg(3)
    );
  dout_3_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_3_OFF_RST
    );
  s_data_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_4_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_4_OFF_RST,
      O => s_data_reg(4)
    );
  dout_4_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_4_OFF_RST
    );
  s_data_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_5_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_5_OFF_RST,
      O => s_data_reg(5)
    );
  dout_5_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_5_OFF_RST
    );
  s_data_reg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_6_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_6_OFF_RST,
      O => s_data_reg(6)
    );
  dout_6_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_6_OFF_RST
    );
  s_data_reg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_7_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_7_OFF_RST,
      O => s_data_reg(7)
    );
  dout_7_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_7_OFF_RST
    );
  s_data_reg_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_8_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_8_OFF_RST,
      O => s_data_reg(8)
    );
  dout_8_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_8_OFF_RST
    );
  s_data_reg_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_9_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_9_OFF_RST,
      O => s_data_reg(9)
    );
  dout_9_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_9_OFF_RST
    );
  U1_timeout_value_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44078,
      CE => U1_n0009,
      CLK => CLK,
      SET => U1_timeout_value_3_FFX_SET,
      RST => GND,
      O => U1_timeout_value(3)
    );
  U1_timeout_value_3_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_timeout_value_3_FFX_SET
    );
  U3_state_FFd18_1129 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd18_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd17_FFY_RST,
      O => U3_state_FFd18
    );
  U3_state_FFd17_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd17_FFY_RST
    );
  U3_state_FFd17_1130 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd18,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd17_FFX_RST,
      O => U3_state_FFd17
    );
  U3_state_FFd17_FFX_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd17_FFX_RST
    );
  U1_per_fifo_1131 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U1_per_fifo_aux_2,
      CE => VCC,
      CLK => CLK,
      SET => U1_per_fifo_FFY_SET,
      RST => GND,
      O => U1_per_fifo
    );
  U1_per_fifo_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF,
      O => U1_per_fifo_FFY_SET
    );
  U3_state_FFd23_1132 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd23_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd23_FFY_RST,
      O => U3_state_FFd23
    );
  U3_state_FFd23_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd23_FFY_RST
    );
  enw2_1133 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => enw1,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => enw2_FFY_RST,
      O => enw2
    );
  enw2_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => enw2_FFY_RST
    );
  U1_paf_reg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U1_n0014(5),
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U1_paf_reg_5_FFY_RST,
      O => U1_paf_reg(5)
    );
  U1_paf_reg_5_FFY_RSTOR : X_OR2
    port map (
      I0 => soft_reset1_1,
      I1 => GSR,
      O => U1_paf_reg_5_FFY_RST
    );
  U1_dis_timo_mask_1134 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44076,
      CE => U1_n0012,
      CLK => CLK,
      SET => GND,
      RST => U1_dis_timo_mask_FFY_RST,
      O => U1_dis_timo_mask
    );
  U1_dis_timo_mask_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_dis_timo_mask_FFY_RST
    );
  U1_nmaxwords_4 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44080,
      CE => U1_n0010,
      CLK => CLK,
      SET => U1_nmaxwords_5_FFY_SET,
      RST => GND,
      O => U1_nmaxwords(4)
    );
  U1_nmaxwords_5_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_nmaxwords_5_FFY_SET
    );
  U1_nmaxwords_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44082,
      CE => U1_n0010,
      CLK => CLK,
      SET => U1_nmaxwords_5_FFX_SET,
      RST => GND,
      O => U1_nmaxwords(5)
    );
  U1_nmaxwords_5_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_nmaxwords_5_FFX_SET
    );
  U1_nmaxwords_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44084,
      CE => U1_n0010,
      CLK => CLK,
      SET => U1_nmaxwords_7_FFY_SET,
      RST => GND,
      O => U1_nmaxwords(6)
    );
  U1_nmaxwords_7_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_nmaxwords_7_FFY_SET
    );
  U1_nmaxwords_7 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44086,
      CE => U1_n0010,
      CLK => CLK,
      SET => U1_nmaxwords_7_FFX_SET,
      RST => GND,
      O => U1_nmaxwords(7)
    );
  U1_nmaxwords_7_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_nmaxwords_7_FFX_SET
    );
  doneout_1135 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => doneout_LOGIC_ONE,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => donein_IBUF,
      O => doneout_OBUF
    );
  U3_state_FFd33_1136 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => U3_state_FFd33_In,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => U3_state_FFd33_FFY_RST,
      O => U3_state_FFd33
    );
  U3_state_FFd33_FFY_RSTOR : X_OR2
    port map (
      I0 => U3_state_FFd33_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => U3_state_FFd33_FFY_RST
    );
  U1_dis_maxw_mask_1137 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44072,
      CE => U1_n0012,
      CLK => CLK,
      SET => U1_dis_maxw_mask_FFY_SET,
      RST => GND,
      O => U1_dis_maxw_mask
    );
  U1_dis_maxw_mask_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_dis_maxw_mask_FFY_SET
    );
  U1_resynch_evidmis_1138 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N44074,
      CE => U1_n0016,
      CLK => CLK,
      SET => U1_resynch_evidmis_FFY_SET,
      RST => GND,
      O => U1_resynch_evidmis
    );
  U1_resynch_evidmis_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => U1_resynch_evidmis_FFY_SET
    );
  reset2_1139 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => reset1,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => reset2_FFY_RST,
      O => reset2
    );
  reset2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => reset2_FFY_RST
    );
  U1_dis_hul_mask_1140 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N44074,
      CE => U1_n0012,
      CLK => CLK,
      SET => GND,
      RST => U1_dis_hul_mask_FFY_RST,
      O => U1_dis_hul_mask
    );
  U1_dis_hul_mask_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => U1_dis_hul_mask_FFY_RST
    );
  U1_etr_fifo_reg_1141 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => U1_etr_fifo_reg_GROM,
      CE => VCC,
      CLK => CLK,
      SET => U1_etr_fifo_reg_FFY_SET,
      RST => GND,
      O => U1_etr_fifo_reg
    );
  U1_etr_fifo_reg_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_IBUF,
      O => U1_etr_fifo_reg_FFY_SET
    );
  ULED1_q1_1142 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => ULED1_q1_LOGIC_ONE,
      CE => U3_ros_done,
      CLK => CLK,
      SET => GND,
      RST => ULED1_q1_FFY_RST,
      O => ULED1_q1
    );
  ULED1_q1_FFY_RSTOR : X_OR2
    port map (
      I0 => ULED1_q3,
      I1 => GSR,
      O => ULED1_q1_FFY_RST
    );
  ULED1_q2_1143 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => ULED1_q1,
      CE => VCC,
      CLK => clk_slow_BUFGP,
      SET => GND,
      RST => ULED1_q2_FFY_RST,
      O => ULED1_q2
    );
  ULED1_q2_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => ULED1_q2_FFY_RST
    );
  ULED1_q3_1144 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => ULED1_q2,
      CE => VCC,
      CLK => clk_slow_BUFGP,
      SET => GND,
      RST => ULED1_q3_FFY_RST,
      O => ULED1_q3
    );
  ULED1_q3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => ULED1_q3_FFY_RST
    );
  ULED2_q1_1145 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => ULED2_q1_LOGIC_ONE,
      CE => spaf_p_OBUF,
      CLK => CLK,
      SET => GND,
      RST => ULED2_q1_FFY_RST,
      O => ULED2_q1
    );
  ULED2_q1_FFY_RSTOR : X_OR2
    port map (
      I0 => ULED2_q3,
      I1 => GSR,
      O => ULED2_q1_FFY_RST
    );
  ULED2_q2_1146 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => ULED2_q1,
      CE => VCC,
      CLK => clk_slow_BUFGP,
      SET => GND,
      RST => ULED2_q2_FFY_RST,
      O => ULED2_q2
    );
  ULED2_q2_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => ULED2_q2_FFY_RST
    );
  ULED2_q3_1147 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => ULED2_q2,
      CE => VCC,
      CLK => clk_slow_BUFGP,
      SET => GND,
      RST => ULED2_q3_FFY_RST,
      O => ULED2_q3
    );
  ULED2_q3_FFY_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF_1,
      I1 => GSR,
      O => ULED2_q3_FFY_RST
    );
  U1_mask_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => db_11_IBUF,
      CE => U1_n0008,
      CLK => CLK,
      SET => GND,
      RST => db_11_IFF_RST,
      O => U1_mask(5)
    );
  db_11_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_largo,
      I1 => GSR,
      O => db_11_IFF_RST
    );
  U1_timeout_value_10 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => db_10_IBUF,
      CE => U1_n0009,
      CLK => CLK,
      SET => db_10_IFF_SET,
      RST => GND,
      O => U1_timeout_value(10)
    );
  db_10_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => reset_largo,
      O => db_10_IFF_SET
    );
  s_data_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_0_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_0_OFF_RST,
      O => s_data_reg(0)
    );
  dout_0_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_0_OFF_RST
    );
  s_data_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_1_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_1_OFF_RST,
      O => s_data_reg(1)
    );
  dout_1_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_1_OFF_RST
    );
  s_data_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_2_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_2_OFF_RST,
      O => s_data_reg(2)
    );
  dout_2_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_2_OFF_RST
    );
  U1_fout_reg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_0_IBUF_36,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_0_IFF_RST,
      O => U1_fout_reg(0)
    );
  fout_0_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_0_IFF_RST
    );
  U1_fout_reg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_1_IBUF_37,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_1_IFF_RST,
      O => U1_fout_reg(1)
    );
  fout_1_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_1_IFF_RST
    );
  U1_fout_reg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_2_IBUF_38,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_2_IFF_RST,
      O => U1_fout_reg(2)
    );
  fout_2_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_2_IFF_RST
    );
  U1_fout_reg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_3_IBUF_39,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_3_IFF_RST,
      O => U1_fout_reg(3)
    );
  fout_3_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_3_IFF_RST
    );
  U1_fout_reg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => fout_4_IBUF_40,
      CE => U1_n0126,
      CLK => CLK,
      SET => GND,
      RST => fout_4_IFF_RST,
      O => U1_fout_reg(4)
    );
  fout_4_IFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => fout_4_IFF_RST
    );
  s_data_reg_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_13_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_13_OFF_RST,
      O => s_data_reg(13)
    );
  dout_13_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_13_OFF_RST
    );
  s_data_reg_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_14_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_14_OFF_RST,
      O => s_data_reg(14)
    );
  dout_14_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_14_OFF_RST
    );
  s_data_reg_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => dout_15_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => dout_15_OFF_RST,
      O => s_data_reg(15)
    );
  dout_15_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => dout_15_OFF_RST
    );
  txena_reg_1148 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => txena_p_OD,
      CE => VCC,
      CLK => CLK,
      SET => GND,
      RST => txena_p_OFF_RST,
      O => txena_reg
    );
  txena_p_OFF_RSTOR : X_OR2
    port map (
      I0 => reset_IBUF,
      I1 => GSR,
      O => txena_p_OFF_RST
    );
  clkin_p_BUF : X_CKBUF
    port map (
      I => clkin_p,
      O => CLKIN
    );
  clk_slow_BUF : X_CKBUF
    port map (
      I => clk_slow,
      O => clk_slow_BUFGP_IBUFG
    );
  UDLL3_BUF : X_CKBUF
    port map (
      I => CLK0,
      O => CLK
    );
  clk_slow_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clk_slow_BUFGP_IBUFG,
      O => clk_slow_BUFGP
    );
  NlwBlock_ceros_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_ceros_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

