//Clase para acceder a los dispositivos JTAG
//Cristina Fern�ndez Bedoya

#include "JTAG.h"

JTAG::JTAG(InterfazIO & myveryInterfazIO):myInterfazIO(myveryInterfazIO) 
{
}

JTAG::~JTAG()
{
}

//**********************************************************
//*********** M�TODOS P�BLICOS
//**********************************************************
unsigned short JTAG::send_1_bit(unsigned short TMS,unsigned short TDI,int JTAG_Reg1,unsigned short fpga)
{
unsigned short tdo=0;
unsigned short TCK=0;
 unsigned short dato=0;
 
// 1a parte: con el clk 0
 TCK = 0;
 dato = ((TDI<<8) | (TMS<<7) | (TCK<<6) | fpga);

 myInterfazIO.write(JTAG_Reg1,dato);
// writeboard(mybus,JTAG_Reg1,dato);

// 2a parte: cambio el clk

 TCK = 1;
 dato = (TDI<<8) | (TMS<<7) | (TCK<<6) | fpga ;
 myInterfazIO.write(JTAG_Reg1,dato);
//writeboard(mybus,JTAG_Reg1,dato);

 //LEO
unsigned long thevalue = myInterfazIO.read(JTAG_Reg1);
// unsigned short thevalue = readboard(mybus,JTAG_Reg1);

 
  if (fpga==0x1) tdo = (thevalue>>9) & 0x1;
  if (fpga==0x2) tdo = (thevalue>>10) & 0x1;
  if (fpga==0x4) tdo = (thevalue>>11) & 0x1;
  if (fpga==0x8) tdo = (thevalue>>12) & 0x1;
  if (fpga==0x10) tdo = (thevalue>>13) & 0x1;
  if (fpga==0x20) tdo = (thevalue>>14) & 0x1;
// 3a parte: cambio de nuevo el clk

 TCK = 0;
 dato = (TDI<<8) | (TMS<<7) | (TCK<<6) | fpga ;
 myInterfazIO.write(JTAG_Reg1,dato);
//writeboard(mybus,JTAG_Reg1,dato);

 //cout<<"SEND 1 BIT send="<<TDI<<" TMS="<<TMS<<" -- get TDO="<<hex<<tdo<<endl;

  return tdo;
};

//////////////////////
//////////////////////
void JTAG::jtag_reset(int JTAG_Reg1,unsigned short fpga)
{
	unsigned short TMS=0;
unsigned short TDI=0;
unsigned short tdo=0;
//cout<<endl<<"Execute a JTAG RESET "<<endl;	
  for (int i=0; i<5; i++){
   TMS = 1;
//   TDI = 1;
   TDI = 0;
   tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
   //  cout<<"escribo tms="<<TMS<<"  tdi="<<TDI<<endl;
  };

// IDLE:
 TMS = 0;
//   TDI = 1;
   TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 // cout<<"escribo tms="<<TMS<<"  tdi="<<TDI<<endl;
 // cout<<"salgo del reset"<<endl;
};

//////////////////////
//////////////////////
unsigned short JTAG::send_n_bit(unsigned short TMS,unsigned short TDI,int JTAG_TDI_Reg2,int JTAG_TDO_Data,int nbits)
{
 unsigned short tdo=0;
 unsigned short dato=0;
 
if (nbits!=0){//protejo no enviar nada

// la sequencia de reloj la hace autom�ticamente la fpga
 //nbits debe ser menor que 8
  dato = (((nbits&0xF)<<9) | (TMS<<8) | (TDI&0xFF));
  myInterfazIO.write(JTAG_TDI_Reg2,dato);

// writeboard(mybus,JTAG_TDI_Reg2,dato);
  //cout<<"SEND N BITS dato="<<hex<<dato<<" nbits="<<dec<<nbits<<" TMS="<<hex<<TMS<<" TDI="<<TDI<<endl;
//  LEO
 int finished=0;
int contador_safe=0;
 while(finished==0){

	 unsigned long thevalue = myInterfazIO.read(JTAG_TDO_Data);
	 //unsigned short thevalue = readboard(mybus,JTAG_TDO_Data);

 // cout<<"SEND N="<<nbits<<" BITS Leo: "<<hex<<thevalue<<endl;
 
finished=(thevalue>>8)&0x1;
 
 tdo = (thevalue & 0xFF);
  contador_safe++;
if (contador_safe>1000){
	finished=1;
 	cout<<endl<<"*******send_nbits no leo finished del registro VME"<<endl;
 	cout<<endl<<"*******Teclear algun valor"<<endl;
	string gg;
	cin>>gg;
 };

 };//while finished

};//if nbits!=0

  return tdo;
};

//////////////////////
//////////////////////
void JTAG::send_IR(int JTAG_Reg1,unsigned short fpga, int nbits, int INSTRUCTION,int SIstatetofinish,int stateIam)
{
	//int nbits = 8;
unsigned short tdo=0;
//int INSTRUCTION=0xFE; // IDCODE in xc18v01 here
unsigned short TMS=0;
unsigned short TDI=0;

//cout<<"entro en SIR nbits="<<nbits<<" INSTRUCTION+0x"<<hex<<INSTRUCTION<<endl;

if (stateIam==6){//estoy en DRPAUSE, voy a IDLE
// DREXIT2:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

 //DRUPDATE:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
}else{
	if (stateIam==13){//estoy en IRPAUSE, voy a IDLE, extraño
	// IREXIT2:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

	 //IRUPDATE:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	};//13
};//stateIam==6

// DR-SCAN:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 //cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;

// SELECT-IR-SCAN:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 //cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;

// CAPTURE-IR:

 TMS = 0;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 //cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;

// SHIFT-IR:

 TMS = 0;
 TDI = 0; 
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 //cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;

// 5to step:

for (int i=0; i<nbits; i++){

TDI = INSTRUCTION & 0x1;
 INSTRUCTION=INSTRUCTION>>1;

if (i==(nbits-1)) TMS=1;
	else TMS=0;

tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);	
//cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;
};
 ///aqui estoy en exit
if (SIstatetofinish==13){
	// IRPAUSE:
	 TMS = 0;
	 TDI = 0; 
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 // cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;

}else{ //doy por hecho que salgo normal
	// UPDATE:
	 TMS = 1;
	 TDI = 0; 
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 // cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;


	// IDLE:
	 TMS = 0;
//   TDI = 1;
   TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 // cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;
};//if SIstatetofinish==13

 //cout<<"salgo del SIR"<<endl;

};

//////////////////////
//////////////////////
unsigned long JTAG::send_DR(int JTAG_Reg1, unsigned short fpga, int nbits, unsigned long dr_data,int SDstatetofinish,int stateIam)
{
//int nbits = 32;
unsigned short tdo=0;
unsigned long data;
data=dr_data;
unsigned short TMS=0;
unsigned short TDI=0;
unsigned long IDCODE=0;

//cout<<"entro en el SDR"<<endl;

if (stateIam==6){//estoy en DRPAUSE, extraño
// DREXIT2:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

 //DRUPDATE:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
}else{
	if (stateIam==13){//estoy en IRPAUSE
	// IREXIT2:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

	 //IRUPDATE:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	};//13
};//stateIam==6


// SELECT-DR-SCAN:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 //  cout<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

// capture-DR:
 TMS = 0;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 //cout<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

 // capture-DR:
 TMS = 0;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 // cout<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;


// SHIFT DR
for (int i=0; i<nbits; i++){

TDI = data & 0x1;
 data=data>>1;

//TDI = 0;
if (i==(nbits-1)) TMS=1;
	else TMS=0;
tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
//cout<<dec<<i<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;
 IDCODE=((IDCODE) | (tdo<<i));

};
//cout<<"  IDOCODE "<<hex<<IDCODE<<endl;
 ///aqui estoy en exit
if (SDstatetofinish==6){
	// DRPAUSE:
	 TMS = 0;
	 TDI = 0; 
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 // cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;

}else{ //doy por hecho que salgo normal
		// UPDATE-DR:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 //cout<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

	// IDLE:
	 TMS = 0;
//   TDI = 1;
   TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 //cout<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

};//if SDstatetofinish==13

 //cout<<"salgo del SDR"<<endl;
return IDCODE;
};

//////////////////////
//////////////////////
unsigned long JTAG::send_DR_middle_sinreg2(int JTAG_Reg1, unsigned short fpga, int nbits, int final, unsigned long dr_data)
{
//int nbits = 32;
unsigned short tdo=0;
unsigned long data;
data=dr_data;
unsigned short TMS=0;
unsigned short TDI=0;
unsigned long IDCODE=0;

//cout<<"entro en el SDR"<<endl;
 

// SHIFT DR
for (int i=0; i<nbits; i++){

TDI = data & 0x1;
data=data>>1;

if (final==1){
if (i==(nbits-1)) TMS=1;
	else TMS=0;
 };

tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

//cout<<dec<<i<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;
 IDCODE=((IDCODE) | (tdo<<i));

};
//cout<<"  IDOCODE "<<hex<<IDCODE<<endl;



 //cout<<"salgo del SDR"<<endl;
return IDCODE;
};

//////////////////////
//////////////////////
void JTAG::prep_send_DR(int JTAG_Reg1, unsigned short fpga,int stateIam)
{
unsigned short tdo=0;
unsigned short TMS=0;
unsigned short TDI=0;

//cout<<"entro en el prep SDR"<<endl;

if (stateIam==6){//estoy en DRPAUSE, extraño
// DREXIT2:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

 //DRUPDATE:
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
}else{
	if (stateIam==13){//estoy en IRPAUSE
	// IREXIT2:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

	 //IRUPDATE:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	};//13
};//stateIam==6


// SELECT-DR-SCAN:
 
 TMS = 1;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 //  cout<<" seldr  SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

// capture-DR:
 TMS = 0;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 // cout<<" capture dr   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

 // capture-DR:
 TMS = 0;
 TDI = 0;
 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
 // cout<<" cap  SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;


 //cout<<"salgo del prep_SDR"<<endl;

};

//////////////////////
//////////////////////
unsigned long JTAG::send_DR_middle(int JTAG_Reg1, unsigned short fpga, int JTAG_TDI_Reg2,int JTAG_TDO_Data, int final, int nbits, unsigned short dr_data)
{
		//nbits <=8
unsigned short tdo=0;
unsigned short tdo_ult=0;
unsigned short TMS=0;
unsigned short TDI=0;

if (nbits!=0){
	 if (final==1){
		if (nbits==1){
		  TMS = 1;
		  TDI = dr_data & 0x1;
		  tdo_ult=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
			//printf("final 1 ULTIMO BIT Middle SR tdi %x nbits %d \n",TDI,1);
		  tdo=(tdo_ult | (tdo>>1));
		}else{
		//mando primero todos los bits menos el �ltimo
		 TMS=0;
		 TDI=dr_data;
	 //	printf("final 1 Middle SR tdi %x nbits %d \n",TDI,(nbits-1));
		tdo=send_n_bit(TMS,TDI,JTAG_TDI_Reg2,JTAG_TDO_Data,(nbits-1));
			//printf("final 1 Middle SR tdi %x TMS %d nbits %d \n",TDI,TMS,(nbits-1));
		//luego mando el �ltimo bit con tms=1
		TMS = 1;
		TDI = (dr_data>>(nbits-1))&0x1;
		tdo_ult=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
			//printf("final 1 ULTIMO BIT Middle SR tdi %x tms %d nbits %d \n",TDI,TMS,1);
		tdo=((tdo_ult<<(nbits-1)) | (tdo>>1));
		//	cout<<" tdo_ult="<<hex<<tdo_ult<< " tdo="<<tdo<<endl;
		};//nbits==1	
	
	 }else{
		if (nbits==1){
		  TMS = 0;
		  TDI = dr_data & 0x1;
		  tdo_ult=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
			//printf("final 1 ULTIMO BIT Middle SR tdi %x nbits %d \n",TDI,1);
		  tdo=(tdo_ult | (tdo>>1));
		}else{
		 TMS=0;
		 TDI=dr_data;
		 tdo=send_n_bit(TMS,TDI,JTAG_TDI_Reg2,JTAG_TDO_Data,nbits);
	//	  printf("final 0 Middle SR tdi %x %d \n",TDI,nbits);
		};//nbits==1	

	 };//final==1

	 //	 cout<<hex<<" SDR MIDDLE  final=  "<<final<<" datain="<<dr_data<<" nbits="<<nbits<<"  tdo="<<tdo<<endl;
	 // cout<<"salgo del SDR middle"<<endl;
};//nbits!=0
 return tdo;
};

//////////////////////
//////////////////////
void JTAG::exit_send_DR(int JTAG_Reg1, unsigned short fpga,int SDstatetofinish)
{
unsigned short tdo=0;
unsigned short TMS=0;
unsigned short TDI=0;

///aqui estoy en exit
if (SDstatetofinish==6){
	// DRPAUSE:
	 TMS = 0;
	 TDI = 0; 
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 // cout<<"SIR TMS="<<TMS<<" TDI="<<TDI<<" tdo="<<tdo<<endl;

}else{ //doy por hecho que salgo normal
		// UPDATE-DR:
	 TMS = 1;
	 TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 //cout<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

	// IDLE:
	 TMS = 0;
//   TDI = 1;
   TDI = 0;
	 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	 //cout<<"   SDR TMS=  "<<TMS<<" TDI="<<TDI<<"  tdo="<<tdo<<endl;

};//if SDstatetofinish==13

 //cout<<"salgo del exit_SDR"<<endl;

};

////////////////////////
///////////////////////
void JTAG::runtest(int JTAG_Reg1, unsigned short fpga,int waittime,int stateIam,int RUNstatetofinish)
{
unsigned short TMS=0;
unsigned short TDI=0;
unsigned short tdo=0;

	if (stateIam!=RUNstatetofinish){ //si son distintos me muevo
		if ((stateIam==6)&(RUNstatetofinish==0)){//estoy en DRPAUSE y voy a IDLE
			// DREXIT2
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DRUPDATE
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // IDLE
			 TMS = 0;
			//   TDI = 1;
			TDI = 0;
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
		};//if s=6

		if ((stateIam==13)&(RUNstatetofinish==0)){//estoy en IRPAUSE y voy a IDLE
			// IREXIT2
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // IRUPDATE
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // IDLE
			 TMS = 0;
			//   TDI = 1;
			TDI = 0;
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
		};//if s=13
	};//if stateIam==RUNstatetofinish

	int time_sleep=(waittime/1); //for using usleep
	usleep(time_sleep);
	
};

////////////////////////
///////////////////////
void JTAG::gotoidle(int JTAG_Reg1, unsigned short fpga,int stateIam,int RUNstatetofinish)
{
unsigned short TMS=0;
unsigned short TDI=0;
unsigned short tdo=0;

	if (stateIam!=RUNstatetofinish){ //si son distintos me muevo
		if ((stateIam==6)&(RUNstatetofinish==0)){//estoy en DRPAUSE y voy a IDLE
			// DREXIT2
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DRUPDATE
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // IDLE
			 TMS = 0;
			//   TDI = 1;
			TDI = 0;
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
		};//if s=6

		if ((stateIam==13)&(RUNstatetofinish==0)){//estoy en IRPAUSE y voy a IDLE
			// IREXIT2
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // IRUPDATE
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // IDLE
			 TMS = 0;
			//   TDI = 1;
			TDI = 0;
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
		};//if s=13
	};//if stateIam==RUNstatetofinish


};

////////////////////////
///////////////////////
void JTAG::stateseq1(int JTAG_Reg1, unsigned short fpga,int stateIam,int RUNstatetofinish)
{
unsigned short TMS=0;
unsigned short TDI=0;
unsigned short tdo=0;
	//if ((strcmp(stron,"STATE  IREXIT2 IRUPDATE DRSELECT DRCAPTURE DREXIT1 DRPAUSE;")==0)){
//se entiende que estamos en IRPAUSE

			// IREXIT2
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			// IRUPDATE
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DRSELECT
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DRCAPTURE
			 TMS = 0;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DREXIT1
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

 			 // DRPAUSE
			 TMS = 0;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

};
////////////////////////
///////////////////////
void JTAG::stateseq2(int JTAG_Reg1, unsigned short fpga,int stateIam,int RUNstatetofinish)
{
unsigned short TMS=0;
unsigned short TDI=0;
unsigned short tdo=0;
//if ((strcmp(stron,"STATE  IREXIT2 IRUPDATE DRSELECT DRCAPTURE DREXIT1 DRPAUSE IDLE;")==0)){
//se entiende que estamos en IRPAUSE

			// IREXIT2
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			// IRUPDATE
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DRSELECT
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DRCAPTURE
			 TMS = 0;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DREXIT1
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

 			 // DRPAUSE
			 TMS = 0;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

 			 // DREXIT2
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

  			 // DRUPDATE
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // IDLE
			 TMS = 0;
			//   TDI = 1;
			TDI = 0;
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

};
////////////////////////
///////////////////////
void JTAG::gotodrpause(int JTAG_Reg1, unsigned short fpga,int stateIam,int RUNstatetofinish)
{
unsigned short TMS=0;
unsigned short TDI=0;
unsigned short tdo=0;
//if ((strcmp(stron,"STATE  DRPAUSE;")==0)){
//se entiende que estamos en IDLE
	if (stateIam==0){
			 // DRSELECT
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DRCAPTURE
			 TMS = 0;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

			 // DREXIT1
			 TMS = 1;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);

 			 // DRPAUSE
			 TMS = 0;
			 TDI = 0; 
			 tdo=send_1_bit(TMS,TDI,JTAG_Reg1,fpga);
	};//if stateIam==0
};
