[COREGEN.VERILOG Component Instantiation.fifo_sc512]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="fifo_sc512 YourInstanceName ("
text007="    .addra(addra),"
text008="    .addrb(addrb),"
text009="    .clka(clka),"
text010="    .clkb(clkb),"
text011="    .dina(dina),"
text012="    .dinb(dinb),"
text013="    .douta(douta),"
text014="    .doutb(doutb),"
text015="    .ena(ena),"
text016="    .enb(enb),"
text017="    .wea(wea),"
text018="    .web(web));"
text019=""
text020=" "
type=template
[COREGEN.VERILOG Component Instantiation.mierda_nacho]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mierda_nacho YourInstanceName ("
text007="    .dividend(dividend),"
text008="    .divisor(divisor),"
text009="    .quot(quot),"
text010="    .remd(remd),"
text011="    .clk(clk),"
text012="    .rfd(rfd),"
text013="    .aclr(aclr),"
text014="    .sclr(sclr),"
text015="    .ce(ce));"
text016=""
text017=" "
type=template
[COREGEN.VHDL Component Instantiation.fifo_sc512]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component fifo_sc512"
text005="    port ("
text006="    addra: IN std_logic_VECTOR(8 downto 0);"
text007="    addrb: IN std_logic_VECTOR(8 downto 0);"
text008="    clka: IN std_logic;"
text009="    clkb: IN std_logic;"
text010="    dina: IN std_logic_VECTOR(15 downto 0);"
text011="    dinb: IN std_logic_VECTOR(15 downto 0);"
text012="    douta: OUT std_logic_VECTOR(15 downto 0);"
text013="    doutb: OUT std_logic_VECTOR(15 downto 0);"
text014="    ena: IN std_logic;"
text015="    enb: IN std_logic;"
text016="    wea: IN std_logic;"
text017="    web: IN std_logic);"
text018="end component;"
text019=""
text020=""
text021=""
text022=" "
text023="-------------------------------------------------------------"
text024=" "
text025="-- The following code must appear in the VHDL architecture body."
text026="-- Substitute your own instance name and net names."
text027=" "
text028="your_instance_name : fifo_sc512"
text029="        port map ("
text030="            addra => addra,"
text031="            addrb => addrb,"
text032="            clka => clka,"
text033="            clkb => clkb,"
text034="            dina => dina,"
text035="            dinb => dinb,"
text036="            douta => douta,"
text037="            doutb => doutb,"
text038="            ena => ena,"
text039="            enb => enb,"
text040="            wea => wea,"
text041="            web => web);"
text042=" "
type=template
[COREGEN.VHDL Component Instantiation.mierda_nacho]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mierda_nacho"
text005="    port ("
text006="    dividend: IN std_logic_VECTOR(7 downto 0);"
text007="    divisor: IN std_logic_VECTOR(7 downto 0);"
text008="    quot: OUT std_logic_VECTOR(7 downto 0);"
text009="    remd: OUT std_logic_VECTOR(7 downto 0);"
text010="    clk: IN std_logic;"
text011="    rfd: OUT std_logic;"
text012="    aclr: IN std_logic;"
text013="    sclr: IN std_logic;"
text014="    ce: IN std_logic);"
text015="end component;"
text016=""
text017=""
text018=""
text019=" "
text020="-------------------------------------------------------------"
text021=" "
text022="-- The following code must appear in the VHDL architecture body."
text023="-- Substitute your own instance name and net names."
text024=" "
text025="your_instance_name : mierda_nacho"
text026="        port map ("
text027="            dividend => dividend,"
text028="            divisor => divisor,"
text029="            quot => quot,"
text030="            remd => remd,"
text031="            clk => clk,"
text032="            rfd => rfd,"
text033="            aclr => aclr,"
text034="            sclr => sclr,"
text035="            ce => ce);"
text036=" "
type=template
