Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.31 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.31 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: rosctrl.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : rosctrl.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : rosctrl
Output Format                      : NGC
Target Device                      : xc2s100e-7-ft256

---- Source Options
Top Module Name                    : rosctrl
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : rosctrl.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/ROSCTRL is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd
WARNING:HDLParsers:3215 - Unit work/ROSCTRL/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd
WARNING:HDLParsers:3215 - Unit work/RC_TRG_ROS is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd
WARNING:HDLParsers:3215 - Unit work/RC_TRG_ROS/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd
WARNING:HDLParsers:3215 - Unit work/SC_FIFO512_CRIS is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd
WARNING:HDLParsers:3215 - Unit work/SC_FIFO512_CRIS/SC_FIFO512_CRIS_HDL is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd
WARNING:HDLParsers:3481 - No primary, secondary unit in the file C:\CRIS\CMS\VHDL\PARA_FINAL\rosctrl_100/fifo_sc512.vhd. Ignore this file from project file rosctrl_vhdl.prj.
WARNING:HDLParsers:3215 - Unit work/RC_REG_CTRL is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd
WARNING:HDLParsers:3215 - Unit work/RC_REG_CTRL/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd
WARNING:HDLParsers:3215 - Unit work/RC_CONTROL is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd
WARNING:HDLParsers:3215 - Unit work/RC_CONTROL/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd
WARNING:HDLParsers:3215 - Unit work/FIFO_255X12 is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd
WARNING:HDLParsers:3215 - Unit work/FIFO_255X12/FIFOCTLR_CC_HDL is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd
WARNING:HDLParsers:3215 - Unit work/RC_ROS is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd
WARNING:HDLParsers:3215 - Unit work/RC_ROS/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd
WARNING:HDLParsers:3215 - Unit work/CR_FIFOS is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd
WARNING:HDLParsers:3215 - Unit work/CR_FIFOS/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd
WARNING:HDLParsers:3215 - Unit work/CR_REGISTROS is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd
WARNING:HDLParsers:3215 - Unit work/CR_REGISTROS/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd
WARNING:HDLParsers:3215 - Unit work/PACK is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/milib.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/milib.vhd
WARNING:HDLParsers:3215 - Unit work/PACK is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/milib.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/milib.vhd
WARNING:HDLParsers:3215 - Unit work/STRETCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd
WARNING:HDLParsers:3215 - Unit work/STRETCH/ARCH is now defined in a different file: was C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd, now is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/milib.vhd in Library work.
Architecture pack of Entity pack is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd in Library work.
Architecture sc_fifo512_cris_hdl of Entity sc_fifo512_cris is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd in Library work.
Architecture fifoctlr_cc_hdl of Entity fifo_255x12 is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd in Library work.
Architecture arch of Entity stretch is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd in Library work.
Architecture arch of Entity cr_registros is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd in Library work.
Architecture arch of Entity cr_fifos is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd in Library work.
Architecture arch of Entity rc_ros is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd in Library work.
Architecture arch of Entity rc_control is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd in Library work.
Architecture arch of Entity rc_reg_ctrl is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd in Library work.
Architecture arch of Entity rc_trg_ros is up to date.
Compiling vhdl file C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd in Library work.
Architecture arch of Entity rosctrl is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rosctrl> (Architecture <arch>).
    Set user-defined property "DUTY_CYCLE_CORRECTION =  true" for instance <UDLL1> in unit <rosctrl>.
INFO:Xst:1304 - Contents of register <doneout> in unit <rosctrl> never changes during circuit operation. The register is replaced by logic.
Entity <rosctrl> analyzed. Unit <rosctrl> generated.

Analyzing Entity <stretch> (Architecture <arch>).
Entity <stretch> analyzed. Unit <stretch> generated.

Analyzing Entity <cr_registros> (Architecture <arch>).
Entity <cr_registros> analyzed. Unit <cr_registros> generated.

Analyzing Entity <cr_fifos> (Architecture <arch>).
Entity <cr_fifos> analyzed. Unit <cr_fifos> generated.

Analyzing Entity <rc_ros> (Architecture <arch>).
Entity <rc_ros> analyzed. Unit <rc_ros> generated.

Analyzing Entity <rc_control> (Architecture <arch>).
Entity <rc_control> analyzed. Unit <rc_control> generated.

Analyzing Entity <fifo_255x12> (Architecture <fifoctlr_cc_hdl>).
Entity <fifo_255x12> analyzed. Unit <fifo_255x12> generated.

Analyzing Entity <rc_reg_ctrl> (Architecture <arch>).
Entity <rc_reg_ctrl> analyzed. Unit <rc_reg_ctrl> generated.

Analyzing Entity <rc_trg_ros> (Architecture <arch>).
Entity <rc_trg_ros> analyzed. Unit <rc_trg_ros> generated.

Analyzing Entity <sc_fifo512_cris> (Architecture <sc_fifo512_cris_hdl>).
Entity <sc_fifo512_cris> analyzed. Unit <sc_fifo512_cris> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sc_fifo512_cris>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd.
WARNING:Xst:646 - Signal <doutb_aux> is assigned but never used.
    Found 1-bit xor2 for signal <$n0010> created at line 237.
    Found 1-bit xor2 for signal <$n0011> created at line 238.
    Found 1-bit register for signal <empty>.
    Found 9-bit updown counter for signal <fcounter>.
    Found 1-bit register for signal <full>.
    Found 9-bit register for signal <read_addr>.
    Found 9-bit register for signal <write_addr>.
    Summary:
	inferred   1 Counter(s).
	inferred  20 D-type flip-flop(s).
Unit <sc_fifo512_cris> synthesized.


Synthesizing Unit <fifo_255x12>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd.
WARNING:Xst:646 - Signal <read_data<15:12>> is assigned but never used.
    Found 1-bit xor4 for signal <$n0011> created at line 211.
    Found 1-bit xor4 for signal <$n0012> created at line 212.
    Found 1-bit register for signal <empty>.
    Found 8-bit updown counter for signal <fcounter>.
    Found 1-bit register for signal <full>.
    Found 8-bit register for signal <read_addr>.
    Found 8-bit register for signal <write_addr>.
    Summary:
	inferred   1 Counter(s).
	inferred  18 D-type flip-flop(s).
	inferred   2 Xor(s).
Unit <fifo_255x12> synthesized.


Synthesizing Unit <rc_trg_ros>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd.
    Found finite state machine <FSM_0> for signal <secol>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 18                                             |
    | Inputs             | 8                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | soft_reset (positive)                          |
    | Reset type         | asynchronous                                   |
    | Reset State        | wait_valen                                     |
    | Power Up State     | wait_valen                                     |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 21                                             |
    | Inputs             | 8                                              |
    | Outputs            | 12                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | soft_reset (positive)                          |
    | Reset type         | asynchronous                                   |
    | Reset State        | start_event                                    |
    | Power Up State     | start_event                                    |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <trg_done>.
    Found 1-bit register for signal <ros_ready>.
    Found 1-bit register for signal <txena>.
    Found 16-bit register for signal <s_data>.
    Found 13-bit subtractor for signal <$n0005> created at line 382.
    Found 16-bit adder for signal <$n0049>.
    Found 1-bit register for signal <fblock_read>.
    Found 1-bit register for signal <sc_timed_out>.
    Found 13-bit register for signal <time_counter>.
    Found 1-bit register for signal <time_out>.
    Found 1-bit register for signal <time_start>.
    Found 16-bit register for signal <trg_data>.
    Found 1-bit register for signal <trg_strobe>.
    Found 16-bit register for signal <word_count>.
    Found 28 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred  69 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred  28 Multiplexer(s).
Unit <rc_trg_ros> synthesized.


Synthesizing Unit <rc_reg_ctrl>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd.
    Found 16-bit tristate buffer for signal <db_out>.
    Found 8-bit comparator greater for signal <$n0002> created at line 243.
    Found 8-bit comparator greater for signal <$n0003> created at line 246.
    Found 8-bit comparator greater for signal <$n0004> created at line 249.
    Found 6-bit register for signal <ceros_mask>.
    Found 4-bit register for signal <cmd_reg>.
    Found 12-bit register for signal <cr_timeout_value>.
    Found 1-bit register for signal <dis_crtimo_mask>.
    Found 1-bit register for signal <dis_L1A>.
    Found 1-bit register for signal <ena_sc_trigger>.
    Found 1-bit register for signal <ena_send_bunch>.
    Found 1-bit register for signal <ena_send_orbit>.
    Found 8-bit register for signal <fblock_count_reg_0>.
    Found 8-bit register for signal <fblock_count_reg_1>.
    Found 8-bit register for signal <fblock_count_reg_2>.
    Found 3-bit register for signal <ffull_reg>.
    Found 1-bit register for signal <read_int_scfifo>.
    Found 1-bit register for signal <resynch_ceros_to>.
    Found 1-bit register for signal <resynch_L1A_FF>.
    Found 1-bit register for signal <sc_fblock_full_reg>.
    Found 1-bit register for signal <sel_local_evid>.
    Summary:
	inferred  59 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred 224 Tristate(s).
Unit <rc_reg_ctrl> synthesized.


Synthesizing Unit <rc_control>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd.
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 28                                             |
    | Transitions        | 46                                             |
    | Inputs             | 13                                             |
    | Outputs            | 28                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | soft_reset (positive)                          |
    | Reset type         | asynchronous                                   |
    | Reset State        | wait_trigger                                   |
    | Power Up State     | wait_trigger                                   |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <txena>.
    Found 16-bit register for signal <s_data>.
    Found 1-bit register for signal <valen>.
    Found 17-bit subtractor for signal <$n0019> created at line 599.
    Found 24-bit adder for signal <$n0117> created at line 670.
    Found 12-bit register for signal <bcnt_reg>.
    Found 1-bit register for signal <bcnt_res_reg>.
    Found 1-bit register for signal <bcnt_strobe_reg>.
    Found 7-bit register for signal <ceros_id>.
    Found 6-bit register for signal <ceros_timed_out>.
    Found 1-bit register for signal <evcnt_high_strobe_reg>.
    Found 1-bit register for signal <evcnt_low_strobe_reg>.
    Found 24-bit register for signal <event_int_counter>.
    Found 12-bit register for signal <evid_p>.
    Found 1-bit register for signal <fblock_full_reg>.
    Found 1-bit register for signal <int_ev_str1>.
    Found 1-bit register for signal <int_ev_str2>.
    Found 1-bit register for signal <is_trigger_lev>.
    Found 1-bit register for signal <L1A_FF_send_error>.
    Found 1-bit register for signal <L1A_total_reg>.
    Found 24-bit up counter for signal <orbit_counter>.
    Found 1-bit register for signal <read_fblock>.
    Found 1-bit register for signal <SC_L1A_reg>.
    Found 17-bit register for signal <time_counter>.
    Found 1-bit register for signal <time_out>.
    Found 1-bit register for signal <time_start>.
    Found 1-bit register for signal <token>.
    Found 16-bit up counter for signal <trigger_counter>.
    Found 1-bit register for signal <txena_par>.
    Found 17-bit up counter for signal <word_count>.
    Found 17 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 Counter(s).
	inferred 112 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred  17 Multiplexer(s).
Unit <rc_control> synthesized.


Synthesizing Unit <rc_ros>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd.
WARNING:Xst:646 - Signal <trailer_reg<15>> is assigned but never used.
WARNING:Xst:646 - Signal <trailer_reg<11:10>> is assigned but never used.
    Found finite state machine <FSM_3> for signal <main>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | valen (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | start_event                                    |
    | Power Up State     | start_event                                    |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_4> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 40                                             |
    | Transitions        | 114                                            |
    | Inputs             | 20                                             |
    | Outputs            | 40                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | valen (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | w_command                                      |
    | Power Up State     | w_command                                      |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <lives_c4>.
    Found 1-bit register for signal <ros_done>.
    Found 12-bit comparator equal for signal <$n0036> created at line 437.
    Found 8-bit comparator not equal for signal <$n0037> created at line 523.
    Found 12-bit adder for signal <$n0104> created at line 528.
    Found 1-bit register for signal <error_evid>.
    Found 1-bit register for signal <evid_mis>.
    Found 8-bit register for signal <header1_reg>.
    Found 16-bit register for signal <header2_reg>.
    Found 1-bit register for signal <maxw_reached>.
    Found 1-bit register for signal <new_fifo>.
    Found 1-bit register for signal <read_fifo_dir>.
    Found 16-bit register for signal <s_data>.
    Found 13-bit down counter for signal <time_counter>.
    Found 1-bit register for signal <time_out>.
    Found 1-bit register for signal <time_start>.
    Found 1-bit register for signal <timed_out>.
    Found 1-bit register for signal <trail>.
    Found 16-bit register for signal <trailer_reg>.
    Found 1-bit register for signal <txena_dir>.
    Found 12-bit register for signal <word_count>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  80 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <rc_ros> synthesized.


Synthesizing Unit <cr_fifos>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd.
INFO:Xst:1608 - Relative priorities of control signals on register <fwrg1> differ from those commonly found in the selected device family. This will result in additional logic around the register.
    Found 1-bit xor2 for signal <$n0050> created at line 79.
    Found 1-bit xor2 for signal <$n0051> created at line 79.
    Found 32-bit register for signal <byte_par>.
    Found 2-bit xor8 for signal <cpar>.
    Found 16-bit up counter for signal <disparity>.
    Found 1-bit register for signal <fwrg1>.
    Found 1-bit register for signal <fwrg2>.
    Found 1-bit register for signal <fwrg3>.
    Found 1-bit register for signal <fwrg4>.
    Found 1-bit register for signal <fwrg5>.
    Found 6-bit up counter for signal <loadcnt>.
    Found 22-bit register for signal <pae_paf_reg>.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q1a>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <q3>.
    Found 1-bit register for signal <q4>.
    Found 16-bit register for signal <word_par>.
    Found 70 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Counter(s).
	inferred  58 D-type flip-flop(s).
	inferred  70 Multiplexer(s).
	inferred   2 Xor(s).
Unit <cr_fifos> synthesized.


Synthesizing Unit <cr_registros>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd.
    Found 16-bit tristate buffer for signal <db_out>.
    Found 1-bit register for signal <dis_evid_bloq>.
    Found 1-bit register for signal <dis_evid_wrong>.
    Found 1-bit register for signal <dis_ffreg_mask>.
    Found 1-bit register for signal <dis_head_trail>.
    Found 1-bit register for signal <dis_hul_mask>.
    Found 1-bit register for signal <dis_lock_mask>.
    Found 1-bit register for signal <dis_paf_warn>.
    Found 1-bit register for signal <dis_timo_mask>.
    Found 1-bit register for signal <etr_fifo_reg>.
    Found 1-bit register for signal <etr_paepaf_reg_1>.
    Found 1-bit register for signal <etr_paepaf_reg_2>.
    Found 1-bit register for signal <ff_reg>.
    Found 16-bit register for signal <fout_reg>.
    Found 1-bit register for signal <hasunlock>.
    Found 1-bit register for signal <mask>.
    Found 9-bit register for signal <nmaxwords>.
    Found 1-bit register for signal <paf_cnt_set>.
    Found 16-bit up counter for signal <paf_counter>.
    Found 1-bit register for signal <paf_reg>.
    Found 1-bit register for signal <per_fifo>.
    Found 1-bit register for signal <per_fifo_aux_2>.
    Found 1-bit register for signal <per_paepaf_reg>.
    Found 1-bit register for signal <recoff>.
    Found 1-bit register for signal <resynch_evidmis>.
    Found 1-bit register for signal <resynch_FF>.
    Found 1-bit register for signal <resynch_maxw>.
    Found 1-bit register for signal <resynch_to>.
    Found 12-bit register for signal <timeout_value>.
    Found 1-bit register for signal <warn_PAF>.
    Found 3 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  62 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred 272 Tristate(s).
Unit <cr_registros> synthesized.


Synthesizing Unit <stretch>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <q3>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <stretch> synthesized.


Synthesizing Unit <rosctrl>.
    Related source file is C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd.
    Found 16-bit tristate buffer for signal <db>.
    Found 1-bit tristate buffer for signal <txena>.
    Found 16-bit tristate buffer for signal <dout>.
    Found 1-bit register for signal <bcnt_res>.
    Found 1-bit register for signal <bcnt_strobe>.
    Found 1-bit register for signal <enw1>.
    Found 1-bit register for signal <enw2>.
    Found 1-bit register for signal <event_reset>.
    Found 1-bit register for signal <L1A>.
    Found 1-bit register for signal <reset1>.
    Found 1-bit register for signal <reset2>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred  33 Tristate(s).
Unit <rosctrl> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_4 ...
Optimizing FSM <FSM_4> on signal <state> with one-hot encoding.
Selecting encoding for FSM_3 ...
Optimizing FSM <FSM_3> on signal <main> with one-hot encoding.
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <state> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <secol> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 5
# Adders/Subtractors               : 5
 12-bit adder                      : 1
 24-bit adder                      : 1
 17-bit subtractor                 : 1
 16-bit adder                      : 1
 13-bit subtractor                 : 1
# Counters                         : 11
 13-bit down counter               : 1
 16-bit up counter                 : 3
 24-bit up counter                 : 1
 8-bit updown counter              : 3
 9-bit updown counter              : 1
 6-bit up counter                  : 1
 17-bit up counter                 : 1
# Registers                        : 361
 1-bit register                    : 338
 16-bit register                   : 9
 9-bit register                    : 1
 8-bit register                    : 4
 12-bit register                   : 5
 24-bit register                   : 1
 7-bit register                    : 1
 4-bit register                    : 1
 22-bit register                   : 1
# Comparators                      : 5
 8-bit comparator not equal        : 1
 12-bit comparator equal           : 1
 8-bit comparator greater          : 3
# Multiplexers                     : 67
 1-bit 2-to-1 multiplexer          : 64
 22-bit 2-to-1 multiplexer         : 1
 16-bit 2-to-1 multiplexer         : 2
# Tristates                        : 34
 1-bit tristate buffer             : 1
 16-bit tristate buffer            : 33
# Xors                             : 12
 1-bit xor8                        : 2
 1-bit xor4                        : 6
 1-bit xor2                        : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "fifo_sc512.ngo" is up to date.
Loading core <fifo_sc512> for timing and area information for instance <U0>.
WARNING:Xst:1291 - FF/Latch <trailer_reg_15> is unconnected in block <rc_ros>.
WARNING:Xst:1291 - FF/Latch <trailer_reg_10> is unconnected in block <rc_ros>.
WARNING:Xst:1291 - FF/Latch <trailer_reg_11> is unconnected in block <rc_ros>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <rosctrl> ...

Optimizing unit <cr_registros> ...

Optimizing unit <rc_ros> ...

Optimizing unit <rc_reg_ctrl> ...

Optimizing unit <fifo_255x12> ...

Optimizing unit <sc_fifo512_cris> ...

Optimizing unit <cr_fifos> ...

Optimizing unit <rc_control> ...

Optimizing unit <rc_trg_ros> ...
Loading device for application Xst from file '2s100e.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block rosctrl, actual ratio is 65.
FlipFlop event_reset has been replicated 1 time(s)
INFO:Xst:1843 - HDL ADVISOR - FlipFlop event_reset connected to a primary input has been replicated
FlipFlop enw1 has been replicated 1 time(s)
INFO:Xst:1843 - HDL ADVISOR - FlipFlop enw1 connected to a primary input has been replicated
FlipFlop U4_ceros_id_4 has been replicated 1 time(s)
FlipFlop U3_state_FFd29 has been replicated 1 time(s)
FlipFlop event_reset_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop bcnt_strobe has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop bcnt_res has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : rosctrl.ngr
Top Level Output File Name         : rosctrl
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 160

Macro Statistics :
# Registers                        : 299
#      1-bit register              : 270
#      12-bit register             : 5
#      16-bit register             : 9
#      24-bit register             : 1
#      4-bit register              : 1
#      7-bit register              : 1
#      8-bit register              : 4
#      9-bit register              : 8
# Counters                         : 4
#      13-bit down counter         : 1
#      16-bit up counter           : 3
# Multiplexers                     : 67
#      2-to-1 multiplexer          : 67
# Tristates                        : 34
#      1-bit tristate buffer       : 1
#      16-bit tristate buffer      : 33
# Adders/Subtractors               : 12
#      12-bit adder                : 1
#      13-bit subtractor           : 1
#      16-bit adder                : 1
#      17-bit subtractor           : 1
#      24-bit adder                : 1
#      9-bit addsub                : 7
# Comparators                      : 5
#      12-bit comparator equal     : 1
#      8-bit comparator greater    : 3
#      8-bit comparator not equal  : 1
# Xors                             : 8
#      1-bit xor4                  : 6
#      1-bit xor8                  : 2

Cell Usage :
# BELS                             : 1849
#      BUF                         : 3
#      GND                         : 2
#      LUT1                        : 143
#      LUT2                        : 185
#      LUT2_D                      : 2
#      LUT2_L                      : 9
#      LUT3                        : 201
#      LUT3_D                      : 6
#      LUT3_L                      : 112
#      LUT4                        : 553
#      LUT4_D                      : 32
#      LUT4_L                      : 138
#      MUXCY                       : 245
#      VCC                         : 1
#      XORCY                       : 217
# FlipFlops/Latches                : 785
#      FD                          : 14
#      FD_1                        : 8
#      FDC                         : 215
#      FDCE                        : 318
#      FDCPE                       : 62
#      FDE                         : 72
#      FDP                         : 19
#      FDPE                        : 77
# RAMS                             : 5
#      RAMB4_S16_S16               : 3
#      RAMB4_S8_S8                 : 2
# Tri-States                       : 496
#      BUFT                        : 496
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 159
#      IBUF                        : 86
#      IBUFG                       : 1
#      IOBUF                       : 16
#      OBUF                        : 39
#      OBUFT                       : 17
# Others                           : 1
#      CLKDLLE                     : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100eft256-7 

 Number of Slices:                     770  out of   1200    64%  
 Number of Slice Flip Flops:           785  out of   2400    32%  
 Number of 4 input LUTs:              1381  out of   2400    57%  
 Number of bonded IOBs:                159  out of    182    87%  
 Number of TBUFs:                      496  out of   1200    41%  
 Number of BRAMs:                        5  out of     10    50%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clkin_p                            | UDLL1:CLK0             | 786   |
clk_slow                           | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 12.789ns (Maximum Frequency: 78.192MHz)
   Minimum input arrival time before clock: 14.626ns
   Maximum output required time after clock: 14.363ns
   Maximum combinational path delay: 16.032ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkin_p'
Delay:               12.789ns (Levels of Logic = 3)
  Source:            enw2 (FF)
  Destination:       U2_byte_par_0 (FF)
  Source Clock:      clkin_p rising
  Destination Clock: clkin_p rising

  Data Path: enw2 to U2_byte_par_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             16   0.886   2.520  enw2 (enw2)
     LUT3_D:I2->O         14   0.418   2.385  U1_Ker335541 (U1_N33556)
     LUT4_D:I0->O         18   0.418   2.610  U1_enw_byte_par01 (enw_byte_par0)
     LUT4:I1->O           16   0.418   2.520  U2__n00841 (U2__n0084)
     FDCE:CE                   0.614          U2_byte_par_14
    ----------------------------------------
    Total                     12.789ns (2.754ns logic, 10.035ns route)
                                       (21.5% logic, 78.5% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_slow'
Delay:               2.569ns (Levels of Logic = 0)
  Source:            ULED1_q2 (FF)
  Destination:       ULED1_q3 (FF)
  Source Clock:      clk_slow rising
  Destination Clock: clk_slow rising

  Data Path: ULED1_q2 to ULED1_q3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.886   1.035  ULED1_q2 (ULED1_q2)
     FDC:D                     0.648          ULED1_q3
    ----------------------------------------
    Total                      2.569ns (1.534ns logic, 1.035ns route)
                                       (59.7% logic, 40.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkin_p'
Offset:              14.626ns (Levels of Logic = 6)
  Source:            add<2> (PAD)
  Destination:       U4_FF2_bram1 (RAM)
  Destination Clock: clkin_p rising

  Data Path: add<2> to U4_FF2_bram1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            38   0.769   3.105  add_2_IBUF (add_2_IBUF)
     LUT4:I0->O            8   0.418   1.845  U5_Ker375941 (U5_N37596)
     LUT3:I2->O            1   0.418   0.828  U5_Ker375821_SW1 (N67058)
     LUT4_D:I3->O          6   0.418   1.665  U5_enw_bcnt1 (enw_bcnt)
     LUT3:I2->O           12   0.418   2.205  U4__n01641 (U4__n0164)
     LUT4:I1->O            3   0.418   1.188  U4_fblock_data_in<10>40 (U4_fblock_data_in<10>)
     RAMB4_S16_S16:DIB10        0.931          U4_FF1_bram1
    ----------------------------------------
    Total                     14.626ns (3.790ns logic, 10.836ns route)
                                       (25.9% logic, 74.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkin_p'
Offset:              14.363ns (Levels of Logic = 3)
  Source:            U4_token (FF)
  Destination:       txena (PAD)
  Source Clock:      clkin_p rising

  Data Path: U4_token to txena
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             18   0.886   2.610  U4_token (U4_token)
     LUT2_D:I1->O         26   0.418   2.835  U4__n00031 (token<4>)
     LUT4:I0->O           17   0.418   2.565  _n0025 (_n0025)
     OBUFT:T->O                4.631          txena_OBUFT (txena)
    ----------------------------------------
    Total                     14.363ns (6.353ns logic, 8.010ns route)
                                       (44.2% logic, 55.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_slow'
Offset:              7.593ns (Levels of Logic = 2)
  Source:            ULED2_q2 (FF)
  Destination:       led<1> (PAD)
  Source Clock:      clk_slow rising

  Data Path: ULED2_q2 to led<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.886   1.035  ULED2_q2 (ULED2_q2)
     LUT1:I0->O            1   0.418   0.828  ULED2_dout1 (led_1_OBUF)
     OBUF:I->O                 4.426          led_1_OBUF (led<1>)
    ----------------------------------------
    Total                      7.593ns (5.730ns logic, 1.863ns route)
                                       (75.5% logic, 24.5% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               16.032ns (Levels of Logic = 6)
  Source:            add<1> (PAD)
  Destination:       db<0> (PAD)

  Data Path: add<1> to db<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            38   0.769   3.105  add_1_IBUF (add_1_IBUF)
     LUT2:I1->O           12   0.418   2.205  U1_Ker335861 (U1_N33588)
     LUT4:I3->O            1   0.418   0.828  U1_I35_EnableTr_INV_SW1 (N67503)
     LUT4:I1->O           16   0.418   2.520  U1_I35_EnableTr_INV (U1_I35_N2482)
     BUFT:T->O             1   0.097   0.828  U1_I35_15 (db_out<0>)
     IOBUF:I->IO               4.426          db_0_IOBUF (db<0>)
    ----------------------------------------
    Total                     16.032ns (6.546ns logic, 9.486ns route)
                                       (40.8% logic, 59.2% route)

=========================================================================
CPU : 21.74 / 23.45 s | Elapsed : 21.00 / 23.00 s
 
--> 

Total memory usage is 96356 kilobytes


