library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_misc.all;
use work.pack.all;
-- synopsys translate off;
library unisim;
use unisim.vcomponents.all;
-- synopsys translate on;

entity rosctrl is
	port (
-- general
	clkin_p, load_paepaf, mrs, reset, clk_slow: in std_logic;
	clk20_p, dll_locked_p: out std_logic;
-- vme
	etr_x, enw, cs_fifo, cs_control: in std_logic;
	add: in std_logic_vector(5 downto 0);
	db: inout std_logic_vector (15 downto 0);
-- fifos
	ef, ff, paf, lock: in std_logic;
	par: in std_logic_vector (1 downto 0);
	fout: in std_logic_vector (15 downto 0);
	hasul: out std_logic;
	fmrs, fsi, fsen, fld, wclkena_p, recoff_p: out std_logic;
--	oe: out std_logic; 
  	ren: out std_logic;
-- transmiter + control
	valen_p: out std_logic;
	token_p: out std_logic_vector (3 downto 0);
	ceros_done_p: in std_logic_vector (3 downto 0);
	txena: out std_logic;
	evid_p: out std_logic_vector (11 downto 0);
	dout: out std_logic_vector (15 downto 0);
	spaf_p, sff: out std_logic;  -- ambos act. alto
	tp: out std_logic_vector (3 downto 0); 
	txena_in: in std_logic;
	ros_waiting: out std_logic;
-- TIM
	ros_ready: out std_logic;
	trg_strobe_p: in std_logic;
	trg_data_p: in std_logic_vector (15 downto 0);
	cmd_p: in std_logic_vector (3 downto 0);
	bcnt_res_p, bcnt_strobe_p, L1A_p, SC_L1A_p: in std_logic; 
	evcnt_high_strobe_p, evcnt_low_strobe_p: in std_logic;
	bcnt_p: in std_logic_vector(11 downto 0);	 
-- varios
--	vspare: out std_logic_vector(1 downto 0);
--	fspare: out std_logic_vector(2 downto 0);
--	vspare: in std_logic_vector(1 downto 0);
	event_reset_p: in std_logic;
	lives_p: in std_logic_vector(3 downto 0);
--	fspare: in std_logic_vector(2 downto 0);
--	cspare: out std_logic_vector(1 downto 0);
	cspare_0, cspare_1: in std_logic;  --cspare_0 = soft_reset
												--cspare_1 = '1' when estado= gol_test (ROSMEM)
	led: out std_logic_vector (1 downto 0);
   is_trigger: out std_logic;
--	donein: in std_logic;
	doneout: out std_logic
	);		
end rosctrl;

architecture arch of rosctrl is
attribute box_type: string;
attribute clkdv_divide: string;
attribute duty_cycle_correction: string;

signal db_in, db_out: std_logic_vector (15 downto 0);
signal spaf: std_logic;

-- cr_registros
signal hasunlock, mask, ff_reg: std_logic; --_vector (5 downto 0);
signal dis_lock_mask, dis_hul_mask, dis_timo_mask: std_logic;
signal dis_ffreg_mask, dis_paf_warn, dis_evid_wrong: std_logic;
signal recoff: std_logic;
signal enw_word_par, enw_byte_par0, enw_byte_par1, enw_dispar,
--       etr_fifo, per_fifo, etr_paepaf, per_paepaf, enw_paf_value,
       per_fifo, per_paepaf, enw_paf_value,
	  enw_timed_out: std_logic;
signal timeout_value: std_logic_vector (11 downto 0);	

-- cr_fifos
signal wclkena, parcheck: std_logic;
signal paf_value: std_logic_vector (10 downto 0);
signal word_par: std_logic_vector(15 downto 0); 
signal byte_par: std_logic_vector(31 downto 0); 
signal disparity: std_logic_vector(15 downto 0);

-- ros & token
signal read, txena_ros, txena_control, txena_sc: std_logic;

--signal sel_read: std_logic_vector (5 downto 0);
signal s_data_ros, s_data_control, s_data_sc: std_logic_vector (15 downto 0);
signal timed_out, sc_timed_out: std_logic; --_vector (5 downto 0);

-- control
signal token, ceros_done, ceros_timed_out: std_logic_vector (5 downto 0);
signal valen, no_token: std_logic;
signal evid: std_logic_vector (11 downto 0);
signal enw_trg_counter: std_logic;
--signal enw_orbit_counter_h, enw_orbit_counter_l: std_logic;
signal trigger_counter: std_logic_vector(15 downto 0);
signal orbit_counter: std_logic_vector(23 downto 0); --(29 downto 0);

-- registros de control
signal enw_crtimed_out, dis_crtimo_mask, ena_sc_trigger, dis_L1A, local_L1A: std_logic;
signal ena_send_bunch, ena_send_orbit, sel_local_evid: std_logic; 

signal ceros_mask: std_logic_vector (5 downto 0);
signal cr_timeout_value: std_logic_vector (11 downto 0);
signal enw_bcnt, enw_evcnt_h, enw_evcnt_l, enw_trg_fblock: std_logic;
signal fblock_count_2, fblock_count_1, fblock_count_0:std_logic_vector(7 downto 0);
signal sc_fblock_count: std_logic_vector (8 downto 0); 
signal bunch_number: std_logic_vector (11 downto 0);
signal event_number: std_logic_vector (23 downto 0);

-- leds
signal disp_led, led_pulse: std_logic_vector (1 downto 0);

signal lives: std_logic_vector(5 downto 0);
signal soft_reset:std_logic;

--components
component cr_fifos port (
	clk, reset: in std_logic;
	read, load_paepaf, mrs: in std_logic;
--	sel_etr: in std_logic_vector (2 downto 0);
--	sel_read: in std_logic_vector (5 downto 0);
	fout, db_in: in std_logic_vector (15 downto 0);
	par: in std_logic_vector (1 downto 0);
	fmrs, fsi, fsen, fld, wclkena: out std_logic;
--	oe, ren: out std_logic_vector(5 downto 0);
	ren: out std_logic;
-- cr_registros
--	etr_fifo, per_fifo, etr_paepaf, per_paepaf, enw_paf_value: in std_logic;
	per_fifo, per_paepaf, enw_paf_value: in std_logic;
	enw_word_par, enw_byte_par0, enw_byte_par1, enw_dispar: in std_logic;
	paf_value: out std_logic_vector (10 downto 0);
	word_par_p: out std_logic_vector(15 downto 0); 
	byte_par_p: out std_logic_vector(31 downto 0); 
	disparity_p: out std_logic_vector(15 downto 0);
	parcheck_p: out std_logic
	);		
end component;

component cr_registros port (
	clk, reset,reset_largo: in std_logic;
	soft_reset: in std_logic;
-- vme
	etr_x, enw_x, cs: in std_logic;
	add: in std_logic_vector(5 downto 0);
	db_in: in std_logic_vector (15 downto 0);
	db_out: out std_logic_vector (15 downto 0);
	fout: in std_logic_vector (15 downto 0);
-- control de registros
	enw_paf_value_p, enw_word_par, enw_byte_par0 , enw_byte_par1, enw_dispar,
--	etr_fifo_p, per_fifo_p, etr_paepaf_p, per_paepaf_p, enw_timed_out: out std_logic;
	per_fifo_p, per_paepaf_p, enw_timed_out: out std_logic;
-- mascaras e inhabilitacion de mascaras
	dis_lock_mask_p, dis_hul_mask_p, dis_timo_mask_p, recoff_p: out std_logic;
	dis_ffreg_mask_p, dis_paf_warn_p, dis_evid_wrong_p, dis_head_trail_p: out std_logic;
	dis_evid_bloq_p, enw_evid_mis: out std_logic;
	mask_p, hasunlock_p, ff_reg_p: out std_logic;
--
	timeout_value_p: out std_logic_vector ( 11 downto 0);
	enw_maxw: out std_logic;
	maxw_reached_p: in std_logic;
	nmaxwords_p: out std_logic_vector (8 downto 0);
--
	resynch_to_p, resynch_evidmis_p, warn_PAF_p: out std_logic;
	resynch_FF_p, resynch_maxw_p: out std_logic;
--
	blocked: in std_logic;
	lock, timed_out, paf, ef, ff, evid_mis: in std_logic;
	paf_value: in std_logic_vector (10 downto 0);
	word_par: in std_logic_vector(15 downto 0); 
	byte_par: in std_logic_vector(31 downto 0); 
	disparity: in std_logic_vector(15 downto 0)
	);
end component;

component rc_ros port (
	clk: in std_logic;
	--reset: in std_logic;
	soft_reset:in std_logic;
-- 
	valen, hastoken, parcheck: in std_logic;
	evid: in std_logic_vector(11 downto 0);
--	ceros_id: in std_logic_vector (1 downto 0);
	txena_p, read_fifo_p, ros_done: out std_logic;
	lives_c4: out std_logic;
	fout: in std_logic_vector(15 downto 0);
	s_data_p: out std_logic_vector(15 downto 0);
	ef, mask: in std_logic; --_vector(5 downto 0);
	db_in: in std_logic; --_vector(5 downto 0);
--	sel_read_p: out std_logic_vector(5 downto 0);
	hasunlock, paf, ff, ff_reg, lock: in std_logic; --_vector(5 downto 0);
	timed_out_p: out std_logic; --_vector(5 downto 0);
	evid_mis_p: out std_logic;--_vector(5 downto 0);
   enw_evid_mis: in std_logic;
	dis_timo_mask: in std_logic;
	enw_timed_out, dis_paf_warn, dis_evid_wrong, dis_head_trail: in std_logic;  
   dis_evid_bloq: in std_logic;
	timeout_value: in std_logic_vector(11 downto 0);
	enw_maxw: in std_logic;
	maxw_reached_p: out std_logic;
	nmaxwords_p: in std_logic_vector (8 downto 0);
	--
	resynch_to_p, resynch_evidmis_p, warn_PAF_p: in std_logic;
	resynch_FF_p, resynch_maxw_p: in std_logic
	);
end component;

component rc_control port (
-- general
	clk, reset, reset_largo: in std_logic;
	soft_reset:in std_logic;
	db_in: in std_logic_vector (15 downto 0);

-- transmiter + control
	valen, is_trigger_p, valen_sc: out std_logic;
	token_p: out std_logic_vector (5 downto 0);
	ceros_done: in std_logic_vector (5 downto 0);
	txena: out std_logic;
	txena_in: in std_logic;
	evid: out std_logic_vector (11 downto 0);
	s_data: out std_logic_vector (15 downto 0);

-- TIM
	event_reset:in std_logic;
	bcnt_res, bcnt_strobe, L1A, SC_L1A, local_L1A: in std_logic; 
	evcnt_high_strobe, evcnt_low_strobe: in std_logic;
	bcnt: in std_logic_vector(11 downto 0);
	enw_trg_counter: in std_logic;
--	enw_orbit_counter_l, enw_orbit_counter_h: in std_logic;
	enw_evint_counter: in std_logic;
	trigger_counter_p: out std_logic_vector(15 downto 0);
	orbit_counter_p: out std_logic_vector(23 downto 0);--(29 downto 0);
	event_int_counter_p: out std_logic_vector(11 downto 0);
	fblock_full_p: out std_logic_vector(2 downto 0);
   resynch_L1A_FF: in std_logic;
	resynch_ceros_to: in std_logic;
-- mascaras, registros, time out
	enw_crtimed_out, dis_crtimo_mask, ena_sc_trigger, dis_L1A: in std_logic;
	ena_send_bunch, ena_send_orbit, sel_local_evid: in std_logic; 
	ceros_mask: in std_logic_vector (5 downto 0);
	sc_timed_out: in std_logic;
	ceros_timed_out_p: out std_logic_vector (5 downto 0);
	lives:in std_logic_vector(5 downto 0);
	cr_timeout_value: in std_logic_vector (11 downto 0);
	enw_bcnt, enw_evcnt_h, enw_evcnt_l: in std_logic;
	fblock_count_2_p, fblock_count_1_p, fblock_count_0_p: out std_logic_vector (7 downto 0); 
	bunch_number_p: out std_logic_vector (11 downto 0);
	event_number_p: out std_logic_vector (23 downto 0);
	ros_waiting: out std_logic
	);
end component;

component rc_reg_ctrl port (
	clk, reset: in std_logic;
	--reset_largo: in std_logic;
	soft_reset: in std_logic;
-- vme
	etr_x, enw_x, cs: in std_logic;
	add: in std_logic_vector(5 downto 0);
	db_in: in std_logic_vector (15 downto 0);
	db_out: out std_logic_vector (15 downto 0);
-- control de registros
	enw_crtimed_out: out std_logic;
	enw_bcnt, enw_evcnt_h, enw_evcnt_l, enw_trg_fblock: out std_logic;
	fblock_count_2, fblock_count_1, fblock_count_0: in std_logic_vector (7 downto 0); 
	sc_fblock_count: in std_logic_vector (8 downto 0);
	bunch_number: in std_logic_vector (11 downto 0);
	event_number: in std_logic_vector (23 downto 0);	 
	enw_trg_counter: out std_logic;
--	enw_orbit_counter_h, enw_orbit_counter_l: out std_logic;
	enw_evint_counter:out std_logic;
	trigger_counter: in std_logic_vector(15 downto 0);
	orbit_counter: in std_logic_vector(23 downto 0);--(29 downto 0);
	event_int_counter: in std_logic_vector(11 downto 0);
	fblock_full_p: in std_logic_vector(2 downto 0);
	resynch_L1A_FF_p:out std_logic;
	resynch_ceros_to_p:out std_logic;
-- mascaras, time out e inhabilitacion de mascaras
 	read_int_scfifo_p: out std_logic;
	cmd: in std_logic_vector (3 downto 0);

	dis_crtimo_mask_p, ena_sc_trigger_p, dis_L1A_p, local_L1A: out std_logic;
	ena_send_bunch_p, ena_send_orbit_p, sel_local_evid_p: out std_logic; 
	ceros_mask_p: out std_logic_vector(5 downto 0);
	cr_timeout_value_p: out std_logic_vector (11 downto 0);
	sc_fblock_full: in std_logic; --domingo 9-04-06
	ceros_timed_out: in std_logic_vector(5 downto 0)
	);		
end component;

component rc_trg_ros port (
-- general
	clk, reset, soft_reset: in std_logic;
--	reset_largo: in std_logic;
	db_in: in std_logic_vector (15 downto 0);
	enw_fblock: in std_logic;

-- transmiter + control
	valen, token, valen_sc: in std_logic;
	trg_done: out std_logic;
	lives_sc: out std_logic;
	txena: out std_logic;
	evid: in std_logic_vector (11 downto 0);
	s_data: out std_logic_vector (15 downto 0);

-- TIM
	ros_ready: out std_logic;
	trg_strobe_in: in std_logic;
	trg_data_in: in std_logic_vector (15 downto 0);

-- mascaras, registros, time out
	enw_crtimed_out, dis_crtimo_mask, ena_trg_data, read_int_scfifo: in std_logic;
	sc_timed_out_p, sc_fblock_full: out std_logic;
	cr_timeout_value: in std_logic_vector (11 downto 0);
	sc_fblock_count_p: out std_logic_vector (8 downto 0) 
	);		
end component;

component stretch port (
	clk_1, clk_2, din, reset: in std_logic;
	dout: out std_logic
	);		
end component;

-- GSR
--cr signal GSR: std_logic;
--cr component startup_spartan2
--cr   port(GSR: in std_logic);
--cr end component;

-- DLL
signal CLKIN, CLK, CLK0, CLK20, DLL_LOCKED, GND : std_logic;
 
component CLKDLLE
-- synthesis translate_off
	generic(clkdv_divide: real :=2.0)
-- synthesis translate_on
      port (CLKIN, CLKFB, RST : in STD_LOGIC;
      CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;
attribute box_type of clkdlle: component is "black_box";
attribute duty_cycle_correction of clkdlle: component is "true";

---------------------------------------------------------------

component IBUFG
     port (I : in STD_LOGIC; O : out std_logic);
end component;
component BUFG
    port (I : in STD_LOGIC; O : out std_logic);
end component;
component OBUF
    port (I : in STD_LOGIC; O : out std_logic);
end component;
attribute box_type of ibufg: component is "black_box";
attribute box_type of bufg: component is "black_box";
attribute box_type of obuf: component is "black_box";


signal trg_strobe: std_logic;
signal trg_data: std_logic_vector (15 downto 0);
signal cmd:  std_logic_vector (3 downto 0);
signal bcnt_res, bcnt_strobe, L1A, SC_L1A:  std_logic; 
signal evcnt_high_strobe, evcnt_low_strobe:  std_logic;
signal bcnt:  std_logic_vector(11 downto 0);	 
signal lives_sc, lives_c4: std_logic;
signal is_trigger_aux: std_logic;
signal fblock_full_p: std_logic_vector(2 downto 0);
signal reset_largo, reset1, reset2: std_logic;
signal read_int_scfifo:std_logic;
signal dis_head_trail: std_logic;
signal blocked, notblocked: std_logic;
signal sc_fblock_full: std_logic;
signal valen_sc: std_logic;

signal enw_evid_mis,dis_evid_bloq,evid_mis: std_logic;
signal enw_evint_counter: std_logic;
signal event_int_counter: std_logic_vector(11 downto 0);
signal event_reset: std_logic;

signal maxw_reached_p:  std_logic;
signal nmaxwords_p:  std_logic_vector (8 downto 0);
signal enw_maxw: std_logic;

	  
signal resynch_to_p, resynch_evidmis_p, warn_PAF_p:  std_logic;
signal resynch_FF_p, resynch_maxw_p:  std_logic;
signal resynch_L1A_FF_p: std_logic;

signal enw_x,enw1,enw2:std_logic;
signal resynch_ceros_to: std_logic;
signal goltest: std_logic;

begin

process (clk, reset)
begin
	if reset='1' then
			enw1 <= '0';
			enw2 <= '0';
	elsif clk'event and clk='1' then
			enw1 <= enw;
			enw2 <= enw1;
	end if;
end process;
enw_x <= enw1 and not(enw2);

trg_strobe <= trg_strobe_p;
trg_data <= trg_data_p;
cmd <= cmd_p;
SC_L1A <= SC_L1A_p;
evcnt_high_strobe <= evcnt_high_strobe_p;
evcnt_low_strobe <= evcnt_low_strobe_p;
bcnt <= bcnt_p;

--lives <= lives_sc & lives_c4 & lives_p;
--lives <= lives_sc & lives_c4 & vspare(0) & fspare;
lives <= lives_sc & lives_c4 & lives_p;

--event_reset <= vspare(1);


--CRIS ENERO event_reset <= event_reset_p;
process(clk)
begin
	if clk'event and clk='0' then
		event_reset <= event_reset_p;
		bcnt_res <= bcnt_res_p;
		bcnt_strobe <= bcnt_strobe_p;
		L1A <= L1A_p;
	end if;
end process;
--		bcnt_res <= bcnt_res_p;


 
-- temporales
--cspare(0) <= '0'; --wclkena & token (2);

--cspare(1) <= '0' when or_reduce(cmd)='0'  else 'Z';
---------------
GND <= '0';
tp(0)<= bcnt_res;	 --TP0 J1
tp(1)<= clk;  --TP 1 J2
tp(2)<= bcnt_strobe;
--tp(0)<= ceros_done(5);	 --TP0 J1
--tp(1)<= token(5);  --TP 1 J2
--tp(2)<= valen; --TP2 J3
--tp(0)<= clk;	 --TP0 J1
--tp(1)<= evcnt_high_strobe;  --TP 1 J2
--tp(2)<= bcnt(0); --TP2 J3
tp(3) <= event_reset;
--tp(3) <= '1' when lives="000001" else '0'; --J4
is_trigger <= is_trigger_aux;

--vspare <= "00";
--fspare <= "000";
wclkena_p <= wclkena;
--recoff_p <= recoff or wclkena;
recoff_p <= not(recoff or wclkena);
spaf_p <= spaf;
--doneout <= '0';


process(clk)
begin
	if clk'event and clk='1' then
		doneout <= '0';
	end if;
end process;
---
token_p <= token (3 downto 0);
ceros_done(3 downto 0) <= ceros_done_p;
valen_p <= valen;
evid_p <= evid;

-- LEDS
-- inputs
disp_led(0) <= valen;
disp_led(1) <= L1A_p;
--outputs
led (0) <= led_pulse(0);
led (1) <= led_pulse(1);

ULED1: stretch port map(clk, clk_slow, disp_led(0), reset, led_pulse(0));
ULED2: stretch port map(clk, clk_slow, disp_led(1), reset, led_pulse(1));

---- DLL 1
UBUF1: IBUFG port map (I=>CLKIN_P, O=>CLKIN);
UDLL1: CLKDLLE 
-- synthesis translate_off
		generic map (dlldv_divide=>2.0);
-- synthesis translate_on
		port map (CLKIN=>CLKIN, CLKFB=>CLK, RST=>GND, CLK0=>CLK0, CLKDV=>CLK20, 
		LOCKED=>DLL_LOCKED, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>open);
UBUF2: BUFG port map (I=>CLK0, O=>CLK);
UBUF3: OBUF port map (I=>CLK20, O=>CLK20_P);
UBUF4: OBUF port map (I=>DLL_LOCKED, O=>DLL_LOCKED_P);
--------

process(clk)
begin
	if clk'event and clk='1' then
		reset1 <= reset;
		reset2 <= reset1;
	end if;
end process;

reset_largo <= reset1 or reset2 or reset;


soft_reset <= reset_largo or cspare_0; 

U1: cr_registros port map(
	clk=>clk, reset=>reset, --: in std_logic;
	soft_reset=>soft_reset,
	reset_largo=> reset_largo,
-- vme
	etr_x=>etr_x, enw_x=>enw_x, cs=>cs_fifo, --: in std_logic;
	add=>add, --: in std_logic_vector(6 downto 0);
	db_in=>db_in, --: in std_logic_vector (15 downto 0);
	db_out=>db_out, --: out std_logic_vector (15 downto 0);
	fout=>fout, --: in std_logic_vector (15 downto 0);
--
	enw_paf_value_p=>enw_paf_value, enw_word_par=>enw_word_par, enw_byte_par0=>enw_byte_par0, 
	enw_byte_par1=>enw_byte_par1, enw_dispar=>enw_dispar,
--	etr_fifo_p=>etr_fifo, per_fifo_p=>per_fifo, etr_paepaf_p=>etr_paepaf, 
	per_fifo_p=>per_fifo, 
	per_paepaf_p=>per_paepaf, enw_timed_out=>enw_timed_out,
	dis_lock_mask_p=>dis_lock_mask, dis_hul_mask_p=>dis_hul_mask, 
	dis_timo_mask_p=>dis_timo_mask, recoff_p=>recoff, --: out std_logic;
	dis_ffreg_mask_p=>dis_ffreg_mask, dis_paf_warn_p=>dis_paf_warn,
	dis_evid_wrong_p=>dis_evid_wrong,
	dis_head_trail_p=>dis_head_trail,
	dis_evid_bloq_p=>dis_evid_bloq,
	enw_evid_mis=>enw_evid_mis,
	mask_p=>mask , hasunlock_p=>hasunlock, ff_reg_p=>ff_reg, --: out std_logic_vector (5 downto 0);
	timeout_value_p=>timeout_value, --: out std_logic_vector ( 11 downto 0);
--
	enw_maxw => enw_maxw,
	maxw_reached_p => maxw_reached_p,
	nmaxwords_p=> nmaxwords_p,
--
	resynch_to_p=> resynch_to_p, resynch_evidmis_p=> resynch_evidmis_p,
	warn_PAF_p => warn_PAF_p,
	resynch_FF_p=> resynch_FF_p, resynch_maxw_p=> resynch_maxw_p,
--
	blocked=>blocked,
	lock=>lock, timed_out=>timed_out, paf=>paf, ef=>ef, ff=>ff, --: in std_logic_vector (5 downto 0);
	evid_mis=>evid_mis,
	paf_value=>paf_value, --: in std_logic_vector (10 downto 0);
	word_par=>word_par, --: in std_logic_vector(15 downto 0); 
	byte_par=>byte_par, --: in std_logic_vector(31 downto 0); 
	disparity=>disparity --: in std_logic_vector(15 downto 0);
	);

U2: cr_fifos port map(
	clk=>clk, reset=>reset, --: in std_logic;
	read=>read, load_paepaf=>load_paepaf, mrs=>mrs, --: in std_logic;
--	sel_etr=>add(2 downto 0), sel_read=>sel_read, 
	fout=>fout, db_in=>db_in, --: in std_logic_vector (15 downto 0);
	par=>par, --: in std_logic_vector (1 downto 0);
	fmrs=>fmrs, fsi=>fsi, fsen=>fsen, fld=>fld, wclkena=>wclkena, --: out std_logic;
--	oe=>oe, ren=>ren, --: out std_logic_vector(5 downto 0);
	ren=>ren, --: out std_logic_vector(5 downto 0);
-- cr_registros
--	etr_fifo=>etr_fifo, per_fifo=>per_fifo, etr_paepaf=>etr_paepaf,
	per_fifo=>per_fifo,
	per_paepaf=>per_paepaf, enw_paf_value=>enw_paf_value, --: in std_logic;
	enw_word_par=>enw_word_par, enw_byte_par0=>enw_byte_par0, 
	enw_byte_par1=>enw_byte_par1, enw_dispar=>enw_dispar, --: in std_logic;
	paf_value=>paf_value, --: out std_logic_vector (10 downto 0);
	word_par_p=>word_par, --: out std_logic_vector(15 downto 0); 
	byte_par_p=>byte_par, --: out std_logic_vector(31 downto 0); 
	disparity_p=>disparity, --: out std_logic_vector(15 downto 0)
	parcheck_p=>parcheck	
	);

U3: rc_ros port map (
	clk=>clk, 
	--reset=>reset, --: in std_logic;
	soft_reset=>soft_reset,
-- 
	valen=>valen, hastoken=>token(4), parcheck=>parcheck, --: in std_logic;
	evid=>evid, --: in std_logic_vector(11 downto 0);
--	ceros_id=>ceros_id, --: in std_logic_vector (1 downto 0);
	txena_p=>txena_ros, read_fifo_p=>read, ros_done=>ceros_done(4), --: out std_logic;
	lives_c4=>lives_c4,
	fout=>fout, --: in std_logic_vector(15 downto 0);
	s_data_p=>s_data_ros, --: out std_logic_vector(15 downto 0);
	ef=>ef, mask=>mask, --: in std_logic_vector(5 downto 0);
	db_in=>db_in(0), --(5 downto 0), --: in std_logic_vector(15 downto 0);
--	sel_read_p=>sel_read, --: out std_logic_vector(5 downto 0);
	hasunlock=>hasunlock, paf=>paf, ff=>ff, ff_reg=>ff_reg, lock=>lock, --: in std_logic_vector(5 downto 0);
	timed_out_p=>timed_out, --: out std_logic_vector(5 downto 0);
	evid_mis_p=>evid_mis,
	enw_evid_mis=>enw_evid_mis,
	dis_timo_mask=>dis_timo_mask,
	enw_timed_out=>enw_timed_out, dis_paf_warn=>dis_paf_warn, 
	dis_evid_wrong=>dis_evid_wrong, --: in std_logic
	dis_head_trail=> dis_head_trail,
	dis_evid_bloq => dis_evid_bloq,
	timeout_value=>timeout_value, --in std_logic_vector (11 downto 0) 
	enw_maxw => enw_maxw,
	maxw_reached_p => maxw_reached_p,
	nmaxwords_p=> nmaxwords_p,
--
	resynch_to_p=> resynch_to_p, resynch_evidmis_p=> resynch_evidmis_p,
	warn_PAF_p => warn_PAF_p,
	resynch_FF_p=> resynch_FF_p, resynch_maxw_p=> resynch_maxw_p
	);

U4: rc_control port map(
-- general
	clk=>clk, reset=>reset, --: in std_logic;
	soft_reset=> soft_reset,
   reset_largo=> reset_largo,
	db_in=>db_in, --: in std_logic_vector (15 downto 0);

-- transmiter + control
	valen=>valen, is_trigger_p=>is_trigger_aux, --: out std_logic;
	valen_sc=> valen_sc,
	token_p=>token, --: out std_logic_vector (4 downto 0);
	ceros_done=>ceros_done, --: in std_logic_vector (4 downto 0);
	lives=>lives,
	txena=>txena_control, --: out std_logic;
	txena_in=>txena_in, --: in std_logic;
	evid=>evid, --: out std_logic_vector (11 downto 0);
	s_data=>s_data_control, --: out std_logic_vector (15 downto 0);

-- TIM
	event_reset=>event_reset,
	bcnt_res=>bcnt_res, bcnt_strobe=>bcnt_strobe, L1A=>L1A, SC_L1A=>SC_L1A,
	local_L1A=>local_L1A,  --: in std_logic; 
	evcnt_high_strobe=>evcnt_high_strobe, 
	evcnt_low_strobe=>evcnt_low_strobe, --: in std_logic;
	bcnt=>bcnt, --: in std_logic_vector(11 downto 0);
	enw_trg_counter=>enw_trg_counter, 
	--enw_orbit_counter_h=>enw_orbit_counter_h, 
   --enw_orbit_counter_l=>enw_orbit_counter_l, --: in std_logic;
	enw_evint_counter=>enw_evint_counter,
	trigger_counter_p=>trigger_counter, 
	orbit_counter_p=>orbit_counter, --: out std_logic_vector(15 downto 0);
	event_int_counter_p=>event_int_counter,
   fblock_full_p=>fblock_full_p, --out(2 downto 0) a los registros
	resynch_L1A_FF=>resynch_L1A_FF_p,
	resynch_ceros_to=>resynch_ceros_to,
-- mascaras, registros, time out
	enw_crtimed_out=>enw_crtimed_out, 
	dis_crtimo_mask=>dis_crtimo_mask, 
	ena_sc_trigger=>ena_sc_trigger, 
	dis_L1A=>dis_L1A, --: in std_logic;
	ena_send_bunch=>ena_send_bunch, ena_send_orbit=>ena_send_orbit, 
   sel_local_evid=>sel_local_evid, --: in std_logic; 
	ceros_mask=>ceros_mask, --: in std_logic_vector (4 downto 0);
	sc_timed_out=> sc_timed_out,
	ceros_timed_out_p=>ceros_timed_out, --: out std_logic_vector (4 downto 0);
	cr_timeout_value=>cr_timeout_value, --: in std_logic_vector (11 downto 0)
	enw_bcnt=>enw_bcnt, enw_evcnt_h=>enw_evcnt_h, 
	enw_evcnt_l=>enw_evcnt_l, --: in std_logic
	fblock_count_2_p=>fblock_count_2, fblock_count_1_p=>fblock_count_1, 
	fblock_count_0_p=>fblock_count_0, --: out std_logic_vector (7 downto 0);
	bunch_number_p=>bunch_number, --: out std_logic_vector (11 downto 0);
	event_number_p=>event_number, --: out std_logic_vector (23 downto 0) 
	ros_waiting=>ros_waiting --: out std_logic
	);

U5:  rc_reg_ctrl port map(
	clk=>clk, reset=>reset,
	-- reset_largo=>reset_largo, --: in std_logic;
	soft_reset=>soft_reset,
-- vme
	etr_x=>etr_x, enw_x=>enw_x, cs=>cs_control, --: in std_logic;
	add=>add, --: in std_logic_vector(5 downto 0);
	db_in=>db_in, --: in std_logic_vector (15 downto 0);
	db_out=>db_out, --: out std_logic_vector (15 downto 0);
-- control de registros
	enw_crtimed_out=>enw_crtimed_out, --: out std_logic;
	enw_bcnt=>enw_bcnt, enw_evcnt_h=>enw_evcnt_h, 
	enw_evcnt_l=>enw_evcnt_l, enw_trg_fblock=>enw_trg_fblock, --: out std_logic
	fblock_count_2=>fblock_count_2, fblock_count_1=>fblock_count_1, 
	fblock_count_0=>fblock_count_0, 
	sc_fblock_count=>sc_fblock_count, --: in std_logic_vector (8 downto 0);
	bunch_number=>bunch_number, --: in std_logic_vector (11 downto 0);
	event_number=>event_number, --: in std_logic_vector (23 downto 0);	 
	enw_trg_counter=>enw_trg_counter,
	-- enw_orbit_counter_h=>enw_orbit_counter_h, 
 --  enw_orbit_counter_l=>enw_orbit_counter_l, --: out std_logic;
	enw_evint_counter => enw_evint_counter,
	trigger_counter=>trigger_counter, 
	orbit_counter=>orbit_counter, --: in std_logic_vector(15 downto 0);
	event_int_counter=> event_int_counter,
	fblock_full_p=>fblock_full_p,
	resynch_L1A_FF_p=> resynch_L1A_FF_p,
	resynch_ceros_to_p=>resynch_ceros_to,
-- mascaras, time out e inhabilitacion de mascaras
	read_int_scfifo_p=>read_int_scfifo,
  	cmd=>cmd,
 
 	dis_crtimo_mask_p=>dis_crtimo_mask, 
	ena_sc_trigger_p=>ena_sc_trigger, dis_L1A_p=>dis_L1A, 
	local_L1A=>local_L1A, --: out std_logic;
	ena_send_bunch_p=>ena_send_bunch, ena_send_orbit_p=>ena_send_orbit,
   sel_local_evid_p=>sel_local_evid, --: out std_logic; 
	ceros_mask_p=>ceros_mask, --: out std_logic_vector(4 downto 0);
	cr_timeout_value_p=>cr_timeout_value, --: out std_logic_vector (11 downto 0);
	sc_fblock_full => sc_fblock_full,--domingo 9-04-06
	ceros_timed_out=>ceros_timed_out --: in std_logic_vector(4 downto 0)
	);		

U6: rc_trg_ros port map(
-- general
	clk=>clk, reset=>reset, --: in std_logic;
	soft_reset=>soft_reset,
--	reset_largo=> reset_largo,
	db_in=>db_in, --: in std_logic_vector (15 downto 0);
	enw_fblock=>enw_trg_fblock, --: in std_logic;

-- transmiter + control
	valen=>valen, token=>token(5), --: in std_logic;
	valen_sc=> valen_sc,
	trg_done=>ceros_done(5), --: out std_logic;
	lives_sc=>lives_sc,
	txena=>txena_sc, --: out std_logic;
	evid=>evid, --: in std_logic_vector (15 downto 0);
	s_data=>s_data_sc, --: out std_logic_vector (15 downto 0);

-- TIM
	ros_ready=>ros_ready, --: out std_logic;
	trg_strobe_in=>trg_strobe, --: in std_logic;
	trg_data_in=>trg_data, --: in std_logic_vector (15 downto 0);

-- mascaras, registros, time out
	enw_crtimed_out=>enw_crtimed_out, 
	dis_crtimo_mask=>dis_crtimo_mask,
	ena_trg_data=>not(ceros_mask(5)), --:in 
	read_int_scfifo=>read_int_scfifo,
	sc_timed_out_p=>sc_timed_out, --: out std_logic;
	sc_fblock_full=> sc_fblock_full,
	cr_timeout_value=>cr_timeout_value, --: in std_logic_vector (11 downto 0);
	sc_fblock_count_p=>sc_fblock_count --: out std_logic_vector (8 downto 0) 
	);		

db_in <= db;
db <= db_out when (cs_fifo='1' or cs_control='1') and etr_x='0' 
	else (others => 'Z');

--hasul a 0 bloquea, a 1 ok, deja pasar lo que sea
hasul <= notblocked;
blocked <= not(notblocked);
notblocked <= (not(mask) and   --mask a 1 enmascara, ok igual que en registro
		(not(hasunlock) or dis_hul_mask) and --hasunlock a 0=se ha desenganchado
		(not(lock) or dis_lock_mask) and 	-- lock act. bajo
		(not(timed_out) or dis_timo_mask) and  --timed_out a 1=timedout
		(not(maxw_reached_p) or dis_timo_mask) and  --maxwords=1=>bloqueo
		(not(ff_reg) or dis_ffreg_mask)) and	--ff_reg a 1=fifo full
		(not(evid_mis) or dis_evid_bloq);

sff <= ff; --or_reduce(ff);	 -- FF activo alto
spaf <= not paf; --and_reduce(paf); -- PAF activo bajo

-- send data & txena
no_token <= not or_reduce (token);

dout <= s_data_ros when token(4)='1' and goltest='0' else
	   s_data_sc when token(5)='1' and goltest='0' else 
	   s_data_control when no_token='1' and goltest='0'  else 
		(others => 'Z');

txena <= txena_ros when token(4)='1' and goltest='0' else
	    txena_sc when token(5)='1' and goltest='0' else 
	    txena_control when no_token='1' and goltest='0' else
		   'Z';

goltest <= cspare_1;

end arch;



	
