V1 59
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd 2007/01/12.16:15:36
EN work/SC_FIFO512_CRIS \
      FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED
AR work/SC_FIFO512_CRIS/SC_FIFO512_CRIS_HDL \
      FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd \
      EN work/SC_FIFO512_CRIS CP FIFO_SC512
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd 2007/01/03.10:55:24
EN work/RC_TRG_ROS      FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_ARITH \
      PB ieee/STD_LOGIC_MISC PB work/PACK
AR work/RC_TRG_ROS/ARCH FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd \
      EN work/RC_TRG_ROS CP SC_FIFO512_CRIS
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_trg_ros.vhd 2007/01/03.09:55:24
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/sc_fifo512_cris.vhd 2007/01/12.15:15:36
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd 2006/05/15.12:36:16
EN work/CR_FIFOS        FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_ARITH \
      PB ieee/STD_LOGIC_MISC PB work/PACK
AR work/CR_FIFOS/ARCH   FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd \
      EN work/CR_FIFOS
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd 2005/03/03.14:55:14
EN work/STRETCH         FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd \
      PB ieee/STD_LOGIC_1164
AR work/STRETCH/ARCH    FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd \
      EN work/STRETCH
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/stretch.vhd 2005/03/03.13:55:14
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/milib.vhd 2005/02/05.14:33:24
PH work/PACK            FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/milib.vhd \
      PB ieee/STD_LOGIC_1164
PB work/PACK            FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/milib.vhd \
      PH work/PACK
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/milib.vhd 2005/02/05.13:33:24
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd 2006/03/17.10:33:30
EN work/FIFO_255X12     FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED
AR work/FIFO_255X12/FIFOCTLR_CC_HDL \
      FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd \
      EN work/FIFO_255X12 CP RAMB4_S16_S16
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd 2007/01/08.18:18:26
EN work/RC_REG_CTRL     FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_ARITH \
      PB ieee/STD_LOGIC_MISC PB work/PACK
AR work/RC_REG_CTRL/ARCH \
      FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd \
      EN work/RC_REG_CTRL
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd 2007/01/25.09:51:22
EN work/ROSCTRL         FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_ARITH \
      PB ieee/STD_LOGIC_MISC PB work/PACK
AR work/ROSCTRL/ARCH    FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd \
      EN work/ROSCTRL   CP STRETCH        CP IBUFG          CP CLKDLLE        CP BUFG \
      CP OBUF           CP CR_REGISTROS   CP CR_FIFOS       CP RC_ROS \
      CP RC_CONTROL     CP RC_REG_CTRL    CP RC_TRG_ROS
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rosctrl.vhd 2007/01/25.08:51:22
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd 2007/01/03.09:45:18
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_fifos.vhd 2006/05/15.12:36:16
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_reg_ctrl.vhd 2007/01/08.17:18:26
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/fifo_255x12.vhd 2006/03/17.09:33:30
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd 2007/01/25.09:51:36
EN work/RC_CONTROL      FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_ARITH \
      PB ieee/STD_LOGIC_MISC PB work/PACK
AR work/RC_CONTROL/ARCH FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd \
      EN work/RC_CONTROL CP FIFO_255X12
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd 2007/01/03.10:52:50
EN work/RC_ROS          FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_MISC \
      PB ieee/STD_LOGIC_ARITH PB work/PACK
AR work/RC_ROS/ARCH     FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd \
      EN work/RC_ROS
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_control.vhd 2007/01/25.08:51:36
FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd 2007/01/03.10:45:18
EN work/CR_REGISTROS    FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_ARITH \
      PB ieee/STD_LOGIC_MISC PB work/PACK
AR work/CR_REGISTROS/ARCH \
      FL C:/CRIS/CMS/VHDL/PARA_FINAL/rosctrl_100/rc_registros.vhd \
      EN work/CR_REGISTROS
FL C:/DATOSLAB/VHDL/PARA_FINAL/rosctrl_100/rc_ros_cris.vhd 2007/01/03.09:52:50
