### Equations

cspare(0) <= '0';
cspare(10) <= vspare_0;
cspare(11) <= (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1);
FDCPE_estado_FFD2: FDCPE port map (estado_FFD2,estado_FFD2_D,clk,reset,'0','1'); estado_FFD2_D <= NOT (((estado_FFD3 AND estado_FFD1) OR (ena_ceros_mem AND N_PZ_30322) OR (N_PZ_30322 AND NOT ena_gol_test) OR (NOT estado_FFD2 AND estado_FFD1 AND NOT enw1.COMB)
OR (estado_FFD2 AND estado_FFD3 AND NOT ena_ceros_mem AND
NOT estado_FFD1 AND NOT ena_gol_test)));
FTCPE_estado_FFD3: FTCPE port map (estado_FFD3,estado_FFD3_T,clk,reset,'0','1'); estado_FFD3_T <= ((NOT estado_FFD3 AND estado_FFD1 AND N_PZ_30599) OR (NOT ena_ceros_mem AND N_PZ_30322 AND ena_gol_test) OR (estado_FFD2 AND NOT estado_FFD3 AND NOT estado_FFD1 AND
NOT is_trigger)
OR (estado_FFD2 AND estado_FFD3 AND NOT ena_ceros_mem AND
NOT estado_FFD1 AND NOT ena_gol_test));
FTCPE_ena_ceros_mem: FTCPE port map (ena_ceros_mem,ena_ceros_mem_T,clk,reset,'0','1'); ena_ceros_mem_T <= ((NOT ena_ceros_mem AND N_PZ_30413 AND db(1).PIN) OR (estado_FFD2 AND estado_FFD3 AND ena_ceros_mem AND NOT estado_FFD1) OR (ena_ceros_mem AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND
NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN));
FDCPE_estado_FFD1: FDCPE port map (estado_FFD1,estado_FFD1_D,clk,reset,'0','1'); estado_FFD1_D <= NOT (((NOT estado_FFD1 AND estado_XX_FFD153) OR (NOT estado_FFD2 AND NOT estado_FFD3 AND estado_XX_FFD153 AND estado_XX_FFD146) OR (NOT estado_FFD2 AND estado_XX_FFD153 AND NOT ena_gol_test AND
estado_XX_FFD146)
OR (NOT estado_FFD3 AND NOT ena_ceros_mem AND estado_XX_FFD153 AND
estado_XX_FFD146)
OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
estado_XX_FFD146 AND mem_is_full)
OR (NOT estado_FFD2 AND estado_XX_FFD153 AND
estado_XX_FFD146 AND NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2)
OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
estado_XX_FFD146 AND NOT ena_event_count AND NOT Mcompar__n0026__n0034 AND
NOT U4/ena_word_count2)
OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
estado_XX_FFD146 AND ena_event_count AND mevent_count(10) AND
mevent_count(8) AND counter(10) AND counter(8) AND NOT Mcompar__n0029__n0027 AND
NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)
OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
estado_XX_FFD146 AND ena_event_count AND mevent_count(10) AND
NOT mevent_count(8) AND counter(10) AND NOT counter(8) AND NOT Mcompar__n0029__n0027 AND
NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)
OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
estado_XX_FFD146 AND ena_event_count AND NOT mevent_count(10) AND
mevent_count(8) AND NOT counter(10) AND counter(8) AND NOT Mcompar__n0029__n0027 AND
NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)
OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
estado_XX_FFD146 AND ena_event_count AND NOT mevent_count(10) AND
NOT mevent_count(8) AND NOT counter(10) AND NOT counter(8) AND NOT Mcompar__n0029__n0027 AND
NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)));
estado_XX_FFD153 <= ((estado_FFD2) OR (estado_FFD1) OR (estado_FFD3 AND NOT ena_cycles) OR (NOT estado_FFD3 AND NOT ena_ceros_mem AND NOT ena_gol_test) OR (estado_FFD3 AND NOT cycle_counter(0) AND
NOT cycle_counter(14) AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
NOT cycle_counter(8) AND NOT cycle_counter(9) AND NOT cycle_counter(11) AND
NOT cycle_counter(12) AND NOT cycle_counter(13) AND NOT cycle_counter(15)));
db(5) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(5).PIN) OR (ena_cycles AND NOT add(2) AND NOT add(1) AND NOT add(0) AND N_PZ_30373) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(5) AND N_PZ_30373)
OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(5) AND
N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(5) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(5) AND
N_PZ_30373));FDCPE_ena_cycles: FDCPE port map (ena_cycles,db(5).PIN,clk,reset,'0',N_PZ_30413);
N_PZ_30413 <= ((NOT estado_FFD2 AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2) OR (NOT estado_FFD3 AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2)
OR (estado_FFD1 AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND
NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2));
enw1.COMB <= (is_trigger AND NOT is_trigger_1);FDCPE_enw1: FDCPE port map (enw1,enw_x,clk,reset,'0','1');
FDCPE_enw2: FDCPE port map (enw2,enw1,clk,reset,'0','1');
_n0086_MC.GLB <= ((cs AND NOT etr) OR (write AND N_PZ_30322 AND N_PZ_30489));
N_PZ_30322 <= (NOT estado_FFD2 AND NOT estado_FFD3 AND NOT estado_FFD1);
N_PZ_30489 <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND NOT ds1 AND NOT ds0 AND am(4) AND am(3) AND NOT brdsel24);
FTCPE_ena_gol_test: FTCPE port map (ena_gol_test,ena_gol_test_T,clk,reset,'0','1'); ena_gol_test_T <= ((estado_FFD2 AND estado_FFD3 AND NOT estado_FFD1 AND ena_gol_test) OR (N_PZ_30413 AND NOT ena_gol_test AND NOT db(1).PIN AND db(0).PIN)
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND ena_gol_test AND
db(1).PIN)
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND ena_gol_test AND
NOT db(0).PIN));
FDCPE_cycle_counter0: FDCPE port map (cycle_counter(0),cycle_counter_D(0),clk,reset,'0','1'); cycle_counter_D(0) <= NOT (((cycle_counter(0) AND N_PZ_30371) OR (N_PZ_30322 AND NOT N_PZ_30371 AND NOT num_cycles(0)) OR (NOT N_PZ_30322 AND NOT cycle_counter(0) AND NOT N_PZ_30371)));
N_PZ_30371 <= (estado_FFD2 AND estado_FFD3 AND estado_FFD1);
FDCPE_num_cycles0: FDCPE port map (num_cycles(0),db(0).PIN,clk,reset,'0',num_cycles_CE(0)); num_cycles_CE(0) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FDCPE_cycle_counter14: FDCPE port map (cycle_counter(14),cycle_counter_D(14),clk,reset,'0','1'); cycle_counter_D(14) <= NOT (((N_PZ_30371 AND NOT _n0033(14)2) OR (N_PZ_30322 AND NOT num_cycles(14) AND NOT _n0033(14)2) OR (NOT N_PZ_30322 AND NOT cycle_counter(14) AND NOT _n0033(14)2)));
FDCPE_num_cycles14: FDCPE port map (num_cycles(14),db(14).PIN,clk,reset,'0',num_cycles_CE(14)); num_cycles_CE(14) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
_n0033(14)2 <= (N_PZ_30371 AND cycle_counter(14)) XOR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
NOT cycle_counter(9) AND NOT cycle_counter(11) AND NOT cycle_counter(12) AND
NOT cycle_counter(13));
FTCPE_cycle_counter10: FTCPE port map (cycle_counter(10),cycle_counter_T(10),clk,reset,'0','1'); cycle_counter_T(10) <= ((N_PZ_30322 AND NOT cycle_counter(10) AND num_cycles(10)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(10) AND NOT num_cycles(10))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
NOT cycle_counter(8) AND NOT cycle_counter(9)));
FDCPE_num_cycles10: FDCPE port map (num_cycles(10),db(10).PIN,clk,reset,'0',num_cycles_CE(10)); num_cycles_CE(10) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter1: FTCPE port map (cycle_counter(1),cycle_counter_T(1),clk,reset,'0','1'); cycle_counter_T(1) <= ((NOT cycle_counter(0) AND N_PZ_30371) OR (N_PZ_30322 AND NOT cycle_counter(1) AND num_cycles(1)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(1) AND
NOT num_cycles(1)));
FDCPE_num_cycles1: FDCPE port map (num_cycles(1),db(1).PIN,clk,reset,'0',num_cycles_CE(1)); num_cycles_CE(1) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter2: FTCPE port map (cycle_counter(2),cycle_counter_T(2),clk,reset,'0','1'); cycle_counter_T(2) <= ((N_PZ_30322 AND NOT cycle_counter(2) AND num_cycles(2)) OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(2) AND
NOT num_cycles(2)));
FDCPE_num_cycles2: FDCPE port map (num_cycles(2),db(2).PIN,clk,reset,'0',num_cycles_CE(2)); num_cycles_CE(2) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter3: FTCPE port map (cycle_counter(3),cycle_counter_T(3),clk,reset,'0','1'); cycle_counter_T(3) <= ((N_PZ_30322 AND NOT cycle_counter(3) AND num_cycles(3)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(3) AND NOT num_cycles(3))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2)));
FDCPE_num_cycles3: FDCPE port map (num_cycles(3),db(3).PIN,clk,reset,'0',num_cycles_CE(3)); num_cycles_CE(3) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter4: FTCPE port map (cycle_counter(4),cycle_counter_T(4),clk,reset,'0','1'); cycle_counter_T(4) <= ((N_PZ_30322 AND NOT cycle_counter(4) AND num_cycles(4)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(4) AND NOT num_cycles(4))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3)));
FDCPE_num_cycles4: FDCPE port map (num_cycles(4),db(4).PIN,clk,reset,'0',num_cycles_CE(4)); num_cycles_CE(4) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter5: FTCPE port map (cycle_counter(5),cycle_counter_T(5),clk,reset,'0','1'); cycle_counter_T(5) <= ((N_PZ_30322 AND NOT cycle_counter(5) AND num_cycles(5)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(5) AND NOT num_cycles(5))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4)));
FDCPE_num_cycles5: FDCPE port map (num_cycles(5),db(5).PIN,clk,reset,'0',num_cycles_CE(5)); num_cycles_CE(5) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter6: FTCPE port map (cycle_counter(6),cycle_counter_T(6),clk,reset,'0','1'); cycle_counter_T(6) <= ((N_PZ_30322 AND NOT cycle_counter(6) AND num_cycles(6)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(6) AND NOT num_cycles(6))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
NOT cycle_counter(5)));
FDCPE_num_cycles6: FDCPE port map (num_cycles(6),db(6).PIN,clk,reset,'0',num_cycles_CE(6)); num_cycles_CE(6) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter7: FTCPE port map (cycle_counter(7),cycle_counter_T(7),clk,reset,'0','1'); cycle_counter_T(7) <= ((N_PZ_30322 AND NOT cycle_counter(7) AND num_cycles(7)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(7) AND NOT num_cycles(7))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
NOT cycle_counter(5) AND NOT cycle_counter(6)));
FDCPE_num_cycles7: FDCPE port map (num_cycles(7),db(7).PIN,clk,reset,'0',num_cycles_CE(7)); num_cycles_CE(7) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter8: FTCPE port map (cycle_counter(8),cycle_counter_T(8),clk,reset,'0','1'); cycle_counter_T(8) <= ((N_PZ_30322 AND NOT cycle_counter(8) AND num_cycles(8)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(8) AND NOT num_cycles(8))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7)));
FDCPE_num_cycles8: FDCPE port map (num_cycles(8),db(8).PIN,clk,reset,'0',num_cycles_CE(8)); num_cycles_CE(8) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter9: FTCPE port map (cycle_counter(9),cycle_counter_T(9),clk,reset,'0','1'); cycle_counter_T(9) <= ((N_PZ_30322 AND NOT cycle_counter(9) AND num_cycles(9)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(9) AND NOT num_cycles(9))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
NOT cycle_counter(8)));
FDCPE_num_cycles9: FDCPE port map (num_cycles(9),db(9).PIN,clk,reset,'0',num_cycles_CE(9)); num_cycles_CE(9) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter11: FTCPE port map (cycle_counter(11),cycle_counter_T(11),clk,reset,'0','1'); cycle_counter_T(11) <= ((N_PZ_30322 AND NOT cycle_counter(11) AND num_cycles(11)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(11) AND NOT num_cycles(11))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND
NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
NOT cycle_counter(9)));
FDCPE_num_cycles11: FDCPE port map (num_cycles(11),db(11).PIN,clk,reset,'0',num_cycles_CE(11)); num_cycles_CE(11) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter12: FTCPE port map (cycle_counter(12),cycle_counter_T(12),clk,reset,'0','1'); cycle_counter_T(12) <= ((N_PZ_30322 AND NOT cycle_counter(12) AND num_cycles(12)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(12) AND NOT num_cycles(12))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND
NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
NOT cycle_counter(9) AND NOT cycle_counter(11)));
FDCPE_num_cycles12: FDCPE port map (num_cycles(12),db(12).PIN,clk,reset,'0',num_cycles_CE(12)); num_cycles_CE(12) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter13: FTCPE port map (cycle_counter(13),cycle_counter_T(13),clk,reset,'0','1'); cycle_counter_T(13) <= ((N_PZ_30322 AND NOT cycle_counter(13) AND num_cycles(13)) OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(13) AND NOT num_cycles(13))
OR (NOT cycle_counter(0) AND N_PZ_30371 AND
NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
NOT cycle_counter(9) AND NOT cycle_counter(11) AND NOT cycle_counter(12)));
FDCPE_num_cycles13: FDCPE port map (num_cycles(13),db(13).PIN,clk,reset,'0',num_cycles_CE(13)); num_cycles_CE(13) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
FTCPE_cycle_counter15: FTCPE port map (cycle_counter(15),cycle_counter_T(15),clk,reset,'0','1'); cycle_counter_T(15) <= ((N_PZ_30322 AND NOT cycle_counter(15) AND num_cycles(15)) OR (N_PZ_30371 AND NOT cycle_counter(14) AND _n0033(14)2) OR (NOT cycle_counter(14) AND _n0033(14)2 AND
NOT cycle_counter(15))
OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(15) AND
NOT num_cycles(15)));
FDCPE_num_cycles15: FDCPE port map (num_cycles(15),db(15).PIN,clk,reset,'0',num_cycles_CE(15)); num_cycles_CE(15) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2);
estado_XX_FFD146 <= ((estado_FFD2) OR (estado_FFD3) OR (ena_event_count AND NOT mevent_count(0) AND NOT mevent_count(10) AND NOT mevent_count(11) AND NOT mevent_count(12) AND NOT mevent_count(13) AND NOT mevent_count(14) AND NOT mevent_count(15) AND
NOT mevent_count(1) AND NOT mevent_count(2) AND NOT mevent_count(3) AND
NOT mevent_count(4) AND NOT mevent_count(5) AND NOT mevent_count(6) AND
NOT mevent_count(7) AND NOT mevent_count(8) AND NOT mevent_count(9) AND enw1.COMB));
db(3) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(3).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(3) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(3) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(3) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(3) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND ena_event_count AND
N_PZ_30373));FDCPE_ena_event_count: FDCPE port map (ena_event_count,db(3).PIN,clk,reset,'0',N_PZ_30413);
db(0) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(0).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(0) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(0) AND N_PZ_30373)
OR (add(2) AND NOT add(1) AND NOT add(0) AND mword_count(16) AND
N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(0) AND
N_PZ_30373)
OR (NOT add(2) AND add(1) AND NOT add(0) AND mem_pointer(16) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(0) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND ena_gol_test AND
N_PZ_30373));FDCPE_mevent_count0: FDCPE port map (mevent_count(0),db(0).PIN,clk,reset,'0',mevent_count_CE(0));
mevent_count_CE(0) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count10: FDCPE port map (mevent_count(10),db(10).PIN,clk,reset,'0',mevent_count_CE(10)); mevent_count_CE(10) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
db(11) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(11).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(11) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(11) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(11) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(11) AND
N_PZ_30373));FDCPE_mevent_count11: FDCPE port map (mevent_count(11),db(11).PIN,clk,reset,'0',mevent_count_CE(11));
mevent_count_CE(11) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
db(12) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(12).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(12) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(12) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(12) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(12) AND
N_PZ_30373));FDCPE_mevent_count12: FDCPE port map (mevent_count(12),db(12).PIN,clk,reset,'0',mevent_count_CE(12));
mevent_count_CE(12) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
db(13) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(13).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(13) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(13) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(13) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(13) AND
N_PZ_30373));FDCPE_mevent_count13: FDCPE port map (mevent_count(13),db(13).PIN,clk,reset,'0',mevent_count_CE(13));
mevent_count_CE(13) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
db(14) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(14).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(14) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(14) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(14) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(14) AND
N_PZ_30373));FDCPE_mevent_count14: FDCPE port map (mevent_count(14),db(14).PIN,clk,reset,'0',mevent_count_CE(14));
mevent_count_CE(14) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
db(15) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(15).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(15) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(15) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(15) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(15) AND
N_PZ_30373));FDCPE_mevent_count15: FDCPE port map (mevent_count(15),db(15).PIN,clk,reset,'0',mevent_count_CE(15));
mevent_count_CE(15) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
db(1) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(1).PIN) OR (ena_ceros_mem AND NOT add(2) AND NOT add(1) AND NOT add(0) AND N_PZ_30373) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(1) AND N_PZ_30373)
OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(1) AND
N_PZ_30373)
OR (add(2) AND NOT add(1) AND NOT add(0) AND mword_count(17) AND
N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(1) AND
N_PZ_30373)
OR (NOT add(2) AND add(1) AND NOT add(0) AND mem_pointer(17) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(1) AND
N_PZ_30373));FDCPE_mevent_count1: FDCPE port map (mevent_count(1),db(1).PIN,clk,reset,'0',mevent_count_CE(1));
mevent_count_CE(1) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count2: FDCPE port map (mevent_count(2),db(2).PIN,clk,reset,'0',mevent_count_CE(2)); mevent_count_CE(2) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count3: FDCPE port map (mevent_count(3),db(3).PIN,clk,reset,'0',mevent_count_CE(3)); mevent_count_CE(3) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
db(4) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(4).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(4) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(4) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(4) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(4) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND U4/ena_fill_mem AND
N_PZ_30373));FDCPE_mevent_count4: FDCPE port map (mevent_count(4),db(4).PIN,clk,reset,'0',mevent_count_CE(4));
mevent_count_CE(4) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count5: FDCPE port map (mevent_count(5),db(5).PIN,clk,reset,'0',mevent_count_CE(5)); mevent_count_CE(5) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count6: FDCPE port map (mevent_count(6),db(6).PIN,clk,reset,'0',mevent_count_CE(6)); mevent_count_CE(6) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count7: FDCPE port map (mevent_count(7),db(7).PIN,clk,reset,'0',mevent_count_CE(7)); mevent_count_CE(7) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count8: FDCPE port map (mevent_count(8),db(8).PIN,clk,reset,'0',mevent_count_CE(8)); mevent_count_CE(8) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mevent_count9: FDCPE port map (mevent_count(9),db(9).PIN,clk,reset,'0',mevent_count_CE(9)); mevent_count_CE(9) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2);
FDCPE_mem_is_full: FDCPE port map (mem_is_full,mem_is_full_D,clk,reset,'0','1'); mem_is_full_D <= ((mem_is_full AND NOT U4/_n0051) OR (NOT mem_is_full AND NOT U4/_n0051 AND NOT mem_pointer(0) AND tp7 AND mem_pointer(10) AND mem_pointer(4) AND mem_pointer(1) AND mem_pointer(2) AND
mem_pointer(3) AND mem_pointer(5) AND mem_pointer(6) AND mem_pointer(7) AND
mem_pointer(8) AND mem_pointer(9) AND mem_pointer(11) AND
mem_pointer(12) AND mem_pointer(13) AND mem_pointer(14) AND
mem_pointer(15) AND mem_pointer(16) AND mem_pointer(17)));
U4/_n0051 <= (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(2).PIN);
FDCPE_mem_pointer0: FDCPE port map (mem_pointer(0),mem_pointer_D(0),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(0) <= ((mem_is_full AND mem_pointer(0) AND NOT U4/_n0081) OR (mem_pointer(0) AND NOT U4/_n0081 AND NOT tp7) OR (NOT mem_is_full AND NOT mem_pointer(0) AND NOT U4/_n0081 AND tp7)
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(0))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(0).PIN));
U4/_n0081 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2));
tp7 <= NOT (((NOT inc_pointer) OR (NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2 AND ena_random AND cspare(11))));
FDCPE_inc_pointer: FDCPE port map (inc_pointer,inc_pointer_D,clk,reset,'0','1'); inc_pointer_D <= NOT (NOT estado_FFD3 XOR ((estado_FFD3 AND NOT estado_FFD1 AND NOT inc_pointer) OR (estado_FFD3 AND N_PZ_30322 AND NOT _n003432) OR (estado_FFD3 AND N_PZ_30371 AND NOT _n003432)
OR (NOT estado_FFD3 AND estado_FFD1 AND _n003432)
OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
NOT ena_gol_test AND NOT _n003432)
OR (estado_FFD2 AND NOT estado_FFD3 AND NOT mem_is_full AND
txena_reg_in AND is_trigger AND _n003432)
OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2 AND NOT _n003432)
OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
NOT txena_out AND NOT ena_random AND NOT _n003432)
OR (estado_FFD3 AND estado_FFD1 AND NOT ena_event_count AND
NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2 AND NOT _n003432)
OR (estado_FFD3 AND estado_FFD1 AND mem_is_full AND
NOT txena_out AND NOT ena_random AND NOT _n003432)
OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
ena_random AND U4/ena_lfsr(0) AND NOT U4/lfsr_0(40) AND NOT _n003432)
OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
ena_random AND U4/ena_lfsr(1) AND NOT U4/lfsr_1(30) AND NOT _n003432)
OR (estado_FFD3 AND estado_FFD1 AND mem_is_full AND
ena_random AND U4/ena_lfsr(0) AND NOT U4/lfsr_0(40) AND NOT _n003432)
OR (estado_FFD3 AND estado_FFD1 AND mem_is_full AND
ena_random AND U4/ena_lfsr(1) AND NOT U4/lfsr_1(30) AND NOT _n003432)
OR (estado_FFD2 AND NOT estado_FFD3 AND NOT estado_FFD1 AND
NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT mem_is_full AND txena_reg_in AND
is_trigger)
OR (estado_FFD2 AND NOT estado_FFD3 AND ena_ceros_mem AND
estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND ena_event_count AND
NOT mem_is_full AND txena_reg_in)
OR (estado_FFD2 AND NOT estado_FFD3 AND ena_ceros_mem AND
estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT mem_is_full AND
txena_reg_in AND Mcompar__n0026__n0034)
OR (estado_FFD2 AND NOT estado_FFD3 AND ena_ceros_mem AND
estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT mem_is_full AND
txena_reg_in AND U4/ena_word_count2)));
txena <= (cspare(11) AND txena_reg_out); txena <= txena_I when txena_OE = '1' else 'Z'; txena_OE <= (NOT estado_FFD2 AND estado_FFD3);FDCPE_txena_reg_in: FDCPE port map (txena_reg_in,txena.PIN,clk,reset,'0','1');
Mcompar__n0026__n0034 <= ((Mcompar__n0026__n003420) OR (counter(10) AND NOT mword_count(10)) OR (NOT counter(10) AND mword_count(10)) OR (counter(8) AND NOT mword_count(8)) OR (NOT counter(8) AND mword_count(8))
OR (counter(4) AND NOT mword_count(4))
OR (NOT counter(4) AND mword_count(4))
OR (counter(5) AND NOT mword_count(5))
OR (NOT counter(5) AND mword_count(5))
OR (counter(6) AND NOT mword_count(6))
OR (NOT counter(6) AND mword_count(6))
OR (counter(7) AND NOT mword_count(7))
OR (NOT counter(7) AND mword_count(7))
OR (counter(9) AND NOT mword_count(9))
OR (NOT counter(9) AND mword_count(9))
OR (counter(11) AND NOT mword_count(11))
OR (NOT counter(11) AND mword_count(11))
OR (counter(13) AND NOT mword_count(13))
OR (NOT counter(13) AND mword_count(13))
OR (counter(14) AND NOT mword_count(14))
OR (NOT counter(14) AND mword_count(14)));
FDCPE_counter10: FDCPE port map (counter(10),counter_D(10),clk,reset,'0','1'); counter_D(10) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(8) AND N_PZ_30589 AND counter(9));
FDCPE_counter8: FDCPE port map (counter(8),counter_D(8),clk,reset,'0','1'); counter_D(8) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(8) AND NOT N_PZ_30589) OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT counter(8) AND N_PZ_30589));
N_PZ_30589 <= (counter(2) AND N_PZ_30591 AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7));
FDCPE_counter2: FDCPE port map (counter(2),counter_D(2),clk,reset,'0','1'); counter_D(2) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND NOT N_PZ_30591) OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT counter(2) AND N_PZ_30591));
N_PZ_30591 <= ((N_PZ_30322 AND counter(0) AND counter(1)) OR (N_PZ_30371 AND counter(0) AND counter(1)) OR (estado_FFD2 AND estado_FFD1 AND txena_reg_in AND counter(0) AND NOT U4/ena_word_count2 AND counter(1)) OR (estado_FFD3 AND estado_FFD1 AND counter(0) AND
NOT U4/ena_word_count2 AND txena_out AND counter(1))
OR (NOT estado_FFD3 AND estado_FFD1 AND ena_event_count AND
enw1.COMB AND counter(0) AND counter(1)));
FTCPE_counter0: FTCPE port map (counter(0),counter_T(0),clk,reset,'0','1'); counter_T(0) <= ((N_PZ_30322 AND counter(0)) OR (N_PZ_30371 AND counter(0)) OR (estado_FFD2 AND estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND txena_reg_in AND NOT U4/ena_word_count2)
OR (estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
NOT N_PZ_30371 AND NOT U4/ena_word_count2 AND txena_out)
OR (NOT estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
NOT N_PZ_30371 AND ena_event_count AND enw1.COMB));
U4/ena_word_count2 <= (NOT U4/ena_fill_mem AND NOT U4/ena_word_count_reg);
FTCPE_U4/ena_fill_mem: FTCPE port map (U4/ena_fill_mem,U4/ena_fill_mem_T,clk,reset,'0','1'); U4/ena_fill_mem_T <= ((N_PZ_30413 AND db(4).PIN AND NOT U4/ena_fill_mem) OR (estado_FFD2 AND estado_FFD3 AND NOT estado_FFD1 AND U4/ena_fill_mem) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(4).PIN AND
U4/ena_fill_mem));
db(2) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(2).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(2) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(2) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(2) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(2) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND NOT U4/ena_word_count2 AND
N_PZ_30373));FDCPE_U4/ena_word_count_reg: FDCPE port map (U4/ena_word_count_reg,db(2).PIN,clk,reset,'0',N_PZ_30413);
FDCPE_txena_out: FDCPE port map (txena_out,txena_out_D,clk,reset,'0','1'); txena_out_D <= NOT (((NOT cspare(11)) OR (txena_out AND NOT ena_random) OR (ena_random AND U4/ena_lfsr(0) AND NOT U4/lfsr_0(40)) OR (ena_random AND U4/ena_lfsr(1) AND NOT U4/lfsr_1(30))));
db(6) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(6).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(6) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(6) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(6) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(6) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND ena_random AND
N_PZ_30373));FDCPE_ena_random: FDCPE port map (ena_random,db(6).PIN,clk,reset,'0',N_PZ_30413);
db(7) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(7).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(7) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(7) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(7) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(7) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND U4/ena_lfsr(0) AND
N_PZ_30373));FDCPE_U4/ena_lfsr0: FDCPE port map (U4/ena_lfsr(0),db(7).PIN,clk,reset,'0',N_PZ_30413);
FDCPE_U4/lfsr_040: FDCPE port map (U4/lfsr_0(40),U4/lfsr_0(39),clk,reset,'0','1');
FDCPE_U4/lfsr_039: FDCPE port map (U4/lfsr_0(39),U4/lfsr_0(38),clk,reset,'0','1');
FDCPE_U4/lfsr_038: FDCPE port map (U4/lfsr_0(38),U4/lfsr_0(37),clk,reset,'0','1');
FDCPE_U4/lfsr_037: FDCPE port map (U4/lfsr_0(37),U4/lfsr_0(36),clk,reset,'0','1');
FDCPE_U4/lfsr_036: FDCPE port map (U4/lfsr_0(36),U4/lfsr_0(35),clk,reset,'0','1');
FDCPE_U4/lfsr_035: FDCPE port map (U4/lfsr_0(35),U4/lfsr_0(34),clk,reset,'0','1');
FDCPE_U4/lfsr_034: FDCPE port map (U4/lfsr_0(34),U4/lfsr_0(33),clk,reset,'0','1');
FDCPE_U4/lfsr_033: FDCPE port map (U4/lfsr_0(33),U4/lfsr_0(32),clk,reset,'0','1');
FDCPE_U4/lfsr_032: FDCPE port map (U4/lfsr_0(32),U4/lfsr_0(31),clk,reset,'0','1');
FDCPE_U4/lfsr_031: FDCPE port map (U4/lfsr_0(31),U4/lfsr_0(30),clk,reset,'0','1');
FDCPE_U4/lfsr_030: FDCPE port map (U4/lfsr_0(30),U4/lfsr_0(29),clk,reset,'0','1');
FDCPE_U4/lfsr_029: FDCPE port map (U4/lfsr_0(29),U4/lfsr_0(28),clk,reset,'0','1');
FDCPE_U4/lfsr_028: FDCPE port map (U4/lfsr_0(28),U4/lfsr_0(27),clk,reset,'0','1');
FDCPE_U4/lfsr_027: FDCPE port map (U4/lfsr_0(27),U4/lfsr_0(26),clk,reset,'0','1');
FDCPE_U4/lfsr_026: FDCPE port map (U4/lfsr_0(26),U4/lfsr_0(25),clk,reset,'0','1');
FDCPE_U4/lfsr_025: FDCPE port map (U4/lfsr_0(25),U4/lfsr_0(24),clk,reset,'0','1');
FDCPE_U4/lfsr_024: FDCPE port map (U4/lfsr_0(24),U4/lfsr_0(23),clk,reset,'0','1');
FDCPE_U4/lfsr_023: FDCPE port map (U4/lfsr_0(23),U4/lfsr_0(22),clk,reset,'0','1');
FDCPE_U4/lfsr_022: FDCPE port map (U4/lfsr_0(22),U4/lfsr_0(21),clk,reset,'0','1');
FDCPE_U4/lfsr_021: FDCPE port map (U4/lfsr_0(21),U4/lfsr_0(20),clk,reset,'0','1');
FDCPE_U4/lfsr_020: FDCPE port map (U4/lfsr_0(20),U4/lfsr_0(19),clk,reset,'0','1');
FDCPE_U4/lfsr_019: FDCPE port map (U4/lfsr_0(19),U4/lfsr_0(18),clk,reset,'0','1');
FDCPE_U4/lfsr_018: FDCPE port map (U4/lfsr_0(18),U4/lfsr_0(17),clk,reset,'0','1');
FDCPE_U4/lfsr_017: FDCPE port map (U4/lfsr_0(17),U4/lfsr_0(16),clk,reset,'0','1');
FDCPE_U4/lfsr_016: FDCPE port map (U4/lfsr_0(16),U4/lfsr_0(15),clk,reset,'0','1');
FDCPE_U4/lfsr_015: FDCPE port map (U4/lfsr_0(15),U4/lfsr_0(14),clk,reset,'0','1');
FDCPE_U4/lfsr_014: FDCPE port map (U4/lfsr_0(14),U4/lfsr_0(13),clk,reset,'0','1');
FDCPE_U4/lfsr_013: FDCPE port map (U4/lfsr_0(13),U4/lfsr_0(12),clk,reset,'0','1');
FDCPE_U4/lfsr_012: FDCPE port map (U4/lfsr_0(12),U4/lfsr_0(11),clk,reset,'0','1');
FDCPE_U4/lfsr_011: FDCPE port map (U4/lfsr_0(11),U4/lfsr_0(10),clk,reset,'0','1');
FDCPE_U4/lfsr_010: FDCPE port map (U4/lfsr_0(10),U4/lfsr_0(9),clk,reset,'0','1');
FDCPE_U4/lfsr_09: FDCPE port map (U4/lfsr_0(9),U4/lfsr_0(8),clk,reset,'0','1');
FDCPE_U4/lfsr_08: FDCPE port map (U4/lfsr_0(8),U4/lfsr_0(7),clk,reset,'0','1');
FDCPE_U4/lfsr_07: FDCPE port map (U4/lfsr_0(7),U4/lfsr_0(6),clk,reset,'0','1');
FDCPE_U4/lfsr_06: FDCPE port map (U4/lfsr_0(6),U4/lfsr_0(5),clk,reset,'0','1');
FDCPE_U4/lfsr_05: FDCPE port map (U4/lfsr_0(5),U4/lfsr_0(4),clk,reset,'0','1');
FDCPE_U4/lfsr_04: FDCPE port map (U4/lfsr_0(4),U4/lfsr_0(3),clk,reset,'0','1');
FDCPE_U4/lfsr_03: FDCPE port map (U4/lfsr_0(3),U4/lfsr_0(2),clk,reset,'0','1');
FDCPE_U4/lfsr_02: FDCPE port map (U4/lfsr_0(2),U4/lfsr_0(1),clk,reset,'0','1');
FDCPE_U4/lfsr_01: FDCPE port map (U4/lfsr_0(1),U4/lfsr_0(0),clk,reset,'0','1');
FDCPE_U4/lfsr_00: FDCPE port map (U4/lfsr_0(0),U4/lfsr_0_D(0),clk,reset,'0','1'); U4/lfsr_0_D(0) <= ((U4/lfsr_0(40) AND U4/lfsr_0(37)) OR (NOT U4/lfsr_0(40) AND NOT U4/lfsr_0(37)));
db(8) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(8).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(8) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(8) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(8) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(8) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND U4/ena_lfsr(1) AND
N_PZ_30373));FDCPE_U4/ena_lfsr1: FDCPE port map (U4/ena_lfsr(1),db(8).PIN,clk,reset,'0',N_PZ_30413);
FDCPE_U4/lfsr_130: FDCPE port map (U4/lfsr_1(30),U4/lfsr_1(29),clk,reset,'0','1');
FDCPE_U4/lfsr_129: FDCPE port map (U4/lfsr_1(29),U4/lfsr_1(28),clk,reset,'0','1');
FDCPE_U4/lfsr_128: FDCPE port map (U4/lfsr_1(28),U4/lfsr_1(27),clk,reset,'0','1');
FDCPE_U4/lfsr_127: FDCPE port map (U4/lfsr_1(27),U4/lfsr_1(26),clk,reset,'0','1');
FDCPE_U4/lfsr_126: FDCPE port map (U4/lfsr_1(26),U4/lfsr_1(25),clk,reset,'0','1');
FDCPE_U4/lfsr_125: FDCPE port map (U4/lfsr_1(25),U4/lfsr_1(24),clk,reset,'0','1');
FDCPE_U4/lfsr_124: FDCPE port map (U4/lfsr_1(24),U4/lfsr_1(23),clk,reset,'0','1');
FDCPE_U4/lfsr_123: FDCPE port map (U4/lfsr_1(23),U4/lfsr_1(22),clk,reset,'0','1');
FDCPE_U4/lfsr_122: FDCPE port map (U4/lfsr_1(22),U4/lfsr_1(21),clk,reset,'0','1');
FDCPE_U4/lfsr_121: FDCPE port map (U4/lfsr_1(21),U4/lfsr_1(20),clk,reset,'0','1');
FDCPE_U4/lfsr_120: FDCPE port map (U4/lfsr_1(20),U4/lfsr_1(19),clk,reset,'0','1');
FDCPE_U4/lfsr_119: FDCPE port map (U4/lfsr_1(19),U4/lfsr_1(18),clk,reset,'0','1');
FDCPE_U4/lfsr_118: FDCPE port map (U4/lfsr_1(18),U4/lfsr_1(17),clk,reset,'0','1');
FDCPE_U4/lfsr_117: FDCPE port map (U4/lfsr_1(17),U4/lfsr_1(16),clk,reset,'0','1');
FDCPE_U4/lfsr_116: FDCPE port map (U4/lfsr_1(16),U4/lfsr_1(15),clk,reset,'0','1');
FDCPE_U4/lfsr_115: FDCPE port map (U4/lfsr_1(15),U4/lfsr_1(14),clk,reset,'0','1');
FDCPE_U4/lfsr_114: FDCPE port map (U4/lfsr_1(14),U4/lfsr_1(13),clk,reset,'0','1');
FDCPE_U4/lfsr_113: FDCPE port map (U4/lfsr_1(13),U4/lfsr_1(12),clk,reset,'0','1');
FDCPE_U4/lfsr_112: FDCPE port map (U4/lfsr_1(12),U4/lfsr_1(11),clk,reset,'0','1');
FDCPE_U4/lfsr_111: FDCPE port map (U4/lfsr_1(11),U4/lfsr_1(10),clk,reset,'0','1');
FDCPE_U4/lfsr_110: FDCPE port map (U4/lfsr_1(10),U4/lfsr_1(9),clk,reset,'0','1');
FDCPE_U4/lfsr_19: FDCPE port map (U4/lfsr_1(9),U4/lfsr_1(8),clk,reset,'0','1');
FDCPE_U4/lfsr_18: FDCPE port map (U4/lfsr_1(8),U4/lfsr_1(7),clk,reset,'0','1');
FDCPE_U4/lfsr_17: FDCPE port map (U4/lfsr_1(7),U4/lfsr_1(6),clk,reset,'0','1');
FDCPE_U4/lfsr_16: FDCPE port map (U4/lfsr_1(6),U4/lfsr_1(5),clk,reset,'0','1');
FDCPE_U4/lfsr_15: FDCPE port map (U4/lfsr_1(5),U4/lfsr_1(4),clk,reset,'0','1');
FDCPE_U4/lfsr_14: FDCPE port map (U4/lfsr_1(4),U4/lfsr_1(3),clk,reset,'0','1');
FDCPE_U4/lfsr_13: FDCPE port map (U4/lfsr_1(3),U4/lfsr_1(2),clk,reset,'0','1');
FDCPE_U4/lfsr_12: FDCPE port map (U4/lfsr_1(2),U4/lfsr_1(1),clk,reset,'0','1');
FDCPE_U4/lfsr_11: FDCPE port map (U4/lfsr_1(1),U4/lfsr_1(0),clk,reset,'0','1');
FDCPE_U4/lfsr_10: FDCPE port map (U4/lfsr_1(0),U4/lfsr_1_D(0),clk,reset,'0','1'); U4/lfsr_1_D(0) <= ((U4/lfsr_1(30) AND U4/lfsr_1(27)) OR (NOT U4/lfsr_1(30) AND NOT U4/lfsr_1(27)));
FDCPE_counter1: FDCPE port map (counter(1),counter_D(1),clk,reset,'0','1'); counter_D(1) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30591 AND counter(1)) OR (estado_FFD2 AND estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND txena_reg_in AND NOT N_PZ_30591 AND counter(0) AND
NOT U4/ena_word_count2)
OR (estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
NOT N_PZ_30371 AND NOT N_PZ_30591 AND counter(0) AND NOT U4/ena_word_count2 AND
txena_out)
OR (NOT estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
NOT N_PZ_30371 AND ena_event_count AND enw1.COMB AND NOT N_PZ_30591 AND
counter(0)));
FDCPE_counter3: FDCPE port map (counter(3),counter_D(3),clk,reset,'0','1'); counter_D(3) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(3)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND N_PZ_30591);
FDCPE_counter4: FDCPE port map (counter(4),counter_D(4),clk,reset,'0','1'); counter_D(4) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(4)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND N_PZ_30591 AND counter(3));
FDCPE_counter5: FDCPE port map (counter(5),counter_D(5),clk,reset,'0','1'); counter_D(5) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(5)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND N_PZ_30591 AND counter(3) AND counter(4));
FDCPE_counter6: FDCPE port map (counter(6),counter_D(6),clk,reset,'0','1'); counter_D(6) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(6)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND N_PZ_30591 AND counter(3) AND counter(4) AND counter(5));
FDCPE_counter7: FDCPE port map (counter(7),counter_D(7),clk,reset,'0','1'); counter_D(7) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30589 AND counter(7)) OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30589 AND counter(2) AND N_PZ_30591 AND counter(3) AND counter(4) AND
counter(5) AND counter(6)));
FDCPE_counter9: FDCPE port map (counter(9),counter_D(9),clk,reset,'0','1'); counter_D(9) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(9)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(8) AND N_PZ_30589);
FDCPE_mword_count10: FDCPE port map (mword_count(10),mword_count_D(10),clk,U4/_n0029,'0','1'); mword_count_D(10) <= NOT (((NOT mword_count(10) AND N_PZ_30354) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(10).PIN)));
N_PZ_30354 <= NOT U4/ena_fill_mem XOR ((NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND U4/ena_fill_mem) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT U4/ena_fill_mem));
U4/_n0029 <= ((reset) OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(2).PIN));
FDCPE_counter11: FDCPE port map (counter(11),counter_D(11),clk,reset,'0','1'); counter_D(11) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(11)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND counter(8) AND N_PZ_30589 AND counter(9));
FDCPE_mword_count11: FDCPE port map (mword_count(11),mword_count_D(11),clk,U4/_n0029,'0','1'); mword_count_D(11) <= NOT (((N_PZ_30354 AND NOT mword_count(11)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(11).PIN)));
FDCPE_counter13: FDCPE port map (counter(13),counter_D(13),clk,reset,'0','1'); counter_D(13) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(13)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND counter(8) AND N_PZ_30589 AND counter(9) AND counter(11) AND
counter(12));
FDCPE_counter12: FDCPE port map (counter(12),counter_D(12),clk,reset,'0','1'); counter_D(12) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(12)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND counter(8) AND N_PZ_30589 AND counter(9) AND counter(11));
FDCPE_mword_count13: FDCPE port map (mword_count(13),mword_count_D(13),clk,U4/_n0029,'0','1'); mword_count_D(13) <= NOT (((N_PZ_30354 AND NOT mword_count(13)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(13).PIN)));
FDCPE_counter14: FDCPE port map (counter(14),counter_D(14),clk,reset,'0','1'); counter_D(14) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(14) AND NOT N_PZ_30547) OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND counter(8) AND N_PZ_30589 AND counter(9) AND counter(11) AND
counter(13) AND counter(12) AND NOT N_PZ_30547));
N_PZ_30547 <= (counter(10) AND counter(8) AND N_PZ_30589 AND counter(9) AND counter(11) AND counter(13) AND counter(12) AND counter(14));
FDCPE_mword_count14: FDCPE port map (mword_count(14),mword_count_D(14),clk,U4/_n0029,'0','1'); mword_count_D(14) <= NOT (((N_PZ_30354 AND NOT mword_count(14)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(14).PIN)));
FDCPE_mword_count4: FDCPE port map (mword_count(4),mword_count_D(4),clk,U4/_n0029,'0','1'); mword_count_D(4) <= NOT (((N_PZ_30354 AND NOT mword_count(4)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(4).PIN)));
FDCPE_mword_count5: FDCPE port map (mword_count(5),mword_count_D(5),clk,U4/_n0029,'0','1'); mword_count_D(5) <= NOT (((N_PZ_30354 AND NOT mword_count(5)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(5).PIN)));
FDCPE_mword_count6: FDCPE port map (mword_count(6),mword_count_D(6),clk,U4/_n0029,'0','1'); mword_count_D(6) <= NOT (((N_PZ_30354 AND NOT mword_count(6)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(6).PIN)));
FDCPE_mword_count7: FDCPE port map (mword_count(7),mword_count_D(7),clk,U4/_n0029,'0','1'); mword_count_D(7) <= NOT (((N_PZ_30354 AND NOT mword_count(7)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(7).PIN)));
FDCPE_mword_count8: FDCPE port map (mword_count(8),mword_count_D(8),clk,U4/_n0029,'0','1'); mword_count_D(8) <= NOT (((N_PZ_30354 AND NOT mword_count(8)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(8).PIN)));
FDCPE_mword_count9: FDCPE port map (mword_count(9),mword_count_D(9),clk,U4/_n0029,'0','1'); mword_count_D(9) <= NOT (((N_PZ_30354 AND NOT mword_count(9)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(9).PIN)));
Mcompar__n0026__n003420 <= ((counter(2) AND NOT mword_count(2)) OR (NOT counter(2) AND mword_count(2)) OR (counter(0) AND NOT mword_count(0)) OR (NOT counter(0) AND mword_count(0)) OR (counter(1) AND NOT mword_count(1))
OR (NOT counter(1) AND mword_count(1))
OR (counter(3) AND NOT mword_count(3))
OR (NOT counter(3) AND mword_count(3))
OR (counter(12) AND NOT mword_count(12))
OR (NOT counter(12) AND mword_count(12))
OR (counter(15) AND NOT mword_count(15))
OR (NOT counter(15) AND mword_count(15))
OR (counter(16) AND NOT mword_count(16))
OR (NOT counter(16) AND mword_count(16))
OR (counter(17) AND NOT mword_count(17))
OR (NOT counter(17) AND mword_count(17)));
FDCPE_mword_count0: FDCPE port map (mword_count(0),mword_count_D(0),clk,U4/_n0029,'0','1'); mword_count_D(0) <= NOT (((N_PZ_30354 AND NOT mword_count(0)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(0).PIN)));
FDCPE_mword_count12: FDCPE port map (mword_count(12),mword_count_D(12),clk,U4/_n0029,'0','1'); mword_count_D(12) <= NOT (((N_PZ_30354 AND NOT mword_count(12)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(12).PIN)));
FDCPE_counter15: FDCPE port map (counter(15),counter_D(15),clk,reset,'0','1'); counter_D(15) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND N_PZ_30547 AND NOT counter(15)) OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30547 AND counter(15)));
FDCPE_mword_count15: FDCPE port map (mword_count(15),mword_count_D(15),clk,U4/_n0029,'0','1'); mword_count_D(15) <= NOT (((N_PZ_30354 AND NOT mword_count(15)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(15).PIN)));
FDCPE_counter16: FDCPE port map (counter(16),counter_D(16),clk,reset,'0','1'); counter_D(16) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(16)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND N_PZ_30547 AND counter(15));
FDCPE_mword_count16: FDCPE port map (mword_count(16),mword_count_D(16),clk,U4/_n0029,'0','1'); mword_count_D(16) <= NOT ((NOT U4/ena_fill_mem AND NOT mword_count(16)) XOR ((NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(0).PIN AND
U4/ena_fill_mem)
OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(0).PIN AND
mword_count(16))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND add(0) AND enw1 AND NOT enw2 AND U4/ena_fill_mem AND
NOT mword_count(16))
OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(0).PIN AND
NOT U4/ena_fill_mem AND NOT mword_count(16))));
FDCPE_counter17: FDCPE port map (counter(17),counter_D(17),clk,reset,'0','1'); counter_D(17) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(17)) XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND N_PZ_30547 AND counter(15) AND counter(16));
FDCPE_mword_count17: FDCPE port map (mword_count(17),mword_count_D(17),clk,U4/_n0029,'0','1'); mword_count_D(17) <= NOT ((NOT U4/ena_fill_mem AND NOT mword_count(17)) XOR ((NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN AND
U4/ena_fill_mem)
OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN AND
mword_count(17))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND add(0) AND enw1 AND NOT enw2 AND U4/ena_fill_mem AND
NOT mword_count(17))
OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(1).PIN AND
NOT U4/ena_fill_mem AND NOT mword_count(17))));
FDCPE_mword_count1: FDCPE port map (mword_count(1),mword_count_D(1),clk,U4/_n0029,'0','1'); mword_count_D(1) <= NOT (((N_PZ_30354 AND NOT mword_count(1)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN)));
FDCPE_mword_count2: FDCPE port map (mword_count(2),mword_count_D(2),clk,U4/_n0029,'0','1'); mword_count_D(2) <= NOT (((N_PZ_30354 AND NOT mword_count(2)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(2).PIN)));
FDCPE_mword_count3: FDCPE port map (mword_count(3),mword_count_D(3),clk,U4/_n0029,'0','1'); mword_count_D(3) <= NOT (((N_PZ_30354 AND NOT mword_count(3)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(3).PIN)));
_n003432 <= (NOT estado_XX_FFD146 AND enw1.COMB AND txena_reg_in);
U4/_n00084 <= (NOT N_PZ_30371 AND NOT U4/_n0051 AND NOT reset);
FDCPE_mem_pointer10: FDCPE port map (mem_pointer(10),mem_pointer_D(10),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(10) <= ((NOT U4/_n0081 AND mem_pointer(10) AND NOT N_PZ_30575) OR (NOT U4/_n0081 AND NOT mem_pointer(10) AND N_PZ_30575) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(10))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(10).PIN));
N_PZ_30575 <= (mem_pointer(4) AND N_PZ_30580 AND mem_pointer(5) AND mem_pointer(6) AND mem_pointer(7) AND mem_pointer(8) AND mem_pointer(9));
FDCPE_mem_pointer4: FDCPE port map (mem_pointer(4),mem_pointer_D(4),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(4) <= ((NOT U4/_n0081 AND mem_pointer(4) AND NOT N_PZ_30580) OR (NOT U4/_n0081 AND NOT mem_pointer(4) AND N_PZ_30580) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(4))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(4).PIN));
N_PZ_30580 <= (NOT mem_is_full AND mem_pointer(0) AND tp7 AND mem_pointer(1) AND mem_pointer(2) AND mem_pointer(3));
FDCPE_mem_pointer1: FDCPE port map (mem_pointer(1),mem_pointer_D(1),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(1) <= mem_pointer(1) XOR ((add(0) AND db(1).PIN AND U4/_n0081 AND NOT mem_pointer(1)) OR (add(0) AND NOT db(1).PIN AND U4/_n0081 AND mem_pointer(1))
OR (NOT mem_is_full AND mem_pointer(0) AND NOT U4/_n0081 AND tp7));
FDCPE_mem_pointer2: FDCPE port map (mem_pointer(2),mem_pointer_D(2),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(2) <= ((mem_is_full AND NOT U4/_n0081 AND mem_pointer(2)) OR (NOT mem_pointer(0) AND NOT U4/_n0081 AND mem_pointer(2)) OR (NOT U4/_n0081 AND NOT tp7 AND mem_pointer(2))
OR (NOT U4/_n0081 AND NOT mem_pointer(1) AND mem_pointer(2))
OR (NOT mem_is_full AND mem_pointer(0) AND NOT U4/_n0081 AND tp7 AND
mem_pointer(1) AND NOT mem_pointer(2))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(2))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(2).PIN));
FDCPE_mem_pointer3: FDCPE port map (mem_pointer(3),mem_pointer_D(3),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(3) <= ((NOT U4/_n0081 AND NOT N_PZ_30580 AND mem_pointer(3)) OR (NOT mem_is_full AND mem_pointer(0) AND NOT U4/_n0081 AND tp7 AND NOT N_PZ_30580 AND mem_pointer(1) AND mem_pointer(2))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(3))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(3).PIN));
FDCPE_mem_pointer5: FDCPE port map (mem_pointer(5),mem_pointer_D(5),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(5) <= NOT ((NOT mem_pointer(5) AND NOT U4/_n002121) XOR ((U4/_n0081 AND mem_pointer(5) AND NOT U4/_n002121) OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
NOT U4/_n002121)));
U4/_n002121 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(5)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(5).PIN));
FDCPE_mem_pointer6: FDCPE port map (mem_pointer(6),mem_pointer_D(6),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(6) <= ((NOT U4/_n0081 AND NOT mem_pointer(4) AND mem_pointer(6)) OR (NOT U4/_n0081 AND NOT N_PZ_30580 AND mem_pointer(6)) OR (NOT U4/_n0081 AND NOT mem_pointer(5) AND mem_pointer(6))
OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
mem_pointer(5) AND NOT mem_pointer(6))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(6))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(6).PIN));
FDCPE_mem_pointer7: FDCPE port map (mem_pointer(7),mem_pointer_D(7),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(7) <= NOT ((NOT mem_pointer(7) AND NOT U4/_n001921) XOR ((U4/_n0081 AND mem_pointer(7) AND NOT U4/_n001921) OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
mem_pointer(5) AND mem_pointer(6) AND NOT U4/_n001921)));
U4/_n001921 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(7)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(7).PIN));
FDCPE_mem_pointer8: FDCPE port map (mem_pointer(8),mem_pointer_D(8),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(8) <= NOT ((NOT mem_pointer(8) AND NOT U4/_n001821) XOR ((U4/_n0081 AND mem_pointer(8) AND NOT U4/_n001821) OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
mem_pointer(5) AND mem_pointer(6) AND mem_pointer(7) AND NOT U4/_n001821)));
U4/_n001821 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(8)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(8).PIN));
FDCPE_mem_pointer9: FDCPE port map (mem_pointer(9),mem_pointer_D(9),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(9) <= ((NOT U4/_n0081 AND NOT N_PZ_30575 AND mem_pointer(9)) OR (NOT U4/_n0081 AND NOT N_PZ_30575 AND mem_pointer(4) AND N_PZ_30580 AND mem_pointer(5) AND mem_pointer(6) AND mem_pointer(7) AND
mem_pointer(8))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(9))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(9).PIN));
FDCPE_mem_pointer11: FDCPE port map (mem_pointer(11),mem_pointer_D(11),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(11) <= NOT ((NOT mem_pointer(11) AND NOT U4/_n001521) XOR ((U4/_n0081 AND mem_pointer(11) AND NOT U4/_n001521) OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND
NOT U4/_n001521)));
U4/_n001521 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(11)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(11).PIN));
FDCPE_mem_pointer12: FDCPE port map (mem_pointer(12),mem_pointer_D(12),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(12) <= ((NOT U4/_n0081 AND NOT mem_pointer(10) AND mem_pointer(12)) OR (NOT U4/_n0081 AND NOT N_PZ_30575 AND mem_pointer(12)) OR (NOT U4/_n0081 AND NOT mem_pointer(11) AND mem_pointer(12))
OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND
mem_pointer(11) AND NOT mem_pointer(12))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(12))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(12).PIN));
FDCPE_mem_pointer13: FDCPE port map (mem_pointer(13),mem_pointer_D(13),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(13) <= NOT ((NOT mem_pointer(13) AND NOT U4/_n001321) XOR ((U4/_n0081 AND mem_pointer(13) AND NOT U4/_n001321) OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND
mem_pointer(11) AND mem_pointer(12) AND NOT U4/_n001321)));
U4/_n001321 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(13)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(13).PIN));
FDCPE_mem_pointer14: FDCPE port map (mem_pointer(14),mem_pointer_D(14),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(14) <= ((NOT U4/_n0081 AND mem_pointer(14) AND NOT N_PZ_30542) OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND mem_pointer(11) AND mem_pointer(12) AND mem_pointer(13) AND NOT N_PZ_30542)
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(14))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(14).PIN));
N_PZ_30542 <= (mem_pointer(10) AND N_PZ_30575 AND mem_pointer(11) AND mem_pointer(12) AND mem_pointer(13) AND mem_pointer(14));
FDCPE_mem_pointer15: FDCPE port map (mem_pointer(15),mem_pointer_D(15),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(15) <= ((NOT U4/_n0081 AND N_PZ_30542 AND NOT mem_pointer(15)) OR (NOT U4/_n0081 AND NOT N_PZ_30542 AND mem_pointer(15)) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(15))
OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(15).PIN));
FDCPE_mem_pointer16: FDCPE port map (mem_pointer(16),mem_pointer_D(16),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(16) <= NOT ((NOT mem_pointer(16) AND NOT U4/_n001021) XOR ((U4/_n0081 AND mem_pointer(16) AND NOT U4/_n001021) OR (NOT U4/_n0081 AND N_PZ_30542 AND mem_pointer(15) AND
NOT U4/_n001021)));
U4/_n001021 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(0).PIN) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND mem_pointer(16)));
FDCPE_mem_pointer17: FDCPE port map (mem_pointer(17),mem_pointer_D(17),clk,NOT U4/_n00084,'0','1'); mem_pointer_D(17) <= NOT ((NOT mem_pointer(17) AND NOT U4/_n000921) XOR ((U4/_n0081 AND mem_pointer(17) AND NOT U4/_n000921) OR (NOT U4/_n0081 AND N_PZ_30542 AND mem_pointer(15) AND
mem_pointer(16) AND NOT U4/_n000921)));
U4/_n000921 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(1).PIN) OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND mem_pointer(17)));
Mcompar__n0029__n0027 <= ((mevent_count(11) AND NOT counter(11)) OR (NOT mevent_count(11) AND counter(11)));
Mcompar__n0029__n0029 <= ((mevent_count(13) AND NOT counter(13)) OR (NOT mevent_count(13) AND counter(13)));
estado_XX_FFD135 <= ((counter(16)) OR (counter(17)) OR (mevent_count(0) AND NOT counter(0)) OR (NOT mevent_count(0) AND counter(0)) OR (mevent_count(12) AND NOT counter(12))
OR (NOT mevent_count(12) AND counter(12))
OR (mevent_count(15) AND NOT counter(15))
OR (NOT mevent_count(15) AND counter(15))
OR (mevent_count(1) AND NOT counter(1))
OR (NOT mevent_count(1) AND counter(1))
OR (mevent_count(2) AND NOT counter(2))
OR (NOT mevent_count(2) AND counter(2))
OR (mevent_count(3) AND NOT counter(3))
OR (NOT mevent_count(3) AND counter(3)));
estado_XX_FFD136 <= ((mevent_count(14) AND mevent_count(9) AND counter(9) AND counter(14)) OR (mevent_count(14) AND NOT mevent_count(9) AND NOT counter(9) AND counter(14)) OR (NOT mevent_count(14) AND mevent_count(9) AND counter(9) AND
NOT counter(14))
OR (NOT mevent_count(14) AND NOT mevent_count(9) AND NOT counter(9) AND
NOT counter(14)));
N_PZ_30372 <= ((mevent_count(4) AND counter(4)) OR (NOT mevent_count(4) AND NOT counter(4)));
N_PZ_30405 <= ((mevent_count(5) AND counter(5)) OR (NOT mevent_count(5) AND NOT counter(5)));
N_PZ_30510 <= ((mevent_count(6) AND counter(6)) OR (NOT mevent_count(6) AND NOT counter(6)));
N_PZ_30539 <= ((mevent_count(7) AND counter(7)) OR (NOT mevent_count(7) AND NOT counter(7)));
N_PZ_30599 <= ((estado_FFD2 AND ena_ceros_mem AND NOT ena_event_count AND NOT mem_is_full AND NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2) OR (NOT estado_FFD2 AND ena_event_count AND NOT mevent_count(0) AND NOT mevent_count(10) AND NOT mevent_count(11) AND NOT mevent_count(12) AND
NOT mevent_count(13) AND NOT mevent_count(14) AND NOT mevent_count(15) AND
NOT mevent_count(1) AND NOT mevent_count(2) AND NOT mevent_count(3) AND
NOT mevent_count(4) AND NOT mevent_count(5) AND NOT mevent_count(6) AND
NOT mevent_count(7) AND NOT mevent_count(8) AND NOT mevent_count(9) AND enw1.COMB));
cspare(1) <= '0';
cspare(2) <= '0';
cspare(3) <= '0';
cspare(4) <= '0';
cspare(5) <= '0';
cspare(6) <= '0';
cspare(7) <= '0';
cspare(8) <= '0';
cspare(9) <= '0';
FDCPE_dout0: FDCPE port map (dout_I(0),mdat(0).PIN,clk,reset,'0','1'); dout(0) <= dout_I(0) when dout_OE(0) = '1' else 'Z'; dout_OE(0) <= cspare(11);
FDCPE_dout10: FDCPE port map (dout_I(10),mdat(10).PIN,clk,reset,'0','1'); dout(10) <= dout_I(10) when dout_OE(10) = '1' else 'Z'; dout_OE(10) <= cspare(11);
FDCPE_dout11: FDCPE port map (dout_I(11),mdat(11).PIN,clk,reset,'0','1'); dout(11) <= dout_I(11) when dout_OE(11) = '1' else 'Z'; dout_OE(11) <= cspare(11);
FDCPE_dout12: FDCPE port map (dout_I(12),mdat(12).PIN,clk,reset,'0','1'); dout(12) <= dout_I(12) when dout_OE(12) = '1' else 'Z'; dout_OE(12) <= cspare(11);
FDCPE_dout13: FDCPE port map (dout_I(13),mdat(13).PIN,clk,reset,'0','1'); dout(13) <= dout_I(13) when dout_OE(13) = '1' else 'Z'; dout_OE(13) <= cspare(11);
FDCPE_dout14: FDCPE port map (dout_I(14),mdat(14).PIN,clk,reset,'0','1'); dout(14) <= dout_I(14) when dout_OE(14) = '1' else 'Z'; dout_OE(14) <= cspare(11);
FDCPE_dout15: FDCPE port map (dout_I(15),mdat(15).PIN,clk,reset,'0','1'); dout(15) <= dout_I(15) when dout_OE(15) = '1' else 'Z'; dout_OE(15) <= cspare(11);
FDCPE_dout1: FDCPE port map (dout_I(1),mdat(1).PIN,clk,reset,'0','1'); dout(1) <= dout_I(1) when dout_OE(1) = '1' else 'Z'; dout_OE(1) <= cspare(11);
FDCPE_dout2: FDCPE port map (dout_I(2),mdat(2).PIN,clk,reset,'0','1'); dout(2) <= dout_I(2) when dout_OE(2) = '1' else 'Z'; dout_OE(2) <= cspare(11);
FDCPE_dout3: FDCPE port map (dout_I(3),mdat(3).PIN,clk,reset,'0','1'); dout(3) <= dout_I(3) when dout_OE(3) = '1' else 'Z'; dout_OE(3) <= cspare(11);
FDCPE_dout4: FDCPE port map (dout_I(4),mdat(4).PIN,clk,reset,'0','1'); dout(4) <= dout_I(4) when dout_OE(4) = '1' else 'Z'; dout_OE(4) <= cspare(11);
FDCPE_dout5: FDCPE port map (dout_I(5),mdat(5).PIN,clk,reset,'0','1'); dout(5) <= dout_I(5) when dout_OE(5) = '1' else 'Z'; dout_OE(5) <= cspare(11);
FDCPE_dout6: FDCPE port map (dout_I(6),mdat(6).PIN,clk,reset,'0','1'); dout(6) <= dout_I(6) when dout_OE(6) = '1' else 'Z'; dout_OE(6) <= cspare(11);
FDCPE_dout7: FDCPE port map (dout_I(7),mdat(7).PIN,clk,reset,'0','1'); dout(7) <= dout_I(7) when dout_OE(7) = '1' else 'Z'; dout_OE(7) <= cspare(11);
FDCPE_dout8: FDCPE port map (dout_I(8),mdat(8).PIN,clk,reset,'0','1'); dout(8) <= dout_I(8) when dout_OE(8) = '1' else 'Z'; dout_OE(8) <= cspare(11);
FDCPE_dout9: FDCPE port map (dout_I(9),mdat(9).PIN,clk,reset,'0','1'); dout(9) <= dout_I(9) when dout_OE(9) = '1' else 'Z'; dout_OE(9) <= cspare(11);
ds_out <= (NOT ds1 AND NOT ds0);
dtack_mem <= NOT ((NOT tp5 AND NOT dtack_blk));
FDCPE_tp5: FDCPE port map (tp5,tp5_D,dsdly<1>,tp5_CLR,'0','1'); tp5_D <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND NOT am(1)); tp5_CLR <= (ds1 AND ds0 AND NOT dsdly(1));
FDCPE_dtack_blk: FDCPE port map (dtack_blk,dtack_blk_D,dsdly<1>,dtack_blk_CLR,'0','1'); dtack_blk_D <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1)); dtack_blk_CLR <= (ds1 AND ds0 AND NOT dsdly(1));
g245_mem <= NOT ((lword AND iack AND am(5) AND am(0) AND NOT am(2) AND NOT ds1 AND NOT ds0 AND am(4) AND am(3) AND NOT brdsel24));
led(0) <= NOT ((NOT U1/q2 AND NOT U2/b2));
FDCPE_U1/q2: FDCPE port map (U1/q2,U1/q2_D,dsdly<0>,dsdly(1),'0','1'); U1/q2_D <= (NOT write AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND NOT am(1));
FDCPE_U2/b2: FDCPE port map (U2/b2,U2/b2_D,dsdly<0>,dsdly(1),'0','1'); U2/b2_D <= (NOT write AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1));
led(1) <= (write AND N_PZ_30489);
madd(0) <= NOT (((NOT add(0) AND NOT N_PZ_30394) OR (NOT N_PZ_30322 AND NOT mem_pointer(0)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(0))));
FDCPE_U3/counter_add0: FDCPE port map (U3/counter_add(0),U3/counter_add_D(0),U3/counter_add_C(0),U3/counter_add_CLR(0),U3/counter_add_PRE(0),'1'); U3/counter_add_D(0) <= NOT (((NOT add(0) AND U2/latch3) OR (U3/counter_add(0) AND NOT U2/latch3)));
U3/counter_add_C(0) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(0) <= (NOT add(0) AND U2/latch3);
U3/counter_add_PRE(0) <= (add(0) AND U2/latch3);
U2/latch3 <= ((ds1 AND NOT U2/qlt) OR (ds0 AND NOT U2/qlt));
FDCPE_U2/qlt: FDCPE port map (U2/qlt,U2/qlt_D,dsdly<0>,as,'0','1'); U2/qlt_D <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1));
N_PZ_30394 <= ((NOT N_PZ_30322) OR (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1)));
madd(10) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(10)) OR (NOT N_PZ_30394 AND NOT add(10)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(2))));
LDCP_U3/add_latched2: LDCP port map (U3/add_latched(2),add(10),U2/latch3,'0','0');
madd(11) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(11)) OR (NOT N_PZ_30394 AND NOT add(11)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(3))));
FDCPE_U3/add_latched3: FDCPE port map (U3/add_latched(3),add(11),U2/latch3,'0','0','1');
madd(12) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(12)) OR (NOT N_PZ_30394 AND NOT add(12)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(4))));
LDCP_U3/add_latched4: LDCP port map (U3/add_latched(4),add(12),U2/latch3,'0','0');
madd(13) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(13)) OR (NOT N_PZ_30394 AND NOT add(13)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(5))));
FDCPE_U3/add_latched5: FDCPE port map (U3/add_latched(5),add(13),U2/latch3,'0','0','1');
madd(14) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(14)) OR (NOT N_PZ_30394 AND NOT add(14)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(6))));
FDCPE_U3/add_latched6: FDCPE port map (U3/add_latched(6),add(14),U2/latch3,'0','0','1');
madd(15) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(15)) OR (NOT N_PZ_30394 AND NOT add(15)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(7))));
FDCPE_U3/add_latched7: FDCPE port map (U3/add_latched(7),add(15),U2/latch3,'0','0','1');
madd(16) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(16)) OR (NOT N_PZ_30394 AND NOT add(16)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(8))));
FDCPE_U3/add_latched8: FDCPE port map (U3/add_latched(8),add(16),U2/latch3,'0','0','1');
madd(17) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(17)) OR (NOT N_PZ_30394 AND NOT add(17)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(9))));
FDCPE_U3/add_latched9: FDCPE port map (U3/add_latched(9),add(17),U2/latch3,'0','0','1');
madd(1) <= NOT (((NOT add(1) AND NOT N_PZ_30394) OR (NOT N_PZ_30322 AND NOT mem_pointer(1)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(1))));
FDCPE_U3/counter_add1: FDCPE port map (U3/counter_add(1),U3/counter_add_D(1),U3/counter_add_C(1),U3/counter_add_CLR(1),U3/counter_add_PRE(1),'1'); U3/counter_add_D(1) <= NOT (((NOT add(1) AND U2/latch3) OR (U3/counter_add(0) AND NOT U2/latch3 AND
U3/counter_add(1))
OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
NOT U3/counter_add(1))));
U3/counter_add_C(1) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(1) <= (NOT add(1) AND U2/latch3);
U3/counter_add_PRE(1) <= (add(1) AND U2/latch3);
madd(2) <= NOT (((NOT add(2) AND NOT N_PZ_30394) OR (NOT N_PZ_30322 AND NOT mem_pointer(2)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(2))));
FDCPE_U3/counter_add2: FDCPE port map (U3/counter_add(2),U3/counter_add_D(2),U3/counter_add_C(2),U3/counter_add_CLR(2),U3/counter_add_PRE(2),'1'); U3/counter_add_D(2) <= ((add(2) AND U2/latch3) OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND U3/counter_add(2))
OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
U3/counter_add(2))
OR (U3/counter_add(0) AND NOT U2/latch3 AND
U3/counter_add(1) AND NOT U3/counter_add(2)));
U3/counter_add_C(2) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(2) <= (NOT add(2) AND U2/latch3);
U3/counter_add_PRE(2) <= (add(2) AND U2/latch3);
madd(3) <= NOT (((NOT add(3) AND NOT N_PZ_30394) OR (NOT N_PZ_30322 AND NOT mem_pointer(3)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(3))));
FDCPE_U3/counter_add3: FDCPE port map (U3/counter_add(3),U3/counter_add_D(3),U3/counter_add_C(3),U3/counter_add_CLR(3),U3/counter_add_PRE(3),'1'); U3/counter_add_D(3) <= NOT (((NOT add(3) AND U2/latch3) OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
NOT U3/counter_add(3))
OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
NOT U3/counter_add(3))
OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
NOT U3/counter_add(3))
OR (U3/counter_add(0) AND NOT U2/latch3 AND
U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3))));
U3/counter_add_C(3) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(3) <= (NOT add(3) AND U2/latch3);
U3/counter_add_PRE(3) <= (add(3) AND U2/latch3);
madd(4) <= NOT (((NOT add(4) AND NOT N_PZ_30394) OR (NOT N_PZ_30322 AND NOT mem_pointer(4)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(4))));
FDCPE_U3/counter_add4: FDCPE port map (U3/counter_add(4),U3/counter_add_D(4),U3/counter_add_C(4),U3/counter_add_CLR(4),U3/counter_add_PRE(4),'1'); U3/counter_add_D(4) <= ((add(4) AND U2/latch3) OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND U3/counter_add(4))
OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
U3/counter_add(4))
OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
U3/counter_add(4))
OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
U3/counter_add(4))
OR (U3/counter_add(0) AND NOT U2/latch3 AND
U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
NOT U3/counter_add(4)));
U3/counter_add_C(4) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(4) <= (NOT add(4) AND U2/latch3);
U3/counter_add_PRE(4) <= (add(4) AND U2/latch3);
madd(5) <= NOT (((NOT add(5) AND NOT N_PZ_30394) OR (NOT N_PZ_30322 AND NOT mem_pointer(5)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(5))));
FDCPE_U3/counter_add5: FDCPE port map (U3/counter_add(5),U3/counter_add_D(5),U3/counter_add_C(5),U3/counter_add_CLR(5),U3/counter_add_PRE(5),'1'); U3/counter_add_D(5) <= NOT (((NOT add(5) AND U2/latch3) OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
NOT U3/counter_add(5))
OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
NOT U3/counter_add(5))
OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
NOT U3/counter_add(5))
OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
NOT U3/counter_add(5))
OR (NOT U2/latch3 AND NOT U3/counter_add(4) AND
NOT U3/counter_add(5))
OR (U3/counter_add(0) AND NOT U2/latch3 AND
U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
U3/counter_add(4) AND U3/counter_add(5))));
U3/counter_add_C(5) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(5) <= (NOT add(5) AND U2/latch3);
U3/counter_add_PRE(5) <= (add(5) AND U2/latch3);
madd(6) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(6)) OR (NOT N_PZ_30394 AND NOT add(6)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(6))));
FDCPE_U3/counter_add6: FDCPE port map (U3/counter_add(6),U3/counter_add_D(6),U3/counter_add_C(6),U3/counter_add_CLR(6),U3/counter_add_PRE(6),'1'); U3/counter_add_D(6) <= NOT (((U2/latch3 AND NOT add(6)) OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
NOT U3/counter_add(6))
OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
NOT U3/counter_add(6))
OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
NOT U3/counter_add(6))
OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
NOT U3/counter_add(6))
OR (NOT U2/latch3 AND NOT U3/counter_add(4) AND
NOT U3/counter_add(6))
OR (NOT U2/latch3 AND NOT U3/counter_add(5) AND
NOT U3/counter_add(6))
OR (U3/counter_add(0) AND NOT U2/latch3 AND
U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
U3/counter_add(4) AND U3/counter_add(5) AND U3/counter_add(6))));
U3/counter_add_C(6) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(6) <= (U2/latch3 AND NOT add(6));
U3/counter_add_PRE(6) <= (U2/latch3 AND add(6));
madd(7) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(7)) OR (NOT N_PZ_30394 AND NOT add(7)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/counter_add(7))));
FDCPE_U3/counter_add7: FDCPE port map (U3/counter_add(7),U3/counter_add_D(7),U3/counter_add_C(7),U3/counter_add_CLR(7),U3/counter_add_PRE(7),'1'); U3/counter_add_D(7) <= NOT (((U2/latch3 AND NOT add(7)) OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
NOT U3/counter_add(7))
OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
NOT U3/counter_add(7))
OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
NOT U3/counter_add(7))
OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
NOT U3/counter_add(7))
OR (NOT U2/latch3 AND NOT U3/counter_add(4) AND
NOT U3/counter_add(7))
OR (NOT U2/latch3 AND NOT U3/counter_add(5) AND
NOT U3/counter_add(7))
OR (NOT U2/latch3 AND NOT U3/counter_add(6) AND
NOT U3/counter_add(7))
OR (U3/counter_add(0) AND NOT U2/latch3 AND
U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
U3/counter_add(4) AND U3/counter_add(5) AND U3/counter_add(6) AND
U3/counter_add(7))));
U3/counter_add_C(7) <= (dsdly(1) AND NOT dsdly(0));
U3/counter_add_CLR(7) <= (U2/latch3 AND NOT add(7));
U3/counter_add_PRE(7) <= (U2/latch3 AND add(7));
madd(8) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(8)) OR (NOT N_PZ_30394 AND NOT add(8)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(0))));
FDCPE_U3/add_latched0: FDCPE port map (U3/add_latched(0),add(8),U2/latch3,'0','0','1');
madd(9) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(9)) OR (NOT N_PZ_30394 AND NOT add(9)) OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND NOT U3/add_latched(1))));
FDCPE_U3/add_latched1: FDCPE port map (U3/add_latched(1),add(9),U2/latch3,'0','0','1');
mdat_I(0) <= NOT (((NOT db(0).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(0))));
N_PZ_30353 <= (NOT write AND N_PZ_30322 AND N_PZ_30489);
FDCPE_dout_reg_in0: FDCPE port map (dout_reg_in(0),dout_reg_in_2(0),clk,reset,'0','1');
FDCPE_dout_reg_in_20: FDCPE port map (dout_reg_in_2(0),dout(0).PIN,clk,reset,'0','1');
_n0088_MC.GLB <= ((estado_FFD2 AND NOT estado_FFD3) OR (NOT estado_FFD3 AND NOT estado_FFD1 AND NOT write AND N_PZ_30489));
mdat_I(10) <= NOT (((NOT db(10).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(10))));
FDCPE_dout_reg_in10: FDCPE port map (dout_reg_in(10),dout_reg_in_2(10),clk,reset,'0','1');
FDCPE_dout_reg_in_210: FDCPE port map (dout_reg_in_2(10),dout(10).PIN,clk,reset,'0','1');
mdat_I(11) <= NOT (((NOT db(11).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(11))));
FDCPE_dout_reg_in11: FDCPE port map (dout_reg_in(11),dout_reg_in_2(11),clk,reset,'0','1');
FDCPE_dout_reg_in_211: FDCPE port map (dout_reg_in_2(11),dout(11).PIN,clk,reset,'0','1');
mdat_I(12) <= NOT (((NOT db(12).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(12))));
FDCPE_dout_reg_in12: FDCPE port map (dout_reg_in(12),dout_reg_in_2(12),clk,reset,'0','1');
FDCPE_dout_reg_in_212: FDCPE port map (dout_reg_in_2(12),dout(12).PIN,clk,reset,'0','1');
mdat_I(13) <= NOT (((NOT db(13).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(13))));
FDCPE_dout_reg_in13: FDCPE port map (dout_reg_in(13),dout_reg_in_2(13),clk,reset,'0','1');
FDCPE_dout_reg_in_213: FDCPE port map (dout_reg_in_2(13),dout(13).PIN,clk,reset,'0','1');
mdat_I(14) <= NOT (((NOT db(14).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(14))));
FDCPE_dout_reg_in14: FDCPE port map (dout_reg_in(14),dout_reg_in_2(14),clk,reset,'0','1');
FDCPE_dout_reg_in_214: FDCPE port map (dout_reg_in_2(14),dout(14).PIN,clk,reset,'0','1');
mdat_I(15) <= NOT (((NOT db(15).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(15))));
FDCPE_dout_reg_in15: FDCPE port map (dout_reg_in(15),dout_reg_in_2(15),clk,reset,'0','1');
FDCPE_dout_reg_in_215: FDCPE port map (dout_reg_in_2(15),dout(15).PIN,clk,reset,'0','1');
mdat_I(1) <= NOT (((NOT db(1).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(1))));
FDCPE_dout_reg_in1: FDCPE port map (dout_reg_in(1),dout_reg_in_2(1),clk,reset,'0','1');
FDCPE_dout_reg_in_21: FDCPE port map (dout_reg_in_2(1),dout(1).PIN,clk,reset,'0','1');
mdat_I(2) <= NOT (((NOT db(2).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(2))));
FDCPE_dout_reg_in2: FDCPE port map (dout_reg_in(2),dout_reg_in_2(2),clk,reset,'0','1');
FDCPE_dout_reg_in_22: FDCPE port map (dout_reg_in_2(2),dout(2).PIN,clk,reset,'0','1');
mdat_I(3) <= NOT (((NOT db(3).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(3))));
FDCPE_dout_reg_in3: FDCPE port map (dout_reg_in(3),dout_reg_in_2(3),clk,reset,'0','1');
FDCPE_dout_reg_in_23: FDCPE port map (dout_reg_in_2(3),dout(3).PIN,clk,reset,'0','1');
mdat_I(4) <= NOT (((NOT db(4).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(4))));
FDCPE_dout_reg_in4: FDCPE port map (dout_reg_in(4),dout_reg_in_2(4),clk,reset,'0','1');
FDCPE_dout_reg_in_24: FDCPE port map (dout_reg_in_2(4),dout(4).PIN,clk,reset,'0','1');
mdat_I(5) <= NOT (((NOT db(5).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(5))));
FDCPE_dout_reg_in5: FDCPE port map (dout_reg_in(5),dout_reg_in_2(5),clk,reset,'0','1');
FDCPE_dout_reg_in_25: FDCPE port map (dout_reg_in_2(5),dout(5).PIN,clk,reset,'0','1');
mdat_I(6) <= NOT (((NOT db(6).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(6))));
FDCPE_dout_reg_in6: FDCPE port map (dout_reg_in(6),dout_reg_in_2(6),clk,reset,'0','1');
FDCPE_dout_reg_in_26: FDCPE port map (dout_reg_in_2(6),dout(6).PIN,clk,reset,'0','1');
mdat_I(7) <= NOT (((NOT db(7).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(7))));
FDCPE_dout_reg_in7: FDCPE port map (dout_reg_in(7),dout_reg_in_2(7),clk,reset,'0','1');
FDCPE_dout_reg_in_27: FDCPE port map (dout_reg_in_2(7),dout(7).PIN,clk,reset,'0','1');
mdat_I(8) <= NOT (((NOT db(8).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(8))));
FDCPE_dout_reg_in8: FDCPE port map (dout_reg_in(8),dout_reg_in_2(8),clk,reset,'0','1');
FDCPE_dout_reg_in_28: FDCPE port map (dout_reg_in_2(8),dout(8).PIN,clk,reset,'0','1');
mdat_I(9) <= NOT (((NOT db(9).PIN AND N_PZ_30353) OR (NOT N_PZ_30353 AND NOT dout_reg_in(9))));
FDCPE_dout_reg_in9: FDCPE port map (dout_reg_in(9),dout_reg_in_2(9),clk,reset,'0','1');
FDCPE_dout_reg_in_29: FDCPE port map (dout_reg_in_2(9),dout(9).PIN,clk,reset,'0','1');
FDCPE_mem_done_p: FDCPE port map (mem_done_p,mem_done_p_D,clk,reset,'0','1'); mem_done_p_D <= ((estado_FFD2 AND estado_FFD3 AND NOT estado_FFD1) OR (NOT ena_ceros_mem AND NOT ena_gol_test AND mem_done_p));
mspare_0 <= '0';
mspare_1 <= '0';
mspare_2 <= '0';
mspare_3 <= '0';
oe <= NOT (((cspare(11)) OR (write AND N_PZ_30489)));
tp6 <= (estado_FFD2 AND estado_FFD3 AND estado_FFD1);
tp8 <= clk_slow;
FDCPE_trigger_led: FDCPE port map (trigger_led,NOT ULED/q1,clk_slow,'0',reset,'1');
FTCPE_ULED/q1: FTCPE port map (ULED/q1,ULED/q1_T,clk,ULED/q3,'0','1'); ULED/q1_T <= (enw1.COMB AND NOT ULED/q1);
FDCPE_ULED/q3: FDCPE port map (ULED/q3,NOT trigger_led,clk_slow,reset,'0','1');
vspare_1 <= '0';
we <= NOT (((N_PZ_30322 AND U1/q2) OR (N_PZ_30322 AND U2/b2) OR (estado_FFD2 AND NOT estado_FFD3 AND NOT we_fifo)));
FDDCPE_we_fifo: FDDCPE port map (we_fifo,we_fifo_D,clk,'0',reset,'1'); we_fifo_D <= NOT ((txena_reg_in AND NOT clk));
N_PZ_30373 <= (NOT add(5) AND NOT add(4) AND NOT add(3)) XOR (NOT add(5) AND NOT add(4) AND NOT add(3) AND write AND N_PZ_30322 AND N_PZ_30489);
db(9) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(9).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(9) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(9) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(9) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(9) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND N_PZ_30373 AND
U4/ena_lfsr(2)));FDCPE_U4/ena_lfsr2: FDCPE port map (U4/ena_lfsr(2),db(9).PIN,clk,reset,'0',N_PZ_30413);
db(10) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(10).PIN) OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(10) AND N_PZ_30373) OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(10) AND N_PZ_30373)
OR (NOT add(2) AND add(1) AND add(0) AND mword_count(10) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(10) AND
N_PZ_30373)
OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND N_PZ_30373 AND
U4/ena_lfsr(3)));FDCPE_U4/ena_lfsr3: FDCPE port map (U4/ena_lfsr(3),db(10).PIN,clk,reset,'0',N_PZ_30413);
FDCPE_is_trigger_1: FDCPE port map (is_trigger_1,is_trigger,clk,reset,'0','1');
FDCPE_txena_reg_out: FDCPE port map (txena_reg_out,txena_out,clk,reset,'0','1');
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);