    cpldfit:  version G.35                              Xilinx Inc.
                                      Fitter Report
    Design Name: rm_memadd                           Date:  1-11-2006,  6:18PM
    Device Used: XC2C512-7-PQ208
    Fitting Status: Successful

    ****************************  Resource Summary  ****************************

    Macrocells     Product Terms    Registers      Pins           Function Block
    Used           Used             Used           Used           Inputs Used
    64 /512 ( 12%) 135 /1792 (  8%) 31 /512 (  6%) 58 /173 ( 34%) 141/1280 ( 11%)

    PIN RESOURCES:

    Signal Type    Required     Mapped  |  Pin Type            Used   Remaining
    ------------------------------------|---------------------------------------
    Input         :   38          38    |  I/O              :    48      115
    Output        :   18          18    |  GCK/IO           :     3        0
    Bidirectional :    0           0    |  GTS/IO           :     4        0
    GCK           :    2           2    |  GSR/IO           :     1        0
    GTS           :    0           0    |  CDR/IO           :     1        0
    GSR           :    0           0    |  DGE/IO           :     1        0
                     ----        ----
            Total     58          58

    MACROCELL RESOURCES:

    Total Macrocells Available                   512
    Registered Macrocells                         31
    Non-registered Macrocell driving I/O          18

    GLOBAL RESOURCES:

    Signal 'as' mapped onto global clock net GCK1.
    Signal 'inc_add' mapped onto global clock net GCK2.
    Global output enable net(s) unused.
    Global set/reset net(s) unused.

    End of Resource Summary
    *************** Summary of Required Resources ******************

    ** LOGIC **
    Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg     I/O      I/O       Reg Init
    Name                Pt    Used            Rate #    Type      Use     Use     STD      Style     State
    Madd__n0003_CARRY_IN<3>                    4       6     FB2_8             (b)       (b)
    Madd__n0003_CARRY_IN<5>                    3       3     FB3_11            (b)       (b)
    Madd__n0003_CARRY_IN<7>                    3       3     FB3_10            (b)       (b)
    N_PZ_184            2       2     FB2_3             (b)       (b)
    N_PZ_189            2       2     FB2_1             (b)       (b)
    N_PZ_193            3       3     FB3_9             (b)       (b)
    N_PZ_203            3       5     FB2_7             (b)       (b)
    N_PZ_255            3       5     FB2_5             (b)       (b)
    N_PZ_256            1       3     FB3_12            (b)       (b)
    N_PZ_265            2       2     FB3_14            (b)       (b)
    N_PZ_266            3       4     FB2_6             (b)       (b)
    N_PZ_273            3       3     FB3_8             (b)       (b)
    N_PZ_275            3       3     FB3_7             (b)       (b)
    N_PZ_276            3       3     FB3_6             (b)       (b)
    N_PZ_283            3       4     FB2_4             (b)       (b)
    add_aux<0>          0       0     FB1_1        7    GTS/I/O   I       DFF                        RESET
    add_aux<10>         0       0     FB1_2        6    I/O       I       DFF                        RESET
    add_aux<11>         0       0     FB1_3        5    GTS/I/O   I       DFF                        RESET
    add_aux<12>         0       0     FB1_4        4    I/O       I       DFF                        RESET
    add_aux<13>         0       0     FB1_13       3    GTS/I/O   I       DFF                        RESET
    add_aux<14>         0       0     FB1_14       2    I/O       I       DFF                        RESET
    add_aux<15>         0       0     FB1_15       208  I/O       I       DFF                        RESET
    add_aux<16>         0       0     FB1_16       206  GSR/I/O   I       DFF                        RESET
    add_aux<17>         0       0     FB2_2        8    I/O       I       DFF                        RESET
    add_aux<1>          0       0     FB2_14       9    GTS/I/O   I       DFF                        RESET
    add_aux<2>          0       0     FB2_15       10   I/O       I       DFF                        RESET
    add_aux<3>          0       0     FB2_16       12   I/O       I       DFF                        RESET
    add_aux<4>          0       0     FB3_1        205  I/O       I       DFF                        RESET
    add_aux<5>          0       0     FB3_3        203  I/O       I       DFF                        RESET
    add_aux<6>          0       0     FB3_5        202  I/O       I       DFF                        RESET
    add_aux<7>          0       0     FB3_13       201  I/O       I       DFF                        RESET
    add_aux<8>          0       0     FB3_15       200  I/O       I       DFF                        RESET
    add_aux<9>          0       0     FB3_16       199  I/O       I       DFF                        RESET
    madd<0>             4       6     FB4_14  FAST 16   I/O       O               LVCMOS18
    madd<10>            4       6     FB4_15  FAST 17   I/O       O               LVCMOS18
    madd<11>            4       7     FB5_2   FAST 197  I/O       O               LVCMOS18
    madd<12>            5       8     FB5_1   FAST 198  I/O       O               LVCMOS18
    madd<13>            4       6     FB4_16  FAST 18   I/O       O               LVCMOS18
    madd<14>            4       8     FB5_3   FAST 196  I/O       O               LVCMOS18
    madd<15>            4       6     FB5_4   FAST 195  I/O       O               LVCMOS18
    madd<16>            4       7     FB5_5   FAST 194  I/O       O               LVCMOS18
    madd<17>            4       8     FB5_13  FAST 193  I/O       O               LVCMOS18
    madd<1>             6       8     FB4_4   FAST 15   I/O       O               LVCMOS18
    madd<2>             6       9     FB4_2   FAST 14   I/O       O               LVCMOS18
    madd<3>             5       7     FB6_1   FAST 19   I/O       O               LVCMOS18
    madd<4>             5       7     FB6_3   FAST 21   I/O       O               LVCMOS18
    madd<5>             5       7     FB7_1   FAST 191  I/O       O               LVCMOS18
    madd<6>             5       7     FB7_3   FAST 189  I/O       O               LVCMOS18
    madd<7>             5       7     FB7_4   FAST 188  I/O       O               LVCMOS18
    madd<8>             4       6     FB5_15  FAST 192  I/O       O               LVCMOS18
    madd<9>             4       6     FB6_2   FAST 20   I/O       O               LVCMOS18
    va_cnt<0>           1       1     FB1_12            (b)       (b)     TFF                        RESET
    va_cnt<10>          2       11    FB2_11            (b)       (b)     TFF                        RESET
    va_cnt<11>          2       12    FB2_10            (b)       (b)     TFF                        RESET
    va_cnt<12>          2       13    FB2_9             (b)       (b)     TFF                        RESET
    va_cnt<1>           2       2     FB1_11            (b)       (b)     TFF                        RESET
    va_cnt<2>           2       3     FB1_10            (b)       (b)     TFF                        RESET
    va_cnt<3>           2       4     FB1_9             (b)       (b)     TFF                        RESET
    va_cnt<4>           2       5     FB1_8             (b)       (b)     TFF                        RESET
    va_cnt<5>           2       6     FB1_7             (b)       (b)     TFF                        RESET
    va_cnt<6>           2       7     FB1_6             (b)       (b)     TFF                        RESET
    va_cnt<7>           2       8     FB1_5             (b)       (b)     TFF                        RESET
    va_cnt<8>           2       9     FB2_13            (b)       (b)     TFF                        RESET
    va_cnt<9>           2       10    FB2_12            (b)       (b)     TFF                        RESET

    ** INPUTS **
    Signal                            Loc          Pin  Pin       Pin     Reg     I/O      I/O
    Name                                           #    Type      Use     Use     STD      Style
    acc_blk                           FB7_5        187  I/O       I               LVCMOS18 KPR
    acc_fifo                          FB7_13       186  I/O       I               LVCMOS18 KPR
    add<0>                            FB1_1        7    GTS/I/O   I               LVCMOS18 KPR
    add<10>                           FB1_2        6    I/O       I               LVCMOS18 KPR
    add<11>                           FB1_3        5    GTS/I/O   I               LVCMOS18 KPR
    add<12>                           FB1_4        4    I/O       I               LVCMOS18 KPR
    add<13>                           FB1_13       3    GTS/I/O   I               LVCMOS18 KPR
    add<14>                           FB1_14       2    I/O       I               LVCMOS18 KPR
    add<15>                           FB1_15       208  I/O       I               LVCMOS18 KPR
    add<16>                           FB1_16       206  GSR/I/O   I               LVCMOS18 KPR
    add<17>                           FB2_2        8    I/O       I               LVCMOS18 KPR
    add<1>                            FB2_14       9    GTS/I/O   I               LVCMOS18 KPR
    add<2>                            FB2_15       10   I/O       I               LVCMOS18 KPR
    add<3>                            FB2_16       12   I/O       I               LVCMOS18 KPR
    add<4>                            FB3_1        205  I/O       I               LVCMOS18 KPR
    add<5>                            FB3_3        203  I/O       I               LVCMOS18 KPR
    add<6>                            FB3_5        202  I/O       I               LVCMOS18 KPR
    add<7>                            FB3_13       201  I/O       I               LVCMOS18 KPR
    add<8>                            FB3_15       200  I/O       I               LVCMOS18 KPR
    add<9>                            FB3_16       199  I/O       I               LVCMOS18 KPR
    as                                FB9_16       46   GCK/I/O   GCK/I           LVCMOS18 KPR
    inc_add                           FB10_3       55   GCK/I/O   GCK             LVCMOS18 KPR
    mem_pointer<0>                    FB8_2        22   I/O       I               LVCMOS18 KPR
    mem_pointer<10>                   FB8_3        23   I/O       I               LVCMOS18 KPR
    mem_pointer<11>                   FB8_14       25   I/O       I               LVCMOS18 KPR
    mem_pointer<12>                   FB9_2        50   I/O       I               LVCMOS18 KPR
    mem_pointer<13>                   FB9_3        49   I/O       I               LVCMOS18 KPR
    mem_pointer<14>                   FB9_4        48   I/O       I               LVCMOS18 KPR
    mem_pointer<15>                   FB9_14       47   I/O       I               LVCMOS18 KPR
    mem_pointer<16>                   FB10_1       51   CDR/I/O   I               LVCMOS18 KPR
    mem_pointer<17>                   FB10_2       54   I/O       I               LVCMOS18 KPR
    mem_pointer<1>                    FB10_4       56   I/O       I               LVCMOS18 KPR
    mem_pointer<2>                    FB10_13      57   I/O       I               LVCMOS18 KPR
    mem_pointer<3>                    FB10_14      58   DGE/I/O   I               LVCMOS18 KPR
    mem_pointer<4>                    FB11_1       45   I/O       I               LVCMOS18 KPR
    mem_pointer<5>                    FB7_14       185  I/O       I               LVCMOS18 KPR
    mem_pointer<6>                    FB7_15       184  I/O       I               LVCMOS18 KPR
    mem_pointer<7>                    FB7_16       183  I/O       I               LVCMOS18 KPR
    mem_pointer<8>                    FB11_3       44   GCK/I/O   I               LVCMOS18 KPR
    mem_pointer<9>                    FB11_4       43   I/O       I               LVCMOS18 KPR

    End of Resources

    Legend:
    I/O Style - OD    - OpenDrain
              - PU    - Pullup
              - KPR   - Keeper
              - S     - SchmittTrigger
              - DG    - DataGate
    Reg Use   - LATCH - Transparent latch
              - DFF   - D-flip-flop
              - DEFF  - D-flip-flop with clock enable
              - TFF   - T-flip-flop
              - TDFF  - Dual-edge-triggered T-flip-flop
              - DDFF  - Dual-edge-triggered flip-flop
              - DDEFF - Dual-edge-triggered flip-flop with clock enable
              /S (after any above flop/latch type) indicates initial state is Set

    *********************Function Block Resource Summary***********************
    Function    # of        FB Inputs   Signals     Total       O/IO      IO
    Block       Macrocells  Used        Used        Pt Used     Req       Avail
    FB1          16           8           8            8         0/0        8
    FB2          16          26          26           26         0/0        4
    FB3          14          23          23           21         0/0        6
    FB4           5          21          21           23         5/0        5
    FB5           7          30          30           28         7/0        7
    FB6           3          16          16           14         3/0        3
    FB7           3          17          17           15         3/0        8
    FB8           0           0           0            0         0/0        3
    FB9           0           0           0            0         0/0        5
    FB10          0           0           0            0         0/0        6
    FB11          0           0           0            0         0/0        7
    FB12          0           0           0            0         0/0        8
    FB13          0           0           0            0         0/0        5
    FB14          0           0           0            0         0/0        5
    FB15          0           0           0            0         0/0        5
    FB16          0           0           0            0         0/0        5
    FB17          0           0           0            0         0/0        9
    FB18          0           0           0            0         0/0        3
    FB19          0           0           0            0         0/0        3
    FB20          0           0           0            0         0/0        6
    FB21          0           0           0            0         0/0        3
    FB22          0           0           0            0         0/0        8
    FB23          0           0           0            0         0/0        3
    FB24          0           0           0            0         0/0        7
    FB25          0           0           0            0         0/0        8
    FB26          0           0           0            0         0/0        8
    FB27          0           0           0            0         0/0        4
    FB28          0           0           0            0         0/0        3
    FB29          0           0           0            0         0/0        3
    FB30          0           0           0            0         0/0        6
    FB31          0           0           0            0         0/0        4
    FB32          0           0           0            0         0/0        5
                ----                                -----       -----     -----
                 64                                  135        18/0      173
    *********************************** FB1 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  8
    Number of function block inputs used/remaining:               8/32
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   8/48
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    add_aux<0>                        0       FB1_1   7     GTS/I/O  I
    add_aux<10>                       0       FB1_2   6     I/O      I
    add_aux<11>                       0       FB1_3   5     GTS/I/O  I
    add_aux<12>                       0       FB1_4   4     I/O      I
    va_cnt<7>                         2       FB1_5         (b)      (b)
    va_cnt<6>                         2       FB1_6         (b)      (b)
    va_cnt<5>                         2       FB1_7         (b)      (b)
    va_cnt<4>                         2       FB1_8         (b)      (b)
    va_cnt<3>                         2       FB1_9         (b)      (b)
    va_cnt<2>                         2       FB1_10        (b)      (b)
    va_cnt<1>                         2       FB1_11        (b)      (b)
    va_cnt<0>                         1       FB1_12        (b)      (b)
    add_aux<13>                       0       FB1_13  3     GTS/I/O  I
    add_aux<14>                       0       FB1_14  2     I/O      I
    add_aux<15>                       0       FB1_15  208   I/O      I
    add_aux<16>                       0       FB1_16  206   GSR/I/O  I

    Signals Used by Logic in Function Block
      1: as                 4: va_cnt<2>          7: va_cnt<5>
      2: va_cnt<0>          5: va_cnt<3>          8: va_cnt<6>
      3: va_cnt<1>          6: va_cnt<4>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    va_cnt<7>         XXXXXXXX................................ 8       8
    va_cnt<6>         XXXXXXX................................. 7       7
    va_cnt<5>         XXXXXX.................................. 6       6
    va_cnt<4>         XXXXX................................... 5       5
    va_cnt<3>         XXXX.................................... 4       4
    va_cnt<2>         XXX..................................... 3       3
    va_cnt<1>         XX...................................... 2       2
    va_cnt<0>         X....................................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB2 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  26
    Number of function block inputs used/remaining:               26/14
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   26/30
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    N_PZ_189                          2       FB2_1         (b)      (b)
    add_aux<17>                       0       FB2_2   8     I/O      I
    N_PZ_184                          2       FB2_3         (b)      (b)
    N_PZ_283                          3       FB2_4         (b)      (b)
    N_PZ_255                          3       FB2_5         (b)      (b)
    N_PZ_266                          3       FB2_6         (b)      (b)
    N_PZ_203                          3       FB2_7         (b)      (b)
    Madd__n0003_CARRY_IN<3>           4       FB2_8         (b)      (b)
    va_cnt<12>                        2       FB2_9         (b)      (b)
    va_cnt<11>                        2       FB2_10        (b)      (b)
    va_cnt<10>                        2       FB2_11        (b)      (b)
    va_cnt<9>                         2       FB2_12        (b)      (b)
    va_cnt<8>                         2       FB2_13        (b)      (b)
    add_aux<1>                        0       FB2_14  9     GTS/I/O  I
    add_aux<2>                        0       FB2_15  10    I/O      I
    add_aux<3>                        0       FB2_16  12    I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_184          10: add_aux<1>        19: va_cnt<2>
      2: N_PZ_189          11: add_aux<2>        20: va_cnt<3>
      3: N_PZ_203          12: add_aux<8>        21: va_cnt<4>
      4: N_PZ_265          13: add_aux<9>        22: va_cnt<5>
      5: N_PZ_266          14: as                23: va_cnt<6>
      6: N_PZ_276          15: va_cnt<0>         24: va_cnt<7>
      7: N_PZ_283          16: va_cnt<10>        25: va_cnt<8>
      8: add_aux<0>        17: va_cnt<11>        26: va_cnt<9>
      9: add_aux<11>       18: va_cnt<1>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    N_PZ_189          ...........X............X............... 2       2
    N_PZ_184          ..........X.......X..................... 2       2
    N_PZ_283          ..XX....X......X........................ 4       4
    N_PZ_255          ..XX..X........XX....................... 5       5
    N_PZ_266          .X...X......X...........X............... 4       4
    N_PZ_203          .X..XX..................XX.............. 5       5
    Madd__n0003_CARRY_IN<3>
                      X......X.X....X..XX..................... 6       6
    va_cnt<12>        .............XXXXXXXXXXXXX.............. 13      13
    va_cnt<11>        .............XXX.XXXXXXXXX.............. 12      12
    va_cnt<10>        .............XX..XXXXXXXXX.............. 11      11
    va_cnt<9>         .............XX..XXXXXXXX............... 10      10
    va_cnt<8>         .............XX..XXXXXXX................ 9       9
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB3 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  23
    Number of function block inputs used/remaining:               23/17
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   21/35
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    add_aux<4>                        0       FB3_1   205   I/O      I
    (unused)                          0       FB3_2         (b)
    add_aux<5>                        0       FB3_3   203   I/O      I
    (unused)                          0       FB3_4         (b)
    add_aux<6>                        0       FB3_5   202   I/O      I
    N_PZ_276                          3       FB3_6         (b)      (b)
    N_PZ_275                          3       FB3_7         (b)      (b)
    N_PZ_273                          3       FB3_8         (b)      (b)
    N_PZ_193                          3       FB3_9         (b)      (b)
    Madd__n0003_CARRY_IN<7>           3       FB3_10        (b)      (b)
    Madd__n0003_CARRY_IN<5>           3       FB3_11        (b)      (b)
    N_PZ_256                          1       FB3_12        (b)      (b)
    add_aux<7>                        0       FB3_13  201   I/O      I
    N_PZ_265                          2       FB3_14        (b)      (b)
    add_aux<8>                        0       FB3_15  200   I/O      I
    add_aux<9>                        0       FB3_16  199   I/O      I

    Signals Used by Logic in Function Block
      1: Madd__n0003_CARRY_IN<3>
                            9: add_aux<12>       17: va_cnt<10>
      2: Madd__n0003_CARRY_IN<5>
                           10: add_aux<13>       18: va_cnt<12>
      3: Madd__n0003_CARRY_IN<7>
                           11: add_aux<14>       19: va_cnt<3>
      4: N_PZ_193          12: add_aux<3>        20: va_cnt<4>
      5: N_PZ_255          13: add_aux<4>        21: va_cnt<5>
      6: N_PZ_273          14: add_aux<5>        22: va_cnt<6>
      7: N_PZ_275          15: add_aux<6>        23: va_cnt<7>
      8: add_aux<10>       16: add_aux<7>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    N_PZ_276          ..X............X......X................. 3       3
    N_PZ_275          X..........X......X..................... 3       3
    N_PZ_273          .X...........X......X................... 3       3
    N_PZ_193          ....X...X........X...................... 3       3
    Madd__n0003_CARRY_IN<7>
                      .....X........X......X.................. 3       3
    Madd__n0003_CARRY_IN<5>
                      ......X.....X......X.................... 3       3
    N_PZ_256          ...X.....XX............................. 3       3
    N_PZ_265          .......X........X....................... 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB4 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  21
    Number of function block inputs used/remaining:               21/19
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   23/33
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB4_1         (b)
    madd<2>                           6       FB4_2   14    I/O      O
    (unused)                          0       FB4_3         (b)
    madd<1>                           6       FB4_4   15    I/O      O
    (unused)                          0       FB4_5         (b)
    (unused)                          0       FB4_6         (b)
    (unused)                          0       FB4_7         (b)
    (unused)                          0       FB4_8         (b)
    (unused)                          0       FB4_9         (b)
    (unused)                          0       FB4_10        (b)
    (unused)                          0       FB4_11        (b)
    (unused)                          0       FB4_12        (b)
    (unused)                          0       FB4_13        (b)
    madd<0>                           4       FB4_14  16    I/O      O
    madd<10>                          4       FB4_15  17    I/O      O
    madd<13>                          4       FB4_16  18    I/O      O

    Signals Used by Logic in Function Block
      1: N_PZ_184           8: add<10>           15: mem_pointer<0>
      2: N_PZ_193           9: add<13>           16: mem_pointer<10>
      3: N_PZ_203          10: add<1>            17: mem_pointer<13>
      4: N_PZ_265          11: add<2>            18: mem_pointer<1>
      5: acc_blk           12: add_aux<0>        19: mem_pointer<2>
      6: acc_fifo          13: add_aux<13>       20: va_cnt<0>
      7: add<0>            14: add_aux<1>        21: va_cnt<1>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<2>           X...XX....XX.X....XXX................... 9       9
    madd<1>           ....XX...X.X.X...X.XX................... 8       8
    madd<0>           ....XXX....X..X....X.................... 6       6
    madd<10>          ..XXXX.X.......X........................ 6       6
    madd<13>          .X..XX..X...X...X....................... 6       6
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB5 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  30
    Number of function block inputs used/remaining:               30/10
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   28/28
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    madd<12>                          5       FB5_1   198   I/O      O
    madd<11>                          4       FB5_2   197   I/O      O
    madd<14>                          4       FB5_3   196   I/O      O
    madd<15>                          4       FB5_4   195   I/O      O
    madd<16>                          4       FB5_5   194   I/O      O
    (unused)                          0       FB5_6         (b)
    (unused)                          0       FB5_7         (b)
    (unused)                          0       FB5_8         (b)
    (unused)                          0       FB5_9         (b)
    (unused)                          0       FB5_10        (b)
    (unused)                          0       FB5_11        (b)
    (unused)                          0       FB5_12        (b)
    madd<17>                          4       FB5_13  193   I/O      O
    (unused)                          0       FB5_14        (b)
    madd<8>                           4       FB5_15  192   I/O      O
    (unused)                          0       FB5_16        (b)

    Signals Used by Logic in Function Block
      1: N_PZ_189          11: add<14>           21: add_aux<17>
      2: N_PZ_193          12: add<15>           22: mem_pointer<11>
      3: N_PZ_255          13: add<16>           23: mem_pointer<12>
      4: N_PZ_256          14: add<17>           24: mem_pointer<14>
      5: N_PZ_276          15: add<8>            25: mem_pointer<15>
      6: N_PZ_283          16: add_aux<12>       26: mem_pointer<16>
      7: acc_blk           17: add_aux<13>       27: mem_pointer<17>
      8: acc_fifo          18: add_aux<14>       28: mem_pointer<8>
      9: add<11>           19: add_aux<15>       29: va_cnt<11>
     10: add<12>           20: add_aux<16>       30: va_cnt<12>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<12>          .XX...XX.X.....X......X......X.......... 8       8
    madd<11>          ..X..XXXX............X......X........... 7       7
    madd<14>          .X.X..XX..X.....XX.....X................ 8       8
    madd<15>          ...X..XX...X......X.....X............... 6       6
    madd<16>          ...X..XX....X.....XX.....X.............. 7       7
    madd<17>          ...X..XX.....X....XXX.....X............. 8       8
    madd<8>           X...X.XX......X............X............ 6       6
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB6 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  16
    Number of function block inputs used/remaining:               16/24
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   14/42
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    madd<3>                           5       FB6_1   19    I/O      O
    madd<9>                           4       FB6_2   20    I/O      O
    madd<4>                           5       FB6_3   21    I/O      O
    (unused)                          0       FB6_4         (b)
    (unused)                          0       FB6_5         (b)
    (unused)                          0       FB6_6         (b)
    (unused)                          0       FB6_7         (b)
    (unused)                          0       FB6_8         (b)
    (unused)                          0       FB6_9         (b)
    (unused)                          0       FB6_10        (b)
    (unused)                          0       FB6_11        (b)
    (unused)                          0       FB6_12        (b)
    (unused)                          0       FB6_13        (b)
    (unused)                          0       FB6_14        (b)
    (unused)                          0       FB6_15        (b)
    (unused)                          0       FB6_16        (b)

    Signals Used by Logic in Function Block
      1: Madd__n0003_CARRY_IN<3>
                            7: add<4>            12: mem_pointer<4>
      2: N_PZ_266           8: add<9>            13: mem_pointer<9>
      3: N_PZ_275           9: add_aux<3>        14: va_cnt<3>
      4: acc_blk           10: add_aux<4>        15: va_cnt<4>
      5: acc_fifo          11: mem_pointer<3>    16: va_cnt<9>
      6: add<3>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<3>           X..XXX..X.X..X.......................... 7       7
    madd<9>           .X.XX..X....X..X........................ 6       6
    madd<4>           ..XXX.X..X.X..X......................... 7       7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB7 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  17
    Number of function block inputs used/remaining:               17/23
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   15/41
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    madd<5>                           5       FB7_1   191   I/O      O
    (unused)                          0       FB7_2         (b)
    madd<6>                           5       FB7_3   189   I/O      O
    madd<7>                           5       FB7_4   188   I/O      O
    (unused)                          0       FB7_5   187   I/O      I
    (unused)                          0       FB7_6         (b)
    (unused)                          0       FB7_7         (b)
    (unused)                          0       FB7_8         (b)
    (unused)                          0       FB7_9         (b)
    (unused)                          0       FB7_10        (b)
    (unused)                          0       FB7_11        (b)
    (unused)                          0       FB7_12        (b)
    (unused)                          0       FB7_13  186   I/O      I
    (unused)                          0       FB7_14  185   I/O      I
    (unused)                          0       FB7_15  184   I/O      I
    (unused)                          0       FB7_16  183   I/O      I

    Signals Used by Logic in Function Block
      1: Madd__n0003_CARRY_IN<5>
                            7: add<6>            13: mem_pointer<6>
      2: Madd__n0003_CARRY_IN<7>
                            8: add<7>            14: mem_pointer<7>
      3: N_PZ_273           9: add_aux<5>        15: va_cnt<5>
      4: acc_blk           10: add_aux<6>        16: va_cnt<6>
      5: acc_fifo          11: add_aux<7>        17: va_cnt<7>
      6: add<5>            12: mem_pointer<5>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<5>           X..XXX..X..X..X......................... 7       7
    madd<6>           ..XXX.X..X..X..X........................ 7       7
    madd<7>           .X.XX..X..X..X..X....................... 7       7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB8 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB8_1         (b)
    (unused)                          0       FB8_2   22    I/O      I
    (unused)                          0       FB8_3   23    I/O      I
    (unused)                          0       FB8_4         (b)
    (unused)                          0       FB8_5         (b)
    (unused)                          0       FB8_6         (b)
    (unused)                          0       FB8_7         (b)
    (unused)                          0       FB8_8         (b)
    (unused)                          0       FB8_9         (b)
    (unused)                          0       FB8_10        (b)
    (unused)                          0       FB8_11        (b)
    (unused)                          0       FB8_12        (b)
    (unused)                          0       FB8_13        (b)
    (unused)                          0       FB8_14  25    I/O      I
    (unused)                          0       FB8_15        (b)
    (unused)                          0       FB8_16        (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB9 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB9_1         (b)
    (unused)                          0       FB9_2   50    I/O      I
    (unused)                          0       FB9_3   49    I/O      I
    (unused)                          0       FB9_4   48    I/O      I
    (unused)                          0       FB9_5         (b)
    (unused)                          0       FB9_6         (b)
    (unused)                          0       FB9_7         (b)
    (unused)                          0       FB9_8         (b)
    (unused)                          0       FB9_9         (b)
    (unused)                          0       FB9_10        (b)
    (unused)                          0       FB9_11        (b)
    (unused)                          0       FB9_12        (b)
    (unused)                          0       FB9_13        (b)
    (unused)                          0       FB9_14  47    I/O      I
    (unused)                          0       FB9_15        (b)
    (unused)                          0       FB9_16  46    GCK/I/O  GCK/I
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB10 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB10_1  51    CDR/I/O  I
    (unused)                          0       FB10_2  54    I/O      I
    (unused)                          0       FB10_3  55    GCK/I/O  GCK
    (unused)                          0       FB10_4  56    I/O      I
    (unused)                          0       FB10_5        (b)
    (unused)                          0       FB10_6        (b)
    (unused)                          0       FB10_7        (b)
    (unused)                          0       FB10_8        (b)
    (unused)                          0       FB10_9        (b)
    (unused)                          0       FB10_10       (b)
    (unused)                          0       FB10_11       (b)
    (unused)                          0       FB10_12       (b)
    (unused)                          0       FB10_13 57    I/O      I
    (unused)                          0       FB10_14 58    DGE/I/O  I
    (unused)                          0       FB10_15       (b)
    (unused)                          0       FB10_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB11 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB11_1  45    I/O      I
    (unused)                          0       FB11_2        (b)
    (unused)                          0       FB11_3  44    GCK/I/O  I
    (unused)                          0       FB11_4  43    I/O      I
    (unused)                          0       FB11_5        (b)
    (unused)                          0       FB11_6        (b)
    (unused)                          0       FB11_7        (b)
    (unused)                          0       FB11_8        (b)
    (unused)                          0       FB11_9        (b)
    (unused)                          0       FB11_10       (b)
    (unused)                          0       FB11_11       (b)
    (unused)                          0       FB11_12       (b)
    (unused)                          0       FB11_13 41    I/O
    (unused)                          0       FB11_14 40    I/O
    (unused)                          0       FB11_15 39    I/O
    (unused)                          0       FB11_16 38    I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB12 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB12_1  60    I/O
    (unused)                          0       FB12_2  61    I/O
    (unused)                          0       FB12_3  62    I/O
    (unused)                          0       FB12_4  63    I/O
    (unused)                          0       FB12_5  64    I/O
    (unused)                          0       FB12_6        (b)
    (unused)                          0       FB12_7        (b)
    (unused)                          0       FB12_8        (b)
    (unused)                          0       FB12_9        (b)
    (unused)                          0       FB12_10       (b)
    (unused)                          0       FB12_11       (b)
    (unused)                          0       FB12_12       (b)
    (unused)                          0       FB12_13 65    I/O
    (unused)                          0       FB12_14 66    I/O
    (unused)                          0       FB12_15 67    I/O
    (unused)                          0       FB12_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB13 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB13_1  37    I/O
    (unused)                          0       FB13_2        (b)
    (unused)                          0       FB13_3  36    I/O
    (unused)                          0       FB13_4  35    I/O
    (unused)                          0       FB13_5        (b)
    (unused)                          0       FB13_6        (b)
    (unused)                          0       FB13_7        (b)
    (unused)                          0       FB13_8        (b)
    (unused)                          0       FB13_9        (b)
    (unused)                          0       FB13_10       (b)
    (unused)                          0       FB13_11       (b)
    (unused)                          0       FB13_12       (b)
    (unused)                          0       FB13_13       (b)
    (unused)                          0       FB13_14 34    I/O
    (unused)                          0       FB13_15 32    I/O
    (unused)                          0       FB13_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB14 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB14_1        (b)
    (unused)                          0       FB14_2        (b)
    (unused)                          0       FB14_3  69    I/O
    (unused)                          0       FB14_4  70    I/O
    (unused)                          0       FB14_5  71    I/O
    (unused)                          0       FB14_6        (b)
    (unused)                          0       FB14_7        (b)
    (unused)                          0       FB14_8        (b)
    (unused)                          0       FB14_9        (b)
    (unused)                          0       FB14_10       (b)
    (unused)                          0       FB14_11       (b)
    (unused)                          0       FB14_12       (b)
    (unused)                          0       FB14_13 72    I/O
    (unused)                          0       FB14_14       (b)
    (unused)                          0       FB14_15 73    I/O
    (unused)                          0       FB14_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB15 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB15_1  31    I/O
    (unused)                          0       FB15_2        (b)
    (unused)                          0       FB15_3  30    I/O
    (unused)                          0       FB15_4  29    I/O
    (unused)                          0       FB15_5        (b)
    (unused)                          0       FB15_6        (b)
    (unused)                          0       FB15_7        (b)
    (unused)                          0       FB15_8        (b)
    (unused)                          0       FB15_9        (b)
    (unused)                          0       FB15_10       (b)
    (unused)                          0       FB15_11       (b)
    (unused)                          0       FB15_12       (b)
    (unused)                          0       FB15_13 28    I/O
    (unused)                          0       FB15_14 27    I/O
    (unused)                          0       FB15_15       (b)
    (unused)                          0       FB15_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB16 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB16_1  74    I/O
    (unused)                          0       FB16_2        (b)
    (unused)                          0       FB16_3  75    I/O
    (unused)                          0       FB16_4  76    I/O
    (unused)                          0       FB16_5  77    I/O
    (unused)                          0       FB16_6        (b)
    (unused)                          0       FB16_7        (b)
    (unused)                          0       FB16_8        (b)
    (unused)                          0       FB16_9        (b)
    (unused)                          0       FB16_10       (b)
    (unused)                          0       FB16_11       (b)
    (unused)                          0       FB16_12       (b)
    (unused)                          0       FB16_13       (b)
    (unused)                          0       FB16_14 78    I/O
    (unused)                          0       FB16_15       (b)
    (unused)                          0       FB16_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB17 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB17_1  161   I/O
    (unused)                          0       FB17_2  162   I/O
    (unused)                          0       FB17_3  163   I/O
    (unused)                          0       FB17_4  164   I/O
    (unused)                          0       FB17_5  165   I/O
    (unused)                          0       FB17_6        (b)
    (unused)                          0       FB17_7        (b)
    (unused)                          0       FB17_8        (b)
    (unused)                          0       FB17_9        (b)
    (unused)                          0       FB17_10       (b)
    (unused)                          0       FB17_11       (b)
    (unused)                          0       FB17_12       (b)
    (unused)                          0       FB17_13 166   I/O
    (unused)                          0       FB17_14 167   I/O
    (unused)                          0       FB17_15 168   I/O
    (unused)                          0       FB17_16 169   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB18 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB18_1  160   I/O
    (unused)                          0       FB18_2        (b)
    (unused)                          0       FB18_3        (b)
    (unused)                          0       FB18_4  159   I/O
    (unused)                          0       FB18_5        (b)
    (unused)                          0       FB18_6        (b)
    (unused)                          0       FB18_7        (b)
    (unused)                          0       FB18_8        (b)
    (unused)                          0       FB18_9        (b)
    (unused)                          0       FB18_10       (b)
    (unused)                          0       FB18_11       (b)
    (unused)                          0       FB18_12       (b)
    (unused)                          0       FB18_13       (b)
    (unused)                          0       FB18_14       (b)
    (unused)                          0       FB18_15 158   I/O
    (unused)                          0       FB18_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB19 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB19_1  170   I/O
    (unused)                          0       FB19_2  171   I/O
    (unused)                          0       FB19_3  173   I/O
    (unused)                          0       FB19_4        (b)
    (unused)                          0       FB19_5        (b)
    (unused)                          0       FB19_6        (b)
    (unused)                          0       FB19_7        (b)
    (unused)                          0       FB19_8        (b)
    (unused)                          0       FB19_9        (b)
    (unused)                          0       FB19_10       (b)
    (unused)                          0       FB19_11       (b)
    (unused)                          0       FB19_12       (b)
    (unused)                          0       FB19_13       (b)
    (unused)                          0       FB19_14       (b)
    (unused)                          0       FB19_15       (b)
    (unused)                          0       FB19_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB20 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB20_1        (b)
    (unused)                          0       FB20_2        (b)
    (unused)                          0       FB20_3  155   I/O
    (unused)                          0       FB20_4  154   I/O
    (unused)                          0       FB20_5        (b)
    (unused)                          0       FB20_6        (b)
    (unused)                          0       FB20_7        (b)
    (unused)                          0       FB20_8        (b)
    (unused)                          0       FB20_9        (b)
    (unused)                          0       FB20_10       (b)
    (unused)                          0       FB20_11       (b)
    (unused)                          0       FB20_12       (b)
    (unused)                          0       FB20_13 153   I/O
    (unused)                          0       FB20_14 152   I/O
    (unused)                          0       FB20_15 151   I/O
    (unused)                          0       FB20_16 150   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB21 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB21_1        (b)
    (unused)                          0       FB21_2  174   I/O
    (unused)                          0       FB21_3  175   I/O
    (unused)                          0       FB21_4        (b)
    (unused)                          0       FB21_5  178   I/O
    (unused)                          0       FB21_6        (b)
    (unused)                          0       FB21_7        (b)
    (unused)                          0       FB21_8        (b)
    (unused)                          0       FB21_9        (b)
    (unused)                          0       FB21_10       (b)
    (unused)                          0       FB21_11       (b)
    (unused)                          0       FB21_12       (b)
    (unused)                          0       FB21_13       (b)
    (unused)                          0       FB21_14       (b)
    (unused)                          0       FB21_15       (b)
    (unused)                          0       FB21_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB22 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB22_1  149   I/O
    (unused)                          0       FB22_2  148   I/O
    (unused)                          0       FB22_3  147   I/O
    (unused)                          0       FB22_4  146   I/O
    (unused)                          0       FB22_5        (b)
    (unused)                          0       FB22_6        (b)
    (unused)                          0       FB22_7        (b)
    (unused)                          0       FB22_8        (b)
    (unused)                          0       FB22_9        (b)
    (unused)                          0       FB22_10       (b)
    (unused)                          0       FB22_11       (b)
    (unused)                          0       FB22_12       (b)
    (unused)                          0       FB22_13 145   I/O
    (unused)                          0       FB22_14 144   I/O
    (unused)                          0       FB22_15 143   I/O
    (unused)                          0       FB22_16 142   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB23 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB23_1  179   I/O
    (unused)                          0       FB23_2  180   I/O
    (unused)                          0       FB23_3        (b)
    (unused)                          0       FB23_4  182   I/O
    (unused)                          0       FB23_5        (b)
    (unused)                          0       FB23_6        (b)
    (unused)                          0       FB23_7        (b)
    (unused)                          0       FB23_8        (b)
    (unused)                          0       FB23_9        (b)
    (unused)                          0       FB23_10       (b)
    (unused)                          0       FB23_11       (b)
    (unused)                          0       FB23_12       (b)
    (unused)                          0       FB23_13       (b)
    (unused)                          0       FB23_14       (b)
    (unused)                          0       FB23_15       (b)
    (unused)                          0       FB23_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB24 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB24_1  140   I/O
    (unused)                          0       FB24_2  139   I/O
    (unused)                          0       FB24_3  138   I/O
    (unused)                          0       FB24_4  137   I/O
    (unused)                          0       FB24_5        (b)
    (unused)                          0       FB24_6        (b)
    (unused)                          0       FB24_7        (b)
    (unused)                          0       FB24_8        (b)
    (unused)                          0       FB24_9        (b)
    (unused)                          0       FB24_10       (b)
    (unused)                          0       FB24_11       (b)
    (unused)                          0       FB24_12       (b)
    (unused)                          0       FB24_13 136   I/O
    (unused)                          0       FB24_14 135   I/O
    (unused)                          0       FB24_15 134   I/O
    (unused)                          0       FB24_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB25 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB25_1  110   I/O
    (unused)                          0       FB25_2  111   I/O
    (unused)                          0       FB25_3  112   I/O
    (unused)                          0       FB25_4  113   I/O
    (unused)                          0       FB25_5        (b)
    (unused)                          0       FB25_6        (b)
    (unused)                          0       FB25_7        (b)
    (unused)                          0       FB25_8        (b)
    (unused)                          0       FB25_9        (b)
    (unused)                          0       FB25_10       (b)
    (unused)                          0       FB25_11       (b)
    (unused)                          0       FB25_12       (b)
    (unused)                          0       FB25_13 114   I/O
    (unused)                          0       FB25_14 115   I/O
    (unused)                          0       FB25_15 116   I/O
    (unused)                          0       FB25_16 117   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB26 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB26_1  109   I/O
    (unused)                          0       FB26_2  108   I/O
    (unused)                          0       FB26_3  107   I/O
    (unused)                          0       FB26_4  106   I/O
    (unused)                          0       FB26_5        (b)
    (unused)                          0       FB26_6        (b)
    (unused)                          0       FB26_7        (b)
    (unused)                          0       FB26_8        (b)
    (unused)                          0       FB26_9        (b)
    (unused)                          0       FB26_10       (b)
    (unused)                          0       FB26_11       (b)
    (unused)                          0       FB26_12       (b)
    (unused)                          0       FB26_13 103   I/O
    (unused)                          0       FB26_14 102   I/O
    (unused)                          0       FB26_15 101   I/O
    (unused)                          0       FB26_16 100   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB27 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB27_1  118   I/O
    (unused)                          0       FB27_2        (b)
    (unused)                          0       FB27_3  119   I/O
    (unused)                          0       FB27_4  120   I/O
    (unused)                          0       FB27_5        (b)
    (unused)                          0       FB27_6        (b)
    (unused)                          0       FB27_7        (b)
    (unused)                          0       FB27_8        (b)
    (unused)                          0       FB27_9        (b)
    (unused)                          0       FB27_10       (b)
    (unused)                          0       FB27_11       (b)
    (unused)                          0       FB27_12       (b)
    (unused)                          0       FB27_13       (b)
    (unused)                          0       FB27_14       (b)
    (unused)                          0       FB27_15 121   I/O
    (unused)                          0       FB27_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB28 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB28_1  99    I/O
    (unused)                          0       FB28_2  97    I/O
    (unused)                          0       FB28_3  95    I/O
    (unused)                          0       FB28_4        (b)
    (unused)                          0       FB28_5        (b)
    (unused)                          0       FB28_6        (b)
    (unused)                          0       FB28_7        (b)
    (unused)                          0       FB28_8        (b)
    (unused)                          0       FB28_9        (b)
    (unused)                          0       FB28_10       (b)
    (unused)                          0       FB28_11       (b)
    (unused)                          0       FB28_12       (b)
    (unused)                          0       FB28_13       (b)
    (unused)                          0       FB28_14       (b)
    (unused)                          0       FB28_15       (b)
    (unused)                          0       FB28_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB29 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB29_1        (b)
    (unused)                          0       FB29_2        (b)
    (unused)                          0       FB29_3  122   I/O
    (unused)                          0       FB29_4  123   I/O
    (unused)                          0       FB29_5        (b)
    (unused)                          0       FB29_6        (b)
    (unused)                          0       FB29_7        (b)
    (unused)                          0       FB29_8        (b)
    (unused)                          0       FB29_9        (b)
    (unused)                          0       FB29_10       (b)
    (unused)                          0       FB29_11       (b)
    (unused)                          0       FB29_12       (b)
    (unused)                          0       FB29_13       (b)
    (unused)                          0       FB29_14 125   I/O
    (unused)                          0       FB29_15       (b)
    (unused)                          0       FB29_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB30 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB30_1        (b)
    (unused)                          0       FB30_2  91    I/O
    (unused)                          0       FB30_3  90    I/O
    (unused)                          0       FB30_4  89    I/O
    (unused)                          0       FB30_5        (b)
    (unused)                          0       FB30_6        (b)
    (unused)                          0       FB30_7        (b)
    (unused)                          0       FB30_8        (b)
    (unused)                          0       FB30_9        (b)
    (unused)                          0       FB30_10       (b)
    (unused)                          0       FB30_11       (b)
    (unused)                          0       FB30_12       (b)
    (unused)                          0       FB30_13 88    I/O
    (unused)                          0       FB30_14 87    I/O
    (unused)                          0       FB30_15       (b)
    (unused)                          0       FB30_16 86    I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB31 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB31_1  126   I/O
    (unused)                          0       FB31_2        (b)
    (unused)                          0       FB31_3  127   I/O
    (unused)                          0       FB31_4  128   I/O
    (unused)                          0       FB31_5        (b)
    (unused)                          0       FB31_6        (b)
    (unused)                          0       FB31_7        (b)
    (unused)                          0       FB31_8        (b)
    (unused)                          0       FB31_9        (b)
    (unused)                          0       FB31_10       (b)
    (unused)                          0       FB31_11       (b)
    (unused)                          0       FB31_12       (b)
    (unused)                          0       FB31_13       (b)
    (unused)                          0       FB31_14       (b)
    (unused)                          0       FB31_15       (b)
    (unused)                          0       FB31_16 131   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB32 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB32_1  85    I/O
    (unused)                          0       FB32_2  84    I/O
    (unused)                          0       FB32_3        (b)
    (unused)                          0       FB32_4  83    I/O
    (unused)                          0       FB32_5        (b)
    (unused)                          0       FB32_6        (b)
    (unused)                          0       FB32_7        (b)
    (unused)                          0       FB32_8        (b)
    (unused)                          0       FB32_9        (b)
    (unused)                          0       FB32_10       (b)
    (unused)                          0       FB32_11       (b)
    (unused)                          0       FB32_12       (b)
    (unused)                          0       FB32_13 82    I/O
    (unused)                          0       FB32_14 80    I/O
    (unused)                          0       FB32_15       (b)
    (unused)                          0       FB32_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    ;;-----------------------------------------------------------------;;
    ; Implemented Equations.

    madd(0) <= NOT (((NOT mem_pointer(0) AND acc_fifo)
    	OR (NOT acc_fifo AND NOT add(0) AND NOT acc_blk)
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0))
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(0) AND NOT add_aux(0))));

    FTCPE_va_cnt0: FTCPE port map (va_cnt(0),'0',inc_add,as,'0','1');

    FDCPE_add_aux0: FDCPE port map (add_aux(0),add(0),NOT as,'0','0','1');

    madd(10) <= NOT (((acc_fifo AND NOT mem_pointer(10))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(10))
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_203 AND N_PZ_265)
    	OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_203 AND NOT N_PZ_265)));

    N_PZ_203 <= ((NOT va_cnt(9) AND N_PZ_266)
    	OR (NOT va_cnt(8) AND NOT N_PZ_266 AND N_PZ_189)
    	OR (NOT N_PZ_266 AND NOT N_PZ_189 AND N_PZ_276));

    FTCPE_va_cnt9: FTCPE port map (va_cnt(9),va_cnt_T(9),inc_add,as,'0','1');
    va_cnt_T(9) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND
    	va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND va_cnt(8));

    FTCPE_va_cnt1: FTCPE port map (va_cnt(1),va_cnt(0),inc_add,as,'0','1');

    FTCPE_va_cnt2: FTCPE port map (va_cnt(2),va_cnt_T(2),inc_add,as,'0','1');
    va_cnt_T(2) <= (va_cnt(0) AND va_cnt(1));

    FTCPE_va_cnt3: FTCPE port map (va_cnt(3),va_cnt_T(3),inc_add,as,'0','1');
    va_cnt_T(3) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2));

    FTCPE_va_cnt4: FTCPE port map (va_cnt(4),va_cnt_T(4),inc_add,as,'0','1');
    va_cnt_T(4) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3));

    FTCPE_va_cnt5: FTCPE port map (va_cnt(5),va_cnt_T(5),inc_add,as,'0','1');
    va_cnt_T(5) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND
    	va_cnt(4));

    FTCPE_va_cnt6: FTCPE port map (va_cnt(6),va_cnt_T(6),inc_add,as,'0','1');
    va_cnt_T(6) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND
    	va_cnt(4) AND va_cnt(5));

    FTCPE_va_cnt7: FTCPE port map (va_cnt(7),va_cnt_T(7),inc_add,as,'0','1');
    va_cnt_T(7) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND
    	va_cnt(4) AND va_cnt(5) AND va_cnt(6));

    FTCPE_va_cnt8: FTCPE port map (va_cnt(8),va_cnt_T(8),inc_add,as,'0','1');
    va_cnt_T(8) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND
    	va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7));

    N_PZ_266 <= add_aux(9)
    	XOR ((va_cnt(8) AND N_PZ_189)
    	OR (NOT N_PZ_189 AND NOT N_PZ_276));

    FDCPE_add_aux9: FDCPE port map (add_aux(9),add(9),NOT as,'0','0','1');

    N_PZ_189 <= ((va_cnt(8) AND add_aux(8))
    	OR (NOT va_cnt(8) AND NOT add_aux(8)));

    FDCPE_add_aux8: FDCPE port map (add_aux(8),add(8),NOT as,'0','0','1');

    N_PZ_276 <= ((NOT va_cnt(7) AND NOT add_aux(7))
    	OR (NOT va_cnt(7) AND Madd__n0003_CARRY_IN(7))
    	OR (NOT add_aux(7) AND Madd__n0003_CARRY_IN(7)));

    FDCPE_add_aux7: FDCPE port map (add_aux(7),add(7),NOT as,'0','0','1');

    Madd__n0003_CARRY_IN(7) <= ((NOT va_cnt(6) AND NOT add_aux(6))
    	OR (va_cnt(6) AND NOT add_aux(6) AND N_PZ_273)
    	OR (NOT va_cnt(6) AND add_aux(6) AND N_PZ_273));

    FDCPE_add_aux6: FDCPE port map (add_aux(6),add(6),NOT as,'0','0','1');

    N_PZ_273 <= ((NOT va_cnt(5) AND NOT add_aux(5))
    	OR (NOT va_cnt(5) AND Madd__n0003_CARRY_IN(5))
    	OR (NOT add_aux(5) AND Madd__n0003_CARRY_IN(5)));

    FDCPE_add_aux5: FDCPE port map (add_aux(5),add(5),NOT as,'0','0','1');

    Madd__n0003_CARRY_IN(5) <= ((NOT va_cnt(4) AND NOT add_aux(4))
    	OR (va_cnt(4) AND NOT add_aux(4) AND N_PZ_275)
    	OR (NOT va_cnt(4) AND add_aux(4) AND N_PZ_275));

    FDCPE_add_aux4: FDCPE port map (add_aux(4),add(4),NOT as,'0','0','1');

    N_PZ_275 <= ((NOT va_cnt(3) AND NOT add_aux(3))
    	OR (NOT va_cnt(3) AND NOT Madd__n0003_CARRY_IN(3))
    	OR (NOT add_aux(3) AND NOT Madd__n0003_CARRY_IN(3)));

    FDCPE_add_aux3: FDCPE port map (add_aux(3),add(3),NOT as,'0','0','1');

    Madd__n0003_CARRY_IN(3) <= ((va_cnt(2) AND N_PZ_184)
    	OR (va_cnt(1) AND NOT N_PZ_184 AND add_aux(1))
    	OR (va_cnt(0) AND add_aux(0) AND va_cnt(1) AND NOT N_PZ_184)
    	OR (va_cnt(0) AND add_aux(0) AND NOT N_PZ_184 AND add_aux(1)));

    N_PZ_184 <= ((va_cnt(2) AND add_aux(2))
    	OR (NOT va_cnt(2) AND NOT add_aux(2)));

    FDCPE_add_aux2: FDCPE port map (add_aux(2),add(2),NOT as,'0','0','1');

    FDCPE_add_aux1: FDCPE port map (add_aux(1),add(1),NOT as,'0','0','1');

    N_PZ_265 <= ((add_aux(10) AND va_cnt(10))
    	OR (NOT add_aux(10) AND NOT va_cnt(10)));

    FDCPE_add_aux10: FDCPE port map (add_aux(10),add(10),NOT as,'0','0','1');

    FTCPE_va_cnt10: FTCPE port map (va_cnt(10),va_cnt_T(10),inc_add,as,'0','1');
    va_cnt_T(10) <= (va_cnt(0) AND va_cnt(9) AND va_cnt(1) AND va_cnt(2) AND
    	va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND
    	va_cnt(8));

    madd(11) <= NOT (((acc_fifo AND NOT mem_pointer(11))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(11))
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(11) AND NOT N_PZ_283)
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_283 AND NOT N_PZ_255)));

    FTCPE_va_cnt11: FTCPE port map (va_cnt(11),va_cnt_T(11),inc_add,as,'0','1');
    va_cnt_T(11) <= (va_cnt(0) AND va_cnt(9) AND va_cnt(1) AND va_cnt(2) AND
    	va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND
    	va_cnt(8) AND va_cnt(10));

    N_PZ_283 <= add_aux(11)
    	XOR ((NOT N_PZ_203 AND NOT N_PZ_265)
    	OR (N_PZ_265 AND va_cnt(10)));

    FDCPE_add_aux11: FDCPE port map (add_aux(11),add(11),NOT as,'0','0','1');

    N_PZ_255 <= ((NOT va_cnt(11) AND N_PZ_283)
    	OR (N_PZ_203 AND NOT N_PZ_265 AND NOT N_PZ_283)
    	OR (N_PZ_265 AND NOT va_cnt(10) AND NOT N_PZ_283));

    madd(12) <= NOT ((NOT acc_fifo AND acc_blk AND NOT N_PZ_193)
    	XOR ((acc_fifo AND NOT mem_pointer(12))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(12))
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_255 AND N_PZ_193 AND
    	NOT add_aux(12) AND NOT va_cnt(12))
    	OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_255 AND NOT N_PZ_193 AND
    	add_aux(12) AND va_cnt(12))));

    N_PZ_193 <= ((N_PZ_255 AND NOT add_aux(12))
    	OR (N_PZ_255 AND NOT va_cnt(12))
    	OR (NOT add_aux(12) AND NOT va_cnt(12)));

    FDCPE_add_aux12: FDCPE port map (add_aux(12),add(12),NOT as,'0','0','1');

    FTCPE_va_cnt12: FTCPE port map (va_cnt(12),va_cnt_T(12),inc_add,as,'0','1');
    va_cnt_T(12) <= (va_cnt(0) AND va_cnt(9) AND va_cnt(1) AND va_cnt(2) AND
    	va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND
    	va_cnt(8) AND va_cnt(10) AND va_cnt(11));

    madd(13) <= NOT (((acc_fifo AND NOT mem_pointer(13))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(13))
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_193 AND NOT add_aux(13))
    	OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_193 AND add_aux(13))));

    FDCPE_add_aux13: FDCPE port map (add_aux(13),add(13),NOT as,'0','0','1');

    madd(14) <= ((acc_fifo AND mem_pointer(14))
    	OR (NOT acc_fifo AND NOT acc_blk AND add(14))
    	OR (NOT acc_fifo AND acc_blk AND add_aux(14) AND NOT N_PZ_256)
    	OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_193 AND add_aux(13) AND
    	NOT N_PZ_256));

    FDCPE_add_aux14: FDCPE port map (add_aux(14),add(14),NOT as,'0','0','1');

    N_PZ_256 <= (NOT N_PZ_193 AND add_aux(13) AND add_aux(14));

    madd(15) <= NOT (((acc_fifo AND NOT mem_pointer(15))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(15))
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_256 AND add_aux(15))
    	OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_256 AND NOT add_aux(15))));

    FDCPE_add_aux15: FDCPE port map (add_aux(15),add(15),NOT as,'0','0','1');

    madd(16) <= NOT ((NOT acc_fifo AND acc_blk AND NOT add_aux(16))
    	XOR ((acc_fifo AND NOT mem_pointer(16))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(16))
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_256 AND add_aux(15))));

    FDCPE_add_aux16: FDCPE port map (add_aux(16),add(16),NOT as,'0','0','1');

    madd(17) <= NOT ((NOT acc_fifo AND acc_blk AND NOT add_aux(17))
    	XOR ((acc_fifo AND NOT mem_pointer(17))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(17))
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_256 AND add_aux(15) AND
    	add_aux(16))));

    FDCPE_add_aux17: FDCPE port map (add_aux(17),add(17),NOT as,'0','0','1');

    madd(1) <= NOT ((NOT acc_fifo AND acc_blk AND add_aux(1))
    	XOR ((acc_fifo AND NOT mem_pointer(1))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(1))
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(0) AND NOT va_cnt(1))
    	OR (NOT acc_fifo AND acc_blk AND NOT add_aux(0) AND NOT va_cnt(1))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0) AND
    	va_cnt(1))));

    madd(2) <= NOT ((NOT acc_fifo AND acc_blk AND N_PZ_184)
    	XOR ((acc_fifo AND NOT mem_pointer(2))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(2))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(1) AND add_aux(1))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0) AND
    	va_cnt(1))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0) AND
    	add_aux(1))));

    madd(3) <= NOT ((NOT acc_fifo AND acc_blk AND Madd__n0003_CARRY_IN(3))
    	XOR ((acc_fifo AND NOT mem_pointer(3))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(3))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(3) AND add_aux(3))
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(3) AND NOT add_aux(3))));

    madd(4) <= NOT ((NOT acc_fifo AND acc_blk AND add_aux(4))
    	XOR ((acc_fifo AND NOT mem_pointer(4))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(4))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(4) AND NOT N_PZ_275)
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(4) AND N_PZ_275)));

    madd(5) <= NOT ((NOT acc_fifo AND acc_blk AND Madd__n0003_CARRY_IN(5))
    	XOR ((acc_fifo AND NOT mem_pointer(5))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(5))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(5) AND NOT add_aux(5))
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(5) AND add_aux(5))));

    madd(6) <= NOT ((NOT acc_fifo AND acc_blk AND add_aux(6))
    	XOR ((acc_fifo AND NOT mem_pointer(6))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(6))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(6) AND NOT N_PZ_273)
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(6) AND N_PZ_273)));

    madd(7) <= NOT ((NOT acc_fifo AND acc_blk AND Madd__n0003_CARRY_IN(7))
    	XOR ((acc_fifo AND NOT mem_pointer(7))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(7))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(7) AND NOT add_aux(7))
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(7) AND add_aux(7))));

    madd(8) <= NOT (((acc_fifo AND NOT mem_pointer(8))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(8))
    	OR (NOT acc_fifo AND acc_blk AND N_PZ_189 AND N_PZ_276)
    	OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_189 AND NOT N_PZ_276)));

    madd(9) <= NOT (((acc_fifo AND NOT mem_pointer(9))
    	OR (NOT acc_fifo AND NOT acc_blk AND NOT add(9))
    	OR (NOT acc_fifo AND acc_blk AND va_cnt(9) AND N_PZ_266)
    	OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(9) AND NOT N_PZ_266)));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FDDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     FTDCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ****************************  Device Pin Out ****************************

    Device : XC2C512-7-PQ208

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 VCC                             105 VCCIO-UNUSED
      2 add<14>                         106 KPR
      3 add<13>                         107 KPR
      4 add<12>                         108 KPR
      5 add<11>                         109 KPR
      6 add<10>                         110 KPR
      7 add<0>                          111 KPR
      8 add<17>                         112 KPR
      9 add<1>                          113 KPR
     10 add<2>                          114 KPR
     11 VCCAUX                          115 KPR
     12 add<3>                          116 KPR
     13 GND                             117 KPR
     14 madd<2>                         118 KPR
     15 madd<1>                         119 KPR
     16 madd<0>                         120 KPR
     17 madd<10>                        121 KPR
     18 madd<13>                        122 KPR
     19 madd<3>                         123 KPR
     20 madd<9>                         124 VCC
     21 madd<4>                         125 KPR
     22 mem_pointer<0>                  126 KPR
     23 mem_pointer<10>                 127 KPR
     24 GND                             128 KPR
     25 mem_pointer<11>                 129 GND
     26 VCCIO-1.8                       130 GND
     27 KPR                             131 KPR
     28 KPR                             132 VCCIO-UNUSED
     29 KPR                             133 VCCIO-UNUSED
     30 KPR                             134 KPR
     31 KPR                             135 KPR
     32 KPR                             136 KPR
     33 VCCIO-1.8                       137 KPR
     34 KPR                             138 KPR
     35 KPR                             139 KPR
     36 KPR                             140 KPR
     37 KPR                             141 GND
     38 KPR                             142 KPR
     39 KPR                             143 KPR
     40 KPR                             144 KPR
     41 KPR                             145 KPR
     42 GND                             146 KPR
     43 mem_pointer<9>                  147 KPR
     44 mem_pointer<8>                  148 KPR
     45 mem_pointer<4>                  149 KPR
     46 as                              150 KPR
     47 mem_pointer<15>                 151 KPR
     48 mem_pointer<14>                 152 KPR
     49 mem_pointer<13>                 153 KPR
     50 mem_pointer<12>                 154 KPR
     51 mem_pointer<16>                 155 KPR
     52 GND                             156 GND
     53 VCC                             157 VCCIO-UNUSED
     54 mem_pointer<17>                 158 KPR
     55 inc_add                         159 KPR
     56 mem_pointer<1>                  160 KPR
     57 mem_pointer<2>                  161 KPR
     58 mem_pointer<3>                  162 KPR
     59 VCCIO-1.8                       163 KPR
     60 KPR                             164 KPR
     61 KPR                             165 KPR
     62 KPR                             166 KPR
     63 KPR                             167 KPR
     64 KPR                             168 KPR
     65 KPR                             169 KPR
     66 KPR                             170 KPR
     67 KPR                             171 KPR
     68 GND                             172 VCCIO-UNUSED
     69 KPR                             173 KPR
     70 KPR                             174 KPR
     71 KPR                             175 KPR
     72 KPR                             176 TDO
     73 KPR                             177 GND
     74 KPR                             178 KPR
     75 KPR                             179 KPR
     76 KPR                             180 KPR
     77 KPR                             181 VCCIO-UNUSED
     78 KPR                             182 KPR
     79 VCCIO-1.8                       183 mem_pointer<7>
     80 KPR                             184 mem_pointer<6>
     81 GND                             185 mem_pointer<5>
     82 KPR                             186 acc_fifo
     83 KPR                             187 acc_blk
     84 KPR                             188 madd<7>
     85 KPR                             189 madd<6>
     86 KPR                             190 GND
     87 KPR                             191 madd<5>
     88 KPR                             192 madd<8>
     89 KPR                             193 madd<17>
     90 KPR                             194 madd<16>
     91 KPR                             195 madd<15>
     92 VCCIO-UNUSED                    196 madd<14>
     93 GND                             197 madd<11>
     94 TDI                             198 madd<12>
     95 KPR                             199 add<9>
     96 TMS                             200 add<8>
     97 KPR                             201 add<7>
     98 TCK                             202 add<6>
     99 KPR                             203 add<5>
    100 KPR                             204 VCCIO-1.8
    101 KPR                             205 add<4>
    102 KPR                             206 add<16>
    103 KPR                             207 GND
    104 GND                             208 add<15>

    Legend :  NC  = Not Connected, unbonded pin
            PGND  = Unused I/O configured as additional Ground pin
             KPR  = Unused I/O with weak keeper (leave unconnected)
             WPU  = Unused I/O with weak pull up (leave unconnected)
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
          VCCAUX  = Power supply for JTAG pins
       VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
       VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
       VCCIO-1.8  = I/O supply voltage for LVCMOS18
       VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
            VREF  = Reference voltage for indicated input standard
           *VREF  = Reference voltage pin selected by software
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc2c512-7-PQ208
    Optimization Method                         : DENSITY
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Set Unused I/O Pin Termination              : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Enable Input Registers                      : ON
    Function Block Fan-in Limit                 : 38
    Use DATA_GATE Attribute                     : ON
    Set Tristate Outputs to Termination Mode    : KEEPER
    Default Voltage Standard for All Outputs    : LVCMOS18
    Input Limit                                 : 32
    Pterm Limit                                 : 28