### Legends

Acronym | Verbose Description
--- | ---
(b) | Buried macrocell
DFF | D Flip-Flop
DDFF | Dual-edge triggered D Flip-Flop
DEFF | D Flip-Flop with Enable
DDEFF | Dual-edge triggered D Flip-Flop with Enable
DG | DataGATE
DGE | DataGATE Enable
FAST | Fast output slew rate
FB# | Function Block number
GCK# | Global Clock number
GTS# | Global Output Enable number
GSR | Global Set/Reset
I | Input
I/O | Input/Output
IR | Direct Input Register
KPR | Unused I/O with weak keeper (leave unconnected)
Latch | Transparent latch
MC# | Macrocell number
O | Output
OD | Open Drain
PU | Pullup
/S | After any flop/latch type indicates initial state is Set
TCK | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.
TDI | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.
TDO | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.
TFF | Toggle Flip-Flop
TDFF | Dual edge triggered Toggle Flip-Flop
TMS | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.