library ieee;
use ieee.std_logic_1164.all;

entity rm_vmeblk is
     port (
     ds0, ds1, dsdly0, dsdly1, iack, as: in std_logic;	--enero 09
--enero 09     ds0, ds1, dsdly0, dsdly1, iack: in std_logic;
     write, brdsel24, lword: in std_logic;
     am: in std_logic_vector (5 downto 0);
--enero 09     we, dtack, g245, oe, inc_add, acc_blk: out std_logic 
     we, dtack, g245, oe, inc_add, acc_blk, latch: out std_logic  --enero 09
     );
end rm_vmeblk;

----------------------------------------------
-- ver esquema INTERFACE A24:D16 BLT ASYNCH --
----------------------------------------------

architecture arch of rm_vmeblk is
component ffrp port (
     d, clk, ce, cr, pr: in std_logic;
     q: out std_logic);
end component;

signal b2: std_logic;
--signal b1,b3, b4, b5: std_logic;
signal acc, accw, accr, blt: std_logic;
signal ds, one, zero, aux_dtack, dtack_aux: std_logic;
--signal not_ds: std_logic;
signal dsrst: std_logic; --enero 09

signal qlt: std_logic;--enero 09

begin
one <= '1';
zero <= '0';
--enero09 ds <= ds0 or ds1;
ds <= not(ds0 or ds1);
--not_ds <= not(ds);

-- A24, standard non-prileged block transfer, mod= $3B
blt <= '1' when am="111011" else '0';
acc <= not brdsel24 and lword and iack and blt;  -- D16
accr <= acc and write;
accw <= acc and not write;
acc_blk <= acc;
--
--we <= not (not ds and accw and not b4 and b1); -- activo bajo
--dtack <= b3 or b4;            -- activo alto
--g245 <= not acc;              -- activo bajo
--oe <= not accr;               -- activo bajo
--inc_add <= b2 and (b3 nor b4); --> b2 and not dtack, activo alto
--
--fb1:  ffrp port map (clk => not_dsdly, d => accw, ce => one, cr => as, pr => zero, q => b1);
--fb2:  ffrp port map (clk => ds,    d => b5,   ce => one, cr => as, pr => zero, q => b2);
--fb3:  ffrp port map (clk => dsdly, d => accr, ce => one, cr => ds, pr => zero, q => b3);
--fb4:  ffrp port map (clk => dsdly, d => accw, ce => one, cr => ds, pr => zero, q => b4);
--fb5:  ffrp port map (clk => ds,    d => acc,  ce => one, cr => as, pr => zero, q => b5);
 
--enero 09 aux_dtack <= dsdly1 and acc;
--
--enero 09 
dsrst <=  (ds0 and ds1 and (not(dsdly1))); --LINCO ago07

--enero 09 g245  <= ds or not(acc); --active low
g245  <= not(ds and acc); --active low

--OCT 06 oe    <= not(b1);      --active low
--enero09 oe <= ds or not(accr);
oe <= not(ds and accr);

--fq1:  ffrp port map (clk => dsdly0, d => accr, ce => one, cr => dsdly1, pr => zero, q => b1);

--WRITE
we  <= not(b2); --active low
fq2:  ffrp port map (clk => dsdly0, d => accw, ce => one, cr => dsdly1, pr => zero, q => b2);

--DTACK
--enero 09 fq3:  ffrp port map (clk => aux_dtack, d => one, ce => one, cr => not(dsdly1), pr => zero, q => dtack_aux);
fq3:  ffrp port map (clk => dsdly1, d => acc, ce => one, cr => dsrst, pr => zero, q => dtack);
  
--enero 09 dtack <= dtack_aux;

--INCREMENTAR CONTADOR
inc_add <= dsdly1 and not(dsdly0); 

--LATCH enero 09
fqlt:  ffrp port map (clk => dsdly0, d => acc, ce => one, cr => as, pr => zero, q => qlt);--enero 0
latch <= (qlt or ds); --enero 09

end arch;
	
