    cpldfit:  version G.35                              Xilinx Inc.
                                      Fitter Report
    Design Name: rm_registros                        Date:  2-22-2006,  4:31PM
    Device Used: XC2C512-7-PQ208
    Fitting Status: Successful

    ****************************  Resource Summary  ****************************

    Macrocells     Product Terms    Registers      Pins           Function Block
    Used           Used             Used           Used           Inputs Used
    288/512 ( 56%) 629 /1792 ( 35%) 225/512 ( 44%) 67 /173 ( 39%) 588/1280 ( 46%)

    PIN RESOURCES:

    Signal Type    Required     Mapped  |  Pin Type            Used   Remaining
    ------------------------------------|---------------------------------------
    Input         :   26          26    |  I/O              :    57      106
    Output        :   39          39    |  GCK/IO           :     3        0
    Bidirectional :    0           0    |  GTS/IO           :     4        0
    GCK           :    1           1    |  GSR/IO           :     1        0
    GTS           :    0           0    |  CDR/IO           :     1        0
    GSR           :    1           1    |  DGE/IO           :     1        0
                     ----        ----
            Total     67          67

    MACROCELL RESOURCES:

    Total Macrocells Available                   512
    Registered Macrocells                        225
    Non-registered Macrocell driving I/O          18

    GLOBAL RESOURCES:

    Signal 'clk' mapped onto global clock net GCK1.
    Global output enable net(s) unused.
    Signal 'reset' mapped onto global set/reset net GSR.

    End of Resource Summary
    *************** Summary of Required Resources ******************

    ** LOGIC **
    Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg     I/O      I/O       Reg Init
    Name                Pt    Used            Rate #    Type      Use     Use     STD      Style     State
    Mcompar__n0095__n0015                    20      20    FB7_13       186  I/O       (b)
    Mcompar__n0096_ANEB2                    1       2     FB18_10           (b)       (b)
    Mcompar__n0096_ANEB3                    1       2     FB18_9            (b)       (b)
    N_PZ_1138           3       12    FB9_4        48   I/O       (b)
    N_PZ_1149           1       8     FB11_9            (b)       (b)
    N_PZ_1156           4       11    FB6_15            (b)       (b)
    N_PZ_1161           1       2     FB18_16           (b)       (b)
    N_PZ_1215           1       12    FB6_16            (b)       (b)
    N_PZ_1252           7       16    FB3_14            (b)       (b)
    N_PZ_1265           2       3     FB18_11           (b)       (b)
    SFDecomp_15         2       2     FB20_12           (b)       (b)
    SFDecomp_163        1       2     FB19_15           (b)       (b)
    SFDecomp_164        1       2     FB19_14           (b)       (b)
    SFDecomp_173        1       2     FB19_13           (b)       (b)
    SFDecomp_174        1       2     FB19_12           (b)       (b)
    SFDecomp_183        1       2     FB19_11           (b)       (b)
    SFDecomp_184        1       2     FB19_10           (b)       (b)
    SFDecomp_193        1       2     FB19_9            (b)       (b)
    SFDecomp_194        1       2     FB19_8            (b)       (b)
    SFDecomp_203        1       2     FB19_7            (b)       (b)
    SFDecomp_204        1       2     FB19_6            (b)       (b)
    SFDecomp_215        1       2     FB18_7            (b)       (b)
    SFDecomp_216        1       2     FB18_6            (b)       (b)
    SFDecomp_223        1       2     FB18_5            (b)       (b)
    SFDecomp_224        1       2     FB18_3            (b)       (b)
    SFDecomp_233        1       2     FB18_2            (b)       (b)
    SFDecomp_234        1       2     FB18_15      158  I/O       (b)
    SFDecomp_243        1       2     FB19_5            (b)       (b)
    SFDecomp_244        1       2     FB19_4            (b)       (b)
    SFDecomp_253        1       2     FB19_3       173  I/O       (b)
    SFDecomp_254        1       2     FB19_2       171  I/O       (b)
    SFDecomp_263        1       2     FB18_4       159  I/O       (b)
    SFDecomp_264        1       2     FB20_11           (b)       (b)
    SFDecomp_273        1       2     FB20_10           (b)       (b)
    SFDecomp_274        1       2     FB20_9            (b)       (b)
    SFDecomp_283        1       2     FB20_8            (b)       (b)
    SFDecomp_284        1       2     FB20_7            (b)       (b)
    SFDecomp_293        1       2     FB20_6            (b)       (b)
    SFDecomp_294        1       2     FB20_5            (b)       (b)
    SFDecomp_73         1       10    FB10_12           (b)       (b)
    SFDecomp_79         1       10    FB10_11           (b)       (b)
    _n0111              1       8     FB11_8            (b)       (b)
    _n0121              3       5     FB19_16           (b)       (b)
    _n0122              1       32    FB5_16            (b)       (b)
    _n0125              18      18    FB18_8            (b)       (b)
    acc_fifo_p          1       2     FB18_1  FAST 160  I/O       O               LVCMOS18
    counter<0>          2       3     FB6_14            (b)       (b)     DFF                        RESET
    counter<10>         2       13    FB7_15       184  I/O       (b)     TFF                        RESET
    counter<11>         2       14    FB7_16       183  I/O       (b)     TFF                        RESET
    counter<12>         2       15    FB7_2             (b)       (b)     TFF                        RESET
    counter<13>         2       16    FB7_6             (b)       (b)     TFF                        RESET
    counter<14>         2       17    FB7_7             (b)       (b)     TFF                        RESET
    counter<15>         2       18    FB7_8             (b)       (b)     TFF                        RESET
    counter<16>         2       19    FB7_9             (b)       (b)     TFF                        RESET
    counter<17>         2       20    FB7_10            (b)       (b)     TFF                        RESET
    counter<18>         2       21    FB7_11            (b)       (b)     TFF                        RESET
    counter<1>          2       4     FB6_13            (b)       (b)     TFF                        RESET
    counter<2>          2       5     FB6_12            (b)       (b)     TFF                        RESET
    counter<3>          2       6     FB6_11            (b)       (b)     TFF                        RESET
    counter<4>          2       7     FB6_10            (b)       (b)     TFF                        RESET
    counter<5>          2       8     FB6_9             (b)       (b)     TFF                        RESET
    counter<6>          2       9     FB6_8             (b)       (b)     TFF                        RESET
    counter<7>          2       10    FB6_7             (b)       (b)     TFF                        RESET
    counter<8>          2       11    FB6_6             (b)       (b)     TFF                        RESET
    counter<9>          2       12    FB7_14       185  I/O       (b)     TFF                        RESET
    cycle_counter<0>    4       5     FB9_1             (b)       (b)     DFF                        RESET
    cycle_counter<10>   4       15    FB8_9             (b)       (b)     TFF                        RESET
    cycle_counter<11>   4       16    FB8_10            (b)       (b)     TFF                        RESET
    cycle_counter<12>   4       17    FB8_11            (b)       (b)     TFF                        RESET
    cycle_counter<13>   4       18    FB8_12            (b)       (b)     TFF                        RESET
    cycle_counter<14>   4       19    FB8_13            (b)       (b)     TFF                        RESET
    cycle_counter<15>   4       20    FB8_15            (b)       (b)     TFF                        RESET
    cycle_counter<1>    4       6     FB9_16       46   GCK/I/O   GCK     TFF                        RESET
    cycle_counter<2>    4       7     FB9_14       47   I/O       (b)     TFF                        RESET
    cycle_counter<3>    4       8     FB8_14       25   I/O       (b)     TFF                        RESET
    cycle_counter<4>    4       9     FB8_1             (b)       (b)     TFF                        RESET
    cycle_counter<5>    4       10    FB8_4             (b)       (b)     TFF                        RESET
    cycle_counter<6>    4       11    FB8_5             (b)       (b)     TFF                        RESET
    cycle_counter<7>    4       12    FB8_6             (b)       (b)     TFF                        RESET
    cycle_counter<8>    4       13    FB8_7             (b)       (b)     TFF                        RESET
    cycle_counter<9>    4       14    FB8_8             (b)       (b)     TFF                        RESET
    db_out<0>           7       13    FB13_1  FAST 37   I/O       O               LVCMOS18
    db_out<10>          5       11    FB13_15 FAST 32   I/O       O               LVCMOS18
    db_out<11>          4       10    FB12_5  FAST 64   I/O       O               LVCMOS18
    db_out<12>          4       10    FB12_13 FAST 65   I/O       O               LVCMOS18
    db_out<13>          4       10    FB13_3  FAST 36   I/O       O               LVCMOS18
    db_out<14>          4       10    FB13_4  FAST 35   I/O       O               LVCMOS18
    db_out<15>          4       10    FB13_14 FAST 34   I/O       O               LVCMOS18
    db_out<1>           7       13    FB14_3  FAST 69   I/O       O               LVCMOS18
    db_out<2>           5       11    FB14_4  FAST 70   I/O       O               LVCMOS18
    db_out<3>           5       11    FB14_5  FAST 71   I/O       O               LVCMOS18
    db_out<4>           5       11    FB14_13 FAST 72   I/O       O               LVCMOS18
    db_out<5>           5       11    FB14_15 FAST 73   I/O       O               LVCMOS18
    db_out<6>           5       11    FB15_1  FAST 31   I/O       O               LVCMOS18
    db_out<7>           5       11    FB15_3  FAST 30   I/O       O               LVCMOS18
    db_out<8>           5       11    FB15_4  FAST 29   I/O       O               LVCMOS18
    db_out<9>           5       11    FB15_13 FAST 28   I/O       O               LVCMOS18
    ena_cycles          1       9     FB1_1        7    GTS/I/O   I       DEFF                       RESET
    ena_event_count     1       9     FB1_2        6    I/O       I       DEFF                       RESET
    ena_fifo_mem_p      4       12    FB10_4  FAST 56   I/O       O       TFF     LVCMOS18           RESET
    ena_fill_mem        1       9     FB1_3        5    GTS/I/O   I       DEFF                       RESET
    ena_lfsr<0>         1       9     FB1_4        4    I/O       I       DEFF                       RESET
    ena_lfsr<1>         1       9     FB1_13       3    GTS/I/O   I       DEFF                       RESET
    ena_lfsr<2>         1       9     FB1_14       2    I/O       I       DEFF                       RESET
    ena_lfsr<3>         1       9     FB1_15       208  I/O       I       DEFF                       RESET
    ena_mem_fifo_p      11      14    FB10_13 FAST 57   I/O       O       TFF     LVCMOS18           RESET
    ena_random          1       9     FB2_2        8    I/O       I       DEFF                       RESET
    ena_word_count      1       9     FB2_14       9    GTS/I/O   I       DEFF                       RESET
    lfsr_0<0>           2       2     FB9_15            (b)       (b)     DFF                        RESET
    lfsr_0<10>          1       1     FB4_13            (b)       (b)     DFF                        RESET
    lfsr_0<11>          1       1     FB4_12            (b)       (b)     DFF                        RESET
    lfsr_0<12>          1       1     FB4_11            (b)       (b)     DFF                        RESET
    lfsr_0<13>          1       1     FB4_10            (b)       (b)     DFF                        RESET
    lfsr_0<14>          1       1     FB4_9             (b)       (b)     DFF                        RESET
    lfsr_0<15>          1       1     FB4_8             (b)       (b)     DFF                        RESET
    lfsr_0<16>          1       1     FB4_7             (b)       (b)     DFF                        RESET
    lfsr_0<17>          1       1     FB4_6             (b)       (b)     DFF                        RESET
    lfsr_0<18>          1       1     FB4_5             (b)       (b)     DFF                        RESET
    lfsr_0<19>          1       1     FB4_3             (b)       (b)     DFF                        RESET
    lfsr_0<1>           1       1     FB4_1             (b)       (b)     DFF                        RESET
    lfsr_0<20>          1       1     FB4_16       18   I/O       (b)     DFF                        RESET
    lfsr_0<21>          1       1     FB4_15       17   I/O       I       DFF                        RESET
    lfsr_0<22>          1       1     FB4_14       16   I/O       I       DFF                        RESET
    lfsr_0<23>          1       1     FB4_4        15   I/O       I       DFF                        RESET
    lfsr_0<24>          1       1     FB4_2        14   I/O       I       DFF                        RESET
    lfsr_0<25>          1       1     FB5_14            (b)       (b)     DFF                        RESET
    lfsr_0<26>          1       1     FB5_12            (b)       (b)     DFF                        RESET
    lfsr_0<27>          1       1     FB5_11            (b)       (b)     DFF                        RESET
    lfsr_0<28>          1       1     FB5_10            (b)       (b)     DFF                        RESET
    lfsr_0<29>          1       1     FB5_9             (b)       (b)     DFF                        RESET
    lfsr_0<2>           1       1     FB5_8             (b)       (b)     DFF                        RESET
    lfsr_0<30>          1       1     FB7_3        189  I/O       (b)     DFF                        RESET
    lfsr_0<31>          1       1     FB11_7            (b)       (b)     DFF                        RESET
    lfsr_0<32>          1       1     FB11_6            (b)       (b)     DFF                        RESET
    lfsr_0<33>          1       1     FB11_5            (b)       (b)     DFF                        RESET
    lfsr_0<34>          1       1     FB11_2            (b)       (b)     DFF                        RESET
    lfsr_0<35>          1       1     FB12_16           (b)       (b)     DFF                        RESET
    lfsr_0<36>          1       1     FB12_12           (b)       (b)     DFF                        RESET
    lfsr_0<37>          1       1     FB12_11           (b)       (b)     DFF                        RESET
    lfsr_0<38>          1       1     FB9_13            (b)       (b)     DFF                        RESET
    lfsr_0<39>          1       1     FB12_10           (b)       (b)     DFF                        RESET
    lfsr_0<3>           1       1     FB12_9            (b)       (b)     DFF                        RESET
    lfsr_0<40>          1       1     FB12_8            (b)       (b)     DFF                        RESET
    lfsr_0<4>           1       1     FB12_7            (b)       (b)     DFF                        RESET
    lfsr_0<5>           1       1     FB12_6            (b)       (b)     DFF                        RESET
    lfsr_0<6>           1       1     FB12_15      67   I/O       I       DFF                        RESET
    lfsr_0<7>           1       1     FB13_16           (b)       (b)     DFF                        RESET
    lfsr_0<8>           1       1     FB13_13           (b)       (b)     DFF                        RESET
    lfsr_0<9>           1       1     FB13_12           (b)       (b)     DFF                        RESET
    lfsr_1<0>           2       2     FB9_12            (b)       (b)     DFF                        RESET
    lfsr_1<10>          1       1     FB13_11           (b)       (b)     DFF                        RESET
    lfsr_1<11>          1       1     FB13_10           (b)       (b)     DFF                        RESET
    lfsr_1<12>          1       1     FB13_9            (b)       (b)     DFF                        RESET
    lfsr_1<13>          1       1     FB13_8            (b)       (b)     DFF                        RESET
    lfsr_1<14>          1       1     FB13_7            (b)       (b)     DFF                        RESET
    lfsr_1<15>          1       1     FB14_16           (b)       (b)     DFF                        RESET
    lfsr_1<16>          1       1     FB14_14           (b)       (b)     DFF                        RESET
    lfsr_1<17>          1       1     FB14_12           (b)       (b)     DFF                        RESET
    lfsr_1<18>          1       1     FB14_11           (b)       (b)     DFF                        RESET
    lfsr_1<19>          1       1     FB14_10           (b)       (b)     DFF                        RESET
    lfsr_1<1>           1       1     FB15_16           (b)       (b)     DFF                        RESET
    lfsr_1<20>          1       1     FB15_15           (b)       (b)     DFF                        RESET
    lfsr_1<21>          1       1     FB15_12           (b)       (b)     DFF                        RESET
    lfsr_1<22>          1       1     FB15_11           (b)       (b)     DFF                        RESET
    lfsr_1<23>          1       1     FB15_10           (b)       (b)     DFF                        RESET
    lfsr_1<24>          1       1     FB15_9            (b)       (b)     DFF                        RESET
    lfsr_1<25>          1       1     FB15_8            (b)       (b)     DFF                        RESET
    lfsr_1<26>          1       1     FB15_7            (b)       (b)     DFF                        RESET
    lfsr_1<27>          1       1     FB15_6            (b)       (b)     DFF                        RESET
    lfsr_1<28>          1       1     FB9_11            (b)       (b)     DFF                        RESET
    lfsr_1<29>          1       1     FB15_5            (b)       (b)     DFF                        RESET
    lfsr_1<2>           1       1     FB15_2            (b)       (b)     DFF                        RESET
    lfsr_1<30>          1       1     FB15_14      27   I/O       I       DFF                        RESET
    lfsr_1<3>           1       1     FB16_16           (b)       (b)     DFF                        RESET
    lfsr_1<4>           1       1     FB16_15           (b)       (b)     DFF                        RESET
    lfsr_1<5>           1       1     FB16_13           (b)       (b)     DFF                        RESET
    lfsr_1<6>           1       1     FB16_12           (b)       (b)     DFF                        RESET
    lfsr_1<7>           1       1     FB16_11           (b)       (b)     DFF                        RESET
    lfsr_1<8>           1       1     FB16_10           (b)       (b)     DFF                        RESET
    lfsr_1<9>           1       1     FB16_9            (b)       (b)     DFF                        RESET
    lfsr_2<0>           2       2     FB9_10            (b)       (b)     DFF                        RESET
    lfsr_2<10>          1       1     FB16_8            (b)       (b)     DFF                        RESET
    lfsr_2<11>          1       1     FB16_7            (b)       (b)     DFF                        RESET
    lfsr_2<12>          1       1     FB16_6            (b)       (b)     DFF                        RESET
    lfsr_2<13>          1       1     FB16_2            (b)       (b)     DFF                        RESET
    lfsr_2<14>          1       1     FB16_14      78   I/O       (b)     DFF                        RESET
    lfsr_2<15>          1       1     FB16_5       77   I/O       (b)     DFF                        RESET
    lfsr_2<16>          1       1     FB16_4       76   I/O       (b)     DFF                        RESET
    lfsr_2<17>          1       1     FB16_3       75   I/O       (b)     DFF                        RESET
    lfsr_2<18>          1       1     FB16_1       74   I/O       I       DFF                        RESET
    lfsr_2<19>          1       1     FB9_9             (b)       (b)     DFF                        RESET
    lfsr_2<1>           1       1     FB17_12           (b)       (b)     DFF                        RESET
    lfsr_2<20>          1       1     FB17_11           (b)       (b)     DFF                        RESET
    lfsr_2<2>           1       1     FB17_10           (b)       (b)     DFF                        RESET
    lfsr_2<3>           1       1     FB17_9            (b)       (b)     DFF                        RESET
    lfsr_2<4>           1       1     FB17_8            (b)       (b)     DFF                        RESET
    lfsr_2<5>           1       1     FB17_7            (b)       (b)     DFF                        RESET
    lfsr_2<6>           1       1     FB17_6            (b)       (b)     DFF                        RESET
    lfsr_2<7>           1       1     FB17_16      169  I/O       (b)     DFF                        RESET
    lfsr_2<8>           1       1     FB17_15      168  I/O       (b)     DFF                        RESET
    lfsr_2<9>           1       1     FB17_14      167  I/O       (b)     DFF                        RESET
    lfsr_3<0>           2       2     FB9_8             (b)       (b)     DFF                        RESET
    lfsr_3<10>          1       1     FB17_13      166  I/O       (b)     DFF                        RESET
    lfsr_3<1>           1       1     FB17_5       165  I/O       (b)     DFF                        RESET
    lfsr_3<2>           1       1     FB17_4       164  I/O       (b)     DFF                        RESET
    lfsr_3<3>           1       1     FB17_3       163  I/O       (b)     DFF                        RESET
    lfsr_3<4>           1       1     FB17_2       162  I/O       (b)     DFF                        RESET
    lfsr_3<5>           1       1     FB17_1       161  I/O       I       DFF                        RESET
    lfsr_3<6>           1       1     FB18_14           (b)       (b)     DFF                        RESET
    lfsr_3<7>           1       1     FB18_13           (b)       (b)     DFF                        RESET
    lfsr_3<8>           1       1     FB18_12           (b)       (b)     DFF                        RESET
    lfsr_3<9>           1       1     FB9_7             (b)       (b)     DFF                        RESET
    mem_done            4       25    FB7_12            (b)       (b)     DFF                        RESET
    mem_done2           2       5     FB7_5        187  I/O       (b)     DFF                        RESET
    mem_done_ev         2       4     FB7_4        188  I/O       (b)     DFF                        RESET
    mem_done_p          1       2     FB19_1  FAST 170  I/O       O               LVCMOS18
    mem_pointer_p<0>    5       15    FB10_3  FAST 55   GCK/I/O   O       DFF     LVCMOS18           RESET
    mem_pointer_p<10>   6       10    FB11_16 FAST 38   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<11>   7       11    FB12_4  FAST 63   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<12>   8       12    FB12_3  FAST 62   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<13>   9       13    FB12_2  FAST 61   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<14>   10      14    FB12_1  FAST 60   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<15>   4       16    FB6_3   FAST 21   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<16>   6       20    FB6_2   FAST 20   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<17>   7       21    FB6_1   FAST 19   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<1>    6       16    FB10_2  FAST 54   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<2>    7       16    FB10_1  FAST 51   CDR/I/O   O       DFF     LVCMOS18           RESET
    mem_pointer_p<3>    8       18    FB3_16  FAST 199  I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<4>    4       11    FB11_13 FAST 41   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<5>    5       12    FB11_4  FAST 43   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<6>    6       13    FB11_3  FAST 44   GCK/I/O   O       DFF     LVCMOS18           RESET
    mem_pointer_p<7>    4       15    FB11_1  FAST 45   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<8>    4       8     FB11_14 FAST 40   I/O       O       DFF     LVCMOS18           RESET
    mem_pointer_p<9>    5       9     FB11_15 FAST 39   I/O       O       DFF     LVCMOS18           RESET
    mevent_count<0>     1       8     FB2_15       10   I/O       I       DEFF                       RESET
    mevent_count<10>    2       9     FB1_12            (b)       (b)     DEFF                       RESET
    mevent_count<11>    1       8     FB2_16       12   I/O       I       DEFF                       RESET
    mevent_count<12>    1       8     FB3_1        205  I/O       I       DEFF                       RESET
    mevent_count<13>    1       8     FB3_3        203  I/O       I       DEFF                       RESET
    mevent_count<14>    1       8     FB3_5        202  I/O       I       DEFF                       RESET
    mevent_count<15>    1       8     FB3_13       201  I/O       I       DEFF                       RESET
    mevent_count<1>     1       8     FB3_15       200  I/O       I       DEFF                       RESET
    mevent_count<2>     2       9     FB2_13            (b)       (b)     DEFF                       RESET
    mevent_count<3>     2       9     FB3_12            (b)       (b)     DEFF                       RESET
    mevent_count<4>     2       9     FB3_7             (b)       (b)     DEFF                       RESET
    mevent_count<5>     2       9     FB3_4             (b)       (b)     DEFF                       RESET
    mevent_count<6>     2       9     FB9_3        49   I/O       (b)     DEFF                       RESET
    mevent_count<7>     2       9     FB10_10           (b)       (b)     DEFF                       RESET
    mevent_count<8>     2       9     FB10_8            (b)       (b)     DEFF                       RESET
    mevent_count<9>     2       9     FB3_9             (b)       (b)     DEFF                       RESET
    mword_count<0>      3       12    FB1_8             (b)       (b)     DFF                        RESET
    mword_count<10>     3       12    FB1_10            (b)       (b)     DFF                        RESET
    mword_count<11>     3       12    FB1_6             (b)       (b)     DFF                        RESET
    mword_count<12>     3       12    FB1_5             (b)       (b)     DFF                        RESET
    mword_count<13>     3       12    FB1_16       206  GSR/I/O   GSR     DFF                        RESET
    mword_count<14>     3       12    FB2_9             (b)       (b)     DFF                        RESET
    mword_count<15>     3       12    FB2_8             (b)       (b)     DFF                        RESET
    mword_count<16>     3       11    FB1_7             (b)       (b)     TFF                        RESET
    mword_count<17>     3       11    FB2_11            (b)       (b)     TFF                        RESET
    mword_count<1>      3       12    FB2_10            (b)       (b)     DFF                        RESET
    mword_count<2>      3       11    FB1_9             (b)       (b)     DFF                        RESET
    mword_count<3>      3       12    FB2_7             (b)       (b)     DFF                        RESET
    mword_count<4>      3       12    FB2_6             (b)       (b)     DFF                        RESET
    mword_count<5>      3       12    FB2_5             (b)       (b)     DFF                        RESET
    mword_count<6>      3       12    FB2_4             (b)       (b)     DFF                        RESET
    mword_count<7>      3       12    FB2_3             (b)       (b)     DFF                        RESET
    mword_count<8>      3       12    FB2_1             (b)       (b)     DFF                        RESET
    mword_count<9>      3       12    FB3_10            (b)       (b)     DFF                        RESET
    num_cycles<0>       2       9     FB10_16           (b)       (b)     DEFF                       RESET
    num_cycles<10>      2       9     FB1_11            (b)       (b)     DEFF                       RESET
    num_cycles<11>      2       9     FB10_6            (b)       (b)     DEFF                       RESET
    num_cycles<12>      2       9     FB10_5            (b)       (b)     DEFF                       RESET
    num_cycles<13>      2       9     FB10_14      58   DGE/I/O   I       DEFF                       RESET
    num_cycles<14>      2       9     FB11_11           (b)       (b)     DEFF                       RESET
    num_cycles<15>      2       9     FB11_10           (b)       (b)     DEFF                       RESET
    num_cycles<1>       2       9     FB10_15           (b)       (b)     DEFF                       RESET
    num_cycles<2>       2       9     FB2_12            (b)       (b)     DEFF                       RESET
    num_cycles<3>       2       9     FB3_11            (b)       (b)     DEFF                       RESET
    num_cycles<4>       2       9     FB3_6             (b)       (b)     DEFF                       RESET
    num_cycles<5>       2       9     FB3_2             (b)       (b)     DEFF                       RESET
    num_cycles<6>       2       9     FB11_12           (b)       (b)     DEFF                       RESET
    num_cycles<7>       2       9     FB10_9            (b)       (b)     DEFF                       RESET
    num_cycles<8>       2       9     FB10_7            (b)       (b)     DEFF                       RESET
    num_cycles<9>       2       9     FB3_8             (b)       (b)     DEFF                       RESET
    state_FFD1          5       6     FB9_6             (b)       (b)     DFF                        RESET
    state_FFD2          4       21    FB8_16            (b)       (b)     DFF                        RESET
    state_FFD3          2       4     FB9_5             (b)       (b)     DFF                        RESET
    txena_out_p         5       12    FB9_2   FAST 50   I/O       O       DFF     LVCMOS18           RESET

    ** INPUTS **
    Signal                            Loc          Pin  Pin       Pin     Reg     I/O      I/O
    Name                                           #    Type      Use     Use     STD      Style
    add<0>                            FB10_14      58   DGE/I/O   I               LVCMOS18
    add<1>                            FB12_14      66   I/O       I               LVCMOS18
    add<2>                            FB12_15      67   I/O       I               LVCMOS18
    add<3>                            FB15_14      27   I/O       I               LVCMOS18
    add<4>                            FB4_2        14   I/O       I               LVCMOS18
    add<5>                            FB4_4        15   I/O       I               LVCMOS18
    clk                               FB9_16       46   GCK/I/O   GCK             LVCMOS18
    cs                                FB4_14       16   I/O       I               LVCMOS18
    db_in<0>                          FB2_15       10   I/O       I               LVCMOS18
    db_in<10>                         FB1_15       208  I/O       I               LVCMOS18
    db_in<11>                         FB2_16       12   I/O       I               LVCMOS18
    db_in<12>                         FB3_1        205  I/O       I               LVCMOS18
    db_in<13>                         FB3_3        203  I/O       I               LVCMOS18
    db_in<14>                         FB3_5        202  I/O       I               LVCMOS18
    db_in<15>                         FB3_13       201  I/O       I               LVCMOS18
    db_in<1>                          FB3_15       200  I/O       I               LVCMOS18
    db_in<2>                          FB2_14       9    GTS/I/O   I               LVCMOS18
    db_in<3>                          FB1_2        6    I/O       I               LVCMOS18
    db_in<4>                          FB1_3        5    GTS/I/O   I               LVCMOS18
    db_in<5>                          FB1_1        7    GTS/I/O   I               LVCMOS18
    db_in<6>                          FB2_2        8    I/O       I               LVCMOS18
    db_in<7>                          FB1_4        4    I/O       I               LVCMOS18
    db_in<8>                          FB1_13       3    GTS/I/O   I               LVCMOS18
    db_in<9>                          FB1_14       2    I/O       I               LVCMOS18
    enw                               FB4_15       17   I/O       I               LVCMOS18
    is_trigger                        FB16_1       74   I/O       I               LVCMOS18
    reset                             FB1_16       206  GSR/I/O   GSR             LVCMOS18
    txena_in                          FB17_1       161  I/O       I               LVCMOS18

    End of Resources

    Legend:
    I/O Style - OD    - OpenDrain
              - PU    - Pullup
              - KPR   - Keeper
              - S     - SchmittTrigger
              - DG    - DataGate
    Reg Use   - LATCH - Transparent latch
              - DFF   - D-flip-flop
              - DEFF  - D-flip-flop with clock enable
              - TFF   - T-flip-flop
              - TDFF  - Dual-edge-triggered T-flip-flop
              - DDFF  - Dual-edge-triggered flip-flop
              - DDEFF - Dual-edge-triggered flip-flop with clock enable
              /S (after any above flop/latch type) indicates initial state is Set

    *********************Function Block Resource Summary***********************
    Function    # of        FB Inputs   Signals     Total       O/IO      IO
    Block       Macrocells  Used        Used        Pt Used     Req       Avail
    FB1          16          23          23           26         0/0        8
    FB2          16          30          30           29         0/0        4
    FB3          16          23          23           31         1/0        6
    FB4          16          16          16           16         0/0        5
    FB5           7          38          38            7         0/0        7
    FB6          14          38          38           40         3/0        3
    FB7          15          38          38           49         0/0        8
    FB8          14          34          34           56         0/0        3
    FB9          16          37          37           38         1/0        5
    FB10         16          29          29           51         5/0        6
    FB11         16          38          38           46         7/0        7
    FB12         15          38          38           51         6/0        8
    FB13         13          38          38           32         5/0        5
    FB14         10          38          38           32         5/0        5
    FB15         16          38          38           32         4/0        5
    FB16         16          16          16           16         0/0        5
    FB17         16          16          16           16         0/0        9
    FB18         16          30          30           34         1/0        3
    FB19         16          20          20           18         1/0        3
    FB20          8          10          10            9         0/0        6
    FB21          0           0           0            0         0/0        3
    FB22          0           0           0            0         0/0        8
    FB23          0           0           0            0         0/0        3
    FB24          0           0           0            0         0/0        7
    FB25          0           0           0            0         0/0        8
    FB26          0           0           0            0         0/0        8
    FB27          0           0           0            0         0/0        4
    FB28          0           0           0            0         0/0        3
    FB29          0           0           0            0         0/0        3
    FB30          0           0           0            0         0/0        6
    FB31          0           0           0            0         0/0        4
    FB32          0           0           0            0         0/0        5
                ----                                -----       -----     -----
                288                                  629        39/0      173
    *********************************** FB1 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  23
    Number of function block inputs used/remaining:               23/17
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   26/30
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    ena_cycles                        1       FB1_1   7     GTS/I/O  I
    ena_event_count                   1       FB1_2   6     I/O      I
    ena_fill_mem                      1       FB1_3   5     GTS/I/O  I
    ena_lfsr<0>                       1       FB1_4   4     I/O      I
    mword_count<12>                   3       FB1_5         (b)      (b)
    mword_count<11>                   3       FB1_6         (b)      (b)
    mword_count<16>                   3       FB1_7         (b)      (b)
    mword_count<0>                    3       FB1_8         (b)      (b)
    mword_count<2>                    3       FB1_9         (b)      (b)
    mword_count<10>                   3       FB1_10        (b)      (b)
    num_cycles<10>                    2       FB1_11        (b)      (b)
    mevent_count<10>                  2       FB1_12        (b)      (b)
    ena_lfsr<1>                       1       FB1_13  3     GTS/I/O  I
    ena_lfsr<2>                       1       FB1_14  2     I/O      I
    ena_lfsr<3>                       1       FB1_15  208   I/O      I
    mword_count<13>                   3       FB1_16  206   GSR/I/O  GSR

    Signals Used by Logic in Function Block
      1: N_PZ_1149          9: db_in<0>          17: mword_count<0>
      2: add<0>            10: db_in<10>         18: mword_count<10>
      3: add<1>            11: db_in<11>         19: mword_count<11>
      4: add<2>            12: db_in<12>         20: mword_count<12>
      5: add<3>            13: db_in<13>         21: mword_count<13>
      6: add<4>            14: db_in<2>          22: mword_count<16>
      7: add<5>            15: enw               23: mword_count<2>
      8: cs                16: mem_done

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mword_count<12>   XXXXXXXX...X.XX....X.................... 12      12
    mword_count<11>   XXXXXXXX..X..XX...X..................... 12      12
    mword_count<16>   .XXXXXXXX....XX......X.................. 11      11
    mword_count<0>    XXXXXXXXX....XX.X....................... 12      12
    mword_count<2>    XXXXXXXX.....XX.......X................. 11      11
    mword_count<10>   XXXXXXXX.X...XX..X...................... 12      12
    num_cycles<10>    .XXXXXXX.X....X......................... 9       9
    mevent_count<10>  .XXXXXXX.X....X......................... 9       9
    mword_count<13>   XXXXXXXX....XXX.....X................... 12      12
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB2 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  30
    Number of function block inputs used/remaining:               30/10
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   29/27
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mword_count<8>                    3       FB2_1         (b)      (b)
    ena_random                        1       FB2_2   8     I/O      I
    mword_count<7>                    3       FB2_3         (b)      (b)
    mword_count<6>                    3       FB2_4         (b)      (b)
    mword_count<5>                    3       FB2_5         (b)      (b)
    mword_count<4>                    3       FB2_6         (b)      (b)
    mword_count<3>                    3       FB2_7         (b)      (b)
    mword_count<15>                   3       FB2_8         (b)      (b)
    mword_count<14>                   3       FB2_9         (b)      (b)
    mword_count<1>                    3       FB2_10        (b)      (b)
    mword_count<17>                   3       FB2_11        (b)      (b)
    num_cycles<2>                     2       FB2_12        (b)      (b)
    mevent_count<2>                   2       FB2_13        (b)      (b)
    ena_word_count                    1       FB2_14  9     GTS/I/O  I
    mevent_count<0>                   1       FB2_15  10    I/O      I
    mevent_count<11>                  1       FB2_16  12    I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_1149         11: db_in<1>          21: mword_count<14>
      2: add<0>            12: db_in<2>          22: mword_count<15>
      3: add<1>            13: db_in<3>          23: mword_count<17>
      4: add<2>            14: db_in<4>          24: mword_count<1>
      5: add<3>            15: db_in<5>          25: mword_count<3>
      6: add<4>            16: db_in<6>          26: mword_count<4>
      7: add<5>            17: db_in<7>          27: mword_count<5>
      8: cs                18: db_in<8>          28: mword_count<6>
      9: db_in<14>         19: enw               29: mword_count<7>
     10: db_in<15>         20: mem_done          30: mword_count<8>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mword_count<8>    XXXXXXXX...X.....XX..........X.......... 12      12
    mword_count<7>    XXXXXXXX...X....X.X.........X........... 12      12
    mword_count<6>    XXXXXXXX...X...X..X........X............ 12      12
    mword_count<5>    XXXXXXXX...X..X...X.......X............. 12      12
    mword_count<4>    XXXXXXXX...X.X....X......X.............. 12      12
    mword_count<3>    XXXXXXXX...XX.....X.....X............... 12      12
    mword_count<15>   XXXXXXXX.X.X......X..X.................. 12      12
    mword_count<14>   XXXXXXXXX..X......X.X................... 12      12
    mword_count<1>    XXXXXXXX..XX......X....X................ 12      12
    mword_count<17>   .XXXXXXX..XX......X...X................. 11      11
    num_cycles<2>     .XXXXXXX...X......X..................... 9       9
    mevent_count<2>   .XXXXXXX...X......X..................... 9       9
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB3 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  23
    Number of function block inputs used/remaining:               23/17
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   31/25
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mevent_count<12>                  1       FB3_1   205   I/O      I
    num_cycles<5>                     2       FB3_2         (b)      (b)
    mevent_count<13>                  1       FB3_3   203   I/O      I
    mevent_count<5>                   2       FB3_4         (b)      (b)
    mevent_count<14>                  1       FB3_5   202   I/O      I
    num_cycles<4>                     2       FB3_6         (b)      (b)
    mevent_count<4>                   2       FB3_7         (b)      (b)
    num_cycles<9>                     2       FB3_8         (b)      (b)
    mevent_count<9>                   2       FB3_9         (b)      (b)
    mword_count<9>                    3       FB3_10        (b)      (b)
    num_cycles<3>                     2       FB3_11        (b)      (b)
    mevent_count<3>                   2       FB3_12        (b)      (b)
    mevent_count<15>                  1       FB3_13  201   I/O      I
    N_PZ_1252                         7       FB3_14        (b)      (b)
    mevent_count<1>                   1       FB3_15  200   I/O      I
    mem_pointer_p<3>                  8       FB3_16  199   I/O      O

    Signals Used by Logic in Function Block
      1: N_PZ_1138          9: add<3>            17: db_in<9>
      2: N_PZ_1149         10: add<4>            18: enw
      3: N_PZ_1161         11: add<5>            19: mem_pointer_p<0>
      4: N_PZ_1265         12: cs                20: mem_pointer_p<1>
      5: _n0111            13: db_in<2>          21: mem_pointer_p<2>
      6: add<0>            14: db_in<3>          22: mem_pointer_p<3>
      7: add<1>            15: db_in<4>          23: mword_count<9>
      8: add<2>            16: db_in<5>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    num_cycles<5>     .....XXXXXXX...X.X...................... 9       9
    mevent_count<5>   .....XXXXXXX...X.X...................... 9       9
    num_cycles<4>     .....XXXXXXX..X..X...................... 9       9
    mevent_count<4>   .....XXXXXXX..X..X...................... 9       9
    num_cycles<9>     .....XXXXXXX....XX...................... 9       9
    mevent_count<9>   .....XXXXXXX....XX...................... 9       9
    mword_count<9>    .X...XXXXXXXX...XX....X................. 12      12
    num_cycles<3>     .....XXXXXXX.X...X...................... 9       9
    mevent_count<3>   .....XXXXXXX.X...X...................... 9       9
    N_PZ_1252         X.XX.XXXXXXXX....XXXXX.................. 16      16
    mem_pointer_p<3>  X.XXXXXXXXXXXX...XXXXX.................. 18      18
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB4 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  16
    Number of function block inputs used/remaining:               16/24
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   16/40
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    lfsr_0<1>                         1       FB4_1         (b)      (b)
    lfsr_0<24>                        1       FB4_2   14    I/O      I
    lfsr_0<19>                        1       FB4_3         (b)      (b)
    lfsr_0<23>                        1       FB4_4   15    I/O      I
    lfsr_0<18>                        1       FB4_5         (b)      (b)
    lfsr_0<17>                        1       FB4_6         (b)      (b)
    lfsr_0<16>                        1       FB4_7         (b)      (b)
    lfsr_0<15>                        1       FB4_8         (b)      (b)
    lfsr_0<14>                        1       FB4_9         (b)      (b)
    lfsr_0<13>                        1       FB4_10        (b)      (b)
    lfsr_0<12>                        1       FB4_11        (b)      (b)
    lfsr_0<11>                        1       FB4_12        (b)      (b)
    lfsr_0<10>                        1       FB4_13        (b)      (b)
    lfsr_0<22>                        1       FB4_14  16    I/O      I
    lfsr_0<21>                        1       FB4_15  17    I/O      I
    lfsr_0<20>                        1       FB4_16  18    I/O      (b)

    Signals Used by Logic in Function Block
      1: lfsr_0<0>          7: lfsr_0<15>        12: lfsr_0<20>
      2: lfsr_0<10>         8: lfsr_0<16>        13: lfsr_0<21>
      3: lfsr_0<11>         9: lfsr_0<17>        14: lfsr_0<22>
      4: lfsr_0<12>        10: lfsr_0<18>        15: lfsr_0<23>
      5: lfsr_0<13>        11: lfsr_0<19>        16: lfsr_0<9>
      6: lfsr_0<14>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    lfsr_0<1>         X....................................... 1       1
    lfsr_0<24>        ..............X......................... 1       1
    lfsr_0<19>        .........X.............................. 1       1
    lfsr_0<23>        .............X.......................... 1       1
    lfsr_0<18>        ........X............................... 1       1
    lfsr_0<17>        .......X................................ 1       1
    lfsr_0<16>        ......X................................. 1       1
    lfsr_0<15>        .....X.................................. 1       1
    lfsr_0<14>        ....X................................... 1       1
    lfsr_0<13>        ...X.................................... 1       1
    lfsr_0<12>        ..X..................................... 1       1
    lfsr_0<11>        .X...................................... 1       1
    lfsr_0<10>        ...............X........................ 1       1
    lfsr_0<22>        ............X........................... 1       1
    lfsr_0<21>        ...........X............................ 1       1
    lfsr_0<20>        ..........X............................. 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB5 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   7/49
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB5_1   198   I/O
    (unused)                          0       FB5_2   197   I/O
    (unused)                          0       FB5_3   196   I/O
    (unused)                          0       FB5_4   195   I/O
    (unused)                          0       FB5_5   194   I/O
    (unused)                          0       FB5_6         (b)
    (unused)                          0       FB5_7         (b)
    lfsr_0<2>                         1       FB5_8         (b)      (b)
    lfsr_0<29>                        1       FB5_9         (b)      (b)
    lfsr_0<28>                        1       FB5_10        (b)      (b)
    lfsr_0<27>                        1       FB5_11        (b)      (b)
    lfsr_0<26>                        1       FB5_12        (b)      (b)
    (unused)                          0       FB5_13  193   I/O
    lfsr_0<25>                        1       FB5_14        (b)      (b)
    (unused)                          0       FB5_15  192   I/O
    _n0122                            1       FB5_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: Mcompar__n0096_ANEB2
                           14: SFDecomp_215      27: SFDecomp_274
      2: Mcompar__n0096_ANEB3
                           15: SFDecomp_216      28: SFDecomp_283
      3: SFDecomp_15       16: SFDecomp_223      29: SFDecomp_284
      4: SFDecomp_163      17: SFDecomp_224      30: SFDecomp_293
      5: SFDecomp_164      18: SFDecomp_233      31: SFDecomp_294
      6: SFDecomp_173      19: SFDecomp_234      32: ena_event_count
      7: SFDecomp_174      20: SFDecomp_243      33: lfsr_0<1>
      8: SFDecomp_183      21: SFDecomp_244      34: lfsr_0<24>
      9: SFDecomp_184      22: SFDecomp_253      35: lfsr_0<25>
     10: SFDecomp_193      23: SFDecomp_254      36: lfsr_0<26>
     11: SFDecomp_194      24: SFDecomp_263      37: lfsr_0<27>
     12: SFDecomp_203      25: SFDecomp_264      38: lfsr_0<28>
     13: SFDecomp_204      26: SFDecomp_273

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    lfsr_0<2>         ................................X....... 1       1
    lfsr_0<29>        .....................................X.. 1       1
    lfsr_0<28>        ....................................X... 1       1
    lfsr_0<27>        ...................................X.... 1       1
    lfsr_0<26>        ..................................X..... 1       1
    lfsr_0<25>        .................................X...... 1       1
    _n0122            XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX........ 32      32
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB6 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   40/16
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mem_pointer_p<17>                 7       FB6_1   19    I/O      O
    mem_pointer_p<16>                 6       FB6_2   20    I/O      O
    mem_pointer_p<15>                 4       FB6_3   21    I/O      O
    (unused)                          0       FB6_4         (b)
    (unused)                          0       FB6_5         (b)
    counter<8>                        2       FB6_6         (b)      (b)
    counter<7>                        2       FB6_7         (b)      (b)
    counter<6>                        2       FB6_8         (b)      (b)
    counter<5>                        2       FB6_9         (b)      (b)
    counter<4>                        2       FB6_10        (b)      (b)
    counter<3>                        2       FB6_11        (b)      (b)
    counter<2>                        2       FB6_12        (b)      (b)
    counter<1>                        2       FB6_13        (b)      (b)
    counter<0>                        2       FB6_14        (b)      (b)
    N_PZ_1156                         4       FB6_15        (b)      (b)
    N_PZ_1215                         1       FB6_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_1138         14: counter<3>        27: mem_pointer_p<15>
      2: N_PZ_1156         15: counter<4>        28: mem_pointer_p<16>
      3: N_PZ_1161         16: counter<5>        29: mem_pointer_p<17>
      4: N_PZ_1215         17: counter<6>        30: mem_pointer_p<1>
      5: N_PZ_1252         18: counter<7>        31: mem_pointer_p<2>
      6: N_PZ_1265         19: counter<8>        32: mem_pointer_p<3>
      7: SFDecomp_73       20: db_in<15>         33: mem_pointer_p<4>
      8: SFDecomp_79       21: mem_pointer_p<0>  34: mem_pointer_p<5>
      9: _n0111            22: mem_pointer_p<10> 35: mem_pointer_p<6>
     10: _n0121            23: mem_pointer_p<11> 36: mem_pointer_p<7>
     11: counter<0>        24: mem_pointer_p<12> 37: mem_pointer_p<8>
     12: counter<1>        25: mem_pointer_p<13> 38: mem_pointer_p<9>
     13: counter<2>        26: mem_pointer_p<14>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mem_pointer_p<17>
                      XXXX.X.XX...........XXXXXXXXXXXX....XX.. 21      21
    mem_pointer_p<16>
                      XXXX.XX.X...........XXXXXXXX.XXX....XX.. 20      20
    mem_pointer_p<15>
                      XXXXXX..X..........X.XXXXXX.........XX.. 16      16
    counter<8>        ..X......XXXXXXXXXX..................... 11      11
    counter<7>        ..X......XXXXXXXXX...................... 10      10
    counter<6>        ..X......XXXXXXXX....................... 9       9
    counter<5>        ..X......XXXXXXX........................ 8       8
    counter<4>        ..X......XXXXXX......................... 7       7
    counter<3>        ..X......XXXXX.......................... 6       6
    counter<2>        ..X......XXXX........................... 5       5
    counter<1>        ..X......XXX............................ 4       4
    counter<0>        ..X......XX............................. 3       3
    N_PZ_1156         X.X..X..............X........XXXXXXX.... 11      11
    N_PZ_1215         XXX..X...............XXXXXX.........XX.. 12      12
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB7 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   49/7
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB7_1   191   I/O
    counter<12>                       2       FB7_2         (b)      (b)
    lfsr_0<30>                        1       FB7_3   189   I/O      (b)
    mem_done_ev                       2       FB7_4   188   I/O      (b)
    mem_done2                         2       FB7_5   187   I/O      (b)
    counter<13>                       2       FB7_6         (b)      (b)
    counter<14>                       2       FB7_7         (b)      (b)
    counter<15>                       2       FB7_8         (b)      (b)
    counter<16>                       2       FB7_9         (b)      (b)
    counter<17>                       2       FB7_10        (b)      (b)
    counter<18>                       2       FB7_11        (b)      (b)
    mem_done                          4       FB7_12        (b)      (b)
    Mcompar__n0095__n0015             20      FB7_13  186   I/O      (b)
    counter<9>                        2       FB7_14  185   I/O      (b)
    counter<10>                       2       FB7_15  184   I/O      (b)
    counter<11>                       2       FB7_16  183   I/O      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_1161         14: counter<18>       27: mem_done2
      2: _n0121            15: counter<1>        28: mem_done_ev
      3: _n0122            16: counter<2>        29: mword_count<0>
      4: _n0125            17: counter<3>        30: mword_count<12>
      5: counter<0>        18: counter<4>        31: mword_count<13>
      6: counter<10>       19: counter<5>        32: mword_count<14>
      7: counter<11>       20: counter<6>        33: mword_count<15>
      8: counter<12>       21: counter<7>        34: mword_count<16>
      9: counter<13>       22: counter<8>        35: mword_count<17>
     10: counter<14>       23: counter<9>        36: mword_count<1>
     11: counter<15>       24: ena_fill_mem      37: mword_count<2>
     12: counter<16>       25: lfsr_0<29>        38: mword_count<3>
     13: counter<17>       26: mem_done

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    counter<12>       XX..XXXX......XXXXXXXXX................. 15      15
    lfsr_0<30>        ........................X............... 1       1
    mem_done_ev       XX........................XX............ 4       4
    mem_done2         X.XX......................XX............ 5       5
    counter<13>       XX..XXXXX.....XXXXXXXXX................. 16      16
    counter<14>       XX..XXXXXX....XXXXXXXXX................. 17      17
    counter<15>       XX..XXXXXXX...XXXXXXXXX................. 18      18
    counter<16>       XX..XXXXXXXX..XXXXXXXXX................. 19      19
    counter<17>       XX..XXXXXXXXX.XXXXXXXXX................. 20      20
    counter<18>       XX..XXXXXXXXXXXXXXXXXXX................. 21      21
    mem_done          X.XXXXXXXXXXXXXXXXXXXXXX.X.X............ 25      25
    Mcompar__n0095__n0015
                      ........XXXXXXXXXX..........XXXXXXXXXX.. 20      20
    counter<9>        XX..X.........XXXXXXXXX................. 12      12
    counter<10>       XX..XX........XXXXXXXXX................. 13      13
    counter<11>       XX..XXX.......XXXXXXXXX................. 14      14
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB8 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  34
    Number of function block inputs used/remaining:               34/6
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   56/0
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    cycle_counter<4>                  4       FB8_1         (b)      (b)
    (unused)                          0       FB8_2   22    I/O
    (unused)                          0       FB8_3   23    I/O
    cycle_counter<5>                  4       FB8_4         (b)      (b)
    cycle_counter<6>                  4       FB8_5         (b)      (b)
    cycle_counter<7>                  4       FB8_6         (b)      (b)
    cycle_counter<8>                  4       FB8_7         (b)      (b)
    cycle_counter<9>                  4       FB8_8         (b)      (b)
    cycle_counter<10>                 4       FB8_9         (b)      (b)
    cycle_counter<11>                 4       FB8_10        (b)      (b)
    cycle_counter<12>                 4       FB8_11        (b)      (b)
    cycle_counter<13>                 4       FB8_12        (b)      (b)
    cycle_counter<14>                 4       FB8_13        (b)      (b)
    cycle_counter<3>                  4       FB8_14  25    I/O      (b)
    cycle_counter<15>                 4       FB8_15        (b)      (b)
    state_FFD2                        4       FB8_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: cycle_counter<0>  13: cycle_counter<6>  24: num_cycles<15>
      2: cycle_counter<10> 14: cycle_counter<7>  25: num_cycles<3>
      3: cycle_counter<11> 15: cycle_counter<8>  26: num_cycles<4>
      4: cycle_counter<12> 16: cycle_counter<9>  27: num_cycles<5>
      5: cycle_counter<13> 17: ena_mem_fifo_p    28: num_cycles<6>
      6: cycle_counter<14> 18: mem_done          29: num_cycles<7>
      7: cycle_counter<15> 19: num_cycles<10>    30: num_cycles<8>
      8: cycle_counter<1>  20: num_cycles<11>    31: num_cycles<9>
      9: cycle_counter<2>  21: num_cycles<12>    32: state_FFD1
     10: cycle_counter<3>  22: num_cycles<13>    33: state_FFD2
     11: cycle_counter<4>  23: num_cycles<14>    34: state_FFD3
     12: cycle_counter<5>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    cycle_counter<4>  X......XXXX..............X.....XXX...... 9       9
    cycle_counter<5>  X......XXXXX..............X....XXX...... 10      10
    cycle_counter<6>  X......XXXXXX..............X...XXX...... 11      11
    cycle_counter<7>  X......XXXXXXX..............X..XXX...... 12      12
    cycle_counter<8>  X......XXXXXXXX..............X.XXX...... 13      13
    cycle_counter<9>  X......XXXXXXXXX..............XXXX...... 14      14
    cycle_counter<10>
                      XX.....XXXXXXXXX..X............XXX...... 15      15
    cycle_counter<11>
                      XXX....XXXXXXXXX...X...........XXX...... 16      16
    cycle_counter<12>
                      XXXX...XXXXXXXXX....X..........XXX...... 17      17
    cycle_counter<13>
                      XXXXX..XXXXXXXXX.....X.........XXX...... 18      18
    cycle_counter<14>
                      XXXXXX.XXXXXXXXX......X........XXX...... 19      19
    cycle_counter<3>  X......XXX..............X......XXX...... 8       8
    cycle_counter<15>
                      XXXXXXXXXXXXXXXX.......X.......XXX...... 20      20
    state_FFD2        XXXXXXXXXXXXXXXXXX.............XXX...... 21      21
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB9 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   38/18
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    cycle_counter<0>                  4       FB9_1         (b)      (b)
    txena_out_p                       5       FB9_2   50    I/O      O
    mevent_count<6>                   2       FB9_3   49    I/O      (b)
    N_PZ_1138                         3       FB9_4   48    I/O      (b)
    state_FFD3                        2       FB9_5         (b)      (b)
    state_FFD1                        5       FB9_6         (b)      (b)
    lfsr_3<9>                         1       FB9_7         (b)      (b)
    lfsr_3<0>                         2       FB9_8         (b)      (b)
    lfsr_2<19>                        1       FB9_9         (b)      (b)
    lfsr_2<0>                         2       FB9_10        (b)      (b)
    lfsr_1<28>                        1       FB9_11        (b)      (b)
    lfsr_1<0>                         2       FB9_12        (b)      (b)
    lfsr_0<38>                        1       FB9_13        (b)      (b)
    cycle_counter<2>                  4       FB9_14  47    I/O      (b)
    lfsr_0<0>                         2       FB9_15        (b)      (b)
    cycle_counter<1>                  4       FB9_16  46    GCK/I/O  GCK

    Signals Used by Logic in Function Block
      1: _n0111            14: ena_cycles        26: lfsr_2<18>
      2: _n0125            15: ena_lfsr<0>       27: lfsr_2<20>
      3: add<0>            16: ena_lfsr<1>       28: lfsr_3<10>
      4: add<1>            17: ena_lfsr<2>       29: lfsr_3<8>
      5: add<2>            18: ena_lfsr<3>       30: mem_done
      6: add<3>            19: ena_mem_fifo_p    31: num_cycles<0>
      7: add<4>            20: ena_random        32: num_cycles<1>
      8: add<5>            21: enw               33: num_cycles<2>
      9: cs                22: lfsr_0<37>        34: state_FFD1
     10: cycle_counter<0>  23: lfsr_0<40>        35: state_FFD2
     11: cycle_counter<1>  24: lfsr_1<27>        36: state_FFD3
     12: cycle_counter<2>  25: lfsr_1<30>        37: txena_out_p
     13: db_in<6>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    cycle_counter<0>  .........X....................X..XXX.... 5       5
    txena_out_p       .X............XXXXXX..X.X.XX........X... 12      12
    mevent_count<6>   ..XXXXXXX...X.......X................... 9       9
    N_PZ_1138         X.XXXXXXX...........X............XXX.... 12      12
    state_FFD3        .............................X...XXX.... 4       4
    state_FFD1        .............X....X..........X...XXX.... 6       6
    lfsr_3<9>         ............................X........... 1       1
    lfsr_3<0>         ...........................XX........... 2       2
    lfsr_2<19>        .........................X.............. 1       1
    lfsr_2<0>         .........................XX............. 2       2
    lfsr_1<28>        .......................X................ 1       1
    lfsr_1<0>         .......................XX............... 2       2
    lfsr_0<38>        .....................X.................. 1       1
    cycle_counter<2>  .........XXX....................XXXX.... 7       7
    lfsr_0<0>         .....................XX................. 2       2
    cycle_counter<1>  .........XX....................X.XXX.... 6       6
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB10 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  29
    Number of function block inputs used/remaining:               29/11
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   51/5
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mem_pointer_p<2>                  7       FB10_1  51    CDR/I/O  O
    mem_pointer_p<1>                  6       FB10_2  54    I/O      O
    mem_pointer_p<0>                  5       FB10_3  55    GCK/I/O  O
    ena_fifo_mem_p                    4       FB10_4  56    I/O      O
    num_cycles<12>                    2       FB10_5        (b)      (b)
    num_cycles<11>                    2       FB10_6        (b)      (b)
    num_cycles<8>                     2       FB10_7        (b)      (b)
    mevent_count<8>                   2       FB10_8        (b)      (b)
    num_cycles<7>                     2       FB10_9        (b)      (b)
    mevent_count<7>                   2       FB10_10       (b)      (b)
    SFDecomp_79                       1       FB10_11       (b)      (b)
    SFDecomp_73                       1       FB10_12       (b)      (b)
    ena_mem_fifo_p                    11      FB10_13 57    I/O      O
    num_cycles<13>                    2       FB10_14 58    DGE/I/O  I
    num_cycles<1>                     2       FB10_15       (b)      (b)
    num_cycles<0>                     2       FB10_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_1138         11: cs                21: ena_mem_fifo_p
      2: N_PZ_1161         12: db_in<0>          22: enw
      3: N_PZ_1265         13: db_in<11>         23: mem_done
      4: _n0111            14: db_in<12>         24: mem_pointer_p<0>
      5: add<0>            15: db_in<13>         25: mem_pointer_p<1>
      6: add<1>            16: db_in<1>          26: mem_pointer_p<2>
      7: add<2>            17: db_in<2>          27: state_FFD1
      8: add<3>            18: db_in<7>          28: state_FFD2
      9: add<4>            19: db_in<8>          29: state_FFD3
     10: add<5>            20: ena_fifo_mem_p

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mem_pointer_p<2>  XXXXXXXXXXX.....X....X.XXX.............. 16      16
    mem_pointer_p<1>  XXXXXXXXXXX....XX....X.XX............... 16      16
    mem_pointer_p<0>  XXXXXXXXXXXX....X....X.X................ 15      15
    ena_fifo_mem_p    ....XXXXXXXX...X...X.XX................. 12      12
    num_cycles<12>    ....XXXXXXX..X.......X.................. 9       9
    num_cycles<11>    ....XXXXXXX.X........X.................. 9       9
    num_cycles<8>     ....XXXXXXX.......X..X.................. 9       9
    mevent_count<8>   ....XXXXXXX.......X..X.................. 9       9
    num_cycles<7>     ....XXXXXXX......X...X.................. 9       9
    mevent_count<7>   ....XXXXXXX......X...X.................. 9       9
    SFDecomp_79       ....XXXXXXX....XX....X.................. 10      10
    SFDecomp_73       ....XXXXXXXX....X....X.................. 10      10
    ena_mem_fifo_p    ....XXXXXXXX........XXX...XXX........... 14      14
    num_cycles<13>    ....XXXXXXX...X......X.................. 9       9
    num_cycles<1>     ....XXXXXXX....X.....X.................. 9       9
    num_cycles<0>     ....XXXXXXXX.........X.................. 9       9
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB11 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   46/10
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mem_pointer_p<7>                  4       FB11_1  45    I/O      O
    lfsr_0<34>                        1       FB11_2        (b)      (b)
    mem_pointer_p<6>                  6       FB11_3  44    GCK/I/O  O
    mem_pointer_p<5>                  5       FB11_4  43    I/O      O
    lfsr_0<33>                        1       FB11_5        (b)      (b)
    lfsr_0<32>                        1       FB11_6        (b)      (b)
    lfsr_0<31>                        1       FB11_7        (b)      (b)
    _n0111                            1       FB11_8        (b)      (b)
    N_PZ_1149                         1       FB11_9        (b)      (b)
    num_cycles<15>                    2       FB11_10       (b)      (b)
    num_cycles<14>                    2       FB11_11       (b)      (b)
    num_cycles<6>                     2       FB11_12       (b)      (b)
    mem_pointer_p<4>                  4       FB11_13 41    I/O      O
    mem_pointer_p<8>                  4       FB11_14 40    I/O      O
    mem_pointer_p<9>                  5       FB11_15 39    I/O      O
    mem_pointer_p<10>                 6       FB11_16 38    I/O      O

    Signals Used by Logic in Function Block
      1: N_PZ_1138         14: db_in<10>         27: lfsr_0<33>
      2: N_PZ_1156         15: db_in<14>         28: mem_pointer_p<0>
      3: N_PZ_1161         16: db_in<15>         29: mem_pointer_p<10>
      4: N_PZ_1252         17: db_in<4>          30: mem_pointer_p<1>
      5: N_PZ_1265         18: db_in<5>          31: mem_pointer_p<2>
      6: _n0111            19: db_in<6>          32: mem_pointer_p<3>
      7: add<0>            20: db_in<7>          33: mem_pointer_p<4>
      8: add<1>            21: db_in<8>          34: mem_pointer_p<5>
      9: add<2>            22: db_in<9>          35: mem_pointer_p<6>
     10: add<3>            23: enw               36: mem_pointer_p<7>
     11: add<4>            24: lfsr_0<30>        37: mem_pointer_p<8>
     12: add<5>            25: lfsr_0<31>        38: mem_pointer_p<9>
     13: cs                26: lfsr_0<32>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mem_pointer_p<7>  XXXXXX.............X.......X.XXXXXXX.... 15      15
    lfsr_0<34>        ..........................X............. 1       1
    mem_pointer_p<6>  X.XXXX............X........X.XXXXXX..... 13      13
    mem_pointer_p<5>  X.XXXX...........X.........X.XXXXX...... 12      12
    lfsr_0<33>        .........................X.............. 1       1
    lfsr_0<32>        ........................X............... 1       1
    lfsr_0<31>        .......................X................ 1       1
    _n0111            ......XXXXXXX.........X................. 8       8
    N_PZ_1149         ......XXXXXXX.........X................. 8       8
    num_cycles<15>    ......XXXXXXX..X......X................. 9       9
    num_cycles<14>    ......XXXXXXX.X.......X................. 9       9
    num_cycles<6>     ......XXXXXXX.....X...X................. 9       9
    mem_pointer_p<4>  X.XXXX..........X..........X.XXXX....... 11      11
    mem_pointer_p<8>  XXXXXX..............X...............X... 8       8
    mem_pointer_p<9>  XXXXXX...............X..............XX.. 9       9
    mem_pointer_p<10>
                      XXXXXX.......X..............X.......XX.. 10      10
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB12 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   51/5
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mem_pointer_p<14>                 10      FB12_1  60    I/O      O
    mem_pointer_p<13>                 9       FB12_2  61    I/O      O
    mem_pointer_p<12>                 8       FB12_3  62    I/O      O
    mem_pointer_p<11>                 7       FB12_4  63    I/O      O
    db_out<11>                        4       FB12_5  64    I/O      O
    lfsr_0<5>                         1       FB12_6        (b)      (b)
    lfsr_0<4>                         1       FB12_7        (b)      (b)
    lfsr_0<40>                        1       FB12_8        (b)      (b)
    lfsr_0<3>                         1       FB12_9        (b)      (b)
    lfsr_0<39>                        1       FB12_10       (b)      (b)
    lfsr_0<37>                        1       FB12_11       (b)      (b)
    lfsr_0<36>                        1       FB12_12       (b)      (b)
    db_out<12>                        4       FB12_13 65    I/O      O
    (unused)                          0       FB12_14 66    I/O      I
    lfsr_0<6>                         1       FB12_15 67    I/O      I
    lfsr_0<35>                        1       FB12_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_1138         14: db_in<12>         27: mem_pointer_p<11>
      2: N_PZ_1156         15: db_in<13>         28: mem_pointer_p<12>
      3: N_PZ_1161         16: db_in<14>         29: mem_pointer_p<13>
      4: N_PZ_1252         17: lfsr_0<2>         30: mem_pointer_p<14>
      5: N_PZ_1265         18: lfsr_0<34>        31: mem_pointer_p<8>
      6: _n0111            19: lfsr_0<35>        32: mem_pointer_p<9>
      7: add<0>            20: lfsr_0<36>        33: mevent_count<11>
      8: add<1>            21: lfsr_0<38>        34: mevent_count<12>
      9: add<2>            22: lfsr_0<39>        35: mword_count<11>
     10: add<3>            23: lfsr_0<3>         36: mword_count<12>
     11: add<4>            24: lfsr_0<4>         37: num_cycles<11>
     12: add<5>            25: lfsr_0<5>         38: num_cycles<12>
     13: db_in<11>         26: mem_pointer_p<10>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mem_pointer_p<14>
                      XXXXXX.........X.........XXXXXXX........ 14      14
    mem_pointer_p<13>
                      XXXXXX........X..........XXXX.XX........ 13      13
    mem_pointer_p<12>
                      XXXXXX.......X...........XXX..XX........ 12      12
    mem_pointer_p<11>
                      XXXXXX......X............XX...XX........ 11      11
    db_out<11>        ......XXXXXX..............X.....X.X.X... 10      10
    lfsr_0<5>         .......................X................ 1       1
    lfsr_0<4>         ......................X................. 1       1
    lfsr_0<40>        .....................X.................. 1       1
    lfsr_0<3>         ................X....................... 1       1
    lfsr_0<39>        ....................X................... 1       1
    lfsr_0<37>        ...................X.................... 1       1
    lfsr_0<36>        ..................X..................... 1       1
    db_out<12>        ......XXXXXX...............X.....X.X.X.. 10      10
    lfsr_0<6>         ........................X............... 1       1
    lfsr_0<35>        .................X...................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB13 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   32/24
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db_out<0>                         7       FB13_1  37    I/O      O
    (unused)                          0       FB13_2        (b)
    db_out<13>                        4       FB13_3  36    I/O      O
    db_out<14>                        4       FB13_4  35    I/O      O
    (unused)                          0       FB13_5        (b)
    (unused)                          0       FB13_6        (b)
    lfsr_1<14>                        1       FB13_7        (b)      (b)
    lfsr_1<13>                        1       FB13_8        (b)      (b)
    lfsr_1<12>                        1       FB13_9        (b)      (b)
    lfsr_1<11>                        1       FB13_10       (b)      (b)
    lfsr_1<10>                        1       FB13_11       (b)      (b)
    lfsr_0<9>                         1       FB13_12       (b)      (b)
    lfsr_0<8>                         1       FB13_13       (b)      (b)
    db_out<15>                        4       FB13_14 34    I/O      O
    db_out<10>                        5       FB13_15 32    I/O      O
    lfsr_0<7>                         1       FB13_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: add<0>            14: lfsr_1<12>        27: mevent_count<15>
      2: add<1>            15: lfsr_1<13>        28: mword_count<0>
      3: add<2>            16: lfsr_1<9>         29: mword_count<10>
      4: add<3>            17: mem_pointer_p<0>  30: mword_count<13>
      5: add<4>            18: mem_pointer_p<10> 31: mword_count<14>
      6: add<5>            19: mem_pointer_p<13> 32: mword_count<15>
      7: ena_lfsr<3>       20: mem_pointer_p<14> 33: mword_count<16>
      8: ena_mem_fifo_p    21: mem_pointer_p<15> 34: num_cycles<0>
      9: lfsr_0<6>         22: mem_pointer_p<16> 35: num_cycles<10>
     10: lfsr_0<7>         23: mevent_count<0>   36: num_cycles<13>
     11: lfsr_0<8>         24: mevent_count<10>  37: num_cycles<14>
     12: lfsr_1<10>        25: mevent_count<13>  38: num_cycles<15>
     13: lfsr_1<11>        26: mevent_count<14>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db_out<0>         XXXXXX.X........X....XX....X....XX...... 13      13
    db_out<13>        XXXXXX............X.....X....X.....X.... 10      10
    db_out<14>        XXXXXX.............X.....X....X.....X... 10      10
    lfsr_1<14>        ..............X......................... 1       1
    lfsr_1<13>        .............X.......................... 1       1
    lfsr_1<12>        ............X........................... 1       1
    lfsr_1<11>        ...........X............................ 1       1
    lfsr_1<10>        ...............X........................ 1       1
    lfsr_0<9>         ..........X............................. 1       1
    lfsr_0<8>         .........X.............................. 1       1
    db_out<15>        XXXXXX..............X.....X....X.....X.. 10      10
    db_out<10>        XXXXXXX..........X.....X....X.....X..... 11      11
    lfsr_0<7>         ........X............................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB14 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   32/24
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB14_1        (b)
    (unused)                          0       FB14_2        (b)
    db_out<1>                         7       FB14_3  69    I/O      O
    db_out<2>                         5       FB14_4  70    I/O      O
    db_out<3>                         5       FB14_5  71    I/O      O
    (unused)                          0       FB14_6        (b)
    (unused)                          0       FB14_7        (b)
    (unused)                          0       FB14_8        (b)
    (unused)                          0       FB14_9        (b)
    lfsr_1<19>                        1       FB14_10       (b)      (b)
    lfsr_1<18>                        1       FB14_11       (b)      (b)
    lfsr_1<17>                        1       FB14_12       (b)      (b)
    db_out<4>                         5       FB14_13 72    I/O      O
    lfsr_1<16>                        1       FB14_14       (b)      (b)
    db_out<5>                         5       FB14_15 73    I/O      O
    lfsr_1<15>                        1       FB14_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: add<0>            14: lfsr_1<16>        27: mevent_count<5>
      2: add<1>            15: lfsr_1<17>        28: mword_count<17>
      3: add<2>            16: lfsr_1<18>        29: mword_count<1>
      4: add<3>            17: mem_pointer_p<17> 30: mword_count<2>
      5: add<4>            18: mem_pointer_p<1>  31: mword_count<3>
      6: add<5>            19: mem_pointer_p<2>  32: mword_count<4>
      7: ena_cycles        20: mem_pointer_p<3>  33: mword_count<5>
      8: ena_event_count   21: mem_pointer_p<4>  34: num_cycles<1>
      9: ena_fifo_mem_p    22: mem_pointer_p<5>  35: num_cycles<2>
     10: ena_fill_mem      23: mevent_count<1>   36: num_cycles<3>
     11: ena_word_count    24: mevent_count<2>   37: num_cycles<4>
     12: lfsr_1<14>        25: mevent_count<3>   38: num_cycles<5>
     13: lfsr_1<15>        26: mevent_count<4>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db_out<1>         XXXXXX..X.......XX....X....XX....X...... 13      13
    db_out<2>         XXXXXX....X.......X....X.....X....X..... 11      11
    db_out<3>         XXXXXX.X...........X....X.....X....X.... 11      11
    lfsr_1<19>        ...............X........................ 1       1
    lfsr_1<18>        ..............X......................... 1       1
    lfsr_1<17>        .............X.......................... 1       1
    db_out<4>         XXXXXX...X..........X....X.....X....X... 11      11
    lfsr_1<16>        ............X........................... 1       1
    db_out<5>         XXXXXXX..............X....X.....X....X.. 11      11
    lfsr_1<15>        ...........X............................ 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB15 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   32/24
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db_out<6>                         5       FB15_1  31    I/O      O
    lfsr_1<2>                         1       FB15_2        (b)      (b)
    db_out<7>                         5       FB15_3  30    I/O      O
    db_out<8>                         5       FB15_4  29    I/O      O
    lfsr_1<29>                        1       FB15_5        (b)      (b)
    lfsr_1<27>                        1       FB15_6        (b)      (b)
    lfsr_1<26>                        1       FB15_7        (b)      (b)
    lfsr_1<25>                        1       FB15_8        (b)      (b)
    lfsr_1<24>                        1       FB15_9        (b)      (b)
    lfsr_1<23>                        1       FB15_10       (b)      (b)
    lfsr_1<22>                        1       FB15_11       (b)      (b)
    lfsr_1<21>                        1       FB15_12       (b)      (b)
    db_out<9>                         5       FB15_13 28    I/O      O
    lfsr_1<30>                        1       FB15_14 27    I/O      I
    lfsr_1<20>                        1       FB15_15       (b)      (b)
    lfsr_1<1>                         1       FB15_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: add<0>            14: lfsr_1<20>        27: mevent_count<6>
      2: add<1>            15: lfsr_1<21>        28: mevent_count<7>
      3: add<2>            16: lfsr_1<22>        29: mevent_count<8>
      4: add<3>            17: lfsr_1<23>        30: mevent_count<9>
      5: add<4>            18: lfsr_1<24>        31: mword_count<6>
      6: add<5>            19: lfsr_1<25>        32: mword_count<7>
      7: ena_lfsr<0>       20: lfsr_1<26>        33: mword_count<8>
      8: ena_lfsr<1>       21: lfsr_1<28>        34: mword_count<9>
      9: ena_lfsr<2>       22: lfsr_1<29>        35: num_cycles<6>
     10: ena_random        23: mem_pointer_p<6>  36: num_cycles<7>
     11: lfsr_1<0>         24: mem_pointer_p<7>  37: num_cycles<8>
     12: lfsr_1<19>        25: mem_pointer_p<8>  38: num_cycles<9>
     13: lfsr_1<1>         26: mem_pointer_p<9>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db_out<6>         XXXXXX...X............X...X...X...X..... 11      11
    lfsr_1<2>         ............X........................... 1       1
    db_out<7>         XXXXXXX................X...X...X...X.... 11      11
    db_out<8>         XXXXXX.X................X...X...X...X... 11      11
    lfsr_1<29>        ....................X................... 1       1
    lfsr_1<27>        ...................X.................... 1       1
    lfsr_1<26>        ..................X..................... 1       1
    lfsr_1<25>        .................X...................... 1       1
    lfsr_1<24>        ................X....................... 1       1
    lfsr_1<23>        ...............X........................ 1       1
    lfsr_1<22>        ..............X......................... 1       1
    lfsr_1<21>        .............X.......................... 1       1
    db_out<9>         XXXXXX..X................X...X...X...X.. 11      11
    lfsr_1<30>        .....................X.................. 1       1
    lfsr_1<20>        ...........X............................ 1       1
    lfsr_1<1>         ..........X............................. 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB16 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  16
    Number of function block inputs used/remaining:               16/24
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   16/40
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    lfsr_2<18>                        1       FB16_1  74    I/O      I
    lfsr_2<13>                        1       FB16_2        (b)      (b)
    lfsr_2<17>                        1       FB16_3  75    I/O      (b)
    lfsr_2<16>                        1       FB16_4  76    I/O      (b)
    lfsr_2<15>                        1       FB16_5  77    I/O      (b)
    lfsr_2<12>                        1       FB16_6        (b)      (b)
    lfsr_2<11>                        1       FB16_7        (b)      (b)
    lfsr_2<10>                        1       FB16_8        (b)      (b)
    lfsr_1<9>                         1       FB16_9        (b)      (b)
    lfsr_1<8>                         1       FB16_10       (b)      (b)
    lfsr_1<7>                         1       FB16_11       (b)      (b)
    lfsr_1<6>                         1       FB16_12       (b)      (b)
    lfsr_1<5>                         1       FB16_13       (b)      (b)
    lfsr_2<14>                        1       FB16_14 78    I/O      (b)
    lfsr_1<4>                         1       FB16_15       (b)      (b)
    lfsr_1<3>                         1       FB16_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: lfsr_1<2>          7: lfsr_1<8>         12: lfsr_2<14>
      2: lfsr_1<3>          8: lfsr_2<10>        13: lfsr_2<15>
      3: lfsr_1<4>          9: lfsr_2<11>        14: lfsr_2<16>
      4: lfsr_1<5>         10: lfsr_2<12>        15: lfsr_2<17>
      5: lfsr_1<6>         11: lfsr_2<13>        16: lfsr_2<9>
      6: lfsr_1<7>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    lfsr_2<18>        ..............X......................... 1       1
    lfsr_2<13>        .........X.............................. 1       1
    lfsr_2<17>        .............X.......................... 1       1
    lfsr_2<16>        ............X........................... 1       1
    lfsr_2<15>        ...........X............................ 1       1
    lfsr_2<12>        ........X............................... 1       1
    lfsr_2<11>        .......X................................ 1       1
    lfsr_2<10>        ...............X........................ 1       1
    lfsr_1<9>         ......X................................. 1       1
    lfsr_1<8>         .....X.................................. 1       1
    lfsr_1<7>         ....X................................... 1       1
    lfsr_1<6>         ...X.................................... 1       1
    lfsr_1<5>         ..X..................................... 1       1
    lfsr_2<14>        ..........X............................. 1       1
    lfsr_1<4>         .X...................................... 1       1
    lfsr_1<3>         X....................................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB17 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  16
    Number of function block inputs used/remaining:               16/24
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   16/40
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    lfsr_3<5>                         1       FB17_1  161   I/O      I
    lfsr_3<4>                         1       FB17_2  162   I/O      (b)
    lfsr_3<3>                         1       FB17_3  163   I/O      (b)
    lfsr_3<2>                         1       FB17_4  164   I/O      (b)
    lfsr_3<1>                         1       FB17_5  165   I/O      (b)
    lfsr_2<6>                         1       FB17_6        (b)      (b)
    lfsr_2<5>                         1       FB17_7        (b)      (b)
    lfsr_2<4>                         1       FB17_8        (b)      (b)
    lfsr_2<3>                         1       FB17_9        (b)      (b)
    lfsr_2<2>                         1       FB17_10       (b)      (b)
    lfsr_2<20>                        1       FB17_11       (b)      (b)
    lfsr_2<1>                         1       FB17_12       (b)      (b)
    lfsr_3<10>                        1       FB17_13 166   I/O      (b)
    lfsr_2<9>                         1       FB17_14 167   I/O      (b)
    lfsr_2<8>                         1       FB17_15 168   I/O      (b)
    lfsr_2<7>                         1       FB17_16 169   I/O      (b)

    Signals Used by Logic in Function Block
      1: lfsr_2<0>          7: lfsr_2<5>         12: lfsr_3<1>
      2: lfsr_2<19>         8: lfsr_2<6>         13: lfsr_3<2>
      3: lfsr_2<1>          9: lfsr_2<7>         14: lfsr_3<3>
      4: lfsr_2<2>         10: lfsr_2<8>         15: lfsr_3<4>
      5: lfsr_2<3>         11: lfsr_3<0>         16: lfsr_3<9>
      6: lfsr_2<4>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    lfsr_3<5>         ..............X......................... 1       1
    lfsr_3<4>         .............X.......................... 1       1
    lfsr_3<3>         ............X........................... 1       1
    lfsr_3<2>         ...........X............................ 1       1
    lfsr_3<1>         ..........X............................. 1       1
    lfsr_2<6>         ......X................................. 1       1
    lfsr_2<5>         .....X.................................. 1       1
    lfsr_2<4>         ....X................................... 1       1
    lfsr_2<3>         ...X.................................... 1       1
    lfsr_2<2>         ..X..................................... 1       1
    lfsr_2<20>        .X...................................... 1       1
    lfsr_2<1>         X....................................... 1       1
    lfsr_3<10>        ...............X........................ 1       1
    lfsr_2<9>         .........X.............................. 1       1
    lfsr_2<8>         ........X............................... 1       1
    lfsr_2<7>         .......X................................ 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB18 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  30
    Number of function block inputs used/remaining:               30/10
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   34/22
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    acc_fifo_p                        1       FB18_1  160   I/O      O
    SFDecomp_233                      1       FB18_2        (b)      (b)
    SFDecomp_224                      1       FB18_3        (b)      (b)
    SFDecomp_263                      1       FB18_4  159   I/O      (b)
    SFDecomp_223                      1       FB18_5        (b)      (b)
    SFDecomp_216                      1       FB18_6        (b)      (b)
    SFDecomp_215                      1       FB18_7        (b)      (b)
    _n0125                            18      FB18_8        (b)      (b)
    Mcompar__n0096_ANEB3              1       FB18_9        (b)      (b)
    Mcompar__n0096_ANEB2              1       FB18_10       (b)      (b)
    N_PZ_1265                         2       FB18_11       (b)      (b)
    lfsr_3<8>                         1       FB18_12       (b)      (b)
    lfsr_3<7>                         1       FB18_13       (b)      (b)
    lfsr_3<6>                         1       FB18_14       (b)      (b)
    SFDecomp_234                      1       FB18_15 158   I/O      (b)
    N_PZ_1161                         1       FB18_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: Mcompar__n0095__n0015
                           11: ena_mem_fifo_p    21: mword_count<10>
      2: counter<10>       12: ena_word_count    22: mword_count<11>
      3: counter<11>       13: lfsr_3<5>         23: mword_count<4>
      4: counter<12>       14: lfsr_3<6>         24: mword_count<5>
      5: counter<5>        15: lfsr_3<7>         25: mword_count<6>
      6: counter<6>        16: mevent_count<11>  26: mword_count<7>
      7: counter<7>        17: mevent_count<12>  27: mword_count<8>
      8: counter<8>        18: mevent_count<5>   28: mword_count<9>
      9: counter<9>        19: mevent_count<6>   29: txena_in
     10: ena_fifo_mem_p    20: mevent_count<8>   30: txena_out_p

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    acc_fifo_p        .........XX............................. 2       2
    SFDecomp_233      ....X............X...................... 2       2
    SFDecomp_224      .....X............X..................... 2       2
    SFDecomp_263      .......X...........X.................... 2       2
    SFDecomp_223      .....X............X..................... 2       2
    SFDecomp_216      ...X............X....................... 2       2
    SFDecomp_215      ...X............X....................... 2       2
    _n0125            XXXXXXXXX..X........XXXXXXXX............ 18      18
    Mcompar__n0096_ANEB3
                      ..X............X........................ 2       2
    Mcompar__n0096_ANEB2
                      ..X............X........................ 2       2
    N_PZ_1265         ..........X.................XX.......... 3       3
    lfsr_3<8>         ..............X......................... 1       1
    lfsr_3<7>         .............X.......................... 1       1
    lfsr_3<6>         ............X........................... 1       1
    SFDecomp_234      ....X............X...................... 2       2
    N_PZ_1161         .........XX............................. 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB19 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  20
    Number of function block inputs used/remaining:               20/20
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   18/38
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mem_done_p                        1       FB19_1  170   I/O      O
    SFDecomp_254                      1       FB19_2  171   I/O      (b)
    SFDecomp_253                      1       FB19_3  173   I/O      (b)
    SFDecomp_244                      1       FB19_4        (b)      (b)
    SFDecomp_243                      1       FB19_5        (b)      (b)
    SFDecomp_204                      1       FB19_6        (b)      (b)
    SFDecomp_203                      1       FB19_7        (b)      (b)
    SFDecomp_194                      1       FB19_8        (b)      (b)
    SFDecomp_193                      1       FB19_9        (b)      (b)
    SFDecomp_184                      1       FB19_10       (b)      (b)
    SFDecomp_183                      1       FB19_11       (b)      (b)
    SFDecomp_174                      1       FB19_12       (b)      (b)
    SFDecomp_173                      1       FB19_13       (b)      (b)
    SFDecomp_164                      1       FB19_14       (b)      (b)
    SFDecomp_163                      1       FB19_15       (b)      (b)
    _n0121                            3       FB19_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_1161          8: counter<3>        15: mevent_count<14>
      2: N_PZ_1265          9: counter<4>        16: mevent_count<15>
      3: counter<13>       10: ena_event_count   17: mevent_count<1>
      4: counter<14>       11: ena_word_count    18: mevent_count<2>
      5: counter<15>       12: is_trigger        19: mevent_count<3>
      6: counter<1>        13: mem_done2         20: mevent_count<4>
      7: counter<2>        14: mevent_count<13>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mem_done_p        X...........X........................... 2       2
    SFDecomp_254      ..X..........X.......................... 2       2
    SFDecomp_253      ..X..........X.......................... 2       2
    SFDecomp_244      .......X..........X..................... 2       2
    SFDecomp_243      .......X..........X..................... 2       2
    SFDecomp_204      ........X..........X.................... 2       2
    SFDecomp_203      ........X..........X.................... 2       2
    SFDecomp_194      ...X..........X......................... 2       2
    SFDecomp_193      ...X..........X......................... 2       2
    SFDecomp_184      ......X..........X...................... 2       2
    SFDecomp_183      ......X..........X...................... 2       2
    SFDecomp_174      ....X..........X........................ 2       2
    SFDecomp_173      ....X..........X........................ 2       2
    SFDecomp_164      .....X..........X....................... 2       2
    SFDecomp_163      .....X..........X....................... 2       2
    _n0121            XX.......XXX............................ 5       5
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB20 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  10
    Number of function block inputs used/remaining:               10/30
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   9/47
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB20_1        (b)
    (unused)                          0       FB20_2        (b)
    (unused)                          0       FB20_3  155   I/O
    (unused)                          0       FB20_4  154   I/O
    SFDecomp_294                      1       FB20_5        (b)      (b)
    SFDecomp_293                      1       FB20_6        (b)      (b)
    SFDecomp_284                      1       FB20_7        (b)      (b)
    SFDecomp_283                      1       FB20_8        (b)      (b)
    SFDecomp_274                      1       FB20_9        (b)      (b)
    SFDecomp_273                      1       FB20_10       (b)      (b)
    SFDecomp_264                      1       FB20_11       (b)      (b)
    SFDecomp_15                       2       FB20_12       (b)      (b)
    (unused)                          0       FB20_13 153   I/O
    (unused)                          0       FB20_14 152   I/O
    (unused)                          0       FB20_15 151   I/O
    (unused)                          0       FB20_16 150   I/O

    Signals Used by Logic in Function Block
      1: counter<0>         5: counter<9>         8: mevent_count<7>
      2: counter<10>        6: mevent_count<0>    9: mevent_count<8>
      3: counter<7>         7: mevent_count<10>  10: mevent_count<9>
      4: counter<8>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    SFDecomp_294      ....X....X.............................. 2       2
    SFDecomp_293      ....X....X.............................. 2       2
    SFDecomp_284      .X....X................................. 2       2
    SFDecomp_283      .X....X................................. 2       2
    SFDecomp_274      ..X....X................................ 2       2
    SFDecomp_273      ..X....X................................ 2       2
    SFDecomp_264      ...X....X............................... 2       2
    SFDecomp_15       X....X.................................. 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB21 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB21_1        (b)
    (unused)                          0       FB21_2  174   I/O
    (unused)                          0       FB21_3  175   I/O
    (unused)                          0       FB21_4        (b)
    (unused)                          0       FB21_5  178   I/O
    (unused)                          0       FB21_6        (b)
    (unused)                          0       FB21_7        (b)
    (unused)                          0       FB21_8        (b)
    (unused)                          0       FB21_9        (b)
    (unused)                          0       FB21_10       (b)
    (unused)                          0       FB21_11       (b)
    (unused)                          0       FB21_12       (b)
    (unused)                          0       FB21_13       (b)
    (unused)                          0       FB21_14       (b)
    (unused)                          0       FB21_15       (b)
    (unused)                          0       FB21_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB22 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB22_1  149   I/O
    (unused)                          0       FB22_2  148   I/O
    (unused)                          0       FB22_3  147   I/O
    (unused)                          0       FB22_4  146   I/O
    (unused)                          0       FB22_5        (b)
    (unused)                          0       FB22_6        (b)
    (unused)                          0       FB22_7        (b)
    (unused)                          0       FB22_8        (b)
    (unused)                          0       FB22_9        (b)
    (unused)                          0       FB22_10       (b)
    (unused)                          0       FB22_11       (b)
    (unused)                          0       FB22_12       (b)
    (unused)                          0       FB22_13 145   I/O
    (unused)                          0       FB22_14 144   I/O
    (unused)                          0       FB22_15 143   I/O
    (unused)                          0       FB22_16 142   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB23 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB23_1  179   I/O
    (unused)                          0       FB23_2  180   I/O
    (unused)                          0       FB23_3        (b)
    (unused)                          0       FB23_4  182   I/O
    (unused)                          0       FB23_5        (b)
    (unused)                          0       FB23_6        (b)
    (unused)                          0       FB23_7        (b)
    (unused)                          0       FB23_8        (b)
    (unused)                          0       FB23_9        (b)
    (unused)                          0       FB23_10       (b)
    (unused)                          0       FB23_11       (b)
    (unused)                          0       FB23_12       (b)
    (unused)                          0       FB23_13       (b)
    (unused)                          0       FB23_14       (b)
    (unused)                          0       FB23_15       (b)
    (unused)                          0       FB23_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB24 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB24_1  140   I/O
    (unused)                          0       FB24_2  139   I/O
    (unused)                          0       FB24_3  138   I/O
    (unused)                          0       FB24_4  137   I/O
    (unused)                          0       FB24_5        (b)
    (unused)                          0       FB24_6        (b)
    (unused)                          0       FB24_7        (b)
    (unused)                          0       FB24_8        (b)
    (unused)                          0       FB24_9        (b)
    (unused)                          0       FB24_10       (b)
    (unused)                          0       FB24_11       (b)
    (unused)                          0       FB24_12       (b)
    (unused)                          0       FB24_13 136   I/O
    (unused)                          0       FB24_14 135   I/O
    (unused)                          0       FB24_15 134   I/O
    (unused)                          0       FB24_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB25 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB25_1  110   I/O
    (unused)                          0       FB25_2  111   I/O
    (unused)                          0       FB25_3  112   I/O
    (unused)                          0       FB25_4  113   I/O
    (unused)                          0       FB25_5        (b)
    (unused)                          0       FB25_6        (b)
    (unused)                          0       FB25_7        (b)
    (unused)                          0       FB25_8        (b)
    (unused)                          0       FB25_9        (b)
    (unused)                          0       FB25_10       (b)
    (unused)                          0       FB25_11       (b)
    (unused)                          0       FB25_12       (b)
    (unused)                          0       FB25_13 114   I/O
    (unused)                          0       FB25_14 115   I/O
    (unused)                          0       FB25_15 116   I/O
    (unused)                          0       FB25_16 117   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB26 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB26_1  109   I/O
    (unused)                          0       FB26_2  108   I/O
    (unused)                          0       FB26_3  107   I/O
    (unused)                          0       FB26_4  106   I/O
    (unused)                          0       FB26_5        (b)
    (unused)                          0       FB26_6        (b)
    (unused)                          0       FB26_7        (b)
    (unused)                          0       FB26_8        (b)
    (unused)                          0       FB26_9        (b)
    (unused)                          0       FB26_10       (b)
    (unused)                          0       FB26_11       (b)
    (unused)                          0       FB26_12       (b)
    (unused)                          0       FB26_13 103   I/O
    (unused)                          0       FB26_14 102   I/O
    (unused)                          0       FB26_15 101   I/O
    (unused)                          0       FB26_16 100   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB27 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB27_1  118   I/O
    (unused)                          0       FB27_2        (b)
    (unused)                          0       FB27_3  119   I/O
    (unused)                          0       FB27_4  120   I/O
    (unused)                          0       FB27_5        (b)
    (unused)                          0       FB27_6        (b)
    (unused)                          0       FB27_7        (b)
    (unused)                          0       FB27_8        (b)
    (unused)                          0       FB27_9        (b)
    (unused)                          0       FB27_10       (b)
    (unused)                          0       FB27_11       (b)
    (unused)                          0       FB27_12       (b)
    (unused)                          0       FB27_13       (b)
    (unused)                          0       FB27_14       (b)
    (unused)                          0       FB27_15 121   I/O
    (unused)                          0       FB27_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB28 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB28_1  99    I/O
    (unused)                          0       FB28_2  97    I/O
    (unused)                          0       FB28_3  95    I/O
    (unused)                          0       FB28_4        (b)
    (unused)                          0       FB28_5        (b)
    (unused)                          0       FB28_6        (b)
    (unused)                          0       FB28_7        (b)
    (unused)                          0       FB28_8        (b)
    (unused)                          0       FB28_9        (b)
    (unused)                          0       FB28_10       (b)
    (unused)                          0       FB28_11       (b)
    (unused)                          0       FB28_12       (b)
    (unused)                          0       FB28_13       (b)
    (unused)                          0       FB28_14       (b)
    (unused)                          0       FB28_15       (b)
    (unused)                          0       FB28_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB29 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB29_1        (b)
    (unused)                          0       FB29_2        (b)
    (unused)                          0       FB29_3  122   I/O
    (unused)                          0       FB29_4  123   I/O
    (unused)                          0       FB29_5        (b)
    (unused)                          0       FB29_6        (b)
    (unused)                          0       FB29_7        (b)
    (unused)                          0       FB29_8        (b)
    (unused)                          0       FB29_9        (b)
    (unused)                          0       FB29_10       (b)
    (unused)                          0       FB29_11       (b)
    (unused)                          0       FB29_12       (b)
    (unused)                          0       FB29_13       (b)
    (unused)                          0       FB29_14 125   I/O
    (unused)                          0       FB29_15       (b)
    (unused)                          0       FB29_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB30 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB30_1        (b)
    (unused)                          0       FB30_2  91    I/O
    (unused)                          0       FB30_3  90    I/O
    (unused)                          0       FB30_4  89    I/O
    (unused)                          0       FB30_5        (b)
    (unused)                          0       FB30_6        (b)
    (unused)                          0       FB30_7        (b)
    (unused)                          0       FB30_8        (b)
    (unused)                          0       FB30_9        (b)
    (unused)                          0       FB30_10       (b)
    (unused)                          0       FB30_11       (b)
    (unused)                          0       FB30_12       (b)
    (unused)                          0       FB30_13 88    I/O
    (unused)                          0       FB30_14 87    I/O
    (unused)                          0       FB30_15       (b)
    (unused)                          0       FB30_16 86    I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB31 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB31_1  126   I/O
    (unused)                          0       FB31_2        (b)
    (unused)                          0       FB31_3  127   I/O
    (unused)                          0       FB31_4  128   I/O
    (unused)                          0       FB31_5        (b)
    (unused)                          0       FB31_6        (b)
    (unused)                          0       FB31_7        (b)
    (unused)                          0       FB31_8        (b)
    (unused)                          0       FB31_9        (b)
    (unused)                          0       FB31_10       (b)
    (unused)                          0       FB31_11       (b)
    (unused)                          0       FB31_12       (b)
    (unused)                          0       FB31_13       (b)
    (unused)                          0       FB31_14       (b)
    (unused)                          0       FB31_15       (b)
    (unused)                          0       FB31_16 131   I/O
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB32 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB32_1  85    I/O
    (unused)                          0       FB32_2  84    I/O
    (unused)                          0       FB32_3        (b)
    (unused)                          0       FB32_4  83    I/O
    (unused)                          0       FB32_5        (b)
    (unused)                          0       FB32_6        (b)
    (unused)                          0       FB32_7        (b)
    (unused)                          0       FB32_8        (b)
    (unused)                          0       FB32_9        (b)
    (unused)                          0       FB32_10       (b)
    (unused)                          0       FB32_11       (b)
    (unused)                          0       FB32_12       (b)
    (unused)                          0       FB32_13 82    I/O
    (unused)                          0       FB32_14 80    I/O
    (unused)                          0       FB32_15       (b)
    (unused)                          0       FB32_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    ;;-----------------------------------------------------------------;;
    ; Implemented Equations.

    acc_fifo_p <= NOT ((NOT ena_fifo_mem_p AND NOT ena_mem_fifo_p));

    FTCPE_ena_fifo_mem_p: FTCPE port map (ena_fifo_mem_p,ena_fifo_mem_p_T,clk,reset,'0','1');
    ena_fifo_mem_p_T <= ((ena_fifo_mem_p AND mem_done)
    	OR (ena_fifo_mem_p AND NOT db_in(1) AND NOT add(5) AND NOT add(4) AND
    	NOT add(3) AND NOT add(2) AND NOT add(0) AND enw AND cs AND NOT add(1))
    	OR (ena_fifo_mem_p AND NOT add(5) AND NOT add(4) AND NOT add(3) AND
    	NOT add(2) AND NOT add(0) AND enw AND cs AND NOT add(1) AND db_in(0))
    	OR (NOT ena_fifo_mem_p AND db_in(1) AND NOT add(5) AND NOT add(4) AND
    	NOT add(3) AND NOT add(2) AND NOT add(0) AND enw AND cs AND NOT add(1) AND
    	NOT db_in(0) AND NOT mem_done));

    FDCPE_mem_done: FDCPE port map (mem_done,mem_done_D,clk,reset,'0','1');
    mem_done_D <= ((mem_done AND NOT N_PZ_1161)
    	OR (NOT mem_done AND NOT N_PZ_1161 AND mem_done_ev)
    	OR (NOT mem_done AND NOT N_PZ_1161 AND NOT _n0125)
    	OR (NOT mem_done AND NOT N_PZ_1161 AND counter(11) AND
    	counter(10) AND counter(1) AND counter(0) AND counter(2) AND
    	counter(3) AND counter(4) AND counter(5) AND counter(6) AND
    	counter(7) AND counter(8) AND counter(9) AND counter(12) AND
    	counter(13) AND counter(14) AND counter(15) AND counter(16) AND
    	counter(17) AND NOT counter(18) AND NOT _n0122 AND ena_fill_mem));

    N_PZ_1161 <= (NOT ena_fifo_mem_p AND NOT ena_mem_fifo_p);

    FTCPE_ena_mem_fifo_p: FTCPE port map (ena_mem_fifo_p,ena_mem_fifo_p_T,clk,reset,'0','1');
    ena_mem_fifo_p_T <= ((mem_done AND ena_mem_fifo_p)
    	OR (add(5) AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (add(4) AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (add(3) AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (add(2) AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (add(0) AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (NOT enw AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (NOT cs AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (add(1) AND NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	NOT state_FFD1 AND NOT state_FFD3)
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT db_in(0) AND ena_mem_fifo_p)
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(0) AND NOT mem_done AND
    	NOT ena_mem_fifo_p));

    FDCPE_state_FFD2: FDCPE port map (state_FFD2,state_FFD2_D,clk,reset,'0','1');
    state_FFD2_D <= NOT (((NOT state_FFD2 AND NOT state_FFD1)
    	OR (NOT state_FFD2 AND state_FFD3)
    	OR (NOT mem_done AND NOT ena_mem_fifo_p AND state_FFD2 AND
    	state_FFD1 AND NOT state_FFD3)
    	OR (state_FFD1 AND state_FFD3 AND NOT cycle_counter(0) AND
    	NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
    	NOT cycle_counter(9) AND NOT cycle_counter(11) AND NOT cycle_counter(12) AND
    	NOT cycle_counter(13) AND NOT cycle_counter(14) AND NOT cycle_counter(15))));

    FDCPE_state_FFD1: FDCPE port map (state_FFD1,state_FFD1_D,clk,reset,'0','1');
    state_FFD1_D <= ((ena_mem_fifo_p AND state_FFD2 AND NOT state_FFD1)
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3)
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3)
    	OR (NOT mem_done AND ena_mem_fifo_p AND state_FFD1 AND
    	NOT state_FFD3)
    	OR (ena_mem_fifo_p AND NOT state_FFD1 AND NOT state_FFD3 AND
    	ena_cycles));

    FDCPE_state_FFD3: FDCPE port map (state_FFD3,state_FFD3_D,clk,reset,'0','1');
    state_FFD3_D <= ((state_FFD2 AND NOT state_FFD1 AND state_FFD3)
    	OR (mem_done AND state_FFD2 AND state_FFD1 AND NOT state_FFD3));

    FDCPE_ena_cycles: FDCPE port map (ena_cycles,db_in(5),clk,reset,'0',ena_cycles_CE);
    ena_cycles_CE <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    FDCPE_cycle_counter0: FDCPE port map (cycle_counter(0),cycle_counter_D(0),clk,reset,'0','1');
    cycle_counter_D(0) <= ((state_FFD2 AND state_FFD1 AND cycle_counter(0))
    	OR (NOT state_FFD1 AND NOT state_FFD3 AND cycle_counter(0))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	num_cycles(0)));

    FDCPE_num_cycles0: FDCPE port map (num_cycles(0),db_in(0),clk,reset,'0',num_cycles_CE(0));
    num_cycles_CE(0) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter10: FTCPE port map (cycle_counter(10),cycle_counter_T(10),clk,reset,'0','1');
    cycle_counter_T(10) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(10))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(10) AND
    	NOT num_cycles(10))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(10) AND num_cycles(10))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
    	NOT cycle_counter(9)));

    FDCPE_num_cycles10: FDCPE port map (num_cycles(10),db_in(10),clk,reset,'0',num_cycles_CE(10));
    num_cycles_CE(10) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter1: FTCPE port map (cycle_counter(1),cycle_counter_T(1),clk,reset,'0','1');
    cycle_counter_T(1) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(1))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(1) AND
    	NOT num_cycles(1))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(1) AND num_cycles(1)));

    FDCPE_num_cycles1: FDCPE port map (num_cycles(1),db_in(1),clk,reset,'0',num_cycles_CE(1));
    num_cycles_CE(1) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter2: FTCPE port map (cycle_counter(2),cycle_counter_T(2),clk,reset,'0','1');
    cycle_counter_T(2) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(2))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(2) AND
    	NOT num_cycles(2))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(2) AND num_cycles(2)));

    FDCPE_num_cycles2: FDCPE port map (num_cycles(2),db_in(2),clk,reset,'0',num_cycles_CE(2));
    num_cycles_CE(2) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter3: FTCPE port map (cycle_counter(3),cycle_counter_T(3),clk,reset,'0','1');
    cycle_counter_T(3) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(3))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(3) AND
    	NOT num_cycles(3))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(3) AND num_cycles(3))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2)));

    FDCPE_num_cycles3: FDCPE port map (num_cycles(3),db_in(3),clk,reset,'0',num_cycles_CE(3));
    num_cycles_CE(3) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter4: FTCPE port map (cycle_counter(4),cycle_counter_T(4),clk,reset,'0','1');
    cycle_counter_T(4) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(4))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(4) AND
    	NOT num_cycles(4))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(4) AND num_cycles(4))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3)));

    FDCPE_num_cycles4: FDCPE port map (num_cycles(4),db_in(4),clk,reset,'0',num_cycles_CE(4));
    num_cycles_CE(4) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter5: FTCPE port map (cycle_counter(5),cycle_counter_T(5),clk,reset,'0','1');
    cycle_counter_T(5) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(5))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(5) AND
    	NOT num_cycles(5))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(5) AND num_cycles(5))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4)));

    FDCPE_num_cycles5: FDCPE port map (num_cycles(5),db_in(5),clk,reset,'0',num_cycles_CE(5));
    num_cycles_CE(5) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter6: FTCPE port map (cycle_counter(6),cycle_counter_T(6),clk,reset,'0','1');
    cycle_counter_T(6) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(6))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(6) AND
    	NOT num_cycles(6))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(6) AND num_cycles(6))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5)));

    FDCPE_num_cycles6: FDCPE port map (num_cycles(6),db_in(6),clk,reset,'0',num_cycles_CE(6));
    num_cycles_CE(6) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter7: FTCPE port map (cycle_counter(7),cycle_counter_T(7),clk,reset,'0','1');
    cycle_counter_T(7) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(7))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(7) AND
    	NOT num_cycles(7))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(7) AND num_cycles(7))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6)));

    FDCPE_num_cycles7: FDCPE port map (num_cycles(7),db_in(7),clk,reset,'0',num_cycles_CE(7));
    num_cycles_CE(7) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter8: FTCPE port map (cycle_counter(8),cycle_counter_T(8),clk,reset,'0','1');
    cycle_counter_T(8) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(8))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(8) AND
    	NOT num_cycles(8))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(8) AND num_cycles(8))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7)));

    FDCPE_num_cycles8: FDCPE port map (num_cycles(8),db_in(8),clk,reset,'0',num_cycles_CE(8));
    num_cycles_CE(8) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter9: FTCPE port map (cycle_counter(9),cycle_counter_T(9),clk,reset,'0','1');
    cycle_counter_T(9) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(9))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(9) AND
    	NOT num_cycles(9))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(9) AND num_cycles(9))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8)));

    FDCPE_num_cycles9: FDCPE port map (num_cycles(9),db_in(9),clk,reset,'0',num_cycles_CE(9));
    num_cycles_CE(9) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter11: FTCPE port map (cycle_counter(11),cycle_counter_T(11),clk,reset,'0','1');
    cycle_counter_T(11) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(11))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(11) AND
    	NOT num_cycles(11))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(11) AND num_cycles(11))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8) AND NOT cycle_counter(9)));

    FDCPE_num_cycles11: FDCPE port map (num_cycles(11),db_in(11),clk,reset,'0',num_cycles_CE(11));
    num_cycles_CE(11) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter12: FTCPE port map (cycle_counter(12),cycle_counter_T(12),clk,reset,'0','1');
    cycle_counter_T(12) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(12))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(12) AND
    	NOT num_cycles(12))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(12) AND num_cycles(12))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8) AND NOT cycle_counter(9) AND NOT cycle_counter(11)));

    FDCPE_num_cycles12: FDCPE port map (num_cycles(12),db_in(12),clk,reset,'0',num_cycles_CE(12));
    num_cycles_CE(12) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter13: FTCPE port map (cycle_counter(13),cycle_counter_T(13),clk,reset,'0','1');
    cycle_counter_T(13) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(13))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(13) AND
    	NOT num_cycles(13))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(13) AND num_cycles(13))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8) AND NOT cycle_counter(9) AND NOT cycle_counter(11) AND
    	NOT cycle_counter(12)));

    FDCPE_num_cycles13: FDCPE port map (num_cycles(13),db_in(13),clk,reset,'0',num_cycles_CE(13));
    num_cycles_CE(13) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter14: FTCPE port map (cycle_counter(14),cycle_counter_T(14),clk,reset,'0','1');
    cycle_counter_T(14) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(14))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(14) AND
    	NOT num_cycles(14))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(14) AND num_cycles(14))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8) AND NOT cycle_counter(9) AND NOT cycle_counter(11) AND
    	NOT cycle_counter(12) AND NOT cycle_counter(13)));

    FDCPE_num_cycles14: FDCPE port map (num_cycles(14),db_in(14),clk,reset,'0',num_cycles_CE(14));
    num_cycles_CE(14) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FTCPE_cycle_counter15: FTCPE port map (cycle_counter(15),cycle_counter_T(15),clk,reset,'0','1');
    cycle_counter_T(15) <= ((NOT state_FFD2 AND state_FFD3 AND cycle_counter(15))
    	OR (NOT state_FFD2 AND state_FFD1 AND cycle_counter(15) AND
    	NOT num_cycles(15))
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3 AND
    	NOT cycle_counter(15) AND num_cycles(15))
    	OR (state_FFD2 AND NOT state_FFD1 AND state_FFD3 AND
    	NOT cycle_counter(0) AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8) AND NOT cycle_counter(9) AND NOT cycle_counter(11) AND
    	NOT cycle_counter(12) AND NOT cycle_counter(13) AND NOT cycle_counter(14)));

    FDCPE_num_cycles15: FDCPE port map (num_cycles(15),db_in(15),clk,reset,'0',num_cycles_CE(15));
    num_cycles_CE(15) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND add(1));

    FDCPE_mem_done_ev: FDCPE port map (mem_done_ev,mem_done_ev_D,clk,reset,'0','1');
    mem_done_ev_D <= ((mem_done_ev AND NOT _n0121)
    	OR (NOT N_PZ_1161 AND mem_done2 AND _n0121));

    FDCPE_mem_done2: FDCPE port map (mem_done2,mem_done2_D,clk,reset,'0','1');
    mem_done2_D <= ((NOT N_PZ_1161 AND mem_done2)
    	OR (NOT N_PZ_1161 AND NOT mem_done_ev AND NOT mem_done2 AND _n0125 AND
    	_n0122));

    _n0125 <= ((NOT ena_word_count)
    	OR (Mcompar__n0095__n0015)
    	OR (counter(11) AND NOT mword_count(10))
    	OR (NOT counter(11) AND mword_count(10))
    	OR (counter(10) AND NOT mword_count(9))
    	OR (NOT counter(10) AND mword_count(9))
    	OR (counter(5) AND NOT mword_count(4))
    	OR (NOT counter(5) AND mword_count(4))
    	OR (counter(6) AND NOT mword_count(5))
    	OR (NOT counter(6) AND mword_count(5))
    	OR (counter(7) AND NOT mword_count(6))
    	OR (NOT counter(7) AND mword_count(6))
    	OR (counter(8) AND NOT mword_count(7))
    	OR (NOT counter(8) AND mword_count(7))
    	OR (counter(9) AND NOT mword_count(8))
    	OR (NOT counter(9) AND mword_count(8))
    	OR (counter(12) AND NOT mword_count(11))
    	OR (NOT counter(12) AND mword_count(11)));

    FDCPE_ena_word_count: FDCPE port map (ena_word_count,db_in(2),clk,reset,'0',ena_word_count_CE);
    ena_word_count_CE <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    FTCPE_counter11: FTCPE port map (counter(11),counter_T(11),clk,reset,'0','1');
    counter_T(11) <= ((N_PZ_1161 AND counter(11) AND _n0121)
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(10) AND counter(1) AND
    	counter(0) AND counter(2) AND counter(3) AND counter(4) AND
    	counter(5) AND counter(6) AND counter(7) AND counter(8) AND
    	counter(9)));

    _n0121 <= ((N_PZ_1161)
    	OR (ena_word_count AND N_PZ_1265)
    	OR (is_trigger AND ena_event_count));

    FDCPE_ena_event_count: FDCPE port map (ena_event_count,db_in(3),clk,reset,'0',ena_event_count_CE);
    ena_event_count_CE <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    N_PZ_1265 <= ((ena_mem_fifo_p AND txena_out_p)
    	OR (NOT ena_mem_fifo_p AND txena_in));

    FDCPE_txena_out_p: FDCPE port map (txena_out_p,txena_out_p_D,clk,reset,'0','1');
    txena_out_p_D <= ((ena_mem_fifo_p AND _n0125 AND NOT txena_out_p AND
    	NOT ena_random)
    	OR (ena_mem_fifo_p AND _n0125 AND ena_random AND
    	ena_lfsr(0) AND lfsr_0(40))
    	OR (ena_mem_fifo_p AND _n0125 AND ena_random AND
    	ena_lfsr(1) AND lfsr_1(30))
    	OR (ena_mem_fifo_p AND _n0125 AND ena_random AND
    	ena_lfsr(2) AND lfsr_2(20))
    	OR (ena_mem_fifo_p AND _n0125 AND ena_random AND
    	ena_lfsr(3) AND lfsr_3(10)));

    FDCPE_ena_random: FDCPE port map (ena_random,db_in(6),clk,reset,'0',ena_random_CE);
    ena_random_CE <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    FDCPE_ena_lfsr0: FDCPE port map (ena_lfsr(0),db_in(7),clk,reset,'0',ena_lfsr_CE(0));
    ena_lfsr_CE(0) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    FDCPE_lfsr_040: FDCPE port map (lfsr_0(40),lfsr_0(39),clk,reset,'0','1');

    FDCPE_lfsr_039: FDCPE port map (lfsr_0(39),lfsr_0(38),clk,reset,'0','1');

    FDCPE_lfsr_038: FDCPE port map (lfsr_0(38),lfsr_0(37),clk,reset,'0','1');

    FDCPE_lfsr_037: FDCPE port map (lfsr_0(37),lfsr_0(36),clk,reset,'0','1');

    FDCPE_lfsr_036: FDCPE port map (lfsr_0(36),lfsr_0(35),clk,reset,'0','1');

    FDCPE_lfsr_035: FDCPE port map (lfsr_0(35),lfsr_0(34),clk,reset,'0','1');

    FDCPE_lfsr_034: FDCPE port map (lfsr_0(34),lfsr_0(33),clk,reset,'0','1');

    FDCPE_lfsr_033: FDCPE port map (lfsr_0(33),lfsr_0(32),clk,reset,'0','1');

    FDCPE_lfsr_032: FDCPE port map (lfsr_0(32),lfsr_0(31),clk,reset,'0','1');

    FDCPE_lfsr_031: FDCPE port map (lfsr_0(31),lfsr_0(30),clk,reset,'0','1');

    FDCPE_lfsr_030: FDCPE port map (lfsr_0(30),lfsr_0(29),clk,reset,'0','1');

    FDCPE_lfsr_029: FDCPE port map (lfsr_0(29),lfsr_0(28),clk,reset,'0','1');

    FDCPE_lfsr_028: FDCPE port map (lfsr_0(28),lfsr_0(27),clk,reset,'0','1');

    FDCPE_lfsr_027: FDCPE port map (lfsr_0(27),lfsr_0(26),clk,reset,'0','1');

    FDCPE_lfsr_026: FDCPE port map (lfsr_0(26),lfsr_0(25),clk,reset,'0','1');

    FDCPE_lfsr_025: FDCPE port map (lfsr_0(25),lfsr_0(24),clk,reset,'0','1');

    FDCPE_lfsr_024: FDCPE port map (lfsr_0(24),lfsr_0(23),clk,reset,'0','1');

    FDCPE_lfsr_023: FDCPE port map (lfsr_0(23),lfsr_0(22),clk,reset,'0','1');

    FDCPE_lfsr_022: FDCPE port map (lfsr_0(22),lfsr_0(21),clk,reset,'0','1');

    FDCPE_lfsr_021: FDCPE port map (lfsr_0(21),lfsr_0(20),clk,reset,'0','1');

    FDCPE_lfsr_020: FDCPE port map (lfsr_0(20),lfsr_0(19),clk,reset,'0','1');

    FDCPE_lfsr_019: FDCPE port map (lfsr_0(19),lfsr_0(18),clk,reset,'0','1');

    FDCPE_lfsr_018: FDCPE port map (lfsr_0(18),lfsr_0(17),clk,reset,'0','1');

    FDCPE_lfsr_017: FDCPE port map (lfsr_0(17),lfsr_0(16),clk,reset,'0','1');

    FDCPE_lfsr_016: FDCPE port map (lfsr_0(16),lfsr_0(15),clk,reset,'0','1');

    FDCPE_lfsr_015: FDCPE port map (lfsr_0(15),lfsr_0(14),clk,reset,'0','1');

    FDCPE_lfsr_014: FDCPE port map (lfsr_0(14),lfsr_0(13),clk,reset,'0','1');

    FDCPE_lfsr_013: FDCPE port map (lfsr_0(13),lfsr_0(12),clk,reset,'0','1');

    FDCPE_lfsr_012: FDCPE port map (lfsr_0(12),lfsr_0(11),clk,reset,'0','1');

    FDCPE_lfsr_011: FDCPE port map (lfsr_0(11),lfsr_0(10),clk,reset,'0','1');

    FDCPE_lfsr_010: FDCPE port map (lfsr_0(10),lfsr_0(9),clk,reset,'0','1');

    FDCPE_lfsr_09: FDCPE port map (lfsr_0(9),lfsr_0(8),clk,reset,'0','1');

    FDCPE_lfsr_08: FDCPE port map (lfsr_0(8),lfsr_0(7),clk,reset,'0','1');

    FDCPE_lfsr_07: FDCPE port map (lfsr_0(7),lfsr_0(6),clk,reset,'0','1');

    FDCPE_lfsr_06: FDCPE port map (lfsr_0(6),lfsr_0(5),clk,reset,'0','1');

    FDCPE_lfsr_05: FDCPE port map (lfsr_0(5),lfsr_0(4),clk,reset,'0','1');

    FDCPE_lfsr_04: FDCPE port map (lfsr_0(4),lfsr_0(3),clk,reset,'0','1');

    FDCPE_lfsr_03: FDCPE port map (lfsr_0(3),lfsr_0(2),clk,reset,'0','1');

    FDCPE_lfsr_02: FDCPE port map (lfsr_0(2),lfsr_0(1),clk,reset,'0','1');

    FDCPE_lfsr_01: FDCPE port map (lfsr_0(1),lfsr_0(0),clk,reset,'0','1');

    FDCPE_lfsr_00: FDCPE port map (lfsr_0(0),lfsr_0_D(0),clk,reset,'0','1');
    lfsr_0_D(0) <= ((lfsr_0(40) AND lfsr_0(37))
    	OR (NOT lfsr_0(40) AND NOT lfsr_0(37)));

    FDCPE_ena_lfsr1: FDCPE port map (ena_lfsr(1),db_in(8),clk,reset,'0',ena_lfsr_CE(1));
    ena_lfsr_CE(1) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    FDCPE_lfsr_130: FDCPE port map (lfsr_1(30),lfsr_1(29),clk,reset,'0','1');

    FDCPE_lfsr_129: FDCPE port map (lfsr_1(29),lfsr_1(28),clk,reset,'0','1');

    FDCPE_lfsr_128: FDCPE port map (lfsr_1(28),lfsr_1(27),clk,reset,'0','1');

    FDCPE_lfsr_127: FDCPE port map (lfsr_1(27),lfsr_1(26),clk,reset,'0','1');

    FDCPE_lfsr_126: FDCPE port map (lfsr_1(26),lfsr_1(25),clk,reset,'0','1');

    FDCPE_lfsr_125: FDCPE port map (lfsr_1(25),lfsr_1(24),clk,reset,'0','1');

    FDCPE_lfsr_124: FDCPE port map (lfsr_1(24),lfsr_1(23),clk,reset,'0','1');

    FDCPE_lfsr_123: FDCPE port map (lfsr_1(23),lfsr_1(22),clk,reset,'0','1');

    FDCPE_lfsr_122: FDCPE port map (lfsr_1(22),lfsr_1(21),clk,reset,'0','1');

    FDCPE_lfsr_121: FDCPE port map (lfsr_1(21),lfsr_1(20),clk,reset,'0','1');

    FDCPE_lfsr_120: FDCPE port map (lfsr_1(20),lfsr_1(19),clk,reset,'0','1');

    FDCPE_lfsr_119: FDCPE port map (lfsr_1(19),lfsr_1(18),clk,reset,'0','1');

    FDCPE_lfsr_118: FDCPE port map (lfsr_1(18),lfsr_1(17),clk,reset,'0','1');

    FDCPE_lfsr_117: FDCPE port map (lfsr_1(17),lfsr_1(16),clk,reset,'0','1');

    FDCPE_lfsr_116: FDCPE port map (lfsr_1(16),lfsr_1(15),clk,reset,'0','1');

    FDCPE_lfsr_115: FDCPE port map (lfsr_1(15),lfsr_1(14),clk,reset,'0','1');

    FDCPE_lfsr_114: FDCPE port map (lfsr_1(14),lfsr_1(13),clk,reset,'0','1');

    FDCPE_lfsr_113: FDCPE port map (lfsr_1(13),lfsr_1(12),clk,reset,'0','1');

    FDCPE_lfsr_112: FDCPE port map (lfsr_1(12),lfsr_1(11),clk,reset,'0','1');

    FDCPE_lfsr_111: FDCPE port map (lfsr_1(11),lfsr_1(10),clk,reset,'0','1');

    FDCPE_lfsr_110: FDCPE port map (lfsr_1(10),lfsr_1(9),clk,reset,'0','1');

    FDCPE_lfsr_19: FDCPE port map (lfsr_1(9),lfsr_1(8),clk,reset,'0','1');

    FDCPE_lfsr_18: FDCPE port map (lfsr_1(8),lfsr_1(7),clk,reset,'0','1');

    FDCPE_lfsr_17: FDCPE port map (lfsr_1(7),lfsr_1(6),clk,reset,'0','1');

    FDCPE_lfsr_16: FDCPE port map (lfsr_1(6),lfsr_1(5),clk,reset,'0','1');

    FDCPE_lfsr_15: FDCPE port map (lfsr_1(5),lfsr_1(4),clk,reset,'0','1');

    FDCPE_lfsr_14: FDCPE port map (lfsr_1(4),lfsr_1(3),clk,reset,'0','1');

    FDCPE_lfsr_13: FDCPE port map (lfsr_1(3),lfsr_1(2),clk,reset,'0','1');

    FDCPE_lfsr_12: FDCPE port map (lfsr_1(2),lfsr_1(1),clk,reset,'0','1');

    FDCPE_lfsr_11: FDCPE port map (lfsr_1(1),lfsr_1(0),clk,reset,'0','1');

    FDCPE_lfsr_10: FDCPE port map (lfsr_1(0),lfsr_1_D(0),clk,reset,'0','1');
    lfsr_1_D(0) <= ((lfsr_1(30) AND lfsr_1(27))
    	OR (NOT lfsr_1(30) AND NOT lfsr_1(27)));

    FDCPE_ena_lfsr2: FDCPE port map (ena_lfsr(2),db_in(9),clk,reset,'0',ena_lfsr_CE(2));
    ena_lfsr_CE(2) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    FDCPE_lfsr_220: FDCPE port map (lfsr_2(20),lfsr_2(19),clk,reset,'0','1');

    FDCPE_lfsr_219: FDCPE port map (lfsr_2(19),lfsr_2(18),clk,reset,'0','1');

    FDCPE_lfsr_218: FDCPE port map (lfsr_2(18),lfsr_2(17),clk,reset,'0','1');

    FDCPE_lfsr_217: FDCPE port map (lfsr_2(17),lfsr_2(16),clk,reset,'0','1');

    FDCPE_lfsr_216: FDCPE port map (lfsr_2(16),lfsr_2(15),clk,reset,'0','1');

    FDCPE_lfsr_215: FDCPE port map (lfsr_2(15),lfsr_2(14),clk,reset,'0','1');

    FDCPE_lfsr_214: FDCPE port map (lfsr_2(14),lfsr_2(13),clk,reset,'0','1');

    FDCPE_lfsr_213: FDCPE port map (lfsr_2(13),lfsr_2(12),clk,reset,'0','1');

    FDCPE_lfsr_212: FDCPE port map (lfsr_2(12),lfsr_2(11),clk,reset,'0','1');

    FDCPE_lfsr_211: FDCPE port map (lfsr_2(11),lfsr_2(10),clk,reset,'0','1');

    FDCPE_lfsr_210: FDCPE port map (lfsr_2(10),lfsr_2(9),clk,reset,'0','1');

    FDCPE_lfsr_29: FDCPE port map (lfsr_2(9),lfsr_2(8),clk,reset,'0','1');

    FDCPE_lfsr_28: FDCPE port map (lfsr_2(8),lfsr_2(7),clk,reset,'0','1');

    FDCPE_lfsr_27: FDCPE port map (lfsr_2(7),lfsr_2(6),clk,reset,'0','1');

    FDCPE_lfsr_26: FDCPE port map (lfsr_2(6),lfsr_2(5),clk,reset,'0','1');

    FDCPE_lfsr_25: FDCPE port map (lfsr_2(5),lfsr_2(4),clk,reset,'0','1');

    FDCPE_lfsr_24: FDCPE port map (lfsr_2(4),lfsr_2(3),clk,reset,'0','1');

    FDCPE_lfsr_23: FDCPE port map (lfsr_2(3),lfsr_2(2),clk,reset,'0','1');

    FDCPE_lfsr_22: FDCPE port map (lfsr_2(2),lfsr_2(1),clk,reset,'0','1');

    FDCPE_lfsr_21: FDCPE port map (lfsr_2(1),lfsr_2(0),clk,reset,'0','1');

    FDCPE_lfsr_20: FDCPE port map (lfsr_2(0),lfsr_2_D(0),clk,reset,'0','1');
    lfsr_2_D(0) <= ((lfsr_2(20) AND lfsr_2(18))
    	OR (NOT lfsr_2(20) AND NOT lfsr_2(18)));

    FDCPE_ena_lfsr3: FDCPE port map (ena_lfsr(3),db_in(10),clk,reset,'0',ena_lfsr_CE(3));
    ena_lfsr_CE(3) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    FDCPE_lfsr_310: FDCPE port map (lfsr_3(10),lfsr_3(9),clk,reset,'0','1');

    FDCPE_lfsr_39: FDCPE port map (lfsr_3(9),lfsr_3(8),clk,reset,'0','1');

    FDCPE_lfsr_38: FDCPE port map (lfsr_3(8),lfsr_3(7),clk,reset,'0','1');

    FDCPE_lfsr_37: FDCPE port map (lfsr_3(7),lfsr_3(6),clk,reset,'0','1');

    FDCPE_lfsr_36: FDCPE port map (lfsr_3(6),lfsr_3(5),clk,reset,'0','1');

    FDCPE_lfsr_35: FDCPE port map (lfsr_3(5),lfsr_3(4),clk,reset,'0','1');

    FDCPE_lfsr_34: FDCPE port map (lfsr_3(4),lfsr_3(3),clk,reset,'0','1');

    FDCPE_lfsr_33: FDCPE port map (lfsr_3(3),lfsr_3(2),clk,reset,'0','1');

    FDCPE_lfsr_32: FDCPE port map (lfsr_3(2),lfsr_3(1),clk,reset,'0','1');

    FDCPE_lfsr_31: FDCPE port map (lfsr_3(1),lfsr_3(0),clk,reset,'0','1');

    FDCPE_lfsr_30: FDCPE port map (lfsr_3(0),lfsr_3_D(0),clk,reset,'0','1');
    lfsr_3_D(0) <= ((lfsr_3(10) AND lfsr_3(8))
    	OR (NOT lfsr_3(10) AND NOT lfsr_3(8)));

    FTCPE_counter10: FTCPE port map (counter(10),counter_T(10),clk,reset,'0','1');
    counter_T(10) <= ((N_PZ_1161 AND _n0121 AND counter(10))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2) AND counter(3) AND counter(4) AND counter(5) AND
    	counter(6) AND counter(7) AND counter(8) AND counter(9)));

    FTCPE_counter1: FTCPE port map (counter(1),counter_T(1),clk,reset,'0','1');
    counter_T(1) <= ((N_PZ_1161 AND _n0121 AND counter(1))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(0)));

    FDCPE_counter0: FDCPE port map (counter(0),counter_D(0),clk,reset,'0','1');
    counter_D(0) <= ((NOT _n0121 AND counter(0))
    	OR (NOT N_PZ_1161 AND _n0121 AND NOT counter(0)));

    FTCPE_counter2: FTCPE port map (counter(2),counter_T(2),clk,reset,'0','1');
    counter_T(2) <= ((N_PZ_1161 AND _n0121 AND counter(2))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0)));

    FTCPE_counter3: FTCPE port map (counter(3),counter_T(3),clk,reset,'0','1');
    counter_T(3) <= ((N_PZ_1161 AND _n0121 AND counter(3))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2)));

    FTCPE_counter4: FTCPE port map (counter(4),counter_T(4),clk,reset,'0','1');
    counter_T(4) <= ((N_PZ_1161 AND _n0121 AND counter(4))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2) AND counter(3)));

    FTCPE_counter5: FTCPE port map (counter(5),counter_T(5),clk,reset,'0','1');
    counter_T(5) <= ((N_PZ_1161 AND _n0121 AND counter(5))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2) AND counter(3) AND counter(4)));

    FTCPE_counter6: FTCPE port map (counter(6),counter_T(6),clk,reset,'0','1');
    counter_T(6) <= ((N_PZ_1161 AND _n0121 AND counter(6))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2) AND counter(3) AND counter(4) AND counter(5)));

    FTCPE_counter7: FTCPE port map (counter(7),counter_T(7),clk,reset,'0','1');
    counter_T(7) <= ((N_PZ_1161 AND _n0121 AND counter(7))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2) AND counter(3) AND counter(4) AND counter(5) AND
    	counter(6)));

    FTCPE_counter8: FTCPE port map (counter(8),counter_T(8),clk,reset,'0','1');
    counter_T(8) <= ((N_PZ_1161 AND _n0121 AND counter(8))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2) AND counter(3) AND counter(4) AND counter(5) AND
    	counter(6) AND counter(7)));

    FTCPE_counter9: FTCPE port map (counter(9),counter_T(9),clk,reset,'0','1');
    counter_T(9) <= ((N_PZ_1161 AND _n0121 AND counter(9))
    	OR (NOT N_PZ_1161 AND _n0121 AND counter(1) AND counter(0) AND
    	counter(2) AND counter(3) AND counter(4) AND counter(5) AND
    	counter(6) AND counter(7) AND counter(8)));

    FDCPE_mword_count10: FDCPE port map (mword_count(10),mword_count_D(10),clk,reset,'0','1');
    mword_count_D(10) <= NOT (((NOT db_in(10) AND N_PZ_1149)
    	OR (NOT mword_count(10) AND NOT N_PZ_1149)
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    N_PZ_1149 <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	enw AND cs AND add(1));

    FTCPE_counter12: FTCPE port map (counter(12),counter_T(12),clk,reset,'0','1');
    counter_T(12) <= ((N_PZ_1161 AND _n0121 AND counter(12))
    	OR (NOT N_PZ_1161 AND counter(11) AND _n0121 AND counter(10) AND
    	counter(1) AND counter(0) AND counter(2) AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7) AND
    	counter(8) AND counter(9)));

    FDCPE_mword_count11: FDCPE port map (mword_count(11),mword_count_D(11),clk,reset,'0','1');
    mword_count_D(11) <= NOT (((NOT db_in(11) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(11))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count4: FDCPE port map (mword_count(4),mword_count_D(4),clk,reset,'0','1');
    mword_count_D(4) <= NOT (((NOT db_in(4) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(4))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count5: FDCPE port map (mword_count(5),mword_count_D(5),clk,reset,'0','1');
    mword_count_D(5) <= NOT (((NOT db_in(5) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(5))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count6: FDCPE port map (mword_count(6),mword_count_D(6),clk,reset,'0','1');
    mword_count_D(6) <= NOT (((NOT db_in(6) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(6))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count7: FDCPE port map (mword_count(7),mword_count_D(7),clk,reset,'0','1');
    mword_count_D(7) <= NOT (((NOT db_in(7) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(7))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count8: FDCPE port map (mword_count(8),mword_count_D(8),clk,reset,'0','1');
    mword_count_D(8) <= NOT (((NOT db_in(8) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(8))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count9: FDCPE port map (mword_count(9),mword_count_D(9),clk,reset,'0','1');
    mword_count_D(9) <= NOT (((NOT db_in(9) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(9))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    Mcompar__n0095__n0015 <= ((counter(1) AND NOT mword_count(0))
    	OR (NOT counter(1) AND mword_count(0))
    	OR (counter(2) AND NOT mword_count(1))
    	OR (NOT counter(2) AND mword_count(1))
    	OR (counter(3) AND NOT mword_count(2))
    	OR (NOT counter(3) AND mword_count(2))
    	OR (counter(4) AND NOT mword_count(3))
    	OR (NOT counter(4) AND mword_count(3))
    	OR (counter(13) AND NOT mword_count(12))
    	OR (NOT counter(13) AND mword_count(12))
    	OR (counter(14) AND NOT mword_count(13))
    	OR (NOT counter(14) AND mword_count(13))
    	OR (counter(15) AND NOT mword_count(14))
    	OR (NOT counter(15) AND mword_count(14))
    	OR (counter(16) AND NOT mword_count(15))
    	OR (NOT counter(16) AND mword_count(15))
    	OR (counter(17) AND NOT mword_count(16))
    	OR (NOT counter(17) AND mword_count(16))
    	OR (counter(18) AND NOT mword_count(17))
    	OR (NOT counter(18) AND mword_count(17)));

    FDCPE_mword_count0: FDCPE port map (mword_count(0),mword_count_D(0),clk,reset,'0','1');
    mword_count_D(0) <= NOT (((NOT db_in(0) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(0))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FTCPE_counter13: FTCPE port map (counter(13),counter_T(13),clk,reset,'0','1');
    counter_T(13) <= ((N_PZ_1161 AND _n0121 AND counter(13))
    	OR (NOT N_PZ_1161 AND counter(11) AND _n0121 AND counter(10) AND
    	counter(1) AND counter(0) AND counter(2) AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7) AND
    	counter(8) AND counter(9) AND counter(12)));

    FDCPE_mword_count12: FDCPE port map (mword_count(12),mword_count_D(12),clk,reset,'0','1');
    mword_count_D(12) <= NOT (((NOT db_in(12) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(12))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FTCPE_counter14: FTCPE port map (counter(14),counter_T(14),clk,reset,'0','1');
    counter_T(14) <= ((N_PZ_1161 AND _n0121 AND counter(14))
    	OR (NOT N_PZ_1161 AND counter(11) AND _n0121 AND counter(10) AND
    	counter(1) AND counter(0) AND counter(2) AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7) AND
    	counter(8) AND counter(9) AND counter(12) AND counter(13)));

    FDCPE_mword_count13: FDCPE port map (mword_count(13),mword_count_D(13),clk,reset,'0','1');
    mword_count_D(13) <= NOT (((NOT db_in(13) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(13))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FTCPE_counter15: FTCPE port map (counter(15),counter_T(15),clk,reset,'0','1');
    counter_T(15) <= ((N_PZ_1161 AND _n0121 AND counter(15))
    	OR (NOT N_PZ_1161 AND counter(11) AND _n0121 AND counter(10) AND
    	counter(1) AND counter(0) AND counter(2) AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7) AND
    	counter(8) AND counter(9) AND counter(12) AND counter(13) AND
    	counter(14)));

    FDCPE_mword_count14: FDCPE port map (mword_count(14),mword_count_D(14),clk,reset,'0','1');
    mword_count_D(14) <= NOT (((NOT db_in(14) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(14))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FTCPE_counter16: FTCPE port map (counter(16),counter_T(16),clk,reset,'0','1');
    counter_T(16) <= ((N_PZ_1161 AND _n0121 AND counter(16))
    	OR (NOT N_PZ_1161 AND counter(11) AND _n0121 AND counter(10) AND
    	counter(1) AND counter(0) AND counter(2) AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7) AND
    	counter(8) AND counter(9) AND counter(12) AND counter(13) AND
    	counter(14) AND counter(15)));

    FDCPE_mword_count15: FDCPE port map (mword_count(15),mword_count_D(15),clk,reset,'0','1');
    mword_count_D(15) <= NOT (((NOT db_in(15) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(15))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FTCPE_counter17: FTCPE port map (counter(17),counter_T(17),clk,reset,'0','1');
    counter_T(17) <= ((N_PZ_1161 AND _n0121 AND counter(17))
    	OR (NOT N_PZ_1161 AND counter(11) AND _n0121 AND counter(10) AND
    	counter(1) AND counter(0) AND counter(2) AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7) AND
    	counter(8) AND counter(9) AND counter(12) AND counter(13) AND
    	counter(14) AND counter(15) AND counter(16)));

    FTCPE_mword_count16: FTCPE port map (mword_count(16),mword_count_T(16),clk,reset,'0','1');
    mword_count_T(16) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT db_in(0) AND mword_count(16))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2) AND mword_count(16))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(0) AND NOT db_in(2) AND
    	NOT mword_count(16)));

    FTCPE_counter18: FTCPE port map (counter(18),counter_T(18),clk,reset,'0','1');
    counter_T(18) <= ((N_PZ_1161 AND _n0121 AND counter(18))
    	OR (NOT N_PZ_1161 AND counter(11) AND _n0121 AND counter(10) AND
    	counter(1) AND counter(0) AND counter(2) AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7) AND
    	counter(8) AND counter(9) AND counter(12) AND counter(13) AND
    	counter(14) AND counter(15) AND counter(16) AND counter(17)));

    FTCPE_mword_count17: FTCPE port map (mword_count(17),mword_count_T(17),clk,reset,'0','1');
    mword_count_T(17) <= ((NOT db_in(1) AND NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND
    	NOT add(0) AND enw AND cs AND NOT add(1) AND mword_count(17))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2) AND mword_count(17))
    	OR (db_in(1) AND NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND
    	NOT add(0) AND enw AND cs AND NOT add(1) AND NOT db_in(2) AND NOT mword_count(17)));

    FDCPE_mword_count1: FDCPE port map (mword_count(1),mword_count_D(1),clk,reset,'0','1');
    mword_count_D(1) <= NOT (((NOT db_in(1) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(1))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count2: FDCPE port map (mword_count(2),mword_count_D(2),clk,reset,'0','1');
    mword_count_D(2) <= NOT (((NOT db_in(2) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(2))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    FDCPE_mword_count3: FDCPE port map (mword_count(3),mword_count_D(3),clk,reset,'0','1');
    mword_count_D(3) <= NOT (((NOT db_in(3) AND N_PZ_1149)
    	OR (NOT N_PZ_1149 AND NOT mword_count(3))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND db_in(2))));

    _n0122 <= (ena_event_count AND NOT SFDecomp_15 AND NOT SFDecomp_164 AND
    	NOT SFDecomp_163 AND NOT SFDecomp_174 AND NOT SFDecomp_173 AND NOT SFDecomp_184 AND
    	NOT SFDecomp_183 AND NOT SFDecomp_193 AND NOT SFDecomp_194 AND NOT SFDecomp_203 AND
    	NOT SFDecomp_204 AND NOT SFDecomp_215 AND NOT SFDecomp_216 AND NOT SFDecomp_224 AND
    	NOT SFDecomp_223 AND NOT SFDecomp_234 AND NOT SFDecomp_233 AND NOT SFDecomp_244 AND
    	NOT SFDecomp_243 AND NOT SFDecomp_253 AND NOT SFDecomp_254 AND NOT SFDecomp_264 AND
    	NOT SFDecomp_263 AND NOT SFDecomp_274 AND NOT SFDecomp_273 AND NOT SFDecomp_284 AND
    	NOT SFDecomp_283 AND NOT SFDecomp_294 AND NOT SFDecomp_293 AND
    	NOT Mcompar__n0096_ANEB3 AND NOT Mcompar__n0096_ANEB2);

    SFDecomp_15 <= ((counter(0) AND NOT mevent_count(0))
    	OR (NOT counter(0) AND mevent_count(0)));

    FDCPE_mevent_count0: FDCPE port map (mevent_count(0),db_in(0),clk,reset,'0',mevent_count_CE(0));
    mevent_count_CE(0) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_164 <= (counter(1) AND NOT mevent_count(1));

    FDCPE_mevent_count1: FDCPE port map (mevent_count(1),db_in(1),clk,reset,'0',mevent_count_CE(1));
    mevent_count_CE(1) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_163 <= (NOT counter(1) AND mevent_count(1));

    SFDecomp_174 <= (counter(15) AND NOT mevent_count(15));

    FDCPE_mevent_count15: FDCPE port map (mevent_count(15),db_in(15),clk,reset,'0',mevent_count_CE(15));
    mevent_count_CE(15) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_173 <= (NOT counter(15) AND mevent_count(15));

    SFDecomp_184 <= (counter(2) AND NOT mevent_count(2));

    FDCPE_mevent_count2: FDCPE port map (mevent_count(2),db_in(2),clk,reset,'0',mevent_count_CE(2));
    mevent_count_CE(2) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_183 <= (NOT counter(2) AND mevent_count(2));

    SFDecomp_193 <= (counter(14) AND NOT mevent_count(14));

    FDCPE_mevent_count14: FDCPE port map (mevent_count(14),db_in(14),clk,reset,'0',mevent_count_CE(14));
    mevent_count_CE(14) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_194 <= (NOT counter(14) AND mevent_count(14));

    SFDecomp_203 <= (counter(4) AND NOT mevent_count(4));

    FDCPE_mevent_count4: FDCPE port map (mevent_count(4),db_in(4),clk,reset,'0',mevent_count_CE(4));
    mevent_count_CE(4) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_204 <= (NOT counter(4) AND mevent_count(4));

    SFDecomp_215 <= (counter(12) AND NOT mevent_count(12));

    FDCPE_mevent_count12: FDCPE port map (mevent_count(12),db_in(12),clk,reset,'0',mevent_count_CE(12));
    mevent_count_CE(12) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_216 <= (NOT counter(12) AND mevent_count(12));

    SFDecomp_224 <= (counter(6) AND NOT mevent_count(6));

    FDCPE_mevent_count6: FDCPE port map (mevent_count(6),db_in(6),clk,reset,'0',mevent_count_CE(6));
    mevent_count_CE(6) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_223 <= (NOT counter(6) AND mevent_count(6));

    SFDecomp_234 <= (counter(5) AND NOT mevent_count(5));

    FDCPE_mevent_count5: FDCPE port map (mevent_count(5),db_in(5),clk,reset,'0',mevent_count_CE(5));
    mevent_count_CE(5) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_233 <= (NOT counter(5) AND mevent_count(5));

    SFDecomp_244 <= (counter(3) AND NOT mevent_count(3));

    FDCPE_mevent_count3: FDCPE port map (mevent_count(3),db_in(3),clk,reset,'0',mevent_count_CE(3));
    mevent_count_CE(3) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_243 <= (NOT counter(3) AND mevent_count(3));

    SFDecomp_253 <= (counter(13) AND NOT mevent_count(13));

    FDCPE_mevent_count13: FDCPE port map (mevent_count(13),db_in(13),clk,reset,'0',mevent_count_CE(13));
    mevent_count_CE(13) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_254 <= (NOT counter(13) AND mevent_count(13));

    SFDecomp_264 <= (counter(8) AND NOT mevent_count(8));

    FDCPE_mevent_count8: FDCPE port map (mevent_count(8),db_in(8),clk,reset,'0',mevent_count_CE(8));
    mevent_count_CE(8) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_263 <= (NOT counter(8) AND mevent_count(8));

    SFDecomp_274 <= (counter(7) AND NOT mevent_count(7));

    FDCPE_mevent_count7: FDCPE port map (mevent_count(7),db_in(7),clk,reset,'0',mevent_count_CE(7));
    mevent_count_CE(7) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_273 <= (NOT counter(7) AND mevent_count(7));

    SFDecomp_284 <= (counter(10) AND NOT mevent_count(10));

    FDCPE_mevent_count10: FDCPE port map (mevent_count(10),db_in(10),clk,reset,'0',mevent_count_CE(10));
    mevent_count_CE(10) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_283 <= (NOT counter(10) AND mevent_count(10));

    SFDecomp_294 <= (counter(9) AND NOT mevent_count(9));

    FDCPE_mevent_count9: FDCPE port map (mevent_count(9),db_in(9),clk,reset,'0',mevent_count_CE(9));
    mevent_count_CE(9) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    SFDecomp_293 <= (NOT counter(9) AND mevent_count(9));

    Mcompar__n0096_ANEB3 <= (counter(11) AND NOT mevent_count(11));

    FDCPE_mevent_count11: FDCPE port map (mevent_count(11),db_in(11),clk,reset,'0',mevent_count_CE(11));
    mevent_count_CE(11) <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    Mcompar__n0096_ANEB2 <= (NOT counter(11) AND mevent_count(11));

    FDCPE_ena_fill_mem: FDCPE port map (ena_fill_mem,db_in(4),clk,reset,'0',ena_fill_mem_CE);
    ena_fill_mem_CE <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND NOT add(1) AND NOT mem_done);

    db_out(0) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(0))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(0))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	NOT add(1) AND mword_count(16))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(0))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(0))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	add(1) AND mem_pointer_p(16))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_mem_fifo_p));

    FDCPE_mem_pointer_p0: FDCPE port map (mem_pointer_p(0),mem_pointer_p_D(0),clk,reset,'0','1');
    mem_pointer_p_D(0) <= ((db_in(0) AND _n0111)
    	OR (N_PZ_1161 AND mem_pointer_p(0) AND NOT N_PZ_1138)
    	OR (NOT N_PZ_1265 AND mem_pointer_p(0) AND NOT N_PZ_1138)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT mem_pointer_p(0) AND
    	NOT N_PZ_1138)
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND add(1) AND NOT db_in(2) AND mem_pointer_p(0)));

    _n0111 <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	enw AND cs AND NOT add(1));

    N_PZ_1138 <= ((_n0111)
    	OR (NOT state_FFD2 AND state_FFD1 AND NOT state_FFD3)
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND add(1)));

    FDCPE_mem_pointer_p16: FDCPE port map (mem_pointer_p(16),mem_pointer_p_D(16),clk,reset,'0','1');
    mem_pointer_p_D(16) <= NOT (((NOT _n0111 AND N_PZ_1138 AND NOT SFDecomp_73)
    	OR (NOT SFDecomp_73 AND NOT N_PZ_1215 AND NOT mem_pointer_p(16))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT mem_pointer_p(0) AND
    	NOT _n0111 AND NOT SFDecomp_73 AND NOT mem_pointer_p(3) AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND mem_pointer_p(10) AND
    	mem_pointer_p(11) AND mem_pointer_p(12) AND mem_pointer_p(13) AND
    	mem_pointer_p(14) AND mem_pointer_p(15) AND mem_pointer_p(16))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT _n0111 AND NOT SFDecomp_73 AND
    	NOT mem_pointer_p(1) AND NOT mem_pointer_p(3) AND mem_pointer_p(8) AND N_PZ_1156 AND
    	mem_pointer_p(9) AND mem_pointer_p(10) AND mem_pointer_p(11) AND
    	mem_pointer_p(12) AND mem_pointer_p(13) AND mem_pointer_p(14) AND
    	mem_pointer_p(15) AND mem_pointer_p(16))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT _n0111 AND NOT SFDecomp_73 AND
    	NOT mem_pointer_p(2) AND NOT mem_pointer_p(3) AND mem_pointer_p(8) AND N_PZ_1156 AND
    	mem_pointer_p(9) AND mem_pointer_p(10) AND mem_pointer_p(11) AND
    	mem_pointer_p(12) AND mem_pointer_p(13) AND mem_pointer_p(14) AND
    	mem_pointer_p(15) AND mem_pointer_p(16))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT _n0111 AND NOT SFDecomp_73 AND mem_pointer_p(1) AND
    	mem_pointer_p(2) AND mem_pointer_p(3) AND mem_pointer_p(8) AND N_PZ_1156 AND
    	mem_pointer_p(9) AND mem_pointer_p(10) AND mem_pointer_p(11) AND
    	mem_pointer_p(12) AND mem_pointer_p(13) AND mem_pointer_p(14) AND
    	mem_pointer_p(15) AND mem_pointer_p(16))));

    SFDecomp_73 <= (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND add(1) AND db_in(0) AND NOT db_in(2));

    FDCPE_mem_pointer_p1: FDCPE port map (mem_pointer_p(1),mem_pointer_p_D(1),clk,reset,'0','1');
    mem_pointer_p_D(1) <= ((db_in(1) AND _n0111)
    	OR (N_PZ_1161 AND NOT N_PZ_1138 AND mem_pointer_p(1))
    	OR (NOT N_PZ_1265 AND NOT N_PZ_1138 AND mem_pointer_p(1))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND NOT mem_pointer_p(1))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND add(1) AND NOT db_in(2) AND mem_pointer_p(1)));

    FDCPE_mem_pointer_p2: FDCPE port map (mem_pointer_p(2),mem_pointer_p_D(2),clk,reset,'0','1');
    mem_pointer_p_D(2) <= ((db_in(2) AND _n0111)
    	OR (N_PZ_1161 AND NOT N_PZ_1138 AND mem_pointer_p(2))
    	OR (NOT N_PZ_1265 AND NOT N_PZ_1138 AND mem_pointer_p(2))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(2))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(1) AND mem_pointer_p(2))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1) AND NOT mem_pointer_p(2))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND add(1) AND NOT db_in(2) AND mem_pointer_p(2)));

    FDCPE_mem_pointer_p3: FDCPE port map (mem_pointer_p(3),mem_pointer_p_D(3),clk,reset,'0','1');
    mem_pointer_p_D(3) <= ((db_in(3) AND _n0111)
    	OR (N_PZ_1161 AND NOT N_PZ_1138 AND mem_pointer_p(3))
    	OR (NOT N_PZ_1265 AND NOT N_PZ_1138 AND mem_pointer_p(3))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(3))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(1) AND mem_pointer_p(3))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(2) AND mem_pointer_p(3))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1) AND mem_pointer_p(2) AND
    	NOT mem_pointer_p(3))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND add(1) AND NOT db_in(2) AND mem_pointer_p(3)));

    FDCPE_mem_pointer_p8: FDCPE port map (mem_pointer_p(8),mem_pointer_p_D(8),clk,reset,'0','1');
    mem_pointer_p_D(8) <= ((db_in(8) AND _n0111)
    	OR (mem_pointer_p(8) AND N_PZ_1252)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND NOT N_PZ_1156)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(8) AND N_PZ_1156));

    N_PZ_1156 <= ((N_PZ_1161 AND mem_pointer_p(5) AND mem_pointer_p(6) AND
    	mem_pointer_p(7))
    	OR (NOT N_PZ_1265 AND mem_pointer_p(5) AND mem_pointer_p(6) AND
    	mem_pointer_p(7))
    	OR (N_PZ_1138 AND mem_pointer_p(5) AND mem_pointer_p(6) AND
    	mem_pointer_p(7))
    	OR (mem_pointer_p(0) AND mem_pointer_p(1) AND
    	mem_pointer_p(2) AND mem_pointer_p(3) AND mem_pointer_p(4) AND
    	mem_pointer_p(5) AND mem_pointer_p(6) AND mem_pointer_p(7)));

    FDCPE_mem_pointer_p4: FDCPE port map (mem_pointer_p(4),mem_pointer_p_D(4),clk,reset,'0','1');
    mem_pointer_p_D(4) <= ((db_in(4) AND _n0111)
    	OR (mem_pointer_p(4) AND N_PZ_1252)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(3) AND mem_pointer_p(4))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1) AND mem_pointer_p(2) AND
    	mem_pointer_p(3) AND NOT mem_pointer_p(4)));

    N_PZ_1252 <= ((N_PZ_1161 AND NOT N_PZ_1138)
    	OR (NOT N_PZ_1265 AND NOT N_PZ_1138)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(3))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(1) AND mem_pointer_p(3))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(2) AND mem_pointer_p(3))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1) AND mem_pointer_p(2) AND
    	NOT mem_pointer_p(3))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	enw AND cs AND add(1) AND NOT db_in(2)));

    FDCPE_mem_pointer_p5: FDCPE port map (mem_pointer_p(5),mem_pointer_p_D(5),clk,reset,'0','1');
    mem_pointer_p_D(5) <= ((db_in(5) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(5))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(3) AND mem_pointer_p(5))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(4) AND mem_pointer_p(5))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1) AND mem_pointer_p(2) AND
    	mem_pointer_p(3) AND mem_pointer_p(4) AND NOT mem_pointer_p(5)));

    FDCPE_mem_pointer_p6: FDCPE port map (mem_pointer_p(6),mem_pointer_p_D(6),clk,reset,'0','1');
    mem_pointer_p_D(6) <= ((db_in(6) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(6))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(3) AND mem_pointer_p(6))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(4) AND mem_pointer_p(6))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(5) AND mem_pointer_p(6))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1) AND mem_pointer_p(2) AND
    	mem_pointer_p(3) AND mem_pointer_p(4) AND mem_pointer_p(5) AND
    	NOT mem_pointer_p(6)));

    FDCPE_mem_pointer_p7: FDCPE port map (mem_pointer_p(7),mem_pointer_p_D(7),clk,reset,'0','1');
    mem_pointer_p_D(7) <= ((db_in(7) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(7))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND NOT N_PZ_1156 AND
    	mem_pointer_p(7))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT N_PZ_1138 AND mem_pointer_p(1) AND mem_pointer_p(2) AND
    	mem_pointer_p(3) AND NOT N_PZ_1156 AND mem_pointer_p(4) AND mem_pointer_p(5) AND
    	mem_pointer_p(6)));

    FDCPE_mem_pointer_p9: FDCPE port map (mem_pointer_p(9),mem_pointer_p_D(9),clk,reset,'0','1');
    mem_pointer_p_D(9) <= ((db_in(9) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(9))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(8) AND mem_pointer_p(9))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND NOT N_PZ_1156 AND
    	mem_pointer_p(9))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND NOT mem_pointer_p(9)));

    FDCPE_mem_pointer_p10: FDCPE port map (mem_pointer_p(10),mem_pointer_p_D(10),clk,reset,'0','1');
    mem_pointer_p_D(10) <= ((db_in(10) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(10))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(8) AND mem_pointer_p(10))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND NOT N_PZ_1156 AND
    	mem_pointer_p(10))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(9) AND mem_pointer_p(10))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND NOT mem_pointer_p(10)));

    FDCPE_mem_pointer_p11: FDCPE port map (mem_pointer_p(11),mem_pointer_p_D(11),clk,reset,'0','1');
    mem_pointer_p_D(11) <= ((db_in(11) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(11))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(8) AND mem_pointer_p(11))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND NOT N_PZ_1156 AND
    	mem_pointer_p(11))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(9) AND mem_pointer_p(11))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(10) AND mem_pointer_p(11))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND mem_pointer_p(10) AND
    	NOT mem_pointer_p(11)));

    FDCPE_mem_pointer_p12: FDCPE port map (mem_pointer_p(12),mem_pointer_p_D(12),clk,reset,'0','1');
    mem_pointer_p_D(12) <= ((db_in(12) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(12))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(8) AND mem_pointer_p(12))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND NOT N_PZ_1156 AND
    	mem_pointer_p(12))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(9) AND mem_pointer_p(12))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(10) AND mem_pointer_p(12))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(11) AND mem_pointer_p(12))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND mem_pointer_p(10) AND
    	mem_pointer_p(11) AND NOT mem_pointer_p(12)));

    FDCPE_mem_pointer_p13: FDCPE port map (mem_pointer_p(13),mem_pointer_p_D(13),clk,reset,'0','1');
    mem_pointer_p_D(13) <= ((db_in(13) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(13))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(8) AND mem_pointer_p(13))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND NOT N_PZ_1156 AND
    	mem_pointer_p(13))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(9) AND mem_pointer_p(13))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(10) AND mem_pointer_p(13))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(11) AND mem_pointer_p(13))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(12) AND mem_pointer_p(13))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND mem_pointer_p(10) AND
    	mem_pointer_p(11) AND mem_pointer_p(12) AND NOT mem_pointer_p(13)));

    FDCPE_mem_pointer_p14: FDCPE port map (mem_pointer_p(14),mem_pointer_p_D(14),clk,reset,'0','1');
    mem_pointer_p_D(14) <= ((db_in(14) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(8) AND mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND NOT N_PZ_1156 AND
    	mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(9) AND mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(10) AND mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(11) AND mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(12) AND mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	NOT mem_pointer_p(13) AND mem_pointer_p(14))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND mem_pointer_p(10) AND
    	mem_pointer_p(11) AND mem_pointer_p(12) AND mem_pointer_p(13) AND
    	NOT mem_pointer_p(14)));

    FDCPE_mem_pointer_p15: FDCPE port map (mem_pointer_p(15),mem_pointer_p_D(15),clk,reset,'0','1');
    mem_pointer_p_D(15) <= ((db_in(15) AND _n0111)
    	OR (N_PZ_1252 AND mem_pointer_p(15))
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(15) AND NOT N_PZ_1215)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND mem_pointer_p(10) AND
    	mem_pointer_p(11) AND mem_pointer_p(12) AND mem_pointer_p(13) AND
    	mem_pointer_p(14) AND NOT N_PZ_1215));

    N_PZ_1215 <= (NOT N_PZ_1161 AND N_PZ_1265 AND NOT N_PZ_1138 AND
    	mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND mem_pointer_p(10) AND
    	mem_pointer_p(11) AND mem_pointer_p(12) AND mem_pointer_p(13) AND
    	mem_pointer_p(14) AND mem_pointer_p(15));

    db_out(10) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(10))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(10))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(10))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(10))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_lfsr(3)));

    db_out(11) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(11))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(11))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(11))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(11)));

    db_out(12) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(12))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(12))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(12))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(12)));

    db_out(13) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(13))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(13))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(13))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(13)));

    db_out(14) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(14))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(14))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(14))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(14)));

    db_out(15) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(15))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(15))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(15))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(15)));

    db_out(1) <= ((ena_fifo_mem_p AND NOT add(5) AND NOT add(4) AND NOT add(3) AND
    	NOT add(2) AND NOT add(0) AND NOT add(1))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(1))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(1))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	NOT add(1) AND mword_count(17))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(1))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(1))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	add(1) AND mem_pointer_p(17)));

    FDCPE_mem_pointer_p17: FDCPE port map (mem_pointer_p(17),mem_pointer_p_D(17),clk,reset,'0','1');
    mem_pointer_p_D(17) <= NOT (((NOT _n0111 AND N_PZ_1138 AND NOT SFDecomp_79)
    	OR (NOT N_PZ_1215 AND NOT mem_pointer_p(17) AND NOT SFDecomp_79)
    	OR (NOT mem_pointer_p(16) AND NOT mem_pointer_p(17) AND
    	NOT SFDecomp_79)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT mem_pointer_p(0) AND
    	NOT _n0111 AND NOT mem_pointer_p(3) AND mem_pointer_p(8) AND N_PZ_1156 AND
    	mem_pointer_p(9) AND mem_pointer_p(10) AND mem_pointer_p(11) AND
    	mem_pointer_p(12) AND mem_pointer_p(13) AND mem_pointer_p(14) AND
    	mem_pointer_p(15) AND mem_pointer_p(16) AND mem_pointer_p(17) AND
    	NOT SFDecomp_79)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT _n0111 AND
    	NOT mem_pointer_p(1) AND NOT mem_pointer_p(3) AND mem_pointer_p(8) AND N_PZ_1156 AND
    	mem_pointer_p(9) AND mem_pointer_p(10) AND mem_pointer_p(11) AND
    	mem_pointer_p(12) AND mem_pointer_p(13) AND mem_pointer_p(14) AND
    	mem_pointer_p(15) AND mem_pointer_p(16) AND mem_pointer_p(17) AND
    	NOT SFDecomp_79)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND NOT _n0111 AND
    	NOT mem_pointer_p(2) AND NOT mem_pointer_p(3) AND mem_pointer_p(8) AND N_PZ_1156 AND
    	mem_pointer_p(9) AND mem_pointer_p(10) AND mem_pointer_p(11) AND
    	mem_pointer_p(12) AND mem_pointer_p(13) AND mem_pointer_p(14) AND
    	mem_pointer_p(15) AND mem_pointer_p(16) AND mem_pointer_p(17) AND
    	NOT SFDecomp_79)
    	OR (NOT N_PZ_1161 AND N_PZ_1265 AND mem_pointer_p(0) AND
    	NOT _n0111 AND mem_pointer_p(1) AND mem_pointer_p(2) AND
    	mem_pointer_p(3) AND mem_pointer_p(8) AND N_PZ_1156 AND mem_pointer_p(9) AND
    	mem_pointer_p(10) AND mem_pointer_p(11) AND mem_pointer_p(12) AND
    	mem_pointer_p(13) AND mem_pointer_p(14) AND mem_pointer_p(15) AND
    	mem_pointer_p(16) AND mem_pointer_p(17) AND NOT SFDecomp_79)));

    SFDecomp_79 <= (db_in(1) AND NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND
    	NOT add(0) AND enw AND cs AND add(1) AND NOT db_in(2));

    db_out(2) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(2))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(2))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(2))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(2))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_word_count));

    db_out(3) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(3))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(3))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(3))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(3))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_event_count));

    db_out(4) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(4))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(4))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(4))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(4))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_fill_mem));

    db_out(5) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(5))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(5))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(5))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(5))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_cycles));

    db_out(6) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(6))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(6))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(6))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(6))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_random));

    db_out(7) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(7))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(7))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(7))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(7))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_lfsr(0)));

    db_out(8) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(8))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(8))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(8))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(8))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_lfsr(1)));

    db_out(9) <= ((NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND add(0) AND
    	NOT add(1) AND mevent_count(9))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND add(2) AND NOT add(0) AND
    	add(1) AND num_cycles(9))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	add(1) AND mword_count(9))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND add(0) AND
    	NOT add(1) AND mem_pointer_p(9))
    	OR (NOT add(5) AND NOT add(4) AND NOT add(3) AND NOT add(2) AND NOT add(0) AND
    	NOT add(1) AND ena_lfsr(2)));

    mem_done_p <= NOT ((NOT N_PZ_1161 AND NOT mem_done2));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FDDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     FTDCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ****************************  Device Pin Out ****************************

    Device : XC2C512-7-PQ208

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 VCC                             105 VCCIO-UNUSED
      2 db_in<9>                        106 KPR
      3 db_in<8>                        107 KPR
      4 db_in<7>                        108 KPR
      5 db_in<4>                        109 KPR
      6 db_in<3>                        110 KPR
      7 db_in<5>                        111 KPR
      8 db_in<6>                        112 KPR
      9 db_in<2>                        113 KPR
     10 db_in<0>                        114 KPR
     11 VCCAUX                          115 KPR
     12 db_in<11>                       116 KPR
     13 GND                             117 KPR
     14 add<4>                          118 KPR
     15 add<5>                          119 KPR
     16 cs                              120 KPR
     17 enw                             121 KPR
     18 KPR                             122 KPR
     19 mem_pointer_p<17>               123 KPR
     20 mem_pointer_p<16>               124 VCC
     21 mem_pointer_p<15>               125 KPR
     22 KPR                             126 KPR
     23 KPR                             127 KPR
     24 GND                             128 KPR
     25 KPR                             129 GND
     26 VCCIO-1.8                       130 GND
     27 add<3>                          131 KPR
     28 db_out<9>                       132 VCCIO-UNUSED
     29 db_out<8>                       133 VCCIO-1.8
     30 db_out<7>                       134 KPR
     31 db_out<6>                       135 KPR
     32 db_out<10>                      136 KPR
     33 VCCIO-1.8                       137 KPR
     34 db_out<15>                      138 KPR
     35 db_out<14>                      139 KPR
     36 db_out<13>                      140 KPR
     37 db_out<0>                       141 GND
     38 mem_pointer_p<10>               142 KPR
     39 mem_pointer_p<9>                143 KPR
     40 mem_pointer_p<8>                144 KPR
     41 mem_pointer_p<4>                145 KPR
     42 GND                             146 KPR
     43 mem_pointer_p<5>                147 KPR
     44 mem_pointer_p<6>                148 KPR
     45 mem_pointer_p<7>                149 KPR
     46 clk                             150 KPR
     47 KPR                             151 KPR
     48 KPR                             152 KPR
     49 KPR                             153 KPR
     50 txena_out_p                     154 KPR
     51 mem_pointer_p<2>                155 KPR
     52 GND                             156 GND
     53 VCC                             157 VCCIO-1.8
     54 mem_pointer_p<1>                158 KPR
     55 mem_pointer_p<0>                159 KPR
     56 ena_fifo_mem_p                  160 acc_fifo_p
     57 ena_mem_fifo_p                  161 txena_in
     58 add<0>                          162 KPR
     59 VCCIO-1.8                       163 KPR
     60 mem_pointer_p<14>               164 KPR
     61 mem_pointer_p<13>               165 KPR
     62 mem_pointer_p<12>               166 KPR
     63 mem_pointer_p<11>               167 KPR
     64 db_out<11>                      168 KPR
     65 db_out<12>                      169 KPR
     66 add<1>                          170 mem_done_p
     67 add<2>                          171 KPR
     68 GND                             172 VCCIO-1.8
     69 db_out<1>                       173 KPR
     70 db_out<2>                       174 KPR
     71 db_out<3>                       175 KPR
     72 db_out<4>                       176 TDO
     73 db_out<5>                       177 GND
     74 is_trigger                      178 KPR
     75 KPR                             179 KPR
     76 KPR                             180 KPR
     77 KPR                             181 VCCIO-1.8
     78 KPR                             182 KPR
     79 VCCIO-1.8                       183 KPR
     80 KPR                             184 KPR
     81 GND                             185 KPR
     82 KPR                             186 KPR
     83 KPR                             187 KPR
     84 KPR                             188 KPR
     85 KPR                             189 KPR
     86 KPR                             190 GND
     87 KPR                             191 KPR
     88 KPR                             192 KPR
     89 KPR                             193 KPR
     90 KPR                             194 KPR
     91 KPR                             195 KPR
     92 VCCIO-UNUSED                    196 KPR
     93 GND                             197 KPR
     94 TDI                             198 KPR
     95 KPR                             199 mem_pointer_p<3>
     96 TMS                             200 db_in<1>
     97 KPR                             201 db_in<15>
     98 TCK                             202 db_in<14>
     99 KPR                             203 db_in<13>
    100 KPR                             204 VCCIO-1.8
    101 KPR                             205 db_in<12>
    102 KPR                             206 reset
    103 KPR                             207 GND
    104 GND                             208 db_in<10>

    Legend :  NC  = Not Connected, unbonded pin
            PGND  = Unused I/O configured as additional Ground pin
             KPR  = Unused I/O with weak keeper (leave unconnected)
             WPU  = Unused I/O with weak pull up (leave unconnected)
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
          VCCAUX  = Power supply for JTAG pins
       VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
       VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
       VCCIO-1.8  = I/O supply voltage for LVCMOS18
       VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
            VREF  = Reference voltage for indicated input standard
           *VREF  = Reference voltage pin selected by software
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc2c512-7-PQ208
    Optimization Method                         : DENSITY
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Set Unused I/O Pin Termination              : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Enable Input Registers                      : ON
    Function Block Fan-in Limit                 : 38
    Use DATA_GATE Attribute                     : ON
    Set Tristate Outputs to Termination Mode    : FLOAT
    Default Voltage Standard for All Outputs    : LVCMOS18
    Input Limit                                 : 32
    Pterm Limit                                 : 28