library ieee;
use ieee.std_logic_1164.all;

entity rm_vmeifc is
     port (
     ds0, ds1, dsdly0, dsdly1, iack,lword: in std_logic;
     write, brdsel24: in std_logic;
     am: in std_logic_vector (5 downto 0);
     we, dtack, g245, oe: out std_logic 
     );
end rm_vmeifc;

architecture arch of rm_vmeifc is
component ffrp port (
     d, clk, ce, cr, pr: in std_logic;
     q: out std_logic);
end component;

--signal q1, q2, aux_dtack: std_logic;
signal q2, aux_dtack: std_logic;
signal acc, accw, accr, amd: std_logic;
signal ds, one, zero: std_logic; 

signal dsrst: std_logic; --LINCO ago07

begin
one <= '1';
zero <= '0';
ds <= not (ds0 or ds1);
--dsrst <= ds0 or ds1;

-- A24, standard non-prileged data access, mod=$39
amd <= '1' when am="111001" else '0'; 
acc <= not brdsel24 and iack and amd and lword;--ds; LINCO agos07
accr <= acc and write;	--activo high
accw <= acc and not write;  --activo high


--aux_dtack <= dsdly1 and acc; LINCO ago07
--
we    <= not(q2); --active low
--dtack <= q2 or q1;        --active high
g245  <= not(ds and acc); --active low
-- OCT 06oe    <= not(q1);      --active low
oe <= not(ds and accr);
-- OCT 06 deberķa poner oe <= not(ds and accr); para que dure igual que el g245


--fq1:  ffrp port map (clk => dsdly0, d => accr, ce => one, cr => dsdly1, pr => zero, q => q1);
fq2:  ffrp port map (clk => dsdly0, d => accw, ce => one, cr => dsdly1, pr => zero, q => q2);

--LINCO ago07
--fq3:  ffrp port map (clk => aux_dtack, d => one, ce => one, cr => not(dsdly1), pr => zero, q => dtack);
fq3:  ffrp port map (clk => dsdly1, d => acc, ce => one, cr => dsrst, pr => zero, q => dtack);

--enero 09 dsrst <= not (ds0 and ds1 and (not(dsdly1))); --LINCO ago07
dsrst <= (ds0 and ds1 and (not(dsdly1))); --LINCO ago07
    
  
end arch;
	
