### Equations

madd(0) <= NOT (((NOT mem_pointer(0) AND acc_fifo) OR (NOT acc_fifo AND NOT add(0) AND NOT acc_blk) OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0)) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(0) AND NOT add_aux(0))));
FTCPE_va_cnt0: FTCPE port map (va_cnt(0),'0',inc_add,as,'0','1');
FDCPE_add_aux0: FDCPE port map (add_aux(0),add(0),NOT as,'0','0','1');
madd(10) <= NOT (((acc_fifo AND NOT mem_pointer(10)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(10)) OR (NOT acc_fifo AND acc_blk AND N_PZ_203 AND N_PZ_265) OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_203 AND NOT N_PZ_265)));
N_PZ_203 <= ((NOT va_cnt(9) AND N_PZ_266) OR (NOT va_cnt(8) AND NOT N_PZ_266 AND N_PZ_189) OR (NOT N_PZ_266 AND NOT N_PZ_189 AND N_PZ_276));
FTCPE_va_cnt9: FTCPE port map (va_cnt(9),va_cnt_T(9),inc_add,as,'0','1'); va_cnt_T(9) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND va_cnt(8));
FTCPE_va_cnt1: FTCPE port map (va_cnt(1),va_cnt(0),inc_add,as,'0','1');
FTCPE_va_cnt2: FTCPE port map (va_cnt(2),va_cnt_T(2),inc_add,as,'0','1'); va_cnt_T(2) <= (va_cnt(0) AND va_cnt(1));
FTCPE_va_cnt3: FTCPE port map (va_cnt(3),va_cnt_T(3),inc_add,as,'0','1'); va_cnt_T(3) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2));
FTCPE_va_cnt4: FTCPE port map (va_cnt(4),va_cnt_T(4),inc_add,as,'0','1'); va_cnt_T(4) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3));
FTCPE_va_cnt5: FTCPE port map (va_cnt(5),va_cnt_T(5),inc_add,as,'0','1'); va_cnt_T(5) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4));
FTCPE_va_cnt6: FTCPE port map (va_cnt(6),va_cnt_T(6),inc_add,as,'0','1'); va_cnt_T(6) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4) AND va_cnt(5));
FTCPE_va_cnt7: FTCPE port map (va_cnt(7),va_cnt_T(7),inc_add,as,'0','1'); va_cnt_T(7) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6));
FTCPE_va_cnt8: FTCPE port map (va_cnt(8),va_cnt_T(8),inc_add,as,'0','1'); va_cnt_T(8) <= (va_cnt(0) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7));
N_PZ_266 <= add_aux(9) XOR ((va_cnt(8) AND N_PZ_189) OR (NOT N_PZ_189 AND NOT N_PZ_276));
FDCPE_add_aux9: FDCPE port map (add_aux(9),add(9),NOT as,'0','0','1');
N_PZ_189 <= ((va_cnt(8) AND add_aux(8)) OR (NOT va_cnt(8) AND NOT add_aux(8)));
FDCPE_add_aux8: FDCPE port map (add_aux(8),add(8),NOT as,'0','0','1');
N_PZ_276 <= ((NOT va_cnt(7) AND NOT add_aux(7)) OR (NOT va_cnt(7) AND Madd__n0003_CARRY_IN(7)) OR (NOT add_aux(7) AND Madd__n0003_CARRY_IN(7)));
FDCPE_add_aux7: FDCPE port map (add_aux(7),add(7),NOT as,'0','0','1');
Madd__n0003_CARRY_IN(7) <= ((NOT va_cnt(6) AND NOT add_aux(6)) OR (va_cnt(6) AND NOT add_aux(6) AND N_PZ_273) OR (NOT va_cnt(6) AND add_aux(6) AND N_PZ_273));
FDCPE_add_aux6: FDCPE port map (add_aux(6),add(6),NOT as,'0','0','1');
N_PZ_273 <= ((NOT va_cnt(5) AND NOT add_aux(5)) OR (NOT va_cnt(5) AND Madd__n0003_CARRY_IN(5)) OR (NOT add_aux(5) AND Madd__n0003_CARRY_IN(5)));
FDCPE_add_aux5: FDCPE port map (add_aux(5),add(5),NOT as,'0','0','1');
Madd__n0003_CARRY_IN(5) <= ((NOT va_cnt(4) AND NOT add_aux(4)) OR (va_cnt(4) AND NOT add_aux(4) AND N_PZ_275) OR (NOT va_cnt(4) AND add_aux(4) AND N_PZ_275));
FDCPE_add_aux4: FDCPE port map (add_aux(4),add(4),NOT as,'0','0','1');
N_PZ_275 <= ((NOT va_cnt(3) AND NOT add_aux(3)) OR (NOT va_cnt(3) AND NOT Madd__n0003_CARRY_IN(3)) OR (NOT add_aux(3) AND NOT Madd__n0003_CARRY_IN(3)));
FDCPE_add_aux3: FDCPE port map (add_aux(3),add(3),NOT as,'0','0','1');
Madd__n0003_CARRY_IN(3) <= ((va_cnt(2) AND N_PZ_184) OR (va_cnt(1) AND NOT N_PZ_184 AND add_aux(1)) OR (va_cnt(0) AND add_aux(0) AND va_cnt(1) AND NOT N_PZ_184) OR (va_cnt(0) AND add_aux(0) AND NOT N_PZ_184 AND add_aux(1)));
N_PZ_184 <= ((va_cnt(2) AND add_aux(2)) OR (NOT va_cnt(2) AND NOT add_aux(2)));
FDCPE_add_aux2: FDCPE port map (add_aux(2),add(2),NOT as,'0','0','1');
FDCPE_add_aux1: FDCPE port map (add_aux(1),add(1),NOT as,'0','0','1');
N_PZ_265 <= ((add_aux(10) AND va_cnt(10)) OR (NOT add_aux(10) AND NOT va_cnt(10)));
FDCPE_add_aux10: FDCPE port map (add_aux(10),add(10),NOT as,'0','0','1');
FTCPE_va_cnt10: FTCPE port map (va_cnt(10),va_cnt_T(10),inc_add,as,'0','1'); va_cnt_T(10) <= (va_cnt(0) AND va_cnt(9) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND va_cnt(8));
madd(11) <= NOT (((acc_fifo AND NOT mem_pointer(11)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(11)) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(11) AND NOT N_PZ_283) OR (NOT acc_fifo AND acc_blk AND N_PZ_283 AND NOT N_PZ_255)));
FTCPE_va_cnt11: FTCPE port map (va_cnt(11),va_cnt_T(11),inc_add,as,'0','1'); va_cnt_T(11) <= (va_cnt(0) AND va_cnt(9) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND va_cnt(8) AND va_cnt(10));
N_PZ_283 <= add_aux(11) XOR ((NOT N_PZ_203 AND NOT N_PZ_265) OR (N_PZ_265 AND va_cnt(10)));
FDCPE_add_aux11: FDCPE port map (add_aux(11),add(11),NOT as,'0','0','1');
N_PZ_255 <= ((NOT va_cnt(11) AND N_PZ_283) OR (N_PZ_203 AND NOT N_PZ_265 AND NOT N_PZ_283) OR (N_PZ_265 AND NOT va_cnt(10) AND NOT N_PZ_283));
madd(12) <= NOT ((NOT acc_fifo AND acc_blk AND NOT N_PZ_193) XOR ((acc_fifo AND NOT mem_pointer(12)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(12)) OR (NOT acc_fifo AND acc_blk AND N_PZ_255 AND N_PZ_193 AND NOT add_aux(12) AND NOT va_cnt(12))
OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_255 AND NOT N_PZ_193 AND
add_aux(12) AND va_cnt(12))));
N_PZ_193 <= ((N_PZ_255 AND NOT add_aux(12)) OR (N_PZ_255 AND NOT va_cnt(12)) OR (NOT add_aux(12) AND NOT va_cnt(12)));
FDCPE_add_aux12: FDCPE port map (add_aux(12),add(12),NOT as,'0','0','1');
FTCPE_va_cnt12: FTCPE port map (va_cnt(12),va_cnt_T(12),inc_add,as,'0','1'); va_cnt_T(12) <= (va_cnt(0) AND va_cnt(9) AND va_cnt(1) AND va_cnt(2) AND va_cnt(3) AND va_cnt(4) AND va_cnt(5) AND va_cnt(6) AND va_cnt(7) AND va_cnt(8) AND va_cnt(10) AND va_cnt(11));
madd(13) <= NOT (((acc_fifo AND NOT mem_pointer(13)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(13)) OR (NOT acc_fifo AND acc_blk AND N_PZ_193 AND NOT add_aux(13)) OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_193 AND add_aux(13))));
FDCPE_add_aux13: FDCPE port map (add_aux(13),add(13),NOT as,'0','0','1');
madd(14) <= ((acc_fifo AND mem_pointer(14)) OR (NOT acc_fifo AND NOT acc_blk AND add(14)) OR (NOT acc_fifo AND acc_blk AND add_aux(14) AND NOT N_PZ_256) OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_193 AND add_aux(13) AND NOT N_PZ_256));
FDCPE_add_aux14: FDCPE port map (add_aux(14),add(14),NOT as,'0','0','1');
N_PZ_256 <= (NOT N_PZ_193 AND add_aux(13) AND add_aux(14));
madd(15) <= NOT (((acc_fifo AND NOT mem_pointer(15)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(15)) OR (NOT acc_fifo AND acc_blk AND N_PZ_256 AND add_aux(15)) OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_256 AND NOT add_aux(15))));
FDCPE_add_aux15: FDCPE port map (add_aux(15),add(15),NOT as,'0','0','1');
madd(16) <= NOT ((NOT acc_fifo AND acc_blk AND NOT add_aux(16)) XOR ((acc_fifo AND NOT mem_pointer(16)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(16)) OR (NOT acc_fifo AND acc_blk AND N_PZ_256 AND add_aux(15))));
FDCPE_add_aux16: FDCPE port map (add_aux(16),add(16),NOT as,'0','0','1');
madd(17) <= NOT ((NOT acc_fifo AND acc_blk AND NOT add_aux(17)) XOR ((acc_fifo AND NOT mem_pointer(17)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(17)) OR (NOT acc_fifo AND acc_blk AND N_PZ_256 AND add_aux(15) AND add_aux(16))));
FDCPE_add_aux17: FDCPE port map (add_aux(17),add(17),NOT as,'0','0','1');
madd(1) <= NOT ((NOT acc_fifo AND acc_blk AND add_aux(1)) XOR ((acc_fifo AND NOT mem_pointer(1)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(1)) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(0) AND NOT va_cnt(1)) OR (NOT acc_fifo AND acc_blk AND NOT add_aux(0) AND NOT va_cnt(1))
OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0) AND
va_cnt(1))));
madd(2) <= NOT ((NOT acc_fifo AND acc_blk AND N_PZ_184) XOR ((acc_fifo AND NOT mem_pointer(2)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(2)) OR (NOT acc_fifo AND acc_blk AND va_cnt(1) AND add_aux(1)) OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0) AND
va_cnt(1))
OR (NOT acc_fifo AND acc_blk AND va_cnt(0) AND add_aux(0) AND
add_aux(1))));
madd(3) <= NOT ((NOT acc_fifo AND acc_blk AND Madd__n0003_CARRY_IN(3)) XOR ((acc_fifo AND NOT mem_pointer(3)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(3)) OR (NOT acc_fifo AND acc_blk AND va_cnt(3) AND add_aux(3)) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(3) AND NOT add_aux(3))));
madd(4) <= NOT ((NOT acc_fifo AND acc_blk AND add_aux(4)) XOR ((acc_fifo AND NOT mem_pointer(4)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(4)) OR (NOT acc_fifo AND acc_blk AND va_cnt(4) AND NOT N_PZ_275) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(4) AND N_PZ_275)));
madd(5) <= NOT ((NOT acc_fifo AND acc_blk AND Madd__n0003_CARRY_IN(5)) XOR ((acc_fifo AND NOT mem_pointer(5)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(5)) OR (NOT acc_fifo AND acc_blk AND va_cnt(5) AND NOT add_aux(5)) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(5) AND add_aux(5))));
madd(6) <= NOT ((NOT acc_fifo AND acc_blk AND add_aux(6)) XOR ((acc_fifo AND NOT mem_pointer(6)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(6)) OR (NOT acc_fifo AND acc_blk AND va_cnt(6) AND NOT N_PZ_273) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(6) AND N_PZ_273)));
madd(7) <= NOT ((NOT acc_fifo AND acc_blk AND Madd__n0003_CARRY_IN(7)) XOR ((acc_fifo AND NOT mem_pointer(7)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(7)) OR (NOT acc_fifo AND acc_blk AND va_cnt(7) AND NOT add_aux(7)) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(7) AND add_aux(7))));
madd(8) <= NOT (((acc_fifo AND NOT mem_pointer(8)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(8)) OR (NOT acc_fifo AND acc_blk AND N_PZ_189 AND N_PZ_276) OR (NOT acc_fifo AND acc_blk AND NOT N_PZ_189 AND NOT N_PZ_276)));
madd(9) <= NOT (((acc_fifo AND NOT mem_pointer(9)) OR (NOT acc_fifo AND NOT acc_blk AND NOT add(9)) OR (NOT acc_fifo AND acc_blk AND va_cnt(9) AND N_PZ_266) OR (NOT acc_fifo AND acc_blk AND NOT va_cnt(9) AND NOT N_PZ_266)));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);