    cpldfit:  version G.35                              Xilinx Inc.
                                      Fitter Report
    Design Name: rosmem                              Date: 12- 4-2009,  6:01PM
    Device Used: XC2C512-7-PQ208
    Fitting Status: Successful

    ****************************  Resource Summary  ****************************

    Macrocells     Product Terms    Registers      Pins           Function Block
    Used           Used             Used           Used           Inputs Used
    375/512 ( 73%) 868 /1792 ( 48%) 272/512 ( 53%) 138/173 ( 80%) 944/1280 ( 74%)

    PIN RESOURCES:

    Signal Type    Required     Mapped  |  Pin Type            Used   Remaining
    ------------------------------------|---------------------------------------
    Input         :   37          37    |  I/O              :   129       34
    Output        :   48          48    |  GCK/IO           :     3        0
    Bidirectional :   49          49    |  GTS/IO           :     4        0
    GCK           :    3           3    |  GSR/IO           :     1        0
    GTS           :    0           0    |  CDR/IO           :     1        0
    GSR           :    1           1    |  DGE/IO           :     0        1
                     ----        ----
            Total    138         138

    MACROCELL RESOURCES:

    Total Macrocells Available                   512
    Registered Macrocells                        272
    Non-registered Macrocell driving I/O          61

    GLOBAL RESOURCES:

    Signal 'dsdly<0>' mapped onto global clock net GCK0.
    Signal 'clk' mapped onto global clock net GCK1.
    Signal 'dsdly<1>' mapped onto global clock net GCK2.
    Signal '_n0086_MC.GLB' mapped onto global output enable net GTS0.
    Signal '_n0088_MC.GLB' mapped onto global output enable net GTS3.
    Signal 'reset' mapped onto global set/reset net GSR.

    End of Resource Summary
    *************** Summary of Required Resources ******************

    ** LOGIC **
    Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg     I/O      I/O       Reg Init
    Name                Pt    Used            Rate #    Type      Use     Use     STD      Style     State
    Mcompar__n0026__n0034                    21      21    FB29_13           (b)       (b)
    Mcompar__n0026__n003420                    16      16    FB30_15           (b)       (b)
    Mcompar__n0029__n0027                    2       2     FB28_12           (b)       (b)
    Mcompar__n0029__n0029                    2       2     FB29_16           (b)       (b)
    N_PZ_30322          1       3     FB4_15       17   I/O       I
    N_PZ_30353          1       3     FB4_14       16   I/O       I
    N_PZ_30354          3       10    FB4_3             (b)       (b)
    N_PZ_30371          1       3     FB11_3       44   GCK/I/O   GCK/I
    N_PZ_30372          2       2     FB29_11           (b)       (b)
    N_PZ_30373          2       6     FB4_16       18   I/O       I
    N_PZ_30394          2       10    FB10_9            (b)       (b)
    N_PZ_30405          2       2     FB29_10           (b)       (b)
    N_PZ_30413          3       12    FB4_10            (b)       (b)
    N_PZ_30489          1       10    FB10_11           (b)       (b)
    N_PZ_30510          2       2     FB29_9            (b)       (b)
    N_PZ_30539          2       2     FB29_8            (b)       (b)
    N_PZ_30542          1       6     FB16_12           (b)       (b)
    N_PZ_30547          1       8     FB29_15           (b)       (b)
    N_PZ_30575          1       7     FB12_10           (b)       (b)
    N_PZ_30580          1       6     FB19_15           (b)       (b)
    N_PZ_30589          1       7     FB11_2            (b)       (b)
    N_PZ_30591          5       12    FB1_5             (b)       (b)
    N_PZ_30599          2       23    FB14_16           (b)       (b)
    U1/q2               2       11    FB10_15           (b)       (b)     DFF                        RESET
    U2/b2               2       11    FB10_12           (b)       (b)     DFF                        RESET
    U2/latch3           2       3     FB22_10           (b)       (b)
    U2/qlt              2       10    FB10_10           (b)       (b)     DFF                        RESET
    U3/add_latched<0>   1       1     FB2_16       12   I/O       I       LATCH                      RESET
    U3/add_latched<1>   1       1     FB3_1        205  I/O       I       LATCH                      RESET
    U3/add_latched<2>   2       2     FB1_12            (b)       (b)     LATCH                      RESET
    U3/add_latched<3>   1       1     FB1_2        6    I/O       I       LATCH                      RESET
    U3/add_latched<4>   2       2     FB1_11            (b)       (b)     LATCH                      RESET
    U3/add_latched<5>   1       1     FB1_4        4    I/O       I       LATCH                      RESET
    U3/add_latched<6>   1       1     FB1_13       3    GTS/I/O   I       LATCH                      RESET
    U3/add_latched<7>   1       1     FB1_14       2    I/O       I       LATCH                      RESET
    U3/add_latched<8>   1       1     FB1_15       208  I/O       I       LATCH                      RESET
    U3/add_latched<9>   1       1     FB2_2        8    I/O       I       LATCH                      RESET
    U3/counter_add<0>   5       5     FB25_11           (b)       (b)     DFF                        RESET
    U3/counter_add<1>   6       6     FB22_11           (b)       (b)     DFF                        RESET
    U3/counter_add<2>   7       7     FB22_12           (b)       (b)     DFF                        RESET
    U3/counter_add<3>   8       8     FB25_10           (b)       (b)     DFF                        RESET
    U3/counter_add<4>   9       9     FB24_12           (b)       (b)     DFF                        RESET
    U3/counter_add<5>   10      10    FB24_16           (b)       (b)     DFF                        RESET
    U3/counter_add<6>   11      11    FB23_16           (b)       (b)     DFF                        RESET
    U3/counter_add<7>   12      12    FB23_15           (b)       (b)     DFF                        RESET
    U4/_n00084          1       3     FB21_3       175  I/O       I
    U4/_n000921         2       11    FB4_6             (b)       (b)
    U4/_n001021         2       11    FB4_5             (b)       (b)
    U4/_n001321         2       11    FB6_6             (b)       (b)
    U4/_n001521         2       11    FB26_6            (b)       (b)
    U4/_n001821         2       11    FB8_12            (b)       (b)
    U4/_n001921         2       11    FB8_11            (b)       (b)
    U4/_n002121         2       11    FB6_5             (b)       (b)
    U4/_n0029           2       11    FB27_7            (b)       (b)
    U4/_n0051           1       10    FB6_4             (b)       (b)
    U4/_n0081           2       9     FB4_1             (b)       (b)
    U4/ena_fill_mem     3       15    FB4_11            (b)       (b)     TFF                        RESET
    U4/ena_word_count2  1       2     FB28_13           (b)       (b)
    U4/lfsr_0<0>        2       2     FB9_12            (b)       (b)     DFF                        RESET
    U4/lfsr_0<10>       1       1     FB2_13            (b)       (b)     DFF                        RESET
    U4/lfsr_0<11>       1       1     FB2_12            (b)       (b)     DFF                        RESET
    U4/lfsr_0<12>       1       1     FB2_11            (b)       (b)     DFF                        RESET
    U4/lfsr_0<13>       1       1     FB2_10            (b)       (b)     DFF                        RESET
    U4/lfsr_0<14>       1       1     FB2_9             (b)       (b)     DFF                        RESET
    U4/lfsr_0<15>       1       1     FB2_8             (b)       (b)     DFF                        RESET
    U4/lfsr_0<16>       1       1     FB2_7             (b)       (b)     DFF                        RESET
    U4/lfsr_0<17>       1       1     FB2_6             (b)       (b)     DFF                        RESET
    U4/lfsr_0<18>       1       1     FB2_5             (b)       (b)     DFF                        RESET
    U4/lfsr_0<19>       1       1     FB2_4             (b)       (b)     DFF                        RESET
    U4/lfsr_0<1>        1       1     FB2_3             (b)       (b)     DFF                        RESET
    U4/lfsr_0<20>       1       1     FB2_1             (b)       (b)     DFF                        RESET
    U4/lfsr_0<21>       1       1     FB2_15       10   I/O       I       DFF                        RESET
    U4/lfsr_0<22>       1       1     FB2_14       9    GTS/I/O   I       DFF                        RESET
    U4/lfsr_0<23>       1       1     FB3_14            (b)       (b)     DFF                        RESET
    U4/lfsr_0<24>       1       1     FB3_12            (b)       (b)     DFF                        RESET
    U4/lfsr_0<25>       1       1     FB3_11            (b)       (b)     DFF                        RESET
    U4/lfsr_0<26>       1       1     FB3_10            (b)       (b)     DFF                        RESET
    U4/lfsr_0<27>       1       1     FB3_9             (b)       (b)     DFF                        RESET
    U4/lfsr_0<28>       1       1     FB3_8             (b)       (b)     DFF                        RESET
    U4/lfsr_0<29>       1       1     FB3_7             (b)       (b)     DFF                        RESET
    U4/lfsr_0<2>        1       1     FB3_6             (b)       (b)     DFF                        RESET
    U4/lfsr_0<30>       1       1     FB3_4             (b)       (b)     DFF                        RESET
    U4/lfsr_0<31>       1       1     FB3_2             (b)       (b)     DFF                        RESET
    U4/lfsr_0<32>       1       1     FB3_16       199  I/O       I       DFF                        RESET
    U4/lfsr_0<33>       1       1     FB3_15       200  I/O       I       DFF                        RESET
    U4/lfsr_0<34>       1       1     FB3_13       201  I/O       I       DFF                        RESET
    U4/lfsr_0<35>       1       1     FB3_5        202  I/O       I       DFF                        RESET
    U4/lfsr_0<36>       1       1     FB3_3        203  I/O       I       DFF                        RESET
    U4/lfsr_0<37>       1       1     FB9_15            (b)       (b)     DFF                        RESET
    U4/lfsr_0<38>       1       1     FB9_13            (b)       (b)     DFF                        RESET
    U4/lfsr_0<39>       1       1     FB9_11            (b)       (b)     DFF                        RESET
    U4/lfsr_0<3>        1       1     FB9_10            (b)       (b)     DFF                        RESET
    U4/lfsr_0<40>       1       1     FB9_9             (b)       (b)     DFF                        RESET
    U4/lfsr_0<4>        1       1     FB9_8             (b)       (b)     DFF                        RESET
    U4/lfsr_0<5>        1       1     FB9_7             (b)       (b)     DFF                        RESET
    U4/lfsr_0<6>        1       1     FB9_6             (b)       (b)     DFF                        RESET
    U4/lfsr_0<7>        1       1     FB9_5             (b)       (b)     DFF                        RESET
    U4/lfsr_0<8>        1       1     FB9_1             (b)       (b)     DFF                        RESET
    U4/lfsr_0<9>        1       1     FB9_16       46   GCK/I/O   GCK/I   DFF                        RESET
    U4/lfsr_1<0>        2       2     FB14_8            (b)       (b)     DFF                        RESET
    U4/lfsr_1<10>       1       1     FB9_14       47   I/O       I       DFF                        RESET
    U4/lfsr_1<11>       1       1     FB9_4        48   I/O       I       DFF                        RESET
    U4/lfsr_1<12>       1       1     FB9_2        50   I/O       I       DFF                        RESET
    U4/lfsr_1<13>       1       1     FB11_1       45   I/O       (b)     DFF                        RESET
    U4/lfsr_1<14>       1       1     FB13_16           (b)       (b)     DFF                        RESET
    U4/lfsr_1<15>       1       1     FB13_13           (b)       (b)     DFF                        RESET
    U4/lfsr_1<16>       1       1     FB13_12           (b)       (b)     DFF                        RESET
    U4/lfsr_1<17>       1       1     FB13_11           (b)       (b)     DFF                        RESET
    U4/lfsr_1<18>       1       1     FB13_10           (b)       (b)     DFF                        RESET
    U4/lfsr_1<19>       1       1     FB13_9            (b)       (b)     DFF                        RESET
    U4/lfsr_1<1>        1       1     FB13_8            (b)       (b)     DFF                        RESET
    U4/lfsr_1<20>       1       1     FB13_7            (b)       (b)     DFF                        RESET
    U4/lfsr_1<21>       1       1     FB13_6            (b)       (b)     DFF                        RESET
    U4/lfsr_1<22>       1       1     FB13_5            (b)       (b)     DFF                        RESET
    U4/lfsr_1<23>       1       1     FB13_2            (b)       (b)     DFF                        RESET
    U4/lfsr_1<24>       1       1     FB13_15      32   I/O       (b)     DFF                        RESET
    U4/lfsr_1<25>       1       1     FB13_1       37   I/O       (b)     DFF                        RESET
    U4/lfsr_1<26>       1       1     FB14_11           (b)       (b)     DFF                        RESET
    U4/lfsr_1<27>       1       1     FB14_10           (b)       (b)     DFF                        RESET
    U4/lfsr_1<28>       1       1     FB14_9            (b)       (b)     DFF                        RESET
    U4/lfsr_1<29>       1       1     FB14_7            (b)       (b)     DFF                        RESET
    U4/lfsr_1<2>        1       1     FB14_6            (b)       (b)     DFF                        RESET
    U4/lfsr_1<30>       1       1     FB15_16           (b)       (b)     DFF                        RESET
    U4/lfsr_1<3>        1       1     FB15_15           (b)       (b)     DFF                        RESET
    U4/lfsr_1<4>        1       1     FB15_12           (b)       (b)     DFF                        RESET
    U4/lfsr_1<5>        1       1     FB15_11           (b)       (b)     DFF                        RESET
    U4/lfsr_1<6>        1       1     FB15_10           (b)       (b)     DFF                        RESET
    U4/lfsr_1<7>        1       1     FB15_9            (b)       (b)     DFF                        RESET
    U4/lfsr_1<8>        1       1     FB15_8            (b)       (b)     DFF                        RESET
    U4/lfsr_1<9>        1       1     FB15_7            (b)       (b)     DFF                        RESET
    ULED/q1             2       3     FB24_11           (b)       (b)     TFF                        RESET
    ULED/q3             2       2     FB17_12           (b)       (b)     DFF                        RESET
    _n0033<14>2         2       16    FB21_1            (b)       (b)
    _n003432            1       3     FB24_10           (b)       (b)
    counter<0>          5       11    FB1_7             (b)       (b)     TFF                        RESET
    counter<10>         2       6     FB11_11           (b)       (b)     DFF                        RESET
    counter<11>         2       7     FB10_3       55   GCK/I/O   GCK/I   DFF                        RESET
    counter<12>         2       8     FB10_13      57   I/O       I       DFF                        RESET
    counter<13>         2       9     FB10_14      58   DGE/I/O   (b)     DFF                        RESET
    counter<14>         2       11    FB10_5            (b)       (b)     DFF                        RESET
    counter<15>         2       4     FB10_8            (b)       (b)     DFF                        RESET
    counter<16>         2       5     FB10_7            (b)       (b)     DFF                        RESET
    counter<17>         2       6     FB10_6            (b)       (b)     DFF                        RESET
    counter<1>          4       13    FB1_6             (b)       (b)     DFF                        RESET
    counter<2>          2       4     FB11_13      41   I/O       (b)     DFF                        RESET
    counter<3>          2       5     FB11_16      38   I/O       (b)     DFF                        RESET
    counter<4>          2       6     FB11_5            (b)       (b)     DFF                        RESET
    counter<5>          2       7     FB11_6            (b)       (b)     DFF                        RESET
    counter<6>          2       8     FB11_7            (b)       (b)     DFF                        RESET
    counter<7>          2       10    FB11_8            (b)       (b)     DFF                        RESET
    counter<8>          2       4     FB11_9            (b)       (b)     DFF                        RESET
    counter<9>          2       5     FB11_10           (b)       (b)     DFF                        RESET
    cspare<0>           0       0     FB31_3  FAST 127  I/O       O               LVCMOS18
    cspare<10>          1       1     FB11_15 FAST 39   I/O       O               LVCMOS18
    cspare<11>          1       3     FB11_14 FAST 40   I/O       O               LVCMOS18
    cspare<1>           0       0     FB31_1  FAST 126  I/O       O               LVCMOS18
    cspare<2>           0       0     FB15_4  FAST 29   I/O       O               LVCMOS18
    cspare<3>           0       0     FB15_3  FAST 30   I/O       O               LVCMOS18
    cspare<4>           0       0     FB18_4  FAST 159  I/O       O               LVCMOS18
    cspare<5>           0       0     FB18_15 FAST 158  I/O       O               LVCMOS18
    cspare<6>           0       0     FB13_14 FAST 34   I/O       O               LVCMOS18
    cspare<7>           0       0     FB13_4  FAST 35   I/O       O               LVCMOS18
    cspare<8>           0       0     FB31_16 FAST 131  I/O       O               LVCMOS18
    cspare<9>           0       0     FB31_4  FAST 128  I/O       O               LVCMOS18
    cycle_counter<0>    3       4     FB11_4       43   I/O       (b)     DFF                        RESET
    cycle_counter<10>   3       14    FB21_8            (b)       (b)     TFF                        RESET
    cycle_counter<11>   3       15    FB21_7            (b)       (b)     TFF                        RESET
    cycle_counter<12>   3       16    FB21_6            (b)       (b)     TFF                        RESET
    cycle_counter<13>   3       17    FB21_4            (b)       (b)     TFF                        RESET
    cycle_counter<14>   3       5     FB20_12           (b)       (b)     DFF                        RESET
    cycle_counter<15>   4       6     FB20_11           (b)       (b)     TFF                        RESET
    cycle_counter<1>    3       5     FB20_10           (b)       (b)     TFF                        RESET
    cycle_counter<2>    3       6     FB20_9            (b)       (b)     TFF                        RESET
    cycle_counter<3>    3       7     FB20_8            (b)       (b)     TFF                        RESET
    cycle_counter<4>    3       8     FB20_7            (b)       (b)     TFF                        RESET
    cycle_counter<5>    3       9     FB20_6            (b)       (b)     TFF                        RESET
    cycle_counter<6>    3       10    FB20_5            (b)       (b)     TFF                        RESET
    cycle_counter<7>    3       11    FB21_11           (b)       (b)     TFF                        RESET
    cycle_counter<8>    3       12    FB21_10           (b)       (b)     TFF                        RESET
    cycle_counter<9>    3       13    FB21_9            (b)       (b)     TFF                        RESET
    db<0>               9       21    FB4_2   FAST 14   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<10>              7       14    FB5_1   FAST 198  I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<11>              6       18    FB5_3   FAST 196  I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<12>              6       18    FB6_1   FAST 19   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<13>              6       18    FB6_3   FAST 21   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<14>              6       18    FB7_1   FAST 191  I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<15>              6       18    FB7_3   FAST 189  I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<1>               9       21    FB4_4   FAST 15   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<2>               7       14    FB7_4   FAST 188  I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<3>               7       14    FB5_2   FAST 197  I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<4>               7       19    FB12_2  FAST 61   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<5>               7       14    FB6_2   FAST 20   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<6>               7       14    FB8_2   FAST 22   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<7>               7       14    FB8_3   FAST 23   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<8>               7       14    FB8_14  FAST 25   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    db<9>               7       14    FB12_1  FAST 60   I/O       I/O     DEFF    LVCMOS18 KPR       RESET
    dout<0>             2       2     FB25_14 FAST 115  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<10>            2       2     FB25_15 FAST 116  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<11>            2       2     FB25_16 FAST 117  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<12>            2       2     FB26_16 FAST 100  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<13>            2       2     FB27_3  FAST 119  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<14>            2       2     FB27_4  FAST 120  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<15>            2       2     FB27_15 FAST 121  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<1>             2       2     FB28_1  FAST 99   I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<2>             2       2     FB28_2  FAST 97   I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<3>             2       2     FB28_3  FAST 95   I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<4>             2       2     FB29_3  FAST 122  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<5>             2       2     FB29_4  FAST 123  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<6>             2       2     FB29_14 FAST 125  I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<7>             2       2     FB30_2  FAST 91   I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<8>             2       2     FB30_3  FAST 90   I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout<9>             2       2     FB30_4  FAST 89   I/O       I/O     DFF     LVCMOS18 KPR       RESET
    dout_reg_in<0>      1       1     FB15_6            (b)       (b)     DFF                        RESET
    dout_reg_in<10>     1       1     FB15_5            (b)       (b)     DFF                        RESET
    dout_reg_in<11>     1       1     FB15_2            (b)       (b)     DFF                        RESET
    dout_reg_in<12>     1       1     FB15_14      27   I/O       (b)     DFF                        RESET
    dout_reg_in<13>     1       1     FB15_13      28   I/O       (b)     DFF                        RESET
    dout_reg_in<14>     1       1     FB15_1       31   I/O       (b)     DFF                        RESET
    dout_reg_in<15>     1       1     FB16_10           (b)       (b)     DFF                        RESET
    dout_reg_in<1>      1       1     FB17_11           (b)       (b)     DFF                        RESET
    dout_reg_in<2>      1       1     FB17_10           (b)       (b)     DFF                        RESET
    dout_reg_in<3>      1       1     FB17_9            (b)       (b)     DFF                        RESET
    dout_reg_in<4>      1       1     FB17_8            (b)       (b)     DFF                        RESET
    dout_reg_in<5>      1       1     FB17_7            (b)       (b)     DFF                        RESET
    dout_reg_in<6>      1       1     FB17_6            (b)       (b)     DFF                        RESET
    dout_reg_in<7>      1       1     FB18_16           (b)       (b)     DFF                        RESET
    dout_reg_in<8>      1       1     FB18_14           (b)       (b)     DFF                        RESET
    dout_reg_in<9>      1       1     FB18_13           (b)       (b)     DFF                        RESET
    dout_reg_in_2<0>    1       1     FB18_12           (b)       (b)     DFF                        RESET
    dout_reg_in_2<10>   1       1     FB18_11           (b)       (b)     DFF                        RESET
    dout_reg_in_2<11>   1       1     FB18_10           (b)       (b)     DFF                        RESET
    dout_reg_in_2<12>   1       1     FB18_9            (b)       (b)     DFF                        RESET
    dout_reg_in_2<13>   1       1     FB18_8            (b)       (b)     DFF                        RESET
    dout_reg_in_2<14>   1       1     FB18_7            (b)       (b)     DFF                        RESET
    dout_reg_in_2<15>   1       1     FB18_6            (b)       (b)     DFF                        RESET
    dout_reg_in_2<1>    1       1     FB18_5            (b)       (b)     DFF                        RESET
    dout_reg_in_2<2>    1       1     FB18_3            (b)       (b)     DFF                        RESET
    dout_reg_in_2<3>    1       1     FB18_2            (b)       (b)     DFF                        RESET
    dout_reg_in_2<4>    1       1     FB18_1       160  I/O       (b)     DFF                        RESET
    dout_reg_in_2<5>    1       1     FB20_2            (b)       (b)     DFF                        RESET
    dout_reg_in_2<6>    1       1     FB21_16           (b)       (b)     DFF                        RESET
    dout_reg_in_2<7>    1       1     FB21_15           (b)       (b)     DFF                        RESET
    dout_reg_in_2<8>    1       1     FB21_14           (b)       (b)     DFF                        RESET
    dout_reg_in_2<9>    1       1     FB21_13           (b)       (b)     DFF                        RESET
    ds_out              1       2     FB26_13 FAST 103  I/O       O               LVCMOS18
    dtack_blk           2       12    FB10_16           (b)       (b)     DFF                        RESET
    dtack_mem           1       2     FB27_1  FAST 118  I/O       O               LVCMOS18
    ena_ceros_mem       3       15    FB4_13            (b)       (b)     TFF                        RESET
    ena_gol_test        4       16    FB4_12            (b)       (b)     TFF                        RESET
    enw1                1       2     FB9_3        49   I/O       I       DFF                        RESET
    enw2                1       1     FB5_9             (b)       (b)     DFF                        RESET
    estado_FFD1         11      23    FB11_12           (b)       (b)     DFF                        RESET
    estado_FFD2         5       7     FB1_10            (b)       (b)     DFF                        RESET
    estado_FFD3         4       8     FB1_9             (b)       (b)     TFF                        RESET
    estado_XX_FFD135    14      14    FB14_12           (b)       (b)
    estado_XX_FFD136    4       4     FB29_12           (b)       (b)
    estado_XX_FFD146    3       20    FB14_14           (b)       (b)
    estado_XX_FFD153    5       22    FB21_5       178  I/O       (b)
    g245_mem            1       10    FB22_4  FAST 146  I/O       O               LVCMOS18
    inc_pointer         19      21    FB1_8             (b)       (b)     DFF                        RESET
    is_trigger_1        0       0     FB10_4       56   I/O       I       DFF                        RESET
    led<0>              1       2     FB26_1  FAST 109  I/O       O               LVCMOS18
    led<1>              1       2     FB26_2  FAST 108  I/O       O               LVCMOS18
    madd<0>             3       14    FB25_4  FAST 113  I/O       O               LVCMOS18
    madd<10>            3       14    FB19_3  FAST 173  I/O       O               LVCMOS18
    madd<11>            3       14    FB19_2  FAST 171  I/O       O               LVCMOS18
    madd<12>            3       14    FB19_1  FAST 170  I/O       O               LVCMOS18
    madd<13>            3       14    FB16_14 FAST 78   I/O       O               LVCMOS18
    madd<14>            3       14    FB16_5  FAST 77   I/O       O               LVCMOS18
    madd<15>            3       14    FB16_4  FAST 76   I/O       O               LVCMOS18
    madd<16>            3       14    FB16_3  FAST 75   I/O       O               LVCMOS18
    madd<17>            3       14    FB16_1  FAST 74   I/O       O               LVCMOS18
    madd<1>             3       14    FB22_14 FAST 144  I/O       O               LVCMOS18
    madd<2>             3       14    FB22_15 FAST 143  I/O       O               LVCMOS18
    madd<3>             3       14    FB23_1  FAST 179  I/O       O               LVCMOS18
    madd<4>             3       14    FB23_2  FAST 180  I/O       O               LVCMOS18
    madd<5>             3       14    FB24_4  FAST 137  I/O       O               LVCMOS18
    madd<6>             3       14    FB23_4  FAST 182  I/O       O               LVCMOS18
    madd<7>             3       14    FB24_3  FAST 138  I/O       O               LVCMOS18
    madd<8>             3       14    FB24_1  FAST 140  I/O       O               LVCMOS18
    madd<9>             3       14    FB24_2  FAST 139  I/O       O               LVCMOS18
    mdat<0>             2       3     FB17_2  FAST 162  I/O       I/O             LVCMOS18 KPR
    mdat<10>            2       3     FB17_3  FAST 163  I/O       I/O             LVCMOS18 KPR
    mdat<11>            2       3     FB17_4  FAST 164  I/O       I/O             LVCMOS18 KPR
    mdat<12>            2       3     FB17_5  FAST 165  I/O       I/O             LVCMOS18 KPR
    mdat<13>            2       3     FB17_13 FAST 166  I/O       I/O             LVCMOS18 KPR
    mdat<14>            2       3     FB17_14 FAST 167  I/O       I/O             LVCMOS18 KPR
    mdat<15>            2       3     FB17_15 FAST 168  I/O       I/O             LVCMOS18 KPR
    mdat<1>             2       3     FB17_16 FAST 169  I/O       I/O             LVCMOS18 KPR
    mdat<2>             2       3     FB20_4  FAST 154  I/O       I/O             LVCMOS18 KPR
    mdat<3>             2       3     FB20_13 FAST 153  I/O       I/O             LVCMOS18 KPR
    mdat<4>             2       3     FB20_14 FAST 152  I/O       I/O             LVCMOS18 KPR
    mdat<5>             2       3     FB20_15 FAST 151  I/O       I/O             LVCMOS18 KPR
    mdat<6>             2       3     FB20_16 FAST 150  I/O       I/O             LVCMOS18 KPR
    mdat<7>             2       3     FB22_1  FAST 149  I/O       I/O             LVCMOS18 KPR
    mdat<8>             2       3     FB22_2  FAST 148  I/O       I/O             LVCMOS18 KPR
    mdat<9>             2       3     FB22_3  FAST 147  I/O       I/O             LVCMOS18 KPR
    mem_done_p          2       6     FB25_2  FAST 111  I/O       O       DFF     LVCMOS18           RESET
    mem_is_full         2       21    FB19_16           (b)       (b)     DFF                        RESET
    mem_pointer<0>      6       15    FB27_9            (b)       (b)     DFF                        RESET
    mem_pointer<10>     5       14    FB5_14            (b)       (b)     DFF                        RESET
    mem_pointer<11>     4       6     FB16_11           (b)       (b)     DFF                        RESET
    mem_pointer<12>     7       16    FB5_16            (b)       (b)     DFF                        RESET
    mem_pointer<13>     4       8     FB16_13           (b)       (b)     DFF                        RESET
    mem_pointer<14>     5       19    FB28_15           (b)       (b)     DFF                        RESET
    mem_pointer<15>     5       14    FB28_16           (b)       (b)     DFF                        RESET
    mem_pointer<16>     4       6     FB16_15           (b)       (b)     DFF                        RESET
    mem_pointer<17>     4       7     FB16_16           (b)       (b)     DFF                        RESET
    mem_pointer<1>      5       8     FB25_12           (b)       (b)     DFF                        RESET
    mem_pointer<2>      8       17    FB27_8            (b)       (b)     DFF                        RESET
    mem_pointer<3>      5       19    FB28_14           (b)       (b)     DFF                        RESET
    mem_pointer<4>      5       14    FB12_11           (b)       (b)     DFF                        RESET
    mem_pointer<5>      4       6     FB23_12           (b)       (b)     DFF                        RESET
    mem_pointer<6>      7       16    FB12_12           (b)       (b)     DFF                        RESET
    mem_pointer<7>      4       8     FB23_14           (b)       (b)     DFF                        RESET
    mem_pointer<8>      4       9     FB23_13           (b)       (b)     DFF                        RESET
    mem_pointer<9>      5       20    FB12_16           (b)       (b)     DFF                        RESET
    mevent_count<10>    2       10    FB5_12            (b)       (b)     DEFF                       RESET
    mevent_count<2>     2       10    FB6_16            (b)       (b)     DEFF                       RESET
    mevent_count<3>     2       10    FB6_14            (b)       (b)     DEFF                       RESET
    mevent_count<5>     2       10    FB6_12            (b)       (b)     DEFF                       RESET
    mevent_count<6>     2       10    FB7_12            (b)       (b)     DEFF                       RESET
    mevent_count<7>     2       10    FB7_10            (b)       (b)     DEFF                       RESET
    mevent_count<8>     2       10    FB7_8             (b)       (b)     DEFF                       RESET
    mevent_count<9>     2       10    FB7_6             (b)       (b)     DEFF                       RESET
    mspare_0            0       0     FB26_4  FAST 106  I/O       O               LVCMOS18
    mspare_1            0       0     FB24_15 FAST 134  I/O       O               LVCMOS18
    mspare_2            0       0     FB26_15 FAST 101  I/O       O               LVCMOS18
    mspare_3            0       0     FB13_3  FAST 36   I/O       O               LVCMOS18
    mword_count<0>      3       13    FB26_12           (b)       (b)     DFF                        RESET
    mword_count<10>     3       13    FB26_11           (b)       (b)     DFF                        RESET
    mword_count<11>     3       13    FB26_10           (b)       (b)     DFF                        RESET
    mword_count<12>     3       13    FB6_9             (b)       (b)     DFF                        RESET
    mword_count<13>     3       13    FB6_8             (b)       (b)     DFF                        RESET
    mword_count<14>     3       13    FB26_9            (b)       (b)     DFF                        RESET
    mword_count<15>     3       13    FB26_8            (b)       (b)     DFF                        RESET
    mword_count<16>     6       13    FB27_11           (b)       (b)     DFF                        RESET
    mword_count<17>     6       13    FB27_10           (b)       (b)     DFF                        RESET
    mword_count<1>      3       13    FB26_7            (b)       (b)     DFF                        RESET
    mword_count<2>      3       13    FB27_16           (b)       (b)     DFF                        RESET
    mword_count<3>      3       13    FB27_14           (b)       (b)     DFF                        RESET
    mword_count<4>      3       13    FB27_13           (b)       (b)     DFF                        RESET
    mword_count<5>      3       13    FB6_10            (b)       (b)     DFF                        RESET
    mword_count<6>      3       13    FB8_16            (b)       (b)     DFF                        RESET
    mword_count<7>      3       13    FB8_15            (b)       (b)     DFF                        RESET
    mword_count<8>      3       13    FB8_13            (b)       (b)     DFF                        RESET
    mword_count<9>      3       13    FB27_12           (b)       (b)     DFF                        RESET
    num_cycles<0>       2       10    FB4_9             (b)       (b)     DEFF                       RESET
    num_cycles<10>      2       10    FB5_11            (b)       (b)     DEFF                       RESET
    num_cycles<11>      2       10    FB7_16       183  I/O       I       DEFF                       RESET
    num_cycles<12>      2       10    FB5_10            (b)       (b)     DEFF                       RESET
    num_cycles<13>      2       10    FB6_7             (b)       (b)     DEFF                       RESET
    num_cycles<14>      2       10    FB7_15       184  I/O       I       DEFF                       RESET
    num_cycles<15>      2       10    FB7_14       185  I/O       I       DEFF                       RESET
    num_cycles<1>       2       10    FB4_8             (b)       (b)     DEFF                       RESET
    num_cycles<2>       2       10    FB6_15            (b)       (b)     DEFF                       RESET
    num_cycles<3>       2       10    FB6_13            (b)       (b)     DEFF                       RESET
    num_cycles<4>       2       10    FB4_7             (b)       (b)     DEFF                       RESET
    num_cycles<5>       2       10    FB6_11            (b)       (b)     DEFF                       RESET
    num_cycles<6>       2       10    FB7_11            (b)       (b)     DEFF                       RESET
    num_cycles<7>       2       10    FB7_9             (b)       (b)     DEFF                       RESET
    num_cycles<8>       2       10    FB7_7             (b)       (b)     DEFF                       RESET
    num_cycles<9>       2       10    FB7_2             (b)       (b)     DEFF                       RESET
    oe                  2       3     FB22_13 FAST 145  I/O       O               LVCMOS18
    tp5                 2       12    FB10_1  FAST 51   CDR/I/O   O       DFF     LVCMOS18           RESET
    tp6                 1       3     FB25_3  FAST 112  I/O       O               LVCMOS18
    tp7                 2       5     FB26_14 FAST 102  I/O       O               LVCMOS18
    tp8                 1       1     FB17_1  FAST 161  I/O       O               LVCMOS18
    trigger_led         2       2     FB26_3  FAST 107  I/O       O       DFF/S   LVCMOS18           SET
    txena               2       4     FB10_2  FAST 54   I/O       I/O     DFF     LVCMOS18 KPR       RESET
    txena_out           4       7     FB1_16       206  GSR/I/O   GSR/I   DFF                        RESET
    txena_reg_out       1       1     FB21_12           (b)       (b)     DFF                        RESET
    vspare_1            0       0     FB25_13 FAST 114  I/O       O               LVCMOS18
    we                  3       6     FB20_3  FAST 155  I/O       O               LVCMOS18
    we_fifo             1       2     FB22_9            (b)       (b)     DDFF                       RESET

    ** INPUTS **
    Signal                            Loc          Pin  Pin       Pin     Reg     I/O      I/O
    Name                                           #    Type      Use     Use     STD      Style
    add<0>                            FB21_2       174  I/O       I               LVCMOS18 KPR
    add<10>                           FB1_1        7    GTS/I/O   I               LVCMOS18 KPR
    add<11>                           FB1_2        6    I/O       I               LVCMOS18 KPR
    add<12>                           FB1_3        5    GTS/I/O   I               LVCMOS18 KPR
    add<13>                           FB1_4        4    I/O       I               LVCMOS18 KPR
    add<14>                           FB1_13       3    GTS/I/O   I               LVCMOS18 KPR
    add<15>                           FB1_14       2    I/O       I               LVCMOS18 KPR
    add<16>                           FB1_15       208  I/O       I               LVCMOS18 KPR
    add<17>                           FB2_2        8    I/O       I               LVCMOS18 KPR
    add<1>                            FB21_3       175  I/O       I               LVCMOS18 KPR
    add<2>                            FB4_14       16   I/O       I               LVCMOS18 KPR
    add<3>                            FB4_15       17   I/O       I               LVCMOS18 KPR
    add<4>                            FB4_16       18   I/O       I               LVCMOS18 KPR
    add<5>                            FB7_5        187  I/O       I               LVCMOS18 KPR
    add<6>                            FB2_14       9    GTS/I/O   I               LVCMOS18 KPR
    add<7>                            FB2_15       10   I/O       I               LVCMOS18 KPR
    add<8>                            FB2_16       12   I/O       I               LVCMOS18 KPR
    add<9>                            FB3_1        205  I/O       I               LVCMOS18 KPR
    am<0>                             FB3_3        203  I/O       I               LVCMOS18 KPR
    am<1>                             FB5_5        194  I/O       I               LVCMOS18 KPR
    am<2>                             FB3_5        202  I/O       I               LVCMOS18 KPR
    am<3>                             FB3_13       201  I/O       I               LVCMOS18 KPR
    am<4>                             FB3_15       200  I/O       I               LVCMOS18 KPR
    am<5>                             FB3_16       199  I/O       I               LVCMOS18 KPR
    as                                FB5_15       192  I/O       I               LVCMOS18 KPR
    brdsel24                          FB7_13       186  I/O       I               LVCMOS18 KPR
    clk                               FB9_16       46   GCK/I/O   GCK/I           LVCMOS18 KPR
    clk_slow                          FB7_14       185  I/O       I               LVCMOS18 KPR
    cs                                FB7_15       184  I/O       I               LVCMOS18 KPR
    ds0                               FB7_16       183  I/O       I               LVCMOS18 KPR
    ds1                               FB9_2        50   I/O       I               LVCMOS18 KPR
    dsdly<0>                          FB11_3       44   GCK/I/O   GCK/I           LVCMOS18 KPR
    dsdly<1>                          FB10_3       55   GCK/I/O   GCK/I           LVCMOS18 KPR
    enw_x                             FB9_3        49   I/O       I               LVCMOS18 KPR
    etr                               FB9_4        48   I/O       I               LVCMOS18 KPR
    iack                              FB9_14       47   I/O       I               LVCMOS18 KPR
    is_trigger                        FB10_4       56   I/O       I               LVCMOS18 KPR
    lword                             FB10_13      57   I/O       I               LVCMOS18 KPR
    reset                             FB1_16       206  GSR/I/O   GSR/I           LVCMOS18 KPR
    vspare_0                          FB24_14      135  I/O       I               LVCMOS18 KPR
    write                             FB5_13       193  I/O       I               LVCMOS18 KPR

    End of Resources

    Legend:
    I/O Style - OD    - OpenDrain
              - PU    - Pullup
              - KPR   - Keeper
              - S     - SchmittTrigger
              - DG    - DataGate
    Reg Use   - LATCH - Transparent latch
              - DFF   - D-flip-flop
              - DEFF  - D-flip-flop with clock enable
              - TFF   - T-flip-flop
              - TDFF  - Dual-edge-triggered T-flip-flop
              - DDFF  - Dual-edge-triggered flip-flop
              - DDEFF - Dual-edge-triggered flip-flop with clock enable
              /S (after any above flop/latch type) indicates initial state is Set

    *********************Function Block Resource Summary***********************
    Function    # of        FB Inputs   Signals     Total       O/IO      IO
    Block       Macrocells  Used        Used        Pt Used     Req       Avail
    FB1          14          34          34           52         0/0        8
    FB2          16          15          15           15         0/0        4
    FB3          16          16          16           16         0/0        6
    FB4          16          37          37           50         0/2        5
    FB5           9          37          37           37         0/3        7
    FB6          16          37          37           42         0/3        3
    FB7          14          37          37           37         0/3        8
    FB8           8          37          37           32         0/3        3
    FB9          16          17          17           17         0/0        5
    FB10         16          32          32           27         1/1        6
    FB11         16          38          38           37         2/0        7
    FB12          6          37          37           30         0/2        8
    FB13         16          13          13           13         3/0        5
    FB14          9          38          38           26         0/0        5
    FB15         16          14          14           14         2/0        5
    FB16         11          38          38           30         5/0        5
    FB17         16          25          25           25         1/8        9
    FB18         16          14          14           14         2/0        3
    FB19          5          38          38           12         3/0        3
    FB20         15          37          37           39         1/5        6
    FB21         15          38          38           34         0/0        3
    FB22         11          36          36           28         4/3        8
    FB23          8          38          38           41         3/0        3
    FB24          9          37          37           31         5/0        7
    FB25         10          37          37           25         4/3        8
    FB26         15          38          38           24         7/1        8
    FB27         13          38          38           40         1/3        4
    FB28          8          37          37           20         0/3        3
    FB29         11          34          34           40         0/3        3
    FB30          4          20          20           20         0/3        6
    FB31          4           0           0            0         4/0        4
    FB32          0           0           0            0         0/0        5
                ----                                -----       -----     -----
                375                                  868        48/49     173
    *********************************** FB1 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  34
    Number of function block inputs used/remaining:               34/6
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   52/4
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB1_1   7     GTS/I/O  I
    U3/add_latched<3>                 1       FB1_2   6     I/O      I
    (unused)                          0       FB1_3   5     GTS/I/O  I
    U3/add_latched<5>                 1       FB1_4   4     I/O      I
    N_PZ_30591                        5       FB1_5         (b)      (b)
    counter<1>                        4       FB1_6         (b)      (b)
    counter<0>                        5       FB1_7         (b)      (b)
    inc_pointer                       19      FB1_8         (b)      (b)
    estado_FFD3                       4       FB1_9         (b)      (b)
    estado_FFD2                       5       FB1_10        (b)      (b)
    U3/add_latched<4>                 2       FB1_11        (b)      (b)
    U3/add_latched<2>                 2       FB1_12        (b)      (b)
    U3/add_latched<6>                 1       FB1_13  3     GTS/I/O  I
    U3/add_latched<7>                 1       FB1_14  2     I/O      I
    U3/add_latched<8>                 1       FB1_15  208   I/O      I
    txena_out                         4       FB1_16  206   GSR/I/O  GSR/I

    Signals Used by Logic in Function Block
      1: Mcompar__n0026__n0034
                           13: add<12>           24: enw1.COMB
      2: N_PZ_30322        14: counter<0>        25: estado_FFD1
      3: N_PZ_30371        15: counter<1>        26: estado_FFD2
      4: N_PZ_30489        16: cs                27: estado_FFD3
      5: N_PZ_30591        17: cspare<11>        28: etr
      6: N_PZ_30599        18: db<3>             29: inc_pointer
      7: U2/latch3         19: db<6>             30: is_trigger
      8: U4/ena_word_count2
                           20: db<7>             31: mem_is_full
      9: U4/lfsr_0<40>     21: db<8>             32: txena
     10: U4/lfsr_1<30>     22: ena_ceros_mem     33: txena_out
     11: _n003432          23: ena_gol_test      34: write
     12: add<10>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    N_PZ_30591        .XX....X.....XX..X.....XXXX....XX....... 12      12
    counter<1>        .XX.X..X.....XX..X.....XXXX....XX....... 13      13
    counter<0>        .XX....X.....X...X.....XXXX....XX....... 11      11
    inc_pointer       XXX....XXXX......XXXXXX.XXX.XXXXX....... 21      21
    estado_FFD3       .X...X...............XX.XXX..X.......... 8       8
    estado_FFD2       .X...................XXXXXX............. 7       7
    U3/add_latched<4>
                      ......X.....X........................... 2       2
    U3/add_latched<2>
                      ......X....X............................ 2       2
    txena_out         ........XX......X.XXX...........X....... 7       7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB2 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  15
    Number of function block inputs used/remaining:               15/25
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   15/41
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U4/lfsr_0<20>                     1       FB2_1         (b)      (b)
    U3/add_latched<9>                 1       FB2_2   8     I/O      I
    U4/lfsr_0<1>                      1       FB2_3         (b)      (b)
    U4/lfsr_0<19>                     1       FB2_4         (b)      (b)
    U4/lfsr_0<18>                     1       FB2_5         (b)      (b)
    U4/lfsr_0<17>                     1       FB2_6         (b)      (b)
    U4/lfsr_0<16>                     1       FB2_7         (b)      (b)
    U4/lfsr_0<15>                     1       FB2_8         (b)      (b)
    U4/lfsr_0<14>                     1       FB2_9         (b)      (b)
    U4/lfsr_0<13>                     1       FB2_10        (b)      (b)
    U4/lfsr_0<12>                     1       FB2_11        (b)      (b)
    U4/lfsr_0<11>                     1       FB2_12        (b)      (b)
    U4/lfsr_0<10>                     1       FB2_13        (b)      (b)
    U4/lfsr_0<22>                     1       FB2_14  9     GTS/I/O  I
    U4/lfsr_0<21>                     1       FB2_15  10    I/O      I
    U3/add_latched<0>                 1       FB2_16  12    I/O      I

    Signals Used by Logic in Function Block
      1: U2/latch3          6: U4/lfsr_0<13>     11: U4/lfsr_0<18>
      2: U4/lfsr_0<0>       7: U4/lfsr_0<14>     12: U4/lfsr_0<19>
      3: U4/lfsr_0<10>      8: U4/lfsr_0<15>     13: U4/lfsr_0<20>
      4: U4/lfsr_0<11>      9: U4/lfsr_0<16>     14: U4/lfsr_0<21>
      5: U4/lfsr_0<12>     10: U4/lfsr_0<17>     15: U4/lfsr_0<9>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U4/lfsr_0<20>     ...........X............................ 1       1
    U4/lfsr_0<1>      .X...................................... 1       1
    U4/lfsr_0<19>     ..........X............................. 1       1
    U4/lfsr_0<18>     .........X.............................. 1       1
    U4/lfsr_0<17>     ........X............................... 1       1
    U4/lfsr_0<16>     .......X................................ 1       1
    U4/lfsr_0<15>     ......X................................. 1       1
    U4/lfsr_0<14>     .....X.................................. 1       1
    U4/lfsr_0<13>     ....X................................... 1       1
    U4/lfsr_0<12>     ...X.................................... 1       1
    U4/lfsr_0<11>     ..X..................................... 1       1
    U4/lfsr_0<10>     ..............X......................... 1       1
    U4/lfsr_0<22>     .............X.......................... 1       1
    U4/lfsr_0<21>     ............X........................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB3 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  16
    Number of function block inputs used/remaining:               16/24
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   16/40
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U3/add_latched<1>                 1       FB3_1   205   I/O      I
    U4/lfsr_0<31>                     1       FB3_2         (b)      (b)
    U4/lfsr_0<36>                     1       FB3_3   203   I/O      I
    U4/lfsr_0<30>                     1       FB3_4         (b)      (b)
    U4/lfsr_0<35>                     1       FB3_5   202   I/O      I
    U4/lfsr_0<2>                      1       FB3_6         (b)      (b)
    U4/lfsr_0<29>                     1       FB3_7         (b)      (b)
    U4/lfsr_0<28>                     1       FB3_8         (b)      (b)
    U4/lfsr_0<27>                     1       FB3_9         (b)      (b)
    U4/lfsr_0<26>                     1       FB3_10        (b)      (b)
    U4/lfsr_0<25>                     1       FB3_11        (b)      (b)
    U4/lfsr_0<24>                     1       FB3_12        (b)      (b)
    U4/lfsr_0<34>                     1       FB3_13  201   I/O      I
    U4/lfsr_0<23>                     1       FB3_14        (b)      (b)
    U4/lfsr_0<33>                     1       FB3_15  200   I/O      I
    U4/lfsr_0<32>                     1       FB3_16  199   I/O      I

    Signals Used by Logic in Function Block
      1: U2/latch3          7: U4/lfsr_0<26>     12: U4/lfsr_0<31>
      2: U4/lfsr_0<1>       8: U4/lfsr_0<27>     13: U4/lfsr_0<32>
      3: U4/lfsr_0<22>      9: U4/lfsr_0<28>     14: U4/lfsr_0<33>
      4: U4/lfsr_0<23>     10: U4/lfsr_0<29>     15: U4/lfsr_0<34>
      5: U4/lfsr_0<24>     11: U4/lfsr_0<30>     16: U4/lfsr_0<35>
      6: U4/lfsr_0<25>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U4/lfsr_0<31>     ..........X............................. 1       1
    U4/lfsr_0<36>     ...............X........................ 1       1
    U4/lfsr_0<30>     .........X.............................. 1       1
    U4/lfsr_0<35>     ..............X......................... 1       1
    U4/lfsr_0<2>      .X...................................... 1       1
    U4/lfsr_0<29>     ........X............................... 1       1
    U4/lfsr_0<28>     .......X................................ 1       1
    U4/lfsr_0<27>     ......X................................. 1       1
    U4/lfsr_0<26>     .....X.................................. 1       1
    U4/lfsr_0<25>     ....X................................... 1       1
    U4/lfsr_0<24>     ...X.................................... 1       1
    U4/lfsr_0<34>     .............X.......................... 1       1
    U4/lfsr_0<23>     ..X..................................... 1       1
    U4/lfsr_0<33>     ............X........................... 1       1
    U4/lfsr_0<32>     ...........X............................ 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB4 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   50/6
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U4/_n0081                         2       FB4_1         (b)      (b)
    db<0>                             9       FB4_2   14    I/O      I/O
    N_PZ_30354                        3       FB4_3         (b)      (b)
    db<1>                             9       FB4_4   15    I/O      I/O
    U4/_n001021                       2       FB4_5         (b)      (b)
    U4/_n000921                       2       FB4_6         (b)      (b)
    num_cycles<4>                     2       FB4_7         (b)      (b)
    num_cycles<1>                     2       FB4_8         (b)      (b)
    num_cycles<0>                     2       FB4_9         (b)      (b)
    N_PZ_30413                        3       FB4_10        (b)      (b)
    U4/ena_fill_mem                   3       FB4_11        (b)      (b)
    ena_gol_test                      4       FB4_12        (b)      (b)
    ena_ceros_mem                     3       FB4_13        (b)      (b)
    N_PZ_30353                        1       FB4_14  16    I/O      I
    N_PZ_30322                        1       FB4_15  17    I/O      I
    N_PZ_30373                        2       FB4_16  18    I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: db<0>.PIN         26: mdat<1>.PIN
      2: N_PZ_30373        15: db<1>             27: mem_pointer<0>
      3: N_PZ_30413        16: db<1>.PIN         28: mem_pointer<16>
      4: N_PZ_30489        17: db<4>.PIN         29: mem_pointer<17>
      5: U4/ena_fill_mem   18: ena_ceros_mem     30: mem_pointer<1>
      6: add<0>            19: ena_gol_test      31: mword_count<0>
      7: add<1>            20: enw1              32: mword_count<16>
      8: add<2>            21: enw2              33: mword_count<17>
      9: add<3>            22: estado_FFD1       34: mword_count<1>
     10: add<4>            23: estado_FFD2       35: num_cycles<0>
     11: add<5>            24: estado_FFD3       36: num_cycles<1>
     12: cs                25: mdat<0>.PIN       37: write
     13: db<0>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U4/_n0081         .....XXXXXXX.......XX................... 9       9
    db<0>             XX.X.XXXXXXXX.....XXX...X.XX..XX..X.X... 21      21
    N_PZ_30354        ....XXXXXXXX.......XX................... 10      10
    db<1>             XX.X.XXXXXXX..X..X.XX....X..XX..XX.XX... 21      21
    U4/_n001021       .....XXXXXXX.X.....XX......X............ 11      11
    U4/_n000921       .....XXXXXXX...X...XX.......X........... 11      11
    num_cycles<4>     .....XXXXXXX....X..XX................... 10      10
    num_cycles<1>     .....XXXXXXX...X...XX................... 10      10
    num_cycles<0>     .....XXXXXXX.X.....XX................... 10      10
    N_PZ_30413        .....XXXXXXX.......XXXXX................ 12      12
    U4/ena_fill_mem   ..X.XXXXXXXX....X..XXXXX................ 15      15
    ena_gol_test      ..X..XXXXXXX.X.X..XXXXXX................ 16      16
    ena_ceros_mem     ..X..XXXXXXX...X.X.XXXXX................ 15      15
    N_PZ_30353        X..X................................X... 3       3
    N_PZ_30322        .....................XXX................ 3       3
    N_PZ_30373        X..X....XXX.........................X... 6       6
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB5 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   37/19
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<10>                            7       FB5_1   198   I/O      I/O
    db<3>                             7       FB5_2   197   I/O      I/O
    db<11>                            6       FB5_3   196   I/O      I/O
    (unused)                          0       FB5_4   195   I/O
    (unused)                          0       FB5_5   194   I/O      I
    (unused)                          0       FB5_6         (b)
    (unused)                          0       FB5_7         (b)
    (unused)                          0       FB5_8         (b)
    enw2                              1       FB5_9         (b)      (b)
    num_cycles<12>                    2       FB5_10        (b)      (b)
    num_cycles<10>                    2       FB5_11        (b)      (b)
    mevent_count<10>                  2       FB5_12        (b)      (b)
    (unused)                          0       FB5_13  193   I/O      I
    mem_pointer<10>                   5       FB5_14        (b)      (b)
    (unused)                          0       FB5_15  192   I/O      I
    mem_pointer<12>                   7       FB5_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: cs                26: mem_pointer<11>
      2: N_PZ_30373        15: db<10>            27: mem_pointer<12>
      3: N_PZ_30413        16: db<10>.PIN        28: mem_pointer<3>
      4: N_PZ_30489        17: db<11>            29: mevent_count<10>
      5: N_PZ_30575        18: db<12>.PIN        30: mevent_count<3>
      6: U4/_n00084        19: db<3>             31: mword_count<10>
      7: U4/_n0081         20: enw1              32: mword_count<11>
      8: add<0>            21: enw2              33: mword_count<3>
      9: add<1>            22: mdat<10>.PIN      34: num_cycles<10>
     10: add<2>            23: mdat<11>.PIN      35: num_cycles<11>
     11: add<3>            24: mdat<3>.PIN       36: num_cycles<3>
     12: add<4>            25: mem_pointer<10>   37: write
     13: add<5>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<10>            XXXX...XXX....X......X..X...X.X..X..X... 14      14
    db<3>             XXXX...XXX........X....X...X.X..X..XX... 14      14
    db<11>            XX.X...XXXXXXX..X..XX.X..X.....X..X.X... 18      18
    enw2              ...................X.................... 1       1
    num_cycles<12>    .......XXXXXXX...X.XX................... 10      10
    num_cycles<10>    .......XXXXXXX.X...XX................... 10      10
    mevent_count<10>  .......XXXXXXX.X...XX................... 10      10
    mem_pointer<10>   ....XXXXXXXXXX.X...XX...X............... 14      14
    mem_pointer<12>   ....XXXXXXXXXX...X.XX...XXX............. 16      16
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB6 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   42/14
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<12>                            6       FB6_1   19    I/O      I/O
    db<5>                             7       FB6_2   20    I/O      I/O
    db<13>                            6       FB6_3   21    I/O      I/O
    U4/_n0051                         1       FB6_4         (b)      (b)
    U4/_n002121                       2       FB6_5         (b)      (b)
    U4/_n001321                       2       FB6_6         (b)      (b)
    num_cycles<13>                    2       FB6_7         (b)      (b)
    mword_count<13>                   3       FB6_8         (b)      (b)
    mword_count<12>                   3       FB6_9         (b)      (b)
    mword_count<5>                    3       FB6_10        (b)      (b)
    num_cycles<5>                     2       FB6_11        (b)      (b)
    mevent_count<5>                   2       FB6_12        (b)      (b)
    num_cycles<3>                     2       FB6_13        (b)      (b)
    mevent_count<3>                   2       FB6_14        (b)      (b)
    num_cycles<2>                     2       FB6_15        (b)      (b)
    mevent_count<2>                   2       FB6_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: db<12>            26: mdat<5>.PIN
      2: N_PZ_30354        15: db<12>.PIN        27: mem_pointer<12>
      3: N_PZ_30373        16: db<13>            28: mem_pointer<13>
      4: N_PZ_30413        17: db<13>.PIN        29: mem_pointer<5>
      5: N_PZ_30489        18: db<2>.PIN         30: mevent_count<5>
      6: U4/_n0029         19: db<3>.PIN         31: mword_count<12>
      7: add<0>            20: db<5>             32: mword_count<13>
      8: add<1>            21: db<5>.PIN         33: mword_count<5>
      9: add<2>            22: enw1              34: num_cycles<12>
     10: add<3>            23: enw2              35: num_cycles<13>
     11: add<4>            24: mdat<12>.PIN      36: num_cycles<5>
     12: add<5>            25: mdat<13>.PIN      37: write
     13: cs

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<12>            X.X.X.XXXXXXXX.......XXX..X...X..X..X... 18      18
    db<5>             X.XXX.XXX..........X.....X..XX..X..XX... 14      14
    db<13>            X.X.X.XXXXXXX..X.....XX.X..X...X..X.X... 18      18
    U4/_n0051         ......XXXXXXX....X...XX................. 10      10
    U4/_n002121       ......XXXXXXX.......XXX.....X........... 11      11
    U4/_n001321       ......XXXXXXX...X....XX....X............ 11      11
    num_cycles<13>    ......XXXXXXX...X....XX................. 10      10
    mword_count<13>   .X...XXXXXXXX...X....XX........X........ 13      13
    mword_count<12>   .X...XXXXXXXX.X......XX.......X......... 13      13
    mword_count<5>    .X...XXXXXXXX.......XXX.........X....... 13      13
    num_cycles<5>     ......XXXXXXX.......XXX................. 10      10
    mevent_count<5>   ......XXXXXXX.......XXX................. 10      10
    num_cycles<3>     ......XXXXXXX.....X..XX................. 10      10
    mevent_count<3>   ......XXXXXXX.....X..XX................. 10      10
    num_cycles<2>     ......XXXXXXX....X...XX................. 10      10
    mevent_count<2>   ......XXXXXXX....X...XX................. 10      10
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB7 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   37/19
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<14>                            6       FB7_1   191   I/O      I/O
    num_cycles<9>                     2       FB7_2         (b)      (b)
    db<15>                            6       FB7_3   189   I/O      I/O
    db<2>                             7       FB7_4   188   I/O      I/O
    (unused)                          0       FB7_5   187   I/O      I
    mevent_count<9>                   2       FB7_6         (b)      (b)
    num_cycles<8>                     2       FB7_7         (b)      (b)
    mevent_count<8>                   2       FB7_8         (b)      (b)
    num_cycles<7>                     2       FB7_9         (b)      (b)
    mevent_count<7>                   2       FB7_10        (b)      (b)
    num_cycles<6>                     2       FB7_11        (b)      (b)
    mevent_count<6>                   2       FB7_12        (b)      (b)
    (unused)                          0       FB7_13  186   I/O      I
    num_cycles<15>                    2       FB7_14  185   I/O      I
    num_cycles<14>                    2       FB7_15  184   I/O      I
    num_cycles<11>                    2       FB7_16  183   I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: db<14>            26: mdat<2>.PIN
      2: N_PZ_30373        15: db<14>.PIN        27: mem_pointer<14>
      3: N_PZ_30413        16: db<15>            28: mem_pointer<15>
      4: N_PZ_30489        17: db<15>.PIN        29: mem_pointer<2>
      5: U4/ena_word_count2
                           18: db<6>.PIN         30: mevent_count<2>
      6: add<0>            19: db<7>.PIN         31: mword_count<14>
      7: add<1>            20: db<8>.PIN         32: mword_count<15>
      8: add<2>            21: db<9>.PIN         33: mword_count<2>
      9: add<3>            22: enw1              34: num_cycles<14>
     10: add<4>            23: enw2              35: num_cycles<15>
     11: add<5>            24: mdat<14>.PIN      36: num_cycles<2>
     12: cs                25: mdat<15>.PIN      37: write
     13: db<11>.PIN

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<14>            XX.X.XXXXXXX.X.......XXX..X...X..X..X... 18      18
    num_cycles<9>     .....XXXXXXX........XXX................. 10      10
    db<15>            XX.X.XXXXXXX...X.....XX.X..X...X..X.X... 18      18
    db<2>             XXXXXXXX.................X..XX..X..XX... 14      14
    mevent_count<9>   .....XXXXXXX........XXX................. 10      10
    num_cycles<8>     .....XXXXXXX.......X.XX................. 10      10
    mevent_count<8>   .....XXXXXXX.......X.XX................. 10      10
    num_cycles<7>     .....XXXXXXX......X..XX................. 10      10
    mevent_count<7>   .....XXXXXXX......X..XX................. 10      10
    num_cycles<6>     .....XXXXXXX.....X...XX................. 10      10
    mevent_count<6>   .....XXXXXXX.....X...XX................. 10      10
    num_cycles<15>    .....XXXXXXX....X....XX................. 10      10
    num_cycles<14>    .....XXXXXXX..X......XX................. 10      10
    num_cycles<11>    .....XXXXXXXX........XX................. 10      10
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB8 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   32/24
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB8_1         (b)
    db<6>                             7       FB8_2   22    I/O      I/O
    db<7>                             7       FB8_3   23    I/O      I/O
    (unused)                          0       FB8_4         (b)
    (unused)                          0       FB8_5         (b)
    (unused)                          0       FB8_6         (b)
    (unused)                          0       FB8_7         (b)
    (unused)                          0       FB8_8         (b)
    (unused)                          0       FB8_9         (b)
    (unused)                          0       FB8_10        (b)
    U4/_n001921                       2       FB8_11        (b)      (b)
    U4/_n001821                       2       FB8_12        (b)      (b)
    mword_count<8>                    3       FB8_13        (b)      (b)
    db<8>                             7       FB8_14  25    I/O      I/O
    mword_count<7>                    3       FB8_15        (b)      (b)
    mword_count<6>                    3       FB8_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: db<6>             26: mem_pointer<7>
      2: N_PZ_30354        15: db<6>.PIN         27: mem_pointer<8>
      3: N_PZ_30373        16: db<7>             28: mevent_count<6>
      4: N_PZ_30413        17: db<7>.PIN         29: mevent_count<7>
      5: N_PZ_30489        18: db<8>             30: mevent_count<8>
      6: U4/_n0029         19: db<8>.PIN         31: mword_count<6>
      7: add<0>            20: enw1              32: mword_count<7>
      8: add<1>            21: enw2              33: mword_count<8>
      9: add<2>            22: mdat<6>.PIN       34: num_cycles<6>
     10: add<3>            23: mdat<7>.PIN       35: num_cycles<7>
     11: add<4>            24: mdat<8>.PIN       36: num_cycles<8>
     12: add<5>            25: mem_pointer<6>    37: write
     13: cs

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<6>             X.XXX.XXX....X.......X..X..X..X..X..X... 14      14
    db<7>             X.XXX.XXX......X......X..X..X..X..X.X... 14      14
    U4/_n001921       ......XXXXXXX...X..XX....X.............. 11      11
    U4/_n001821       ......XXXXXXX.....XXX.....X............. 11      11
    mword_count<8>    .X...XXXXXXXX.....XXX...........X....... 13      13
    db<8>             X.XXX.XXX........X.....X..X..X..X..XX... 14      14
    mword_count<7>    .X...XXXXXXXX...X..XX..........X........ 13      13
    mword_count<6>    .X...XXXXXXXX.X....XX.........X......... 13      13
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB9 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  17
    Number of function block inputs used/remaining:               17/23
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   17/39
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U4/lfsr_0<8>                      1       FB9_1         (b)      (b)
    U4/lfsr_1<12>                     1       FB9_2   50    I/O      I
    enw1                              1       FB9_3   49    I/O      I
    U4/lfsr_1<11>                     1       FB9_4   48    I/O      I
    U4/lfsr_0<7>                      1       FB9_5         (b)      (b)
    U4/lfsr_0<6>                      1       FB9_6         (b)      (b)
    U4/lfsr_0<5>                      1       FB9_7         (b)      (b)
    U4/lfsr_0<4>                      1       FB9_8         (b)      (b)
    U4/lfsr_0<40>                     1       FB9_9         (b)      (b)
    U4/lfsr_0<3>                      1       FB9_10        (b)      (b)
    U4/lfsr_0<39>                     1       FB9_11        (b)      (b)
    U4/lfsr_0<0>                      2       FB9_12        (b)      (b)
    U4/lfsr_0<38>                     1       FB9_13        (b)      (b)
    U4/lfsr_1<10>                     1       FB9_14  47    I/O      I
    U4/lfsr_0<37>                     1       FB9_15        (b)      (b)
    U4/lfsr_0<9>                      1       FB9_16  46    GCK/I/O  GCK/I

    Signals Used by Logic in Function Block
      1: U4/lfsr_0<2>       7: U4/lfsr_0<40>     13: U4/lfsr_1<10>
      2: U4/lfsr_0<36>      8: U4/lfsr_0<4>      14: U4/lfsr_1<11>
      3: U4/lfsr_0<37>      9: U4/lfsr_0<5>      15: U4/lfsr_1<9>
      4: U4/lfsr_0<38>     10: U4/lfsr_0<6>      16: is_trigger_1
      5: U4/lfsr_0<39>     11: U4/lfsr_0<7>      17: is_trigger
      6: U4/lfsr_0<3>      12: U4/lfsr_0<8>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U4/lfsr_0<8>      ..........X............................. 1       1
    U4/lfsr_1<12>     .............X.......................... 1       1
    enw1              ...............XX....................... 2       2
    U4/lfsr_1<11>     ............X........................... 1       1
    U4/lfsr_0<7>      .........X.............................. 1       1
    U4/lfsr_0<6>      ........X............................... 1       1
    U4/lfsr_0<5>      .......X................................ 1       1
    U4/lfsr_0<4>      .....X.................................. 1       1
    U4/lfsr_0<40>     ....X................................... 1       1
    U4/lfsr_0<3>      X....................................... 1       1
    U4/lfsr_0<39>     ...X.................................... 1       1
    U4/lfsr_0<0>      ..X...X................................. 2       2
    U4/lfsr_0<38>     ..X..................................... 1       1
    U4/lfsr_1<10>     ..............X......................... 1       1
    U4/lfsr_0<37>     .X...................................... 1       1
    U4/lfsr_0<9>      ...........X............................ 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB10 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  32
    Number of function block inputs used/remaining:               32/8
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   27/29
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    tp5                               2       FB10_1  51    CDR/I/O  O
    txena                             2       FB10_2  54    I/O      I/O
    counter<11>                       2       FB10_3  55    GCK/I/O  GCK/I
    is_trigger_1                      0       FB10_4  56    I/O      I
    counter<14>                       2       FB10_5        (b)      (b)
    counter<17>                       2       FB10_6        (b)      (b)
    counter<16>                       2       FB10_7        (b)      (b)
    counter<15>                       2       FB10_8        (b)      (b)
    N_PZ_30394                        2       FB10_9        (b)      (b)
    U2/qlt                            2       FB10_10       (b)      (b)
    N_PZ_30489                        1       FB10_11       (b)      (b)
    U2/b2                             2       FB10_12       (b)      (b)
    counter<12>                       2       FB10_13 57    I/O      I
    counter<13>                       2       FB10_14 58    DGE/I/O  (b)
    U1/q2                             2       FB10_15       (b)      (b)
    dtack_blk                         2       FB10_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        12: brdsel24          23: cspare<11>
      2: N_PZ_30371        13: counter<10>       24: ds0
      3: N_PZ_30547        14: counter<11>       25: ds1
      4: N_PZ_30589        15: counter<12>       26: dsdly<1>
      5: am<0>             16: counter<13>       27: estado_FFD2
      6: am<1>             17: counter<14>       28: estado_FFD3
      7: am<2>             18: counter<15>       29: iack
      8: am<3>             19: counter<16>       30: lword
      9: am<4>             20: counter<17>       31: txena_reg_out
     10: am<5>             21: counter<8>        32: write
     11: as                22: counter<9>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    tp5               ....XXXXXX.X...........XXX..XX.......... 12      12
    txena             ......................X...XX..X......... 4       4
    counter<11>       XX.X........XX......XX.................. 7       7
    counter<14>       XXXX........XXXXX...XX.................. 11      11
    counter<17>       XXX..............XXX.................... 6       6
    counter<16>       XXX..............XX..................... 5       5
    counter<15>       XXX..............X...................... 4       4
    N_PZ_30394        X...XXXXXX.X................XX.......... 10      10
    U2/qlt            ....XXXXXXXX................XX.......... 10      10
    N_PZ_30489        ....X.XXXX.X...........XX...XX.......... 10      10
    U2/b2             ....XXXXXX.X.............X..XX.X........ 11      11
    counter<12>       XX.X........XXX.....XX.................. 8       8
    counter<13>       XX.X........XXXX....XX.................. 9       9
    U1/q2             ....XXXXXX.X.............X..XX.X........ 11      11
    dtack_blk         ....XXXXXX.X...........XXX..XX.......... 12      12
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB11 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   37/19
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U4/lfsr_1<13>                     1       FB11_1  45    I/O      (b)
    N_PZ_30589                        1       FB11_2        (b)      (b)
    N_PZ_30371                        1       FB11_3  44    GCK/I/O  GCK/I
    cycle_counter<0>                  3       FB11_4  43    I/O      (b)
    counter<4>                        2       FB11_5        (b)      (b)
    counter<5>                        2       FB11_6        (b)      (b)
    counter<6>                        2       FB11_7        (b)      (b)
    counter<7>                        2       FB11_8        (b)      (b)
    counter<8>                        2       FB11_9        (b)      (b)
    counter<9>                        2       FB11_10       (b)      (b)
    counter<10>                       2       FB11_11       (b)      (b)
    estado_FFD1                       11      FB11_12       (b)      (b)
    counter<2>                        2       FB11_13 41    I/O      (b)
    cspare<11>                        1       FB11_14 40    I/O      O
    cspare<10>                        1       FB11_15 39    I/O      O
    counter<3>                        2       FB11_16 38    I/O      (b)

    Signals Used by Logic in Function Block
      1: Mcompar__n0026__n0034
                           14: counter<10>       27: estado_FFD1
      2: Mcompar__n0029__n0027
                           15: counter<2>        28: estado_FFD2
      3: Mcompar__n0029__n0029
                           16: counter<3>        29: estado_FFD3
      4: N_PZ_30322        17: counter<4>        30: estado_XX_FFD135
      5: N_PZ_30371        18: counter<5>        31: estado_XX_FFD136
      6: N_PZ_30372        19: counter<6>        32: estado_XX_FFD146
      7: N_PZ_30405        20: counter<7>        33: estado_XX_FFD153
      8: N_PZ_30510        21: counter<8>        34: mem_is_full
      9: N_PZ_30539        22: counter<9>        35: mevent_count<10>
     10: N_PZ_30589        23: cycle_counter<0>  36: mevent_count<8>
     11: N_PZ_30591        24: db<3>             37: num_cycles<0>
     12: U4/ena_word_count2
                           25: ena_ceros_mem     38: vspare_0
     13: U4/lfsr_1<12>     26: ena_gol_test

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U4/lfsr_1<13>     ............X........................... 1       1
    N_PZ_30589        ..........X...XXXXXX.................... 7       7
    N_PZ_30371        ..........................XXX........... 3       3
    cycle_counter<0>  ...XX.................X.............X... 4       4
    counter<4>        ...XX.....X...XXX....................... 6       6
    counter<5>        ...XX.....X...XXXX...................... 7       7
    counter<6>        ...XX.....X...XXXXX..................... 8       8
    counter<7>        ...XX....XX...XXXXXX.................... 10      10
    counter<8>        ...XX....X..........X................... 4       4
    counter<9>        ...XX....X..........XX.................. 5       5
    counter<10>       ...XX....X...X......XX.................. 6       6
    estado_FFD1       XXX..XXXX..X.X......X..XXXXXXXXXXXXX.... 23      23
    counter<2>        ...XX.....X...X......................... 4       4
    cspare<11>        ..........................XXX........... 3       3
    cspare<10>        .....................................X.. 1       1
    counter<3>        ...XX.....X...XX........................ 5       5
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB12 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   30/26
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<9>                             7       FB12_1  60    I/O      I/O
    db<4>                             7       FB12_2  61    I/O      I/O
    (unused)                          0       FB12_3  62    I/O
    (unused)                          0       FB12_4  63    I/O
    (unused)                          0       FB12_5  64    I/O
    (unused)                          0       FB12_6        (b)
    (unused)                          0       FB12_7        (b)
    (unused)                          0       FB12_8        (b)
    (unused)                          0       FB12_9        (b)
    N_PZ_30575                        1       FB12_10       (b)      (b)
    mem_pointer<4>                    5       FB12_11       (b)      (b)
    mem_pointer<6>                    7       FB12_12       (b)      (b)
    (unused)                          0       FB12_13 65    I/O
    (unused)                          0       FB12_14 66    I/O
    (unused)                          0       FB12_15 67    I/O
    mem_pointer<9>                    5       FB12_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: add<4>            26: mem_pointer<4>
      2: N_PZ_30373        15: add<5>            27: mem_pointer<5>
      3: N_PZ_30413        16: cs                28: mem_pointer<6>
      4: N_PZ_30489        17: db<4>             29: mem_pointer<7>
      5: N_PZ_30575        18: db<4>.PIN         30: mem_pointer<8>
      6: N_PZ_30580        19: db<6>.PIN         31: mem_pointer<9>
      7: U4/_n00084        20: db<9>             32: mevent_count<9>
      8: U4/_n0081         21: db<9>.PIN         33: mword_count<4>
      9: U4/ena_fill_mem   22: enw1              34: mword_count<9>
     10: add<0>            23: enw2              35: num_cycles<4>
     11: add<1>            24: mdat<4>.PIN       36: num_cycles<9>
     12: add<2>            25: mdat<9>.PIN       37: write
     13: add<3>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<9>             XXXX.....XXX.......X....X.....XX.X.XX... 14      14
    db<4>             XX.X....XXXXXXXXX....XXX.X......X.X.X... 19      19
    N_PZ_30575        .....X...................XXXXXX......... 7       7
    mem_pointer<4>    .....XXX.XXXXXXX.X...XX..X.............. 14      14
    mem_pointer<6>    .....XXX.XXXXXXX..X..XX..XXX............ 16      16
    mem_pointer<9>    ....XXXX.XXXXXXX....XXX..XXXXXX......... 20      20
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB13 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  13
    Number of function block inputs used/remaining:               13/27
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   13/43
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U4/lfsr_1<25>                     1       FB13_1  37    I/O      (b)
    U4/lfsr_1<23>                     1       FB13_2        (b)      (b)
    mspare_3                          0       FB13_3  36    I/O      O
    cspare<7>                         0       FB13_4  35    I/O      O
    U4/lfsr_1<22>                     1       FB13_5        (b)      (b)
    U4/lfsr_1<21>                     1       FB13_6        (b)      (b)
    U4/lfsr_1<20>                     1       FB13_7        (b)      (b)
    U4/lfsr_1<1>                      1       FB13_8        (b)      (b)
    U4/lfsr_1<19>                     1       FB13_9        (b)      (b)
    U4/lfsr_1<18>                     1       FB13_10       (b)      (b)
    U4/lfsr_1<17>                     1       FB13_11       (b)      (b)
    U4/lfsr_1<16>                     1       FB13_12       (b)      (b)
    U4/lfsr_1<15>                     1       FB13_13       (b)      (b)
    cspare<6>                         0       FB13_14 34    I/O      O
    U4/lfsr_1<24>                     1       FB13_15 32    I/O      (b)
    U4/lfsr_1<14>                     1       FB13_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: U4/lfsr_1<0>       6: U4/lfsr_1<17>     10: U4/lfsr_1<21>
      2: U4/lfsr_1<13>      7: U4/lfsr_1<18>     11: U4/lfsr_1<22>
      3: U4/lfsr_1<14>      8: U4/lfsr_1<19>     12: U4/lfsr_1<23>
      4: U4/lfsr_1<15>      9: U4/lfsr_1<20>     13: U4/lfsr_1<24>
      5: U4/lfsr_1<16>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U4/lfsr_1<25>     ............X........................... 1       1
    U4/lfsr_1<23>     ..........X............................. 1       1
    mspare_3          ........................................ 0       0
    cspare<7>         ........................................ 0       0
    U4/lfsr_1<22>     .........X.............................. 1       1
    U4/lfsr_1<21>     ........X............................... 1       1
    U4/lfsr_1<20>     .......X................................ 1       1
    U4/lfsr_1<1>      X....................................... 1       1
    U4/lfsr_1<19>     ......X................................. 1       1
    U4/lfsr_1<18>     .....X.................................. 1       1
    U4/lfsr_1<17>     ....X................................... 1       1
    U4/lfsr_1<16>     ...X.................................... 1       1
    U4/lfsr_1<15>     ..X..................................... 1       1
    cspare<6>         ........................................ 0       0
    U4/lfsr_1<24>     ...........X............................ 1       1
    U4/lfsr_1<14>     .X...................................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB14 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   26/30
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB14_1        (b)
    (unused)                          0       FB14_2        (b)
    (unused)                          0       FB14_3  69    I/O
    (unused)                          0       FB14_4  70    I/O
    (unused)                          0       FB14_5  71    I/O
    U4/lfsr_1<2>                      1       FB14_6        (b)      (b)
    U4/lfsr_1<29>                     1       FB14_7        (b)      (b)
    U4/lfsr_1<0>                      2       FB14_8        (b)      (b)
    U4/lfsr_1<28>                     1       FB14_9        (b)      (b)
    U4/lfsr_1<27>                     1       FB14_10       (b)      (b)
    U4/lfsr_1<26>                     1       FB14_11       (b)      (b)
    estado_XX_FFD135                  14      FB14_12       (b)      (b)
    (unused)                          0       FB14_13 72    I/O
    estado_XX_FFD146                  3       FB14_14       (b)      (b)
    (unused)                          0       FB14_15 73    I/O
    N_PZ_30599                        2       FB14_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: Mcompar__n0026__n0034
                           14: counter<1>        27: enw1.COMB
      2: U4/ena_word_count2
                           15: counter<2>        28: estado_FFD2
      3: U4/lfsr_1<1>      16: counter<3>        29: estado_FFD3
      4: U4/lfsr_1<25>     17: db<0>             30: mem_is_full
      5: U4/lfsr_1<26>     18: db<11>            31: mevent_count<10>
      6: U4/lfsr_1<27>     19: db<12>            32: mevent_count<2>
      7: U4/lfsr_1<28>     20: db<13>            33: mevent_count<3>
      8: U4/lfsr_1<30>     21: db<14>            34: mevent_count<5>
      9: counter<0>        22: db<15>            35: mevent_count<6>
     10: counter<12>       23: db<1>             36: mevent_count<7>
     11: counter<15>       24: db<3>             37: mevent_count<8>
     12: counter<16>       25: db<4>             38: mevent_count<9>
     13: counter<17>       26: ena_ceros_mem

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U4/lfsr_1<2>      ..X..................................... 1       1
    U4/lfsr_1<29>     ......X................................. 1       1
    U4/lfsr_1<0>      .....X.X................................ 2       2
    U4/lfsr_1<28>     .....X.................................. 1       1
    U4/lfsr_1<27>     ....X................................... 1       1
    U4/lfsr_1<26>     ...X.................................... 1       1
    estado_XX_FFD135  ........XXXXXXXXX.X..XX........XX....... 14      14
    estado_XX_FFD146  ................XXXXXXXXX.XXX.XXXXXXXX.. 20      20
    N_PZ_30599        XX..............XXXXXXXXXXXX.XXXXXXXXX.. 23      23
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB15 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  14
    Number of function block inputs used/remaining:               14/26
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   14/42
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    dout_reg_in<14>                   1       FB15_1  31    I/O      (b)
    dout_reg_in<11>                   1       FB15_2        (b)      (b)
    cspare<3>                         0       FB15_3  30    I/O      O
    cspare<2>                         0       FB15_4  29    I/O      O
    dout_reg_in<10>                   1       FB15_5        (b)      (b)
    dout_reg_in<0>                    1       FB15_6        (b)      (b)
    U4/lfsr_1<9>                      1       FB15_7        (b)      (b)
    U4/lfsr_1<8>                      1       FB15_8        (b)      (b)
    U4/lfsr_1<7>                      1       FB15_9        (b)      (b)
    U4/lfsr_1<6>                      1       FB15_10       (b)      (b)
    U4/lfsr_1<5>                      1       FB15_11       (b)      (b)
    U4/lfsr_1<4>                      1       FB15_12       (b)      (b)
    dout_reg_in<13>                   1       FB15_13 28    I/O      (b)
    dout_reg_in<12>                   1       FB15_14 27    I/O      (b)
    U4/lfsr_1<3>                      1       FB15_15       (b)      (b)
    U4/lfsr_1<30>                     1       FB15_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: U4/lfsr_1<29>      6: U4/lfsr_1<6>      11: dout_reg_in_2<11>
      2: U4/lfsr_1<2>       7: U4/lfsr_1<7>      12: dout_reg_in_2<12>
      3: U4/lfsr_1<3>       8: U4/lfsr_1<8>      13: dout_reg_in_2<13>
      4: U4/lfsr_1<4>       9: dout_reg_in_2<0>  14: dout_reg_in_2<14>
      5: U4/lfsr_1<5>      10: dout_reg_in_2<10>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    dout_reg_in<14>   .............X.......................... 1       1
    dout_reg_in<11>   ..........X............................. 1       1
    cspare<3>         ........................................ 0       0
    cspare<2>         ........................................ 0       0
    dout_reg_in<10>   .........X.............................. 1       1
    dout_reg_in<0>    ........X............................... 1       1
    U4/lfsr_1<9>      .......X................................ 1       1
    U4/lfsr_1<8>      ......X................................. 1       1
    U4/lfsr_1<7>      .....X.................................. 1       1
    U4/lfsr_1<6>      ....X................................... 1       1
    U4/lfsr_1<5>      ...X.................................... 1       1
    U4/lfsr_1<4>      ..X..................................... 1       1
    dout_reg_in<13>   ............X........................... 1       1
    dout_reg_in<12>   ...........X............................ 1       1
    U4/lfsr_1<3>      .X...................................... 1       1
    U4/lfsr_1<30>     X....................................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB16 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   30/26
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    madd<17>                          3       FB16_1  74    I/O      O
    (unused)                          0       FB16_2        (b)
    madd<16>                          3       FB16_3  75    I/O      O
    madd<15>                          3       FB16_4  76    I/O      O
    madd<14>                          3       FB16_5  77    I/O      O
    (unused)                          0       FB16_6        (b)
    (unused)                          0       FB16_7        (b)
    (unused)                          0       FB16_8        (b)
    (unused)                          0       FB16_9        (b)
    dout_reg_in<15>                   1       FB16_10       (b)      (b)
    mem_pointer<11>                   4       FB16_11       (b)      (b)
    N_PZ_30542                        1       FB16_12       (b)      (b)
    mem_pointer<13>                   4       FB16_13       (b)      (b)
    madd<13>                          3       FB16_14 78    I/O      O
    mem_pointer<16>                   4       FB16_15       (b)      (b)
    mem_pointer<17>                   4       FB16_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: U4/_n001521       27: brdsel24
      2: N_PZ_30394        15: U4/_n0081         28: dout_reg_in_2<15>
      3: N_PZ_30542        16: add<13>           29: iack
      4: N_PZ_30575        17: add<14>           30: lword
      5: U3/add_latched<5> 18: add<15>           31: mem_pointer<10>
      6: U3/add_latched<6> 19: add<16>           32: mem_pointer<11>
      7: U3/add_latched<7> 20: add<17>           33: mem_pointer<12>
      8: U3/add_latched<8> 21: am<0>             34: mem_pointer<13>
      9: U3/add_latched<9> 22: am<1>             35: mem_pointer<14>
     10: U4/_n00084        23: am<2>             36: mem_pointer<15>
     11: U4/_n000921       24: am<3>             37: mem_pointer<16>
     12: U4/_n001021       25: am<4>             38: mem_pointer<17>
     13: U4/_n001321       26: am<5>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<17>          XX......X..........XXXXXXXX.XX.......X.. 14      14
    madd<16>          XX.....X..........X.XXXXXXX.XX......X... 14      14
    madd<15>          XX....X..........X..XXXXXXX.XX.....X.... 14      14
    madd<14>          XX...X..........X...XXXXXXX.XX....X..... 14      14
    dout_reg_in<15>   ...........................X............ 1       1
    mem_pointer<11>   ...X.....X...XX...............XX........ 6       6
    N_PZ_30542        ...X..........................XXXXX..... 6       6
    mem_pointer<13>   ...X.....X..X.X...............XXXX...... 8       8
    madd<13>          XX..X..........X....XXXXXXX.XX...X...... 14      14
    mem_pointer<16>   ..X......X.X..X....................XX... 6       6
    mem_pointer<17>   ..X......XX...X....................XXX.. 7       7
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB17 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  25
    Number of function block inputs used/remaining:               25/15
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   25/31
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    tp8                               1       FB17_1  161   I/O      O
    mdat<0>                           2       FB17_2  162   I/O      I/O
    mdat<10>                          2       FB17_3  163   I/O      I/O
    mdat<11>                          2       FB17_4  164   I/O      I/O
    mdat<12>                          2       FB17_5  165   I/O      I/O
    dout_reg_in<6>                    1       FB17_6        (b)      (b)
    dout_reg_in<5>                    1       FB17_7        (b)      (b)
    dout_reg_in<4>                    1       FB17_8        (b)      (b)
    dout_reg_in<3>                    1       FB17_9        (b)      (b)
    dout_reg_in<2>                    1       FB17_10       (b)      (b)
    dout_reg_in<1>                    1       FB17_11       (b)      (b)
    ULED/q3                           2       FB17_12       (b)      (b)
    mdat<13>                          2       FB17_13 166   I/O      I/O
    mdat<14>                          2       FB17_14 167   I/O      I/O
    mdat<15>                          2       FB17_15 168   I/O      I/O
    mdat<1>                           2       FB17_16 169   I/O      I/O

    Signals Used by Logic in Function Block
      1: N_PZ_30353        10: db<1>.PIN         18: dout_reg_in<1>
      2: clk_slow          11: dout_reg_in<0>    19: dout_reg_in_2<1>
      3: db<0>.PIN         12: dout_reg_in<10>   20: dout_reg_in_2<2>
      4: db<10>.PIN        13: dout_reg_in<11>   21: dout_reg_in_2<3>
      5: db<11>.PIN        14: dout_reg_in<12>   22: dout_reg_in_2<4>
      6: db<12>.PIN        15: dout_reg_in<13>   23: dout_reg_in_2<5>
      7: db<13>.PIN        16: dout_reg_in<14>   24: dout_reg_in_2<6>
      8: db<14>.PIN        17: dout_reg_in<15>   25: trigger_led
      9: db<15>.PIN

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    tp8               .X...................................... 1       1
    mdat<0>           X.X.......X............................. 3       3
    mdat<10>          X..X.......X............................ 3       3
    mdat<11>          X...X.......X........................... 3       3
    mdat<12>          X....X.......X.......................... 3       3
    dout_reg_in<6>    .......................X................ 1       1
    dout_reg_in<5>    ......................X................. 1       1
    dout_reg_in<4>    .....................X.................. 1       1
    dout_reg_in<3>    ....................X................... 1       1
    dout_reg_in<2>    ...................X.................... 1       1
    dout_reg_in<1>    ..................X..................... 1       1
    ULED/q3           .X......................X............... 2       2
    mdat<13>          X.....X.......X......................... 3       3
    mdat<14>          X......X.......X........................ 3       3
    mdat<15>          X.......X.......X....................... 3       3
    mdat<1>           X........X.......X...................... 3       3
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB18 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  14
    Number of function block inputs used/remaining:               14/26
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   14/42
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    dout_reg_in_2<4>                  1       FB18_1  160   I/O      (b)
    dout_reg_in_2<3>                  1       FB18_2        (b)      (b)
    dout_reg_in_2<2>                  1       FB18_3        (b)      (b)
    cspare<4>                         0       FB18_4  159   I/O      O
    dout_reg_in_2<1>                  1       FB18_5        (b)      (b)
    dout_reg_in_2<15>                 1       FB18_6        (b)      (b)
    dout_reg_in_2<14>                 1       FB18_7        (b)      (b)
    dout_reg_in_2<13>                 1       FB18_8        (b)      (b)
    dout_reg_in_2<12>                 1       FB18_9        (b)      (b)
    dout_reg_in_2<11>                 1       FB18_10       (b)      (b)
    dout_reg_in_2<10>                 1       FB18_11       (b)      (b)
    dout_reg_in_2<0>                  1       FB18_12       (b)      (b)
    dout_reg_in<9>                    1       FB18_13       (b)      (b)
    dout_reg_in<8>                    1       FB18_14       (b)      (b)
    cspare<5>                         0       FB18_15 158   I/O      O
    dout_reg_in<7>                    1       FB18_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: dout<0>.PIN        6: dout<14>.PIN      11: dout<4>.PIN
      2: dout<10>.PIN       7: dout<15>.PIN      12: dout_reg_in_2<7>
      3: dout<11>.PIN       8: dout<1>.PIN       13: dout_reg_in_2<8>
      4: dout<12>.PIN       9: dout<2>.PIN       14: dout_reg_in_2<9>
      5: dout<13>.PIN      10: dout<3>.PIN

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    dout_reg_in_2<4>  ..........X............................. 1       1
    dout_reg_in_2<3>  .........X.............................. 1       1
    dout_reg_in_2<2>  ........X............................... 1       1
    cspare<4>         ........................................ 0       0
    dout_reg_in_2<1>  .......X................................ 1       1
    dout_reg_in_2<15>
                      ......X................................. 1       1
    dout_reg_in_2<14>
                      .....X.................................. 1       1
    dout_reg_in_2<13>
                      ....X................................... 1       1
    dout_reg_in_2<12>
                      ...X.................................... 1       1
    dout_reg_in_2<11>
                      ..X..................................... 1       1
    dout_reg_in_2<10>
                      .X...................................... 1       1
    dout_reg_in_2<0>  X....................................... 1       1
    dout_reg_in<9>    .............X.......................... 1       1
    dout_reg_in<8>    ............X........................... 1       1
    cspare<5>         ........................................ 0       0
    dout_reg_in<7>    ...........X............................ 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB19 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   12/44
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    madd<12>                          3       FB19_1  170   I/O      O
    madd<11>                          3       FB19_2  171   I/O      O
    madd<10>                          3       FB19_3  173   I/O      O
    (unused)                          0       FB19_4        (b)
    (unused)                          0       FB19_5        (b)
    (unused)                          0       FB19_6        (b)
    (unused)                          0       FB19_7        (b)
    (unused)                          0       FB19_8        (b)
    (unused)                          0       FB19_9        (b)
    (unused)                          0       FB19_10       (b)
    (unused)                          0       FB19_11       (b)
    (unused)                          0       FB19_12       (b)
    (unused)                          0       FB19_13       (b)
    (unused)                          0       FB19_14       (b)
    N_PZ_30580                        1       FB19_15       (b)      (b)
    mem_is_full                       2       FB19_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: am<4>             27: mem_pointer<16>
      2: N_PZ_30394        15: am<5>             28: mem_pointer<17>
      3: U3/add_latched<2> 16: brdsel24          29: mem_pointer<1>
      4: U3/add_latched<3> 17: iack              30: mem_pointer<2>
      5: U3/add_latched<4> 18: lword             31: mem_pointer<3>
      6: U4/_n0051         19: mem_is_full       32: mem_pointer<4>
      7: add<10>           20: mem_pointer<0>    33: mem_pointer<5>
      8: add<11>           21: mem_pointer<10>   34: mem_pointer<6>
      9: add<12>           22: mem_pointer<11>   35: mem_pointer<7>
     10: am<0>             23: mem_pointer<12>   36: mem_pointer<8>
     11: am<1>             24: mem_pointer<13>   37: mem_pointer<9>
     12: am<2>             25: mem_pointer<14>   38: tp7
     13: am<3>             26: mem_pointer<15>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<12>          XX..X...XXXXXXXXXX....X................. 14      14
    madd<11>          XX.X...X.XXXXXXXXX...X.................. 14      14
    madd<10>          XXX...X..XXXXXXXXX..X................... 14      14
    N_PZ_30580        ..................XX........XXX......X.. 6       6
    mem_is_full       .....X............XXXXXXXXXXXXXXXXXXXX.. 21      21
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB20 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   39/17
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB20_1        (b)
    dout_reg_in_2<5>                  1       FB20_2        (b)      (b)
    we                                3       FB20_3  155   I/O      O
    mdat<2>                           2       FB20_4  154   I/O      I/O
    cycle_counter<6>                  3       FB20_5        (b)      (b)
    cycle_counter<5>                  3       FB20_6        (b)      (b)
    cycle_counter<4>                  3       FB20_7        (b)      (b)
    cycle_counter<3>                  3       FB20_8        (b)      (b)
    cycle_counter<2>                  3       FB20_9        (b)      (b)
    cycle_counter<1>                  3       FB20_10       (b)      (b)
    cycle_counter<15>                 4       FB20_11       (b)      (b)
    cycle_counter<14>                 3       FB20_12       (b)      (b)
    mdat<3>                           2       FB20_13 153   I/O      I/O
    mdat<4>                           2       FB20_14 152   I/O      I/O
    mdat<5>                           2       FB20_15 151   I/O      I/O
    mdat<6>                           2       FB20_16 150   I/O      I/O

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: cycle_counter<5>  26: dout_reg_in<6>
      2: N_PZ_30353        15: cycle_counter<6>  27: estado_FFD2
      3: N_PZ_30371        16: db<2>.PIN         28: estado_FFD3
      4: U1/q2             17: db<3>.PIN         29: num_cycles<14>
      5: U2/b2             18: db<4>.PIN         30: num_cycles<15>
      6: _n0033<14>2       19: db<5>.PIN         31: num_cycles<1>
      7: cycle_counter<0>  20: db<6>.PIN         32: num_cycles<2>
      8: cycle_counter<14> 21: dout<5>.PIN       33: num_cycles<3>
      9: cycle_counter<15> 22: dout_reg_in<2>    34: num_cycles<4>
     10: cycle_counter<1>  23: dout_reg_in<3>    35: num_cycles<5>
     11: cycle_counter<2>  24: dout_reg_in<4>    36: num_cycles<6>
     12: cycle_counter<3>  25: dout_reg_in<5>    37: we_fifo
     13: cycle_counter<4>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    dout_reg_in_2<5>  ....................X................... 1       1
    we                X..XX.....................XX........X... 6       6
    mdat<2>           .X.............X.....X.................. 3       3
    cycle_counter<6>  X.X...X..XXXXXX....................X.... 10      10
    cycle_counter<5>  X.X...X..XXXXX....................X..... 9       9
    cycle_counter<4>  X.X...X..XXXX....................X...... 8       8
    cycle_counter<3>  X.X...X..XXX....................X....... 7       7
    cycle_counter<2>  X.X...X..XX....................X........ 6       6
    cycle_counter<1>  X.X...X..X....................X......... 5       5
    cycle_counter<15>
                      X.X..X.XX....................X.......... 6       6
    cycle_counter<14>
                      X.X..X.X....................X........... 5       5
    mdat<3>           .X..............X.....X................. 3       3
    mdat<4>           .X...............X.....X................ 3       3
    mdat<5>           .X................X.....X............... 3       3
    mdat<6>           .X.................X.....X.............. 3       3
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB21 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   34/22
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    _n0033<14>2                       2       FB21_1        (b)      (b)
    (unused)                          0       FB21_2  174   I/O      I
    U4/_n00084                        1       FB21_3  175   I/O      I
    cycle_counter<13>                 3       FB21_4        (b)      (b)
    estado_XX_FFD153                  5       FB21_5  178   I/O      (b)
    cycle_counter<12>                 3       FB21_6        (b)      (b)
    cycle_counter<11>                 3       FB21_7        (b)      (b)
    cycle_counter<10>                 3       FB21_8        (b)      (b)
    cycle_counter<9>                  3       FB21_9        (b)      (b)
    cycle_counter<8>                  3       FB21_10       (b)      (b)
    cycle_counter<7>                  3       FB21_11       (b)      (b)
    txena_reg_out                     1       FB21_12       (b)      (b)
    dout_reg_in_2<9>                  1       FB21_13       (b)      (b)
    dout_reg_in_2<8>                  1       FB21_14       (b)      (b)
    dout_reg_in_2<7>                  1       FB21_15       (b)      (b)
    dout_reg_in_2<6>                  1       FB21_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: cycle_counter<4>  27: estado_FFD1
      2: N_PZ_30371        15: cycle_counter<5>  28: estado_FFD2
      3: U4/_n0051         16: cycle_counter<6>  29: estado_FFD3
      4: cycle_counter<0>  17: cycle_counter<7>  30: num_cycles<10>
      5: cycle_counter<10> 18: cycle_counter<8>  31: num_cycles<11>
      6: cycle_counter<11> 19: cycle_counter<9>  32: num_cycles<12>
      7: cycle_counter<12> 20: db<5>             33: num_cycles<13>
      8: cycle_counter<13> 21: dout<6>.PIN       34: num_cycles<7>
      9: cycle_counter<14> 22: dout<7>.PIN       35: num_cycles<8>
     10: cycle_counter<15> 23: dout<8>.PIN       36: num_cycles<9>
     11: cycle_counter<1>  24: dout<9>.PIN       37: reset
     12: cycle_counter<2>  25: ena_ceros_mem     38: txena_out
     13: cycle_counter<3>  26: ena_gol_test

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    _n0033<14>2       .X.XXXXXX.XXXXXXXXX..................... 16      16
    U4/_n00084        .XX.................................X... 3       3
    cycle_counter<13>
                      XX.XXXXX..XXXXXXXXX.............X....... 17      17
    estado_XX_FFD153  ...XXXXXXXXXXXXXXXXX....XXXXX........... 22      22
    cycle_counter<12>
                      XX.XXXX...XXXXXXXXX............X........ 16      16
    cycle_counter<11>
                      XX.XXX....XXXXXXXXX...........X......... 15      15
    cycle_counter<10>
                      XX.XX.....XXXXXXXXX..........X.......... 14      14
    cycle_counter<9>  XX.X......XXXXXXXXX................X.... 13      13
    cycle_counter<8>  XX.X......XXXXXXXX................X..... 12      12
    cycle_counter<7>  XX.X......XXXXXXX................X...... 11      11
    txena_reg_out     .....................................X.. 1       1
    dout_reg_in_2<9>  .......................X................ 1       1
    dout_reg_in_2<8>  ......................X................. 1       1
    dout_reg_in_2<7>  .....................X.................. 1       1
    dout_reg_in_2<6>  ....................X................... 1       1
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB22 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  36
    Number of function block inputs used/remaining:               36/4
    Number of function block control terms used/remaining:        3/1
    Number of PLA product terms used/remaining:                   28/28
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mdat<7>                           2       FB22_1  149   I/O      I/O
    mdat<8>                           2       FB22_2  148   I/O      I/O
    mdat<9>                           2       FB22_3  147   I/O      I/O
    g245_mem                          1       FB22_4  146   I/O      O
    (unused)                          0       FB22_5        (b)
    (unused)                          0       FB22_6        (b)
    (unused)                          0       FB22_7        (b)
    (unused)                          0       FB22_8        (b)
    we_fifo                           1       FB22_9        (b)      (b)
    U2/latch3                         2       FB22_10       (b)      (b)
    U3/counter_add<1>                 6       FB22_11       (b)      (b)
    U3/counter_add<2>                 7       FB22_12       (b)      (b)
    oe                                2       FB22_13 145   I/O      O
    madd<1>                           3       FB22_14 144   I/O      O
    madd<2>                           3       FB22_15 143   I/O      O
    (unused)                          0       FB22_16 142   I/O

    Signals Used by Logic in Function Block
      1: N_PZ_30322        13: am<1>             25: dout_reg_in<8>
      2: N_PZ_30353        14: am<2>             26: dout_reg_in<9>
      3: N_PZ_30394        15: am<3>             27: ds0
      4: N_PZ_30489        16: am<4>             28: ds1
      5: U2/latch3         17: am<5>             29: dsdly<0>
      6: U2/qlt            18: brdsel24          30: dsdly<1>
      7: U3/counter_add<0> 19: clk               31: iack
      8: U3/counter_add<1> 20: cspare<11>        32: lword
      9: U3/counter_add<2> 21: db<7>.PIN         33: mem_pointer<1>
     10: add<1>            22: db<8>.PIN         34: mem_pointer<2>
     11: add<2>            23: db<9>.PIN         35: txena
     12: am<0>             24: dout_reg_in<7>    36: write

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mdat<7>           .X..................X..X................ 3       3
    mdat<8>           .X...................X..X............... 3       3
    mdat<9>           .X....................X..X.............. 3       3
    g245_mem          ...........X.XXXXX........XX..XX........ 10      10
    we_fifo           ..................X...............X..... 2       2
    U2/latch3         .....X....................XX............ 3       3
    U3/counter_add<1>
                      ....X.XX.X..................XX.......... 6       6
    U3/counter_add<2>
                      ....X.XXX.X.................XX.......... 7       7
    oe                ...X...............X...............X.... 3       3
    madd<1>           X.X....X.X.XXXXXXX............XXX....... 14      14
    madd<2>           X.X.....X.XXXXXXXX............XX.X...... 14      14
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB23 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        3/1
    Number of PLA product terms used/remaining:                   41/15
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    madd<3>                           3       FB23_1  179   I/O      O
    madd<4>                           3       FB23_2  180   I/O      O
    (unused)                          0       FB23_3        (b)
    madd<6>                           3       FB23_4  182   I/O      O
    (unused)                          0       FB23_5        (b)
    (unused)                          0       FB23_6        (b)
    (unused)                          0       FB23_7        (b)
    (unused)                          0       FB23_8        (b)
    (unused)                          0       FB23_9        (b)
    (unused)                          0       FB23_10       (b)
    (unused)                          0       FB23_11       (b)
    mem_pointer<5>                    4       FB23_12       (b)      (b)
    mem_pointer<8>                    4       FB23_13       (b)      (b)
    mem_pointer<7>                    4       FB23_14       (b)      (b)
    U3/counter_add<7>                 12      FB23_15       (b)      (b)
    U3/counter_add<6>                 11      FB23_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: U4/_n001821       27: am<5>
      2: N_PZ_30394        15: U4/_n001921       28: brdsel24
      3: N_PZ_30580        16: U4/_n002121       29: dsdly<0>
      4: U2/latch3         17: U4/_n0081         30: dsdly<1>
      5: U3/counter_add<0> 18: add<3>            31: iack
      6: U3/counter_add<1> 19: add<4>            32: lword
      7: U3/counter_add<2> 20: add<6>            33: mem_pointer<3>
      8: U3/counter_add<3> 21: add<7>            34: mem_pointer<4>
      9: U3/counter_add<4> 22: am<0>             35: mem_pointer<5>
     10: U3/counter_add<5> 23: am<1>             36: mem_pointer<6>
     11: U3/counter_add<6> 24: am<2>             37: mem_pointer<7>
     12: U3/counter_add<7> 25: am<3>             38: mem_pointer<8>
     13: U4/_n00084        26: am<4>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<3>           XX.....X.........X...XXXXXXX..XXX....... 14      14
    madd<4>           XX......X.........X..XXXXXXX..XX.X...... 14      14
    madd<6>           XX........X........X.XXXXXXX..XX...X.... 14      14
    mem_pointer<5>    ..X.........X..XX................XX..... 6       6
    mem_pointer<8>    ..X.........XX..X................XXXXX.. 9       9
    mem_pointer<7>    ..X.........X.X.X................XXXX... 8       8
    U3/counter_add<7>
                      ...XXXXXXXXX........X.......XX.......... 12      12
    U3/counter_add<6>
                      ...XXXXXXXX........X........XX.......... 11      11
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB24 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        3/1
    Number of PLA product terms used/remaining:                   31/25
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    madd<8>                           3       FB24_1  140   I/O      O
    madd<9>                           3       FB24_2  139   I/O      O
    madd<7>                           3       FB24_3  138   I/O      O
    madd<5>                           3       FB24_4  137   I/O      O
    (unused)                          0       FB24_5        (b)
    (unused)                          0       FB24_6        (b)
    (unused)                          0       FB24_7        (b)
    (unused)                          0       FB24_8        (b)
    (unused)                          0       FB24_9        (b)
    _n003432                          1       FB24_10       (b)      (b)
    ULED/q1                           2       FB24_11       (b)      (b)
    U3/counter_add<4>                 9       FB24_12       (b)      (b)
    (unused)                          0       FB24_13 136   I/O
    (unused)                          0       FB24_14 135   I/O      I
    mspare_1                          0       FB24_15 134   I/O      O
    U3/counter_add<5>                 10      FB24_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: ULED/q3           26: brdsel24
      2: N_PZ_30394        15: add<4>            27: dsdly<0>
      3: U2/latch3         16: add<5>            28: dsdly<1>
      4: U3/add_latched<0> 17: add<7>            29: enw1.COMB
      5: U3/add_latched<1> 18: add<8>            30: estado_XX_FFD146
      6: U3/counter_add<0> 19: add<9>            31: iack
      7: U3/counter_add<1> 20: am<0>             32: lword
      8: U3/counter_add<2> 21: am<1>             33: mem_pointer<5>
      9: U3/counter_add<3> 22: am<2>             34: mem_pointer<7>
     10: U3/counter_add<4> 23: am<3>             35: mem_pointer<8>
     11: U3/counter_add<5> 24: am<4>             36: mem_pointer<9>
     12: U3/counter_add<7> 25: am<5>             37: txena
     13: ULED/q1

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    madd<8>           XX.X.............X.XXXXXXX....XX..X..... 14      14
    madd<9>           XX..X.............XXXXXXXX....XX...X.... 14      14
    madd<7>           XX.........X....X..XXXXXXX....XX.X...... 14      14
    madd<5>           XX........X....X...XXXXXXX....XXX....... 14      14
    _n003432          ............................XX......X... 3       3
    ULED/q1           ............XX..............X........... 3       3
    U3/counter_add<4>
                      ..X..XXXXX....X...........XX............ 9       9
    mspare_1          ........................................ 0       0
    U3/counter_add<5>
                      ..X..XXXXXX....X..........XX............ 10      10
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB25 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        4/0
    Number of PLA product terms used/remaining:                   25/31
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB25_1  110   I/O
    mem_done_p                        2       FB25_2  111   I/O      O
    tp6                               1       FB25_3  112   I/O      O
    madd<0>                           3       FB25_4  113   I/O      O
    (unused)                          0       FB25_5        (b)
    (unused)                          0       FB25_6        (b)
    (unused)                          0       FB25_7        (b)
    (unused)                          0       FB25_8        (b)
    (unused)                          0       FB25_9        (b)
    U3/counter_add<3>                 8       FB25_10       (b)      (b)
    U3/counter_add<0>                 5       FB25_11       (b)      (b)
    mem_pointer<1>                    5       FB25_12       (b)      (b)
    vspare_1                          0       FB25_13 114   I/O      O
    dout<0>                           2       FB25_14 115   I/O      I/O
    dout<10>                          2       FB25_15 116   I/O      I/O
    dout<11>                          2       FB25_16 117   I/O      I/O

    Signals Used by Logic in Function Block
      1: N_PZ_30322        14: am<2>             26: estado_FFD2
      2: N_PZ_30394        15: am<3>             27: estado_FFD3
      3: U2/latch3         16: am<4>             28: iack
      4: U3/counter_add<0> 17: am<5>             29: lword
      5: U3/counter_add<1> 18: brdsel24          30: mdat<0>.PIN
      6: U3/counter_add<2> 19: cspare<11>        31: mdat<10>.PIN
      7: U3/counter_add<3> 20: db<1>.PIN         32: mdat<11>.PIN
      8: U4/_n00084        21: dsdly<0>          33: mem_done_p
      9: U4/_n0081         22: dsdly<1>          34: mem_is_full
     10: add<0>            23: ena_ceros_mem     35: mem_pointer<0>
     11: add<3>            24: ena_gol_test      36: mem_pointer<1>
     12: am<0>             25: estado_FFD1       37: tp7
     13: am<1>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    mem_done_p        ......................XXXXX.....X....... 6       6
    tp6               ........................XXX............. 3       3
    madd<0>           XX.X.....X.XXXXXXX.........XX.....X..... 14      14
    U3/counter_add<3>
                      ..XXXXX...X.........XX.................. 8       8
    U3/counter_add<0>
                      ..XX.....X..........XX.................. 5       5
    mem_pointer<1>    .......XXX.........X.............XXXX... 8       8
    vspare_1          ........................................ 0       0
    dout<0>           ..................X..........X.......... 2       2
    dout<10>          ..................X...........X......... 2       2
    dout<11>          ..................X............X........ 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB26 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        3/1
    Number of PLA product terms used/remaining:                   24/32
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    led<0>                            1       FB26_1  109   I/O      O
    led<1>                            1       FB26_2  108   I/O      O
    trigger_led                       2       FB26_3  107   I/O      O
    mspare_0                          0       FB26_4  106   I/O      O
    (unused)                          0       FB26_5        (b)
    U4/_n001521                       2       FB26_6        (b)      (b)
    mword_count<1>                    3       FB26_7        (b)      (b)
    mword_count<15>                   3       FB26_8        (b)      (b)
    mword_count<14>                   3       FB26_9        (b)      (b)
    mword_count<11>                   3       FB26_10       (b)      (b)
    mword_count<10>                   3       FB26_11       (b)      (b)
    mword_count<0>                    3       FB26_12       (b)      (b)
    ds_out                            1       FB26_13 103   I/O      O
    tp7                               2       FB26_14 102   I/O      O
    mspare_2                          0       FB26_15 101   I/O      O
    dout<12>                          2       FB26_16 100   I/O      I/O

    Signals Used by Logic in Function Block
      1: Mcompar__n0026__n0034
                           14: add<5>            27: enw1
      2: N_PZ_30354        15: clk_slow          28: enw2
      3: N_PZ_30489        16: cs                29: inc_pointer
      4: U1/q2             17: cspare<11>        30: mdat<12>.PIN
      5: U2/b2             18: db<0>.PIN         31: mem_pointer<11>
      6: U4/_n0029         19: db<10>.PIN        32: mword_count<0>
      7: U4/ena_word_count2
                           20: db<11>.PIN        33: mword_count<10>
      8: ULED/q1           21: db<14>.PIN        34: mword_count<11>
      9: add<0>            22: db<15>.PIN        35: mword_count<14>
     10: add<1>            23: db<1>.PIN         36: mword_count<15>
     11: add<2>            24: db<6>             37: mword_count<1>
     12: add<3>            25: ds0               38: write
     13: add<4>            26: ds1

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    led<0>            ...XX................................... 2       2
    led<1>            ..X..................................X.. 2       2
    trigger_led       .......X......X......................... 2       2
    mspare_0          ........................................ 0       0
    U4/_n001521       ........XXXXXX.X...X......XX..X......... 11      11
    mword_count<1>    .X...X..XXXXXX.X......X...XX........X... 13      13
    mword_count<15>   .X...X..XXXXXX.X.....X....XX.......X.... 13      13
    mword_count<14>   .X...X..XXXXXX.X....X.....XX......X..... 13      13
    mword_count<11>   .X...X..XXXXXX.X...X......XX.....X...... 13      13
    mword_count<10>   .X...X..XXXXXX.X..X.......XX....X....... 13      13
    mword_count<0>    .X...X..XXXXXX.X.X........XX...X........ 13      13
    ds_out            ........................XX.............. 2       2
    tp7               X.....X.........X......X....X........... 5       5
    mspare_2          ........................................ 0       0
    dout<12>          ................X............X.......... 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB27 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   40/16
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    dtack_mem                         1       FB27_1  118   I/O      O
    (unused)                          0       FB27_2        (b)
    dout<13>                          2       FB27_3  119   I/O      I/O
    dout<14>                          2       FB27_4  120   I/O      I/O
    (unused)                          0       FB27_5        (b)
    (unused)                          0       FB27_6        (b)
    U4/_n0029                         2       FB27_7        (b)      (b)
    mem_pointer<2>                    8       FB27_8        (b)      (b)
    mem_pointer<0>                    6       FB27_9        (b)      (b)
    mword_count<17>                   6       FB27_10       (b)      (b)
    mword_count<16>                   6       FB27_11       (b)      (b)
    mword_count<9>                    3       FB27_12       (b)      (b)
    mword_count<4>                    3       FB27_13       (b)      (b)
    mword_count<3>                    3       FB27_14       (b)      (b)
    dout<15>                          2       FB27_15 121   I/O      I/O
    mword_count<2>                    3       FB27_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30354        14: db<0>.PIN         27: mem_pointer<0>
      2: U4/_n00084        15: db<1>.PIN         28: mem_pointer<1>
      3: U4/_n0029         16: db<2>.PIN         29: mem_pointer<2>
      4: U4/_n0081         17: db<3>.PIN         30: mword_count<16>
      5: U4/ena_fill_mem   18: db<4>.PIN         31: mword_count<17>
      6: add<0>            19: db<9>.PIN         32: mword_count<2>
      7: add<1>            20: dtack_blk         33: mword_count<3>
      8: add<2>            21: enw1              34: mword_count<4>
      9: add<3>            22: enw2              35: mword_count<9>
     10: add<4>            23: mdat<13>.PIN      36: reset
     11: add<5>            24: mdat<14>.PIN      37: tp5
     12: cs                25: mdat<15>.PIN      38: tp7
     13: cspare<11>        26: mem_is_full

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    dtack_mem         ...................X................X... 2       2
    dout<13>          ............X.........X................. 2       2
    dout<14>          ............X..........X................ 2       2
    U4/_n0029         .....XXXXXXX...X....XX.............X.... 11      11
    mem_pointer<2>    .X.X.XXXXXXX...X....XX...XXXX........X.. 17      17
    mem_pointer<0>    .X.X.XXXXXXX.X......XX...XX..........X.. 15      15
    mword_count<17>   ..X.XXXXXXXX..X.....XX........X......... 13      13
    mword_count<16>   ..X.XXXXXXXX.X......XX.......X.......... 13      13
    mword_count<9>    X.X..XXXXXXX......X.XX............X..... 13      13
    mword_count<4>    X.X..XXXXXXX.....X..XX...........X...... 13      13
    mword_count<3>    X.X..XXXXXXX....X...XX..........X....... 13      13
    dout<15>          ............X...........X............... 2       2
    mword_count<2>    X.X..XXXXXXX...X....XX.........X........ 13      13
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB28 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   20/36
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    dout<1>                           2       FB28_1  99    I/O      I/O
    dout<2>                           2       FB28_2  97    I/O      I/O
    dout<3>                           2       FB28_3  95    I/O      I/O
    (unused)                          0       FB28_4        (b)
    (unused)                          0       FB28_5        (b)
    (unused)                          0       FB28_6        (b)
    (unused)                          0       FB28_7        (b)
    (unused)                          0       FB28_8        (b)
    (unused)                          0       FB28_9        (b)
    (unused)                          0       FB28_10       (b)
    (unused)                          0       FB28_11       (b)
    Mcompar__n0029__n0027             2       FB28_12       (b)      (b)
    U4/ena_word_count2                1       FB28_13       (b)      (b)
    mem_pointer<3>                    5       FB28_14       (b)      (b)
    mem_pointer<14>                   5       FB28_15       (b)      (b)
    mem_pointer<15>                   5       FB28_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_30542        14: cs                26: mem_is_full
      2: N_PZ_30575        15: cspare<11>        27: mem_pointer<0>
      3: N_PZ_30580        16: db<11>            28: mem_pointer<10>
      4: U4/_n00084        17: db<14>.PIN        29: mem_pointer<11>
      5: U4/_n0081         18: db<15>.PIN        30: mem_pointer<12>
      6: U4/ena_fill_mem   19: db<2>             31: mem_pointer<13>
      7: add<0>            20: db<3>.PIN         32: mem_pointer<14>
      8: add<1>            21: enw1              33: mem_pointer<15>
      9: add<2>            22: enw2              34: mem_pointer<1>
     10: add<3>            23: mdat<1>.PIN       35: mem_pointer<2>
     11: add<4>            24: mdat<2>.PIN       36: mem_pointer<3>
     12: add<5>            25: mdat<3>.PIN       37: tp7
     13: counter<11>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    dout<1>           ..............X.......X................. 2       2
    dout<2>           ..............X........X................ 2       2
    dout<3>           ..............X.........X............... 2       2
    Mcompar__n0029__n0027
                      ............X..X........................ 2       2
    U4/ena_word_count2
                      .....X............X..................... 2       2
    mem_pointer<3>    ..XXX.XXXXXX.X.....XXX...XX......XXXX... 19      19
    mem_pointer<14>   XX.XX.XXXXXX.X..X...XX.....XXXXX........ 19      19
    mem_pointer<15>   X..XX.XXXXXX.X...X..XX..........X....... 14      14
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB29 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  34
    Number of function block inputs used/remaining:               34/6
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   40/16
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB29_1        (b)
    (unused)                          0       FB29_2        (b)
    dout<4>                           2       FB29_3  122   I/O      I/O
    dout<5>                           2       FB29_4  123   I/O      I/O
    (unused)                          0       FB29_5        (b)
    (unused)                          0       FB29_6        (b)
    (unused)                          0       FB29_7        (b)
    N_PZ_30539                        2       FB29_8        (b)      (b)
    N_PZ_30510                        2       FB29_9        (b)      (b)
    N_PZ_30405                        2       FB29_10       (b)      (b)
    N_PZ_30372                        2       FB29_11       (b)      (b)
    estado_XX_FFD136                  4       FB29_12       (b)      (b)
    Mcompar__n0026__n0034             21      FB29_13       (b)      (b)
    dout<6>                           2       FB29_14 125   I/O      I/O
    N_PZ_30547                        1       FB29_15       (b)      (b)
    Mcompar__n0029__n0029             2       FB29_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: Mcompar__n0026__n003420
                           13: counter<9>        24: mevent_count<9>
      2: N_PZ_30589        14: cspare<11>        25: mword_count<10>
      3: counter<10>       15: db<13>            26: mword_count<11>
      4: counter<11>       16: db<14>            27: mword_count<13>
      5: counter<12>       17: db<4>             28: mword_count<14>
      6: counter<13>       18: mdat<4>.PIN       29: mword_count<4>
      7: counter<14>       19: mdat<5>.PIN       30: mword_count<5>
      8: counter<4>        20: mdat<6>.PIN       31: mword_count<6>
      9: counter<5>        21: mevent_count<5>   32: mword_count<7>
     10: counter<6>        22: mevent_count<6>   33: mword_count<8>
     11: counter<7>        23: mevent_count<7>   34: mword_count<9>
     12: counter<8>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    dout<4>           .............X...X...................... 2       2
    dout<5>           .............X....X..................... 2       2
    N_PZ_30539        ..........X...........X................. 2       2
    N_PZ_30510        .........X...........X.................. 2       2
    N_PZ_30405        ........X...........X................... 2       2
    N_PZ_30372        .......X........X....................... 2       2
    estado_XX_FFD136  ......X.....X..X.......X................ 4       4
    Mcompar__n0026__n0034
                      X.XX.XXXXXXXX...........XXXXXXXXXX...... 21      21
    dout<6>           .............X.....X.................... 2       2
    N_PZ_30547        .XXXXXX....XX........................... 8       8
    Mcompar__n0029__n0029
                      .....X........X......................... 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB30 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  20
    Number of function block inputs used/remaining:               20/20
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   20/36
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB30_1        (b)
    dout<7>                           2       FB30_2  91    I/O      I/O
    dout<8>                           2       FB30_3  90    I/O      I/O
    dout<9>                           2       FB30_4  89    I/O      I/O
    (unused)                          0       FB30_5        (b)
    (unused)                          0       FB30_6        (b)
    (unused)                          0       FB30_7        (b)
    (unused)                          0       FB30_8        (b)
    (unused)                          0       FB30_9        (b)
    (unused)                          0       FB30_10       (b)
    (unused)                          0       FB30_11       (b)
    (unused)                          0       FB30_12       (b)
    (unused)                          0       FB30_13 88    I/O
    (unused)                          0       FB30_14 87    I/O
    Mcompar__n0026__n003420           16      FB30_15       (b)      (b)
    (unused)                          0       FB30_16 86    I/O

    Signals Used by Logic in Function Block
      1: counter<0>         8: counter<3>        15: mword_count<15>
      2: counter<12>        9: cspare<11>        16: mword_count<16>
      3: counter<15>       10: mdat<7>.PIN       17: mword_count<17>
      4: counter<16>       11: mdat<8>.PIN       18: mword_count<1>
      5: counter<17>       12: mdat<9>.PIN       19: mword_count<2>
      6: counter<1>        13: mword_count<0>    20: mword_count<3>
      7: counter<2>        14: mword_count<12>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    dout<7>           ........XX.............................. 2       2
    dout<8>           ........X.X............................. 2       2
    dout<9>           ........X..X............................ 2       2
    Mcompar__n0026__n003420
                      XXXXXXXX....XXXXXXXX.................... 16      16
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB31 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    cspare<1>                         0       FB31_1  126   I/O      O
    (unused)                          0       FB31_2        (b)
    cspare<0>                         0       FB31_3  127   I/O      O
    cspare<9>                         0       FB31_4  128   I/O      O
    (unused)                          0       FB31_5        (b)
    (unused)                          0       FB31_6        (b)
    (unused)                          0       FB31_7        (b)
    (unused)                          0       FB31_8        (b)
    (unused)                          0       FB31_9        (b)
    (unused)                          0       FB31_10       (b)
    (unused)                          0       FB31_11       (b)
    (unused)                          0       FB31_12       (b)
    (unused)                          0       FB31_13       (b)
    (unused)                          0       FB31_14       (b)
    (unused)                          0       FB31_15       (b)
    cspare<8>                         0       FB31_16 131   I/O      O

    Signals Used by Logic in Function Block

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    cspare<1>         ........................................ 0       0
    cspare<0>         ........................................ 0       0
    cspare<9>         ........................................ 0       0
    cspare<8>         ........................................ 0       0
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB32 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB32_1  85    I/O
    (unused)                          0       FB32_2  84    I/O
    (unused)                          0       FB32_3        (b)
    (unused)                          0       FB32_4  83    I/O
    (unused)                          0       FB32_5        (b)
    (unused)                          0       FB32_6        (b)
    (unused)                          0       FB32_7        (b)
    (unused)                          0       FB32_8        (b)
    (unused)                          0       FB32_9        (b)
    (unused)                          0       FB32_10       (b)
    (unused)                          0       FB32_11       (b)
    (unused)                          0       FB32_12       (b)
    (unused)                          0       FB32_13 82    I/O
    (unused)                          0       FB32_14 80    I/O
    (unused)                          0       FB32_15       (b)
    (unused)                          0       FB32_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    ;;-----------------------------------------------------------------;;
    ; Implemented Equations.

    cspare(0) <= '0';

    cspare(10) <= vspare_0;

    cspare(11) <= (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1);

    FDCPE_estado_FFD2: FDCPE port map (estado_FFD2,estado_FFD2_D,clk,reset,'0','1');
    estado_FFD2_D <= NOT (((estado_FFD3 AND estado_FFD1)
    	OR (ena_ceros_mem AND N_PZ_30322)
    	OR (N_PZ_30322 AND NOT ena_gol_test)
    	OR (NOT estado_FFD2 AND estado_FFD1 AND NOT enw1.COMB)
    	OR (estado_FFD2 AND estado_FFD3 AND NOT ena_ceros_mem AND
    	NOT estado_FFD1 AND NOT ena_gol_test)));

    FTCPE_estado_FFD3: FTCPE port map (estado_FFD3,estado_FFD3_T,clk,reset,'0','1');
    estado_FFD3_T <= ((NOT estado_FFD3 AND estado_FFD1 AND N_PZ_30599)
    	OR (NOT ena_ceros_mem AND N_PZ_30322 AND ena_gol_test)
    	OR (estado_FFD2 AND NOT estado_FFD3 AND NOT estado_FFD1 AND
    	NOT is_trigger)
    	OR (estado_FFD2 AND estado_FFD3 AND NOT ena_ceros_mem AND
    	NOT estado_FFD1 AND NOT ena_gol_test));

    FTCPE_ena_ceros_mem: FTCPE port map (ena_ceros_mem,ena_ceros_mem_T,clk,reset,'0','1');
    ena_ceros_mem_T <= ((NOT ena_ceros_mem AND N_PZ_30413 AND db(1).PIN)
    	OR (estado_FFD2 AND estado_FFD3 AND ena_ceros_mem AND
    	NOT estado_FFD1)
    	OR (ena_ceros_mem AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND
    	NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN));

    FDCPE_estado_FFD1: FDCPE port map (estado_FFD1,estado_FFD1_D,clk,reset,'0','1');
    estado_FFD1_D <= NOT (((NOT estado_FFD1 AND estado_XX_FFD153)
    	OR (NOT estado_FFD2 AND NOT estado_FFD3 AND estado_XX_FFD153 AND
    	estado_XX_FFD146)
    	OR (NOT estado_FFD2 AND estado_XX_FFD153 AND NOT ena_gol_test AND
    	estado_XX_FFD146)
    	OR (NOT estado_FFD3 AND NOT ena_ceros_mem AND estado_XX_FFD153 AND
    	estado_XX_FFD146)
    	OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
    	estado_XX_FFD146 AND mem_is_full)
    	OR (NOT estado_FFD2 AND estado_XX_FFD153 AND
    	estado_XX_FFD146 AND NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2)
    	OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
    	estado_XX_FFD146 AND NOT ena_event_count AND NOT Mcompar__n0026__n0034 AND
    	NOT U4/ena_word_count2)
    	OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
    	estado_XX_FFD146 AND ena_event_count AND mevent_count(10) AND
    	mevent_count(8) AND counter(10) AND counter(8) AND NOT Mcompar__n0029__n0027 AND
    	NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
    	N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)
    	OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
    	estado_XX_FFD146 AND ena_event_count AND mevent_count(10) AND
    	NOT mevent_count(8) AND counter(10) AND NOT counter(8) AND NOT Mcompar__n0029__n0027 AND
    	NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
    	N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)
    	OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
    	estado_XX_FFD146 AND ena_event_count AND NOT mevent_count(10) AND
    	mevent_count(8) AND NOT counter(10) AND counter(8) AND NOT Mcompar__n0029__n0027 AND
    	NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
    	N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)
    	OR (NOT estado_FFD3 AND estado_XX_FFD153 AND
    	estado_XX_FFD146 AND ena_event_count AND NOT mevent_count(10) AND
    	NOT mevent_count(8) AND NOT counter(10) AND NOT counter(8) AND NOT Mcompar__n0029__n0027 AND
    	NOT Mcompar__n0029__n0029 AND NOT estado_XX_FFD135 AND estado_XX_FFD136 AND N_PZ_30372 AND
    	N_PZ_30405 AND N_PZ_30510 AND N_PZ_30539)));

    estado_XX_FFD153 <= ((estado_FFD2)
    	OR (estado_FFD1)
    	OR (estado_FFD3 AND NOT ena_cycles)
    	OR (NOT estado_FFD3 AND NOT ena_ceros_mem AND NOT ena_gol_test)
    	OR (estado_FFD3 AND NOT cycle_counter(0) AND
    	NOT cycle_counter(14) AND NOT cycle_counter(10) AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8) AND NOT cycle_counter(9) AND NOT cycle_counter(11) AND
    	NOT cycle_counter(12) AND NOT cycle_counter(13) AND NOT cycle_counter(15)));

    db(5) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(5).PIN)
    	OR (ena_cycles AND NOT add(2) AND NOT add(1) AND NOT add(0) AND
    	N_PZ_30373)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(5) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(5) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(5) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(5) AND
    	N_PZ_30373));FDCPE_ena_cycles: FDCPE port map (ena_cycles,db(5).PIN,clk,reset,'0',N_PZ_30413);

    N_PZ_30413 <= ((NOT estado_FFD2 AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND
    	NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2)
    	OR (NOT estado_FFD3 AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND
    	NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2)
    	OR (estado_FFD1 AND NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND
    	NOT add(3) AND NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2));

    enw1.COMB <= (is_trigger AND NOT is_trigger_1);FDCPE_enw1: FDCPE port map (enw1,enw_x,clk,reset,'0','1');

    FDCPE_enw2: FDCPE port map (enw2,enw1,clk,reset,'0','1');

    _n0086_MC.GLB <= ((cs AND NOT etr)
    	OR (write AND N_PZ_30322 AND N_PZ_30489));

    N_PZ_30322 <= (NOT estado_FFD2 AND NOT estado_FFD3 AND NOT estado_FFD1);

    N_PZ_30489 <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND NOT ds1 AND
    	NOT ds0 AND am(4) AND am(3) AND NOT brdsel24);

    FTCPE_ena_gol_test: FTCPE port map (ena_gol_test,ena_gol_test_T,clk,reset,'0','1');
    ena_gol_test_T <= ((estado_FFD2 AND estado_FFD3 AND NOT estado_FFD1 AND
    	ena_gol_test)
    	OR (N_PZ_30413 AND NOT ena_gol_test AND NOT db(1).PIN AND
    	db(0).PIN)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND ena_gol_test AND
    	db(1).PIN)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND ena_gol_test AND
    	NOT db(0).PIN));

    FDCPE_cycle_counter0: FDCPE port map (cycle_counter(0),cycle_counter_D(0),clk,reset,'0','1');
    cycle_counter_D(0) <= NOT (((cycle_counter(0) AND N_PZ_30371)
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND NOT num_cycles(0))
    	OR (NOT N_PZ_30322 AND NOT cycle_counter(0) AND NOT N_PZ_30371)));

    N_PZ_30371 <= (estado_FFD2 AND estado_FFD3 AND estado_FFD1);

    FDCPE_num_cycles0: FDCPE port map (num_cycles(0),db(0).PIN,clk,reset,'0',num_cycles_CE(0));
    num_cycles_CE(0) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FDCPE_cycle_counter14: FDCPE port map (cycle_counter(14),cycle_counter_D(14),clk,reset,'0','1');
    cycle_counter_D(14) <= NOT (((N_PZ_30371 AND NOT _n0033(14)2)
    	OR (N_PZ_30322 AND NOT num_cycles(14) AND NOT _n0033(14)2)
    	OR (NOT N_PZ_30322 AND NOT cycle_counter(14) AND NOT _n0033(14)2)));

    FDCPE_num_cycles14: FDCPE port map (num_cycles(14),db(14).PIN,clk,reset,'0',num_cycles_CE(14));
    num_cycles_CE(14) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    _n0033(14)2 <= (N_PZ_30371 AND cycle_counter(14))
    	XOR (NOT cycle_counter(0) AND N_PZ_30371 AND
    	NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
    	NOT cycle_counter(9) AND NOT cycle_counter(11) AND NOT cycle_counter(12) AND
    	NOT cycle_counter(13));

    FTCPE_cycle_counter10: FTCPE port map (cycle_counter(10),cycle_counter_T(10),clk,reset,'0','1');
    cycle_counter_T(10) <= ((N_PZ_30322 AND NOT cycle_counter(10) AND num_cycles(10))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(10) AND
    	NOT num_cycles(10))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8) AND NOT cycle_counter(9)));

    FDCPE_num_cycles10: FDCPE port map (num_cycles(10),db(10).PIN,clk,reset,'0',num_cycles_CE(10));
    num_cycles_CE(10) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter1: FTCPE port map (cycle_counter(1),cycle_counter_T(1),clk,reset,'0','1');
    cycle_counter_T(1) <= ((NOT cycle_counter(0) AND N_PZ_30371)
    	OR (N_PZ_30322 AND NOT cycle_counter(1) AND num_cycles(1))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(1) AND
    	NOT num_cycles(1)));

    FDCPE_num_cycles1: FDCPE port map (num_cycles(1),db(1).PIN,clk,reset,'0',num_cycles_CE(1));
    num_cycles_CE(1) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter2: FTCPE port map (cycle_counter(2),cycle_counter_T(2),clk,reset,'0','1');
    cycle_counter_T(2) <= ((N_PZ_30322 AND NOT cycle_counter(2) AND num_cycles(2))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(2) AND
    	NOT num_cycles(2)));

    FDCPE_num_cycles2: FDCPE port map (num_cycles(2),db(2).PIN,clk,reset,'0',num_cycles_CE(2));
    num_cycles_CE(2) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter3: FTCPE port map (cycle_counter(3),cycle_counter_T(3),clk,reset,'0','1');
    cycle_counter_T(3) <= ((N_PZ_30322 AND NOT cycle_counter(3) AND num_cycles(3))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(3) AND
    	NOT num_cycles(3))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2)));

    FDCPE_num_cycles3: FDCPE port map (num_cycles(3),db(3).PIN,clk,reset,'0',num_cycles_CE(3));
    num_cycles_CE(3) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter4: FTCPE port map (cycle_counter(4),cycle_counter_T(4),clk,reset,'0','1');
    cycle_counter_T(4) <= ((N_PZ_30322 AND NOT cycle_counter(4) AND num_cycles(4))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(4) AND
    	NOT num_cycles(4))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3)));

    FDCPE_num_cycles4: FDCPE port map (num_cycles(4),db(4).PIN,clk,reset,'0',num_cycles_CE(4));
    num_cycles_CE(4) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter5: FTCPE port map (cycle_counter(5),cycle_counter_T(5),clk,reset,'0','1');
    cycle_counter_T(5) <= ((N_PZ_30322 AND NOT cycle_counter(5) AND num_cycles(5))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(5) AND
    	NOT num_cycles(5))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4)));

    FDCPE_num_cycles5: FDCPE port map (num_cycles(5),db(5).PIN,clk,reset,'0',num_cycles_CE(5));
    num_cycles_CE(5) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter6: FTCPE port map (cycle_counter(6),cycle_counter_T(6),clk,reset,'0','1');
    cycle_counter_T(6) <= ((N_PZ_30322 AND NOT cycle_counter(6) AND num_cycles(6))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(6) AND
    	NOT num_cycles(6))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5)));

    FDCPE_num_cycles6: FDCPE port map (num_cycles(6),db(6).PIN,clk,reset,'0',num_cycles_CE(6));
    num_cycles_CE(6) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter7: FTCPE port map (cycle_counter(7),cycle_counter_T(7),clk,reset,'0','1');
    cycle_counter_T(7) <= ((N_PZ_30322 AND NOT cycle_counter(7) AND num_cycles(7))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(7) AND
    	NOT num_cycles(7))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6)));

    FDCPE_num_cycles7: FDCPE port map (num_cycles(7),db(7).PIN,clk,reset,'0',num_cycles_CE(7));
    num_cycles_CE(7) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter8: FTCPE port map (cycle_counter(8),cycle_counter_T(8),clk,reset,'0','1');
    cycle_counter_T(8) <= ((N_PZ_30322 AND NOT cycle_counter(8) AND num_cycles(8))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(8) AND
    	NOT num_cycles(8))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7)));

    FDCPE_num_cycles8: FDCPE port map (num_cycles(8),db(8).PIN,clk,reset,'0',num_cycles_CE(8));
    num_cycles_CE(8) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter9: FTCPE port map (cycle_counter(9),cycle_counter_T(9),clk,reset,'0','1');
    cycle_counter_T(9) <= ((N_PZ_30322 AND NOT cycle_counter(9) AND num_cycles(9))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(9) AND
    	NOT num_cycles(9))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND NOT cycle_counter(1) AND
    	NOT cycle_counter(2) AND NOT cycle_counter(3) AND NOT cycle_counter(4) AND
    	NOT cycle_counter(5) AND NOT cycle_counter(6) AND NOT cycle_counter(7) AND
    	NOT cycle_counter(8)));

    FDCPE_num_cycles9: FDCPE port map (num_cycles(9),db(9).PIN,clk,reset,'0',num_cycles_CE(9));
    num_cycles_CE(9) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter11: FTCPE port map (cycle_counter(11),cycle_counter_T(11),clk,reset,'0','1');
    cycle_counter_T(11) <= ((N_PZ_30322 AND NOT cycle_counter(11) AND num_cycles(11))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(11) AND
    	NOT num_cycles(11))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND
    	NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
    	NOT cycle_counter(9)));

    FDCPE_num_cycles11: FDCPE port map (num_cycles(11),db(11).PIN,clk,reset,'0',num_cycles_CE(11));
    num_cycles_CE(11) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter12: FTCPE port map (cycle_counter(12),cycle_counter_T(12),clk,reset,'0','1');
    cycle_counter_T(12) <= ((N_PZ_30322 AND NOT cycle_counter(12) AND num_cycles(12))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(12) AND
    	NOT num_cycles(12))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND
    	NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
    	NOT cycle_counter(9) AND NOT cycle_counter(11)));

    FDCPE_num_cycles12: FDCPE port map (num_cycles(12),db(12).PIN,clk,reset,'0',num_cycles_CE(12));
    num_cycles_CE(12) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter13: FTCPE port map (cycle_counter(13),cycle_counter_T(13),clk,reset,'0','1');
    cycle_counter_T(13) <= ((N_PZ_30322 AND NOT cycle_counter(13) AND num_cycles(13))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(13) AND
    	NOT num_cycles(13))
    	OR (NOT cycle_counter(0) AND N_PZ_30371 AND
    	NOT cycle_counter(10) AND NOT cycle_counter(1) AND NOT cycle_counter(2) AND
    	NOT cycle_counter(3) AND NOT cycle_counter(4) AND NOT cycle_counter(5) AND
    	NOT cycle_counter(6) AND NOT cycle_counter(7) AND NOT cycle_counter(8) AND
    	NOT cycle_counter(9) AND NOT cycle_counter(11) AND NOT cycle_counter(12)));

    FDCPE_num_cycles13: FDCPE port map (num_cycles(13),db(13).PIN,clk,reset,'0',num_cycles_CE(13));
    num_cycles_CE(13) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    FTCPE_cycle_counter15: FTCPE port map (cycle_counter(15),cycle_counter_T(15),clk,reset,'0','1');
    cycle_counter_T(15) <= ((N_PZ_30322 AND NOT cycle_counter(15) AND num_cycles(15))
    	OR (N_PZ_30371 AND NOT cycle_counter(14) AND _n0033(14)2)
    	OR (NOT cycle_counter(14) AND _n0033(14)2 AND
    	NOT cycle_counter(15))
    	OR (N_PZ_30322 AND NOT N_PZ_30371 AND cycle_counter(15) AND
    	NOT num_cycles(15)));

    FDCPE_num_cycles15: FDCPE port map (num_cycles(15),db(15).PIN,clk,reset,'0',num_cycles_CE(15));
    num_cycles_CE(15) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2);

    estado_XX_FFD146 <= ((estado_FFD2)
    	OR (estado_FFD3)
    	OR (ena_event_count AND NOT mevent_count(0) AND
    	NOT mevent_count(10) AND NOT mevent_count(11) AND NOT mevent_count(12) AND
    	NOT mevent_count(13) AND NOT mevent_count(14) AND NOT mevent_count(15) AND
    	NOT mevent_count(1) AND NOT mevent_count(2) AND NOT mevent_count(3) AND
    	NOT mevent_count(4) AND NOT mevent_count(5) AND NOT mevent_count(6) AND
    	NOT mevent_count(7) AND NOT mevent_count(8) AND NOT mevent_count(9) AND enw1.COMB));

    db(3) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(3).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(3) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(3) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(3) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(3) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND ena_event_count AND
    	N_PZ_30373));FDCPE_ena_event_count: FDCPE port map (ena_event_count,db(3).PIN,clk,reset,'0',N_PZ_30413);

    db(0) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(0).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(0) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(0) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND NOT add(0) AND mword_count(16) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(0) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND NOT add(0) AND mem_pointer(16) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(0) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND ena_gol_test AND
    	N_PZ_30373));FDCPE_mevent_count0: FDCPE port map (mevent_count(0),db(0).PIN,clk,reset,'0',mevent_count_CE(0));
    mevent_count_CE(0) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count10: FDCPE port map (mevent_count(10),db(10).PIN,clk,reset,'0',mevent_count_CE(10));
    mevent_count_CE(10) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    db(11) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(11).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(11) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(11) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(11) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(11) AND
    	N_PZ_30373));FDCPE_mevent_count11: FDCPE port map (mevent_count(11),db(11).PIN,clk,reset,'0',mevent_count_CE(11));
    mevent_count_CE(11) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    db(12) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(12).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(12) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(12) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(12) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(12) AND
    	N_PZ_30373));FDCPE_mevent_count12: FDCPE port map (mevent_count(12),db(12).PIN,clk,reset,'0',mevent_count_CE(12));
    mevent_count_CE(12) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    db(13) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(13).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(13) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(13) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(13) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(13) AND
    	N_PZ_30373));FDCPE_mevent_count13: FDCPE port map (mevent_count(13),db(13).PIN,clk,reset,'0',mevent_count_CE(13));
    mevent_count_CE(13) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    db(14) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(14).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(14) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(14) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(14) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(14) AND
    	N_PZ_30373));FDCPE_mevent_count14: FDCPE port map (mevent_count(14),db(14).PIN,clk,reset,'0',mevent_count_CE(14));
    mevent_count_CE(14) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    db(15) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(15).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(15) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(15) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(15) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(15) AND
    	N_PZ_30373));FDCPE_mevent_count15: FDCPE port map (mevent_count(15),db(15).PIN,clk,reset,'0',mevent_count_CE(15));
    mevent_count_CE(15) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    db(1) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(1).PIN)
    	OR (ena_ceros_mem AND NOT add(2) AND NOT add(1) AND NOT add(0) AND
    	N_PZ_30373)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(1) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(1) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND NOT add(0) AND mword_count(17) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(1) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND NOT add(0) AND mem_pointer(17) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(1) AND
    	N_PZ_30373));FDCPE_mevent_count1: FDCPE port map (mevent_count(1),db(1).PIN,clk,reset,'0',mevent_count_CE(1));
    mevent_count_CE(1) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count2: FDCPE port map (mevent_count(2),db(2).PIN,clk,reset,'0',mevent_count_CE(2));
    mevent_count_CE(2) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count3: FDCPE port map (mevent_count(3),db(3).PIN,clk,reset,'0',mevent_count_CE(3));
    mevent_count_CE(3) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    db(4) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(4).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(4) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(4) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(4) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(4) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND U4/ena_fill_mem AND
    	N_PZ_30373));FDCPE_mevent_count4: FDCPE port map (mevent_count(4),db(4).PIN,clk,reset,'0',mevent_count_CE(4));
    mevent_count_CE(4) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count5: FDCPE port map (mevent_count(5),db(5).PIN,clk,reset,'0',mevent_count_CE(5));
    mevent_count_CE(5) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count6: FDCPE port map (mevent_count(6),db(6).PIN,clk,reset,'0',mevent_count_CE(6));
    mevent_count_CE(6) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count7: FDCPE port map (mevent_count(7),db(7).PIN,clk,reset,'0',mevent_count_CE(7));
    mevent_count_CE(7) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count8: FDCPE port map (mevent_count(8),db(8).PIN,clk,reset,'0',mevent_count_CE(8));
    mevent_count_CE(8) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mevent_count9: FDCPE port map (mevent_count(9),db(9).PIN,clk,reset,'0',mevent_count_CE(9));
    mevent_count_CE(9) <= (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2);

    FDCPE_mem_is_full: FDCPE port map (mem_is_full,mem_is_full_D,clk,reset,'0','1');
    mem_is_full_D <= ((mem_is_full AND NOT U4/_n0051)
    	OR (NOT mem_is_full AND NOT U4/_n0051 AND NOT mem_pointer(0) AND tp7 AND
    	mem_pointer(10) AND mem_pointer(4) AND mem_pointer(1) AND mem_pointer(2) AND
    	mem_pointer(3) AND mem_pointer(5) AND mem_pointer(6) AND mem_pointer(7) AND
    	mem_pointer(8) AND mem_pointer(9) AND mem_pointer(11) AND
    	mem_pointer(12) AND mem_pointer(13) AND mem_pointer(14) AND
    	mem_pointer(15) AND mem_pointer(16) AND mem_pointer(17)));

    U4/_n0051 <= (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(2).PIN);

    FDCPE_mem_pointer0: FDCPE port map (mem_pointer(0),mem_pointer_D(0),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(0) <= ((mem_is_full AND mem_pointer(0) AND NOT U4/_n0081)
    	OR (mem_pointer(0) AND NOT U4/_n0081 AND NOT tp7)
    	OR (NOT mem_is_full AND NOT mem_pointer(0) AND NOT U4/_n0081 AND tp7)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(0))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(0).PIN));

    U4/_n0081 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2));

    tp7 <= NOT (((NOT inc_pointer)
    	OR (NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2 AND
    	ena_random AND cspare(11))));

    FDCPE_inc_pointer: FDCPE port map (inc_pointer,inc_pointer_D,clk,reset,'0','1');
    inc_pointer_D <= NOT (NOT estado_FFD3
    	XOR ((estado_FFD3 AND NOT estado_FFD1 AND NOT inc_pointer)
    	OR (estado_FFD3 AND N_PZ_30322 AND NOT _n003432)
    	OR (estado_FFD3 AND N_PZ_30371 AND NOT _n003432)
    	OR (NOT estado_FFD3 AND estado_FFD1 AND _n003432)
    	OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
    	NOT ena_gol_test AND NOT _n003432)
    	OR (estado_FFD2 AND NOT estado_FFD3 AND NOT mem_is_full AND
    	txena_reg_in AND is_trigger AND _n003432)
    	OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
    	NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2 AND NOT _n003432)
    	OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
    	NOT txena_out AND NOT ena_random AND NOT _n003432)
    	OR (estado_FFD3 AND estado_FFD1 AND NOT ena_event_count AND
    	NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2 AND NOT _n003432)
    	OR (estado_FFD3 AND estado_FFD1 AND mem_is_full AND
    	NOT txena_out AND NOT ena_random AND NOT _n003432)
    	OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
    	ena_random AND U4/ena_lfsr(0) AND NOT U4/lfsr_0(40) AND NOT _n003432)
    	OR (NOT estado_FFD2 AND estado_FFD3 AND estado_FFD1 AND
    	ena_random AND U4/ena_lfsr(1) AND NOT U4/lfsr_1(30) AND NOT _n003432)
    	OR (estado_FFD3 AND estado_FFD1 AND mem_is_full AND
    	ena_random AND U4/ena_lfsr(0) AND NOT U4/lfsr_0(40) AND NOT _n003432)
    	OR (estado_FFD3 AND estado_FFD1 AND mem_is_full AND
    	ena_random AND U4/ena_lfsr(1) AND NOT U4/lfsr_1(30) AND NOT _n003432)
    	OR (estado_FFD2 AND NOT estado_FFD3 AND NOT estado_FFD1 AND
    	NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT mem_is_full AND txena_reg_in AND
    	is_trigger)
    	OR (estado_FFD2 AND NOT estado_FFD3 AND ena_ceros_mem AND
    	estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND ena_event_count AND
    	NOT mem_is_full AND txena_reg_in)
    	OR (estado_FFD2 AND NOT estado_FFD3 AND ena_ceros_mem AND
    	estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT mem_is_full AND
    	txena_reg_in AND Mcompar__n0026__n0034)
    	OR (estado_FFD2 AND NOT estado_FFD3 AND ena_ceros_mem AND
    	estado_FFD1 AND NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT mem_is_full AND
    	txena_reg_in AND U4/ena_word_count2)));

    txena <= (cspare(11) AND txena_reg_out);
    txena <= txena_I when txena_OE = '1' else 'Z';
    txena_OE <= (NOT estado_FFD2 AND estado_FFD3);FDCPE_txena_reg_in: FDCPE port map (txena_reg_in,txena.PIN,clk,reset,'0','1');

    Mcompar__n0026__n0034 <= ((Mcompar__n0026__n003420)
    	OR (counter(10) AND NOT mword_count(10))
    	OR (NOT counter(10) AND mword_count(10))
    	OR (counter(8) AND NOT mword_count(8))
    	OR (NOT counter(8) AND mword_count(8))
    	OR (counter(4) AND NOT mword_count(4))
    	OR (NOT counter(4) AND mword_count(4))
    	OR (counter(5) AND NOT mword_count(5))
    	OR (NOT counter(5) AND mword_count(5))
    	OR (counter(6) AND NOT mword_count(6))
    	OR (NOT counter(6) AND mword_count(6))
    	OR (counter(7) AND NOT mword_count(7))
    	OR (NOT counter(7) AND mword_count(7))
    	OR (counter(9) AND NOT mword_count(9))
    	OR (NOT counter(9) AND mword_count(9))
    	OR (counter(11) AND NOT mword_count(11))
    	OR (NOT counter(11) AND mword_count(11))
    	OR (counter(13) AND NOT mword_count(13))
    	OR (NOT counter(13) AND mword_count(13))
    	OR (counter(14) AND NOT mword_count(14))
    	OR (NOT counter(14) AND mword_count(14)));

    FDCPE_counter10: FDCPE port map (counter(10),counter_D(10),clk,reset,'0','1');
    counter_D(10) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(8) AND
    	N_PZ_30589 AND counter(9));

    FDCPE_counter8: FDCPE port map (counter(8),counter_D(8),clk,reset,'0','1');
    counter_D(8) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(8) AND
    	NOT N_PZ_30589)
    	OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT counter(8) AND
    	N_PZ_30589));

    N_PZ_30589 <= (counter(2) AND N_PZ_30591 AND counter(3) AND
    	counter(4) AND counter(5) AND counter(6) AND counter(7));

    FDCPE_counter2: FDCPE port map (counter(2),counter_D(2),clk,reset,'0','1');
    counter_D(2) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND
    	NOT N_PZ_30591)
    	OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT counter(2) AND
    	N_PZ_30591));

    N_PZ_30591 <= ((N_PZ_30322 AND counter(0) AND counter(1))
    	OR (N_PZ_30371 AND counter(0) AND counter(1))
    	OR (estado_FFD2 AND estado_FFD1 AND txena_reg_in AND
    	counter(0) AND NOT U4/ena_word_count2 AND counter(1))
    	OR (estado_FFD3 AND estado_FFD1 AND counter(0) AND
    	NOT U4/ena_word_count2 AND txena_out AND counter(1))
    	OR (NOT estado_FFD3 AND estado_FFD1 AND ena_event_count AND
    	enw1.COMB AND counter(0) AND counter(1)));

    FTCPE_counter0: FTCPE port map (counter(0),counter_T(0),clk,reset,'0','1');
    counter_T(0) <= ((N_PZ_30322 AND counter(0))
    	OR (N_PZ_30371 AND counter(0))
    	OR (estado_FFD2 AND estado_FFD1 AND NOT N_PZ_30322 AND
    	NOT N_PZ_30371 AND txena_reg_in AND NOT U4/ena_word_count2)
    	OR (estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
    	NOT N_PZ_30371 AND NOT U4/ena_word_count2 AND txena_out)
    	OR (NOT estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
    	NOT N_PZ_30371 AND ena_event_count AND enw1.COMB));

    U4/ena_word_count2 <= (NOT U4/ena_fill_mem AND NOT U4/ena_word_count_reg);

    FTCPE_U4/ena_fill_mem: FTCPE port map (U4/ena_fill_mem,U4/ena_fill_mem_T,clk,reset,'0','1');
    U4/ena_fill_mem_T <= ((N_PZ_30413 AND db(4).PIN AND NOT U4/ena_fill_mem)
    	OR (estado_FFD2 AND estado_FFD3 AND NOT estado_FFD1 AND
    	U4/ena_fill_mem)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(4).PIN AND
    	U4/ena_fill_mem));

    db(2) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(2).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(2) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(2) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(2) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(2) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND NOT U4/ena_word_count2 AND
    	N_PZ_30373));FDCPE_U4/ena_word_count_reg: FDCPE port map (U4/ena_word_count_reg,db(2).PIN,clk,reset,'0',N_PZ_30413);

    FDCPE_txena_out: FDCPE port map (txena_out,txena_out_D,clk,reset,'0','1');
    txena_out_D <= NOT (((NOT cspare(11))
    	OR (txena_out AND NOT ena_random)
    	OR (ena_random AND U4/ena_lfsr(0) AND NOT U4/lfsr_0(40))
    	OR (ena_random AND U4/ena_lfsr(1) AND NOT U4/lfsr_1(30))));

    db(6) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(6).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(6) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(6) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(6) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(6) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND ena_random AND
    	N_PZ_30373));FDCPE_ena_random: FDCPE port map (ena_random,db(6).PIN,clk,reset,'0',N_PZ_30413);

    db(7) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(7).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(7) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(7) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(7) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(7) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND U4/ena_lfsr(0) AND
    	N_PZ_30373));FDCPE_U4/ena_lfsr0: FDCPE port map (U4/ena_lfsr(0),db(7).PIN,clk,reset,'0',N_PZ_30413);

    FDCPE_U4/lfsr_040: FDCPE port map (U4/lfsr_0(40),U4/lfsr_0(39),clk,reset,'0','1');

    FDCPE_U4/lfsr_039: FDCPE port map (U4/lfsr_0(39),U4/lfsr_0(38),clk,reset,'0','1');

    FDCPE_U4/lfsr_038: FDCPE port map (U4/lfsr_0(38),U4/lfsr_0(37),clk,reset,'0','1');

    FDCPE_U4/lfsr_037: FDCPE port map (U4/lfsr_0(37),U4/lfsr_0(36),clk,reset,'0','1');

    FDCPE_U4/lfsr_036: FDCPE port map (U4/lfsr_0(36),U4/lfsr_0(35),clk,reset,'0','1');

    FDCPE_U4/lfsr_035: FDCPE port map (U4/lfsr_0(35),U4/lfsr_0(34),clk,reset,'0','1');

    FDCPE_U4/lfsr_034: FDCPE port map (U4/lfsr_0(34),U4/lfsr_0(33),clk,reset,'0','1');

    FDCPE_U4/lfsr_033: FDCPE port map (U4/lfsr_0(33),U4/lfsr_0(32),clk,reset,'0','1');

    FDCPE_U4/lfsr_032: FDCPE port map (U4/lfsr_0(32),U4/lfsr_0(31),clk,reset,'0','1');

    FDCPE_U4/lfsr_031: FDCPE port map (U4/lfsr_0(31),U4/lfsr_0(30),clk,reset,'0','1');

    FDCPE_U4/lfsr_030: FDCPE port map (U4/lfsr_0(30),U4/lfsr_0(29),clk,reset,'0','1');

    FDCPE_U4/lfsr_029: FDCPE port map (U4/lfsr_0(29),U4/lfsr_0(28),clk,reset,'0','1');

    FDCPE_U4/lfsr_028: FDCPE port map (U4/lfsr_0(28),U4/lfsr_0(27),clk,reset,'0','1');

    FDCPE_U4/lfsr_027: FDCPE port map (U4/lfsr_0(27),U4/lfsr_0(26),clk,reset,'0','1');

    FDCPE_U4/lfsr_026: FDCPE port map (U4/lfsr_0(26),U4/lfsr_0(25),clk,reset,'0','1');

    FDCPE_U4/lfsr_025: FDCPE port map (U4/lfsr_0(25),U4/lfsr_0(24),clk,reset,'0','1');

    FDCPE_U4/lfsr_024: FDCPE port map (U4/lfsr_0(24),U4/lfsr_0(23),clk,reset,'0','1');

    FDCPE_U4/lfsr_023: FDCPE port map (U4/lfsr_0(23),U4/lfsr_0(22),clk,reset,'0','1');

    FDCPE_U4/lfsr_022: FDCPE port map (U4/lfsr_0(22),U4/lfsr_0(21),clk,reset,'0','1');

    FDCPE_U4/lfsr_021: FDCPE port map (U4/lfsr_0(21),U4/lfsr_0(20),clk,reset,'0','1');

    FDCPE_U4/lfsr_020: FDCPE port map (U4/lfsr_0(20),U4/lfsr_0(19),clk,reset,'0','1');

    FDCPE_U4/lfsr_019: FDCPE port map (U4/lfsr_0(19),U4/lfsr_0(18),clk,reset,'0','1');

    FDCPE_U4/lfsr_018: FDCPE port map (U4/lfsr_0(18),U4/lfsr_0(17),clk,reset,'0','1');

    FDCPE_U4/lfsr_017: FDCPE port map (U4/lfsr_0(17),U4/lfsr_0(16),clk,reset,'0','1');

    FDCPE_U4/lfsr_016: FDCPE port map (U4/lfsr_0(16),U4/lfsr_0(15),clk,reset,'0','1');

    FDCPE_U4/lfsr_015: FDCPE port map (U4/lfsr_0(15),U4/lfsr_0(14),clk,reset,'0','1');

    FDCPE_U4/lfsr_014: FDCPE port map (U4/lfsr_0(14),U4/lfsr_0(13),clk,reset,'0','1');

    FDCPE_U4/lfsr_013: FDCPE port map (U4/lfsr_0(13),U4/lfsr_0(12),clk,reset,'0','1');

    FDCPE_U4/lfsr_012: FDCPE port map (U4/lfsr_0(12),U4/lfsr_0(11),clk,reset,'0','1');

    FDCPE_U4/lfsr_011: FDCPE port map (U4/lfsr_0(11),U4/lfsr_0(10),clk,reset,'0','1');

    FDCPE_U4/lfsr_010: FDCPE port map (U4/lfsr_0(10),U4/lfsr_0(9),clk,reset,'0','1');

    FDCPE_U4/lfsr_09: FDCPE port map (U4/lfsr_0(9),U4/lfsr_0(8),clk,reset,'0','1');

    FDCPE_U4/lfsr_08: FDCPE port map (U4/lfsr_0(8),U4/lfsr_0(7),clk,reset,'0','1');

    FDCPE_U4/lfsr_07: FDCPE port map (U4/lfsr_0(7),U4/lfsr_0(6),clk,reset,'0','1');

    FDCPE_U4/lfsr_06: FDCPE port map (U4/lfsr_0(6),U4/lfsr_0(5),clk,reset,'0','1');

    FDCPE_U4/lfsr_05: FDCPE port map (U4/lfsr_0(5),U4/lfsr_0(4),clk,reset,'0','1');

    FDCPE_U4/lfsr_04: FDCPE port map (U4/lfsr_0(4),U4/lfsr_0(3),clk,reset,'0','1');

    FDCPE_U4/lfsr_03: FDCPE port map (U4/lfsr_0(3),U4/lfsr_0(2),clk,reset,'0','1');

    FDCPE_U4/lfsr_02: FDCPE port map (U4/lfsr_0(2),U4/lfsr_0(1),clk,reset,'0','1');

    FDCPE_U4/lfsr_01: FDCPE port map (U4/lfsr_0(1),U4/lfsr_0(0),clk,reset,'0','1');

    FDCPE_U4/lfsr_00: FDCPE port map (U4/lfsr_0(0),U4/lfsr_0_D(0),clk,reset,'0','1');
    U4/lfsr_0_D(0) <= ((U4/lfsr_0(40) AND U4/lfsr_0(37))
    	OR (NOT U4/lfsr_0(40) AND NOT U4/lfsr_0(37)));

    db(8) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(8).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(8) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(8) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(8) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(8) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND U4/ena_lfsr(1) AND
    	N_PZ_30373));FDCPE_U4/ena_lfsr1: FDCPE port map (U4/ena_lfsr(1),db(8).PIN,clk,reset,'0',N_PZ_30413);

    FDCPE_U4/lfsr_130: FDCPE port map (U4/lfsr_1(30),U4/lfsr_1(29),clk,reset,'0','1');

    FDCPE_U4/lfsr_129: FDCPE port map (U4/lfsr_1(29),U4/lfsr_1(28),clk,reset,'0','1');

    FDCPE_U4/lfsr_128: FDCPE port map (U4/lfsr_1(28),U4/lfsr_1(27),clk,reset,'0','1');

    FDCPE_U4/lfsr_127: FDCPE port map (U4/lfsr_1(27),U4/lfsr_1(26),clk,reset,'0','1');

    FDCPE_U4/lfsr_126: FDCPE port map (U4/lfsr_1(26),U4/lfsr_1(25),clk,reset,'0','1');

    FDCPE_U4/lfsr_125: FDCPE port map (U4/lfsr_1(25),U4/lfsr_1(24),clk,reset,'0','1');

    FDCPE_U4/lfsr_124: FDCPE port map (U4/lfsr_1(24),U4/lfsr_1(23),clk,reset,'0','1');

    FDCPE_U4/lfsr_123: FDCPE port map (U4/lfsr_1(23),U4/lfsr_1(22),clk,reset,'0','1');

    FDCPE_U4/lfsr_122: FDCPE port map (U4/lfsr_1(22),U4/lfsr_1(21),clk,reset,'0','1');

    FDCPE_U4/lfsr_121: FDCPE port map (U4/lfsr_1(21),U4/lfsr_1(20),clk,reset,'0','1');

    FDCPE_U4/lfsr_120: FDCPE port map (U4/lfsr_1(20),U4/lfsr_1(19),clk,reset,'0','1');

    FDCPE_U4/lfsr_119: FDCPE port map (U4/lfsr_1(19),U4/lfsr_1(18),clk,reset,'0','1');

    FDCPE_U4/lfsr_118: FDCPE port map (U4/lfsr_1(18),U4/lfsr_1(17),clk,reset,'0','1');

    FDCPE_U4/lfsr_117: FDCPE port map (U4/lfsr_1(17),U4/lfsr_1(16),clk,reset,'0','1');

    FDCPE_U4/lfsr_116: FDCPE port map (U4/lfsr_1(16),U4/lfsr_1(15),clk,reset,'0','1');

    FDCPE_U4/lfsr_115: FDCPE port map (U4/lfsr_1(15),U4/lfsr_1(14),clk,reset,'0','1');

    FDCPE_U4/lfsr_114: FDCPE port map (U4/lfsr_1(14),U4/lfsr_1(13),clk,reset,'0','1');

    FDCPE_U4/lfsr_113: FDCPE port map (U4/lfsr_1(13),U4/lfsr_1(12),clk,reset,'0','1');

    FDCPE_U4/lfsr_112: FDCPE port map (U4/lfsr_1(12),U4/lfsr_1(11),clk,reset,'0','1');

    FDCPE_U4/lfsr_111: FDCPE port map (U4/lfsr_1(11),U4/lfsr_1(10),clk,reset,'0','1');

    FDCPE_U4/lfsr_110: FDCPE port map (U4/lfsr_1(10),U4/lfsr_1(9),clk,reset,'0','1');

    FDCPE_U4/lfsr_19: FDCPE port map (U4/lfsr_1(9),U4/lfsr_1(8),clk,reset,'0','1');

    FDCPE_U4/lfsr_18: FDCPE port map (U4/lfsr_1(8),U4/lfsr_1(7),clk,reset,'0','1');

    FDCPE_U4/lfsr_17: FDCPE port map (U4/lfsr_1(7),U4/lfsr_1(6),clk,reset,'0','1');

    FDCPE_U4/lfsr_16: FDCPE port map (U4/lfsr_1(6),U4/lfsr_1(5),clk,reset,'0','1');

    FDCPE_U4/lfsr_15: FDCPE port map (U4/lfsr_1(5),U4/lfsr_1(4),clk,reset,'0','1');

    FDCPE_U4/lfsr_14: FDCPE port map (U4/lfsr_1(4),U4/lfsr_1(3),clk,reset,'0','1');

    FDCPE_U4/lfsr_13: FDCPE port map (U4/lfsr_1(3),U4/lfsr_1(2),clk,reset,'0','1');

    FDCPE_U4/lfsr_12: FDCPE port map (U4/lfsr_1(2),U4/lfsr_1(1),clk,reset,'0','1');

    FDCPE_U4/lfsr_11: FDCPE port map (U4/lfsr_1(1),U4/lfsr_1(0),clk,reset,'0','1');

    FDCPE_U4/lfsr_10: FDCPE port map (U4/lfsr_1(0),U4/lfsr_1_D(0),clk,reset,'0','1');
    U4/lfsr_1_D(0) <= ((U4/lfsr_1(30) AND U4/lfsr_1(27))
    	OR (NOT U4/lfsr_1(30) AND NOT U4/lfsr_1(27)));

    FDCPE_counter1: FDCPE port map (counter(1),counter_D(1),clk,reset,'0','1');
    counter_D(1) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30591 AND
    	counter(1))
    	OR (estado_FFD2 AND estado_FFD1 AND NOT N_PZ_30322 AND
    	NOT N_PZ_30371 AND txena_reg_in AND NOT N_PZ_30591 AND counter(0) AND
    	NOT U4/ena_word_count2)
    	OR (estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
    	NOT N_PZ_30371 AND NOT N_PZ_30591 AND counter(0) AND NOT U4/ena_word_count2 AND
    	txena_out)
    	OR (NOT estado_FFD3 AND estado_FFD1 AND NOT N_PZ_30322 AND
    	NOT N_PZ_30371 AND ena_event_count AND enw1.COMB AND NOT N_PZ_30591 AND
    	counter(0)));

    FDCPE_counter3: FDCPE port map (counter(3),counter_D(3),clk,reset,'0','1');
    counter_D(3) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(3))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND
    	N_PZ_30591);

    FDCPE_counter4: FDCPE port map (counter(4),counter_D(4),clk,reset,'0','1');
    counter_D(4) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(4))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND
    	N_PZ_30591 AND counter(3));

    FDCPE_counter5: FDCPE port map (counter(5),counter_D(5),clk,reset,'0','1');
    counter_D(5) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(5))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND
    	N_PZ_30591 AND counter(3) AND counter(4));

    FDCPE_counter6: FDCPE port map (counter(6),counter_D(6),clk,reset,'0','1');
    counter_D(6) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(6))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(2) AND
    	N_PZ_30591 AND counter(3) AND counter(4) AND counter(5));

    FDCPE_counter7: FDCPE port map (counter(7),counter_D(7),clk,reset,'0','1');
    counter_D(7) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30589 AND
    	counter(7))
    	OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30589 AND
    	counter(2) AND N_PZ_30591 AND counter(3) AND counter(4) AND
    	counter(5) AND counter(6)));

    FDCPE_counter9: FDCPE port map (counter(9),counter_D(9),clk,reset,'0','1');
    counter_D(9) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(9))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(8) AND
    	N_PZ_30589);

    FDCPE_mword_count10: FDCPE port map (mword_count(10),mword_count_D(10),clk,U4/_n0029,'0','1');
    mword_count_D(10) <= NOT (((NOT mword_count(10) AND N_PZ_30354)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(10).PIN)));

    N_PZ_30354 <= NOT U4/ena_fill_mem
    	XOR ((NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND U4/ena_fill_mem)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT U4/ena_fill_mem));

    U4/_n0029 <= ((reset)
    	OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(2).PIN));

    FDCPE_counter11: FDCPE port map (counter(11),counter_D(11),clk,reset,'0','1');
    counter_D(11) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(11))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND
    	counter(8) AND N_PZ_30589 AND counter(9));

    FDCPE_mword_count11: FDCPE port map (mword_count(11),mword_count_D(11),clk,U4/_n0029,'0','1');
    mword_count_D(11) <= NOT (((N_PZ_30354 AND NOT mword_count(11))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(11).PIN)));

    FDCPE_counter13: FDCPE port map (counter(13),counter_D(13),clk,reset,'0','1');
    counter_D(13) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(13))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND
    	counter(8) AND N_PZ_30589 AND counter(9) AND counter(11) AND
    	counter(12));

    FDCPE_counter12: FDCPE port map (counter(12),counter_D(12),clk,reset,'0','1');
    counter_D(12) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(12))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND
    	counter(8) AND N_PZ_30589 AND counter(9) AND counter(11));

    FDCPE_mword_count13: FDCPE port map (mword_count(13),mword_count_D(13),clk,U4/_n0029,'0','1');
    mword_count_D(13) <= NOT (((N_PZ_30354 AND NOT mword_count(13))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(13).PIN)));

    FDCPE_counter14: FDCPE port map (counter(14),counter_D(14),clk,reset,'0','1');
    counter_D(14) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(14) AND
    	NOT N_PZ_30547)
    	OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(10) AND
    	counter(8) AND N_PZ_30589 AND counter(9) AND counter(11) AND
    	counter(13) AND counter(12) AND NOT N_PZ_30547));

    N_PZ_30547 <= (counter(10) AND counter(8) AND N_PZ_30589 AND
    	counter(9) AND counter(11) AND counter(13) AND counter(12) AND
    	counter(14));

    FDCPE_mword_count14: FDCPE port map (mword_count(14),mword_count_D(14),clk,U4/_n0029,'0','1');
    mword_count_D(14) <= NOT (((N_PZ_30354 AND NOT mword_count(14))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(14).PIN)));

    FDCPE_mword_count4: FDCPE port map (mword_count(4),mword_count_D(4),clk,U4/_n0029,'0','1');
    mword_count_D(4) <= NOT (((N_PZ_30354 AND NOT mword_count(4))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(4).PIN)));

    FDCPE_mword_count5: FDCPE port map (mword_count(5),mword_count_D(5),clk,U4/_n0029,'0','1');
    mword_count_D(5) <= NOT (((N_PZ_30354 AND NOT mword_count(5))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(5).PIN)));

    FDCPE_mword_count6: FDCPE port map (mword_count(6),mword_count_D(6),clk,U4/_n0029,'0','1');
    mword_count_D(6) <= NOT (((N_PZ_30354 AND NOT mword_count(6))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(6).PIN)));

    FDCPE_mword_count7: FDCPE port map (mword_count(7),mword_count_D(7),clk,U4/_n0029,'0','1');
    mword_count_D(7) <= NOT (((N_PZ_30354 AND NOT mword_count(7))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(7).PIN)));

    FDCPE_mword_count8: FDCPE port map (mword_count(8),mword_count_D(8),clk,U4/_n0029,'0','1');
    mword_count_D(8) <= NOT (((N_PZ_30354 AND NOT mword_count(8))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(8).PIN)));

    FDCPE_mword_count9: FDCPE port map (mword_count(9),mword_count_D(9),clk,U4/_n0029,'0','1');
    mword_count_D(9) <= NOT (((N_PZ_30354 AND NOT mword_count(9))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(9).PIN)));

    Mcompar__n0026__n003420 <= ((counter(2) AND NOT mword_count(2))
    	OR (NOT counter(2) AND mword_count(2))
    	OR (counter(0) AND NOT mword_count(0))
    	OR (NOT counter(0) AND mword_count(0))
    	OR (counter(1) AND NOT mword_count(1))
    	OR (NOT counter(1) AND mword_count(1))
    	OR (counter(3) AND NOT mword_count(3))
    	OR (NOT counter(3) AND mword_count(3))
    	OR (counter(12) AND NOT mword_count(12))
    	OR (NOT counter(12) AND mword_count(12))
    	OR (counter(15) AND NOT mword_count(15))
    	OR (NOT counter(15) AND mword_count(15))
    	OR (counter(16) AND NOT mword_count(16))
    	OR (NOT counter(16) AND mword_count(16))
    	OR (counter(17) AND NOT mword_count(17))
    	OR (NOT counter(17) AND mword_count(17)));

    FDCPE_mword_count0: FDCPE port map (mword_count(0),mword_count_D(0),clk,U4/_n0029,'0','1');
    mword_count_D(0) <= NOT (((N_PZ_30354 AND NOT mword_count(0))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(0).PIN)));

    FDCPE_mword_count12: FDCPE port map (mword_count(12),mword_count_D(12),clk,U4/_n0029,'0','1');
    mword_count_D(12) <= NOT (((N_PZ_30354 AND NOT mword_count(12))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(12).PIN)));

    FDCPE_counter15: FDCPE port map (counter(15),counter_D(15),clk,reset,'0','1');
    counter_D(15) <= ((NOT N_PZ_30322 AND NOT N_PZ_30371 AND N_PZ_30547 AND
    	NOT counter(15))
    	OR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND NOT N_PZ_30547 AND
    	counter(15)));

    FDCPE_mword_count15: FDCPE port map (mword_count(15),mword_count_D(15),clk,U4/_n0029,'0','1');
    mword_count_D(15) <= NOT (((N_PZ_30354 AND NOT mword_count(15))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(15).PIN)));

    FDCPE_counter16: FDCPE port map (counter(16),counter_D(16),clk,reset,'0','1');
    counter_D(16) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(16))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND N_PZ_30547 AND
    	counter(15));

    FDCPE_mword_count16: FDCPE port map (mword_count(16),mword_count_D(16),clk,U4/_n0029,'0','1');
    mword_count_D(16) <= NOT ((NOT U4/ena_fill_mem AND NOT mword_count(16))
    	XOR ((NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(0).PIN AND
    	U4/ena_fill_mem)
    	OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(0).PIN AND
    	mword_count(16))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND U4/ena_fill_mem AND
    	NOT mword_count(16))
    	OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(0).PIN AND
    	NOT U4/ena_fill_mem AND NOT mword_count(16))));

    FDCPE_counter17: FDCPE port map (counter(17),counter_D(17),clk,reset,'0','1');
    counter_D(17) <= (NOT N_PZ_30322 AND NOT N_PZ_30371 AND counter(17))
    	XOR (NOT N_PZ_30322 AND NOT N_PZ_30371 AND N_PZ_30547 AND
    	counter(15) AND counter(16));

    FDCPE_mword_count17: FDCPE port map (mword_count(17),mword_count_D(17),clk,U4/_n0029,'0','1');
    mword_count_D(17) <= NOT ((NOT U4/ena_fill_mem AND NOT mword_count(17))
    	XOR ((NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN AND
    	U4/ena_fill_mem)
    	OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN AND
    	mword_count(17))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND U4/ena_fill_mem AND
    	NOT mword_count(17))
    	OR (NOT add(5) AND cs AND add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(1).PIN AND
    	NOT U4/ena_fill_mem AND NOT mword_count(17))));

    FDCPE_mword_count1: FDCPE port map (mword_count(1),mword_count_D(1),clk,U4/_n0029,'0','1');
    mword_count_D(1) <= NOT (((N_PZ_30354 AND NOT mword_count(1))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(1).PIN)));

    FDCPE_mword_count2: FDCPE port map (mword_count(2),mword_count_D(2),clk,U4/_n0029,'0','1');
    mword_count_D(2) <= NOT (((N_PZ_30354 AND NOT mword_count(2))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(2).PIN)));

    FDCPE_mword_count3: FDCPE port map (mword_count(3),mword_count_D(3),clk,U4/_n0029,'0','1');
    mword_count_D(3) <= NOT (((N_PZ_30354 AND NOT mword_count(3))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND add(0) AND enw1 AND NOT enw2 AND NOT db(3).PIN)));

    _n003432 <= (NOT estado_XX_FFD146 AND enw1.COMB AND txena_reg_in);

    U4/_n00084 <= (NOT N_PZ_30371 AND NOT U4/_n0051 AND NOT reset);

    FDCPE_mem_pointer10: FDCPE port map (mem_pointer(10),mem_pointer_D(10),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(10) <= ((NOT U4/_n0081 AND mem_pointer(10) AND NOT N_PZ_30575)
    	OR (NOT U4/_n0081 AND NOT mem_pointer(10) AND N_PZ_30575)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(10))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(10).PIN));

    N_PZ_30575 <= (mem_pointer(4) AND N_PZ_30580 AND mem_pointer(5) AND
    	mem_pointer(6) AND mem_pointer(7) AND mem_pointer(8) AND mem_pointer(9));

    FDCPE_mem_pointer4: FDCPE port map (mem_pointer(4),mem_pointer_D(4),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(4) <= ((NOT U4/_n0081 AND mem_pointer(4) AND NOT N_PZ_30580)
    	OR (NOT U4/_n0081 AND NOT mem_pointer(4) AND N_PZ_30580)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(4))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(4).PIN));

    N_PZ_30580 <= (NOT mem_is_full AND mem_pointer(0) AND tp7 AND
    	mem_pointer(1) AND mem_pointer(2) AND mem_pointer(3));

    FDCPE_mem_pointer1: FDCPE port map (mem_pointer(1),mem_pointer_D(1),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(1) <= mem_pointer(1)
    	XOR ((add(0) AND db(1).PIN AND U4/_n0081 AND NOT mem_pointer(1))
    	OR (add(0) AND NOT db(1).PIN AND U4/_n0081 AND mem_pointer(1))
    	OR (NOT mem_is_full AND mem_pointer(0) AND NOT U4/_n0081 AND tp7));

    FDCPE_mem_pointer2: FDCPE port map (mem_pointer(2),mem_pointer_D(2),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(2) <= ((mem_is_full AND NOT U4/_n0081 AND mem_pointer(2))
    	OR (NOT mem_pointer(0) AND NOT U4/_n0081 AND mem_pointer(2))
    	OR (NOT U4/_n0081 AND NOT tp7 AND mem_pointer(2))
    	OR (NOT U4/_n0081 AND NOT mem_pointer(1) AND mem_pointer(2))
    	OR (NOT mem_is_full AND mem_pointer(0) AND NOT U4/_n0081 AND tp7 AND
    	mem_pointer(1) AND NOT mem_pointer(2))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(2))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(2).PIN));

    FDCPE_mem_pointer3: FDCPE port map (mem_pointer(3),mem_pointer_D(3),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(3) <= ((NOT U4/_n0081 AND NOT N_PZ_30580 AND mem_pointer(3))
    	OR (NOT mem_is_full AND mem_pointer(0) AND NOT U4/_n0081 AND tp7 AND
    	NOT N_PZ_30580 AND mem_pointer(1) AND mem_pointer(2))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(3))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(3).PIN));

    FDCPE_mem_pointer5: FDCPE port map (mem_pointer(5),mem_pointer_D(5),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(5) <= NOT ((NOT mem_pointer(5) AND NOT U4/_n002121)
    	XOR ((U4/_n0081 AND mem_pointer(5) AND NOT U4/_n002121)
    	OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
    	NOT U4/_n002121)));

    U4/_n002121 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(5))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(5).PIN));

    FDCPE_mem_pointer6: FDCPE port map (mem_pointer(6),mem_pointer_D(6),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(6) <= ((NOT U4/_n0081 AND NOT mem_pointer(4) AND mem_pointer(6))
    	OR (NOT U4/_n0081 AND NOT N_PZ_30580 AND mem_pointer(6))
    	OR (NOT U4/_n0081 AND NOT mem_pointer(5) AND mem_pointer(6))
    	OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
    	mem_pointer(5) AND NOT mem_pointer(6))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(6))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(6).PIN));

    FDCPE_mem_pointer7: FDCPE port map (mem_pointer(7),mem_pointer_D(7),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(7) <= NOT ((NOT mem_pointer(7) AND NOT U4/_n001921)
    	XOR ((U4/_n0081 AND mem_pointer(7) AND NOT U4/_n001921)
    	OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
    	mem_pointer(5) AND mem_pointer(6) AND NOT U4/_n001921)));

    U4/_n001921 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(7))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(7).PIN));

    FDCPE_mem_pointer8: FDCPE port map (mem_pointer(8),mem_pointer_D(8),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(8) <= NOT ((NOT mem_pointer(8) AND NOT U4/_n001821)
    	XOR ((U4/_n0081 AND mem_pointer(8) AND NOT U4/_n001821)
    	OR (NOT U4/_n0081 AND mem_pointer(4) AND N_PZ_30580 AND
    	mem_pointer(5) AND mem_pointer(6) AND mem_pointer(7) AND NOT U4/_n001821)));

    U4/_n001821 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(8))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(8).PIN));

    FDCPE_mem_pointer9: FDCPE port map (mem_pointer(9),mem_pointer_D(9),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(9) <= ((NOT U4/_n0081 AND NOT N_PZ_30575 AND mem_pointer(9))
    	OR (NOT U4/_n0081 AND NOT N_PZ_30575 AND mem_pointer(4) AND
    	N_PZ_30580 AND mem_pointer(5) AND mem_pointer(6) AND mem_pointer(7) AND
    	mem_pointer(8))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(9))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(9).PIN));

    FDCPE_mem_pointer11: FDCPE port map (mem_pointer(11),mem_pointer_D(11),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(11) <= NOT ((NOT mem_pointer(11) AND NOT U4/_n001521)
    	XOR ((U4/_n0081 AND mem_pointer(11) AND NOT U4/_n001521)
    	OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND
    	NOT U4/_n001521)));

    U4/_n001521 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(11))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(11).PIN));

    FDCPE_mem_pointer12: FDCPE port map (mem_pointer(12),mem_pointer_D(12),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(12) <= ((NOT U4/_n0081 AND NOT mem_pointer(10) AND mem_pointer(12))
    	OR (NOT U4/_n0081 AND NOT N_PZ_30575 AND mem_pointer(12))
    	OR (NOT U4/_n0081 AND NOT mem_pointer(11) AND mem_pointer(12))
    	OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND
    	mem_pointer(11) AND NOT mem_pointer(12))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(12))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(12).PIN));

    FDCPE_mem_pointer13: FDCPE port map (mem_pointer(13),mem_pointer_D(13),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(13) <= NOT ((NOT mem_pointer(13) AND NOT U4/_n001321)
    	XOR ((U4/_n0081 AND mem_pointer(13) AND NOT U4/_n001321)
    	OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND
    	mem_pointer(11) AND mem_pointer(12) AND NOT U4/_n001321)));

    U4/_n001321 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(13))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(13).PIN));

    FDCPE_mem_pointer14: FDCPE port map (mem_pointer(14),mem_pointer_D(14),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(14) <= ((NOT U4/_n0081 AND mem_pointer(14) AND NOT N_PZ_30542)
    	OR (NOT U4/_n0081 AND mem_pointer(10) AND N_PZ_30575 AND
    	mem_pointer(11) AND mem_pointer(12) AND mem_pointer(13) AND NOT N_PZ_30542)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(14))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(14).PIN));

    N_PZ_30542 <= (mem_pointer(10) AND N_PZ_30575 AND mem_pointer(11) AND
    	mem_pointer(12) AND mem_pointer(13) AND mem_pointer(14));

    FDCPE_mem_pointer15: FDCPE port map (mem_pointer(15),mem_pointer_D(15),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(15) <= ((NOT U4/_n0081 AND N_PZ_30542 AND NOT mem_pointer(15))
    	OR (NOT U4/_n0081 AND NOT N_PZ_30542 AND mem_pointer(15))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND mem_pointer(15))
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND db(15).PIN));

    FDCPE_mem_pointer16: FDCPE port map (mem_pointer(16),mem_pointer_D(16),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(16) <= NOT ((NOT mem_pointer(16) AND NOT U4/_n001021)
    	XOR ((U4/_n0081 AND mem_pointer(16) AND NOT U4/_n001021)
    	OR (NOT U4/_n0081 AND N_PZ_30542 AND mem_pointer(15) AND
    	NOT U4/_n001021)));

    U4/_n001021 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(0).PIN)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND mem_pointer(16)));

    FDCPE_mem_pointer17: FDCPE port map (mem_pointer(17),mem_pointer_D(17),clk,NOT U4/_n00084,'0','1');
    mem_pointer_D(17) <= NOT ((NOT mem_pointer(17) AND NOT U4/_n000921)
    	XOR ((U4/_n0081 AND mem_pointer(17) AND NOT U4/_n000921)
    	OR (NOT U4/_n0081 AND N_PZ_30542 AND mem_pointer(15) AND
    	mem_pointer(16) AND NOT U4/_n000921)));

    U4/_n000921 <= ((NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	add(1) AND NOT add(0) AND enw1 AND NOT enw2 AND db(1).PIN)
    	OR (NOT add(5) AND cs AND NOT add(2) AND NOT add(4) AND NOT add(3) AND
    	NOT add(1) AND add(0) AND enw1 AND NOT enw2 AND mem_pointer(17)));

    Mcompar__n0029__n0027 <= ((mevent_count(11) AND NOT counter(11))
    	OR (NOT mevent_count(11) AND counter(11)));

    Mcompar__n0029__n0029 <= ((mevent_count(13) AND NOT counter(13))
    	OR (NOT mevent_count(13) AND counter(13)));

    estado_XX_FFD135 <= ((counter(16))
    	OR (counter(17))
    	OR (mevent_count(0) AND NOT counter(0))
    	OR (NOT mevent_count(0) AND counter(0))
    	OR (mevent_count(12) AND NOT counter(12))
    	OR (NOT mevent_count(12) AND counter(12))
    	OR (mevent_count(15) AND NOT counter(15))
    	OR (NOT mevent_count(15) AND counter(15))
    	OR (mevent_count(1) AND NOT counter(1))
    	OR (NOT mevent_count(1) AND counter(1))
    	OR (mevent_count(2) AND NOT counter(2))
    	OR (NOT mevent_count(2) AND counter(2))
    	OR (mevent_count(3) AND NOT counter(3))
    	OR (NOT mevent_count(3) AND counter(3)));

    estado_XX_FFD136 <= ((mevent_count(14) AND mevent_count(9) AND counter(9) AND
    	counter(14))
    	OR (mevent_count(14) AND NOT mevent_count(9) AND NOT counter(9) AND
    	counter(14))
    	OR (NOT mevent_count(14) AND mevent_count(9) AND counter(9) AND
    	NOT counter(14))
    	OR (NOT mevent_count(14) AND NOT mevent_count(9) AND NOT counter(9) AND
    	NOT counter(14)));

    N_PZ_30372 <= ((mevent_count(4) AND counter(4))
    	OR (NOT mevent_count(4) AND NOT counter(4)));

    N_PZ_30405 <= ((mevent_count(5) AND counter(5))
    	OR (NOT mevent_count(5) AND NOT counter(5)));

    N_PZ_30510 <= ((mevent_count(6) AND counter(6))
    	OR (NOT mevent_count(6) AND NOT counter(6)));

    N_PZ_30539 <= ((mevent_count(7) AND counter(7))
    	OR (NOT mevent_count(7) AND NOT counter(7)));

    N_PZ_30599 <= ((estado_FFD2 AND ena_ceros_mem AND NOT ena_event_count AND
    	NOT mem_is_full AND NOT Mcompar__n0026__n0034 AND NOT U4/ena_word_count2)
    	OR (NOT estado_FFD2 AND ena_event_count AND NOT mevent_count(0) AND
    	NOT mevent_count(10) AND NOT mevent_count(11) AND NOT mevent_count(12) AND
    	NOT mevent_count(13) AND NOT mevent_count(14) AND NOT mevent_count(15) AND
    	NOT mevent_count(1) AND NOT mevent_count(2) AND NOT mevent_count(3) AND
    	NOT mevent_count(4) AND NOT mevent_count(5) AND NOT mevent_count(6) AND
    	NOT mevent_count(7) AND NOT mevent_count(8) AND NOT mevent_count(9) AND enw1.COMB));

    cspare(1) <= '0';

    cspare(2) <= '0';

    cspare(3) <= '0';

    cspare(4) <= '0';

    cspare(5) <= '0';

    cspare(6) <= '0';

    cspare(7) <= '0';

    cspare(8) <= '0';

    cspare(9) <= '0';

    FDCPE_dout0: FDCPE port map (dout_I(0),mdat(0).PIN,clk,reset,'0','1');
    dout(0) <= dout_I(0) when dout_OE(0) = '1' else 'Z';
    dout_OE(0) <= cspare(11);

    FDCPE_dout10: FDCPE port map (dout_I(10),mdat(10).PIN,clk,reset,'0','1');
    dout(10) <= dout_I(10) when dout_OE(10) = '1' else 'Z';
    dout_OE(10) <= cspare(11);

    FDCPE_dout11: FDCPE port map (dout_I(11),mdat(11).PIN,clk,reset,'0','1');
    dout(11) <= dout_I(11) when dout_OE(11) = '1' else 'Z';
    dout_OE(11) <= cspare(11);

    FDCPE_dout12: FDCPE port map (dout_I(12),mdat(12).PIN,clk,reset,'0','1');
    dout(12) <= dout_I(12) when dout_OE(12) = '1' else 'Z';
    dout_OE(12) <= cspare(11);

    FDCPE_dout13: FDCPE port map (dout_I(13),mdat(13).PIN,clk,reset,'0','1');
    dout(13) <= dout_I(13) when dout_OE(13) = '1' else 'Z';
    dout_OE(13) <= cspare(11);

    FDCPE_dout14: FDCPE port map (dout_I(14),mdat(14).PIN,clk,reset,'0','1');
    dout(14) <= dout_I(14) when dout_OE(14) = '1' else 'Z';
    dout_OE(14) <= cspare(11);

    FDCPE_dout15: FDCPE port map (dout_I(15),mdat(15).PIN,clk,reset,'0','1');
    dout(15) <= dout_I(15) when dout_OE(15) = '1' else 'Z';
    dout_OE(15) <= cspare(11);

    FDCPE_dout1: FDCPE port map (dout_I(1),mdat(1).PIN,clk,reset,'0','1');
    dout(1) <= dout_I(1) when dout_OE(1) = '1' else 'Z';
    dout_OE(1) <= cspare(11);

    FDCPE_dout2: FDCPE port map (dout_I(2),mdat(2).PIN,clk,reset,'0','1');
    dout(2) <= dout_I(2) when dout_OE(2) = '1' else 'Z';
    dout_OE(2) <= cspare(11);

    FDCPE_dout3: FDCPE port map (dout_I(3),mdat(3).PIN,clk,reset,'0','1');
    dout(3) <= dout_I(3) when dout_OE(3) = '1' else 'Z';
    dout_OE(3) <= cspare(11);

    FDCPE_dout4: FDCPE port map (dout_I(4),mdat(4).PIN,clk,reset,'0','1');
    dout(4) <= dout_I(4) when dout_OE(4) = '1' else 'Z';
    dout_OE(4) <= cspare(11);

    FDCPE_dout5: FDCPE port map (dout_I(5),mdat(5).PIN,clk,reset,'0','1');
    dout(5) <= dout_I(5) when dout_OE(5) = '1' else 'Z';
    dout_OE(5) <= cspare(11);

    FDCPE_dout6: FDCPE port map (dout_I(6),mdat(6).PIN,clk,reset,'0','1');
    dout(6) <= dout_I(6) when dout_OE(6) = '1' else 'Z';
    dout_OE(6) <= cspare(11);

    FDCPE_dout7: FDCPE port map (dout_I(7),mdat(7).PIN,clk,reset,'0','1');
    dout(7) <= dout_I(7) when dout_OE(7) = '1' else 'Z';
    dout_OE(7) <= cspare(11);

    FDCPE_dout8: FDCPE port map (dout_I(8),mdat(8).PIN,clk,reset,'0','1');
    dout(8) <= dout_I(8) when dout_OE(8) = '1' else 'Z';
    dout_OE(8) <= cspare(11);

    FDCPE_dout9: FDCPE port map (dout_I(9),mdat(9).PIN,clk,reset,'0','1');
    dout(9) <= dout_I(9) when dout_OE(9) = '1' else 'Z';
    dout_OE(9) <= cspare(11);

    ds_out <= (NOT ds1 AND NOT ds0);

    dtack_mem <= NOT ((NOT tp5 AND NOT dtack_blk));

    FDCPE_tp5: FDCPE port map (tp5,tp5_D,dsdly<1>,tp5_CLR,'0','1');
    tp5_D <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND
    	am(3) AND NOT brdsel24 AND NOT am(1));
    tp5_CLR <= (ds1 AND ds0 AND NOT dsdly(1));

    FDCPE_dtack_blk: FDCPE port map (dtack_blk,dtack_blk_D,dsdly<1>,dtack_blk_CLR,'0','1');
    dtack_blk_D <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND
    	am(3) AND NOT brdsel24 AND am(1));
    dtack_blk_CLR <= (ds1 AND ds0 AND NOT dsdly(1));

    g245_mem <= NOT ((lword AND iack AND am(5) AND am(0) AND NOT am(2) AND NOT ds1 AND
    	NOT ds0 AND am(4) AND am(3) AND NOT brdsel24));

    led(0) <= NOT ((NOT U1/q2 AND NOT U2/b2));

    FDCPE_U1/q2: FDCPE port map (U1/q2,U1/q2_D,dsdly<0>,dsdly(1),'0','1');
    U1/q2_D <= (NOT write AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND
    	am(4) AND am(3) AND NOT brdsel24 AND NOT am(1));

    FDCPE_U2/b2: FDCPE port map (U2/b2,U2/b2_D,dsdly<0>,dsdly(1),'0','1');
    U2/b2_D <= (NOT write AND lword AND iack AND am(5) AND am(0) AND NOT am(2) AND
    	am(4) AND am(3) AND NOT brdsel24 AND am(1));

    led(1) <= (write AND N_PZ_30489);

    madd(0) <= NOT (((NOT add(0) AND NOT N_PZ_30394)
    	OR (NOT N_PZ_30322 AND NOT mem_pointer(0))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(0))));

    FDCPE_U3/counter_add0: FDCPE port map (U3/counter_add(0),U3/counter_add_D(0),U3/counter_add_C(0),U3/counter_add_CLR(0),U3/counter_add_PRE(0),'1');
    U3/counter_add_D(0) <= NOT (((NOT add(0) AND U2/latch3)
    	OR (U3/counter_add(0) AND NOT U2/latch3)));
    U3/counter_add_C(0) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(0) <= (NOT add(0) AND U2/latch3);
    U3/counter_add_PRE(0) <= (add(0) AND U2/latch3);

    U2/latch3 <= ((ds1 AND NOT U2/qlt)
    	OR (ds0 AND NOT U2/qlt));

    FDCPE_U2/qlt: FDCPE port map (U2/qlt,U2/qlt_D,dsdly<0>,as,'0','1');
    U2/qlt_D <= (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND
    	am(3) AND NOT brdsel24 AND am(1));

    N_PZ_30394 <= ((NOT N_PZ_30322)
    	OR (lword AND iack AND am(5) AND am(0) AND NOT am(2) AND am(4) AND
    	am(3) AND NOT brdsel24 AND am(1)));

    madd(10) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(10))
    	OR (NOT N_PZ_30394 AND NOT add(10))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(2))));

    LDCP_U3/add_latched2: LDCP port map (U3/add_latched(2),add(10),U2/latch3,'0','0');

    madd(11) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(11))
    	OR (NOT N_PZ_30394 AND NOT add(11))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(3))));

    FDCPE_U3/add_latched3: FDCPE port map (U3/add_latched(3),add(11),U2/latch3,'0','0','1');

    madd(12) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(12))
    	OR (NOT N_PZ_30394 AND NOT add(12))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(4))));

    LDCP_U3/add_latched4: LDCP port map (U3/add_latched(4),add(12),U2/latch3,'0','0');

    madd(13) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(13))
    	OR (NOT N_PZ_30394 AND NOT add(13))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(5))));

    FDCPE_U3/add_latched5: FDCPE port map (U3/add_latched(5),add(13),U2/latch3,'0','0','1');

    madd(14) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(14))
    	OR (NOT N_PZ_30394 AND NOT add(14))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(6))));

    FDCPE_U3/add_latched6: FDCPE port map (U3/add_latched(6),add(14),U2/latch3,'0','0','1');

    madd(15) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(15))
    	OR (NOT N_PZ_30394 AND NOT add(15))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(7))));

    FDCPE_U3/add_latched7: FDCPE port map (U3/add_latched(7),add(15),U2/latch3,'0','0','1');

    madd(16) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(16))
    	OR (NOT N_PZ_30394 AND NOT add(16))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(8))));

    FDCPE_U3/add_latched8: FDCPE port map (U3/add_latched(8),add(16),U2/latch3,'0','0','1');

    madd(17) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(17))
    	OR (NOT N_PZ_30394 AND NOT add(17))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(9))));

    FDCPE_U3/add_latched9: FDCPE port map (U3/add_latched(9),add(17),U2/latch3,'0','0','1');

    madd(1) <= NOT (((NOT add(1) AND NOT N_PZ_30394)
    	OR (NOT N_PZ_30322 AND NOT mem_pointer(1))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(1))));

    FDCPE_U3/counter_add1: FDCPE port map (U3/counter_add(1),U3/counter_add_D(1),U3/counter_add_C(1),U3/counter_add_CLR(1),U3/counter_add_PRE(1),'1');
    U3/counter_add_D(1) <= NOT (((NOT add(1) AND U2/latch3)
    	OR (U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(1))
    	OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
    	NOT U3/counter_add(1))));
    U3/counter_add_C(1) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(1) <= (NOT add(1) AND U2/latch3);
    U3/counter_add_PRE(1) <= (add(1) AND U2/latch3);

    madd(2) <= NOT (((NOT add(2) AND NOT N_PZ_30394)
    	OR (NOT N_PZ_30322 AND NOT mem_pointer(2))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(2))));

    FDCPE_U3/counter_add2: FDCPE port map (U3/counter_add(2),U3/counter_add_D(2),U3/counter_add_C(2),U3/counter_add_CLR(2),U3/counter_add_PRE(2),'1');
    U3/counter_add_D(2) <= ((add(2) AND U2/latch3)
    	OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(2))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
    	U3/counter_add(2))
    	OR (U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(1) AND NOT U3/counter_add(2)));
    U3/counter_add_C(2) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(2) <= (NOT add(2) AND U2/latch3);
    U3/counter_add_PRE(2) <= (add(2) AND U2/latch3);

    madd(3) <= NOT (((NOT add(3) AND NOT N_PZ_30394)
    	OR (NOT N_PZ_30322 AND NOT mem_pointer(3))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(3))));

    FDCPE_U3/counter_add3: FDCPE port map (U3/counter_add(3),U3/counter_add_D(3),U3/counter_add_C(3),U3/counter_add_CLR(3),U3/counter_add_PRE(3),'1');
    U3/counter_add_D(3) <= NOT (((NOT add(3) AND U2/latch3)
    	OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
    	NOT U3/counter_add(3))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
    	NOT U3/counter_add(3))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
    	NOT U3/counter_add(3))
    	OR (U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3))));
    U3/counter_add_C(3) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(3) <= (NOT add(3) AND U2/latch3);
    U3/counter_add_PRE(3) <= (add(3) AND U2/latch3);

    madd(4) <= NOT (((NOT add(4) AND NOT N_PZ_30394)
    	OR (NOT N_PZ_30322 AND NOT mem_pointer(4))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(4))));

    FDCPE_U3/counter_add4: FDCPE port map (U3/counter_add(4),U3/counter_add_D(4),U3/counter_add_C(4),U3/counter_add_CLR(4),U3/counter_add_PRE(4),'1');
    U3/counter_add_D(4) <= ((add(4) AND U2/latch3)
    	OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(4))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
    	U3/counter_add(4))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
    	U3/counter_add(4))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
    	U3/counter_add(4))
    	OR (U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
    	NOT U3/counter_add(4)));
    U3/counter_add_C(4) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(4) <= (NOT add(4) AND U2/latch3);
    U3/counter_add_PRE(4) <= (add(4) AND U2/latch3);

    madd(5) <= NOT (((NOT add(5) AND NOT N_PZ_30394)
    	OR (NOT N_PZ_30322 AND NOT mem_pointer(5))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(5))));

    FDCPE_U3/counter_add5: FDCPE port map (U3/counter_add(5),U3/counter_add_D(5),U3/counter_add_C(5),U3/counter_add_CLR(5),U3/counter_add_PRE(5),'1');
    U3/counter_add_D(5) <= NOT (((NOT add(5) AND U2/latch3)
    	OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
    	NOT U3/counter_add(5))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
    	NOT U3/counter_add(5))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
    	NOT U3/counter_add(5))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
    	NOT U3/counter_add(5))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(4) AND
    	NOT U3/counter_add(5))
    	OR (U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
    	U3/counter_add(4) AND U3/counter_add(5))));
    U3/counter_add_C(5) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(5) <= (NOT add(5) AND U2/latch3);
    U3/counter_add_PRE(5) <= (add(5) AND U2/latch3);

    madd(6) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(6))
    	OR (NOT N_PZ_30394 AND NOT add(6))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(6))));

    FDCPE_U3/counter_add6: FDCPE port map (U3/counter_add(6),U3/counter_add_D(6),U3/counter_add_C(6),U3/counter_add_CLR(6),U3/counter_add_PRE(6),'1');
    U3/counter_add_D(6) <= NOT (((U2/latch3 AND NOT add(6))
    	OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
    	NOT U3/counter_add(6))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
    	NOT U3/counter_add(6))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
    	NOT U3/counter_add(6))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
    	NOT U3/counter_add(6))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(4) AND
    	NOT U3/counter_add(6))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(5) AND
    	NOT U3/counter_add(6))
    	OR (U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
    	U3/counter_add(4) AND U3/counter_add(5) AND U3/counter_add(6))));
    U3/counter_add_C(6) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(6) <= (U2/latch3 AND NOT add(6));
    U3/counter_add_PRE(6) <= (U2/latch3 AND add(6));

    madd(7) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(7))
    	OR (NOT N_PZ_30394 AND NOT add(7))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/counter_add(7))));

    FDCPE_U3/counter_add7: FDCPE port map (U3/counter_add(7),U3/counter_add_D(7),U3/counter_add_C(7),U3/counter_add_CLR(7),U3/counter_add_PRE(7),'1');
    U3/counter_add_D(7) <= NOT (((U2/latch3 AND NOT add(7))
    	OR (NOT U3/counter_add(0) AND NOT U2/latch3 AND
    	NOT U3/counter_add(7))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(1) AND
    	NOT U3/counter_add(7))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(2) AND
    	NOT U3/counter_add(7))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(3) AND
    	NOT U3/counter_add(7))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(4) AND
    	NOT U3/counter_add(7))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(5) AND
    	NOT U3/counter_add(7))
    	OR (NOT U2/latch3 AND NOT U3/counter_add(6) AND
    	NOT U3/counter_add(7))
    	OR (U3/counter_add(0) AND NOT U2/latch3 AND
    	U3/counter_add(1) AND U3/counter_add(2) AND U3/counter_add(3) AND
    	U3/counter_add(4) AND U3/counter_add(5) AND U3/counter_add(6) AND
    	U3/counter_add(7))));
    U3/counter_add_C(7) <= (dsdly(1) AND NOT dsdly(0));
    U3/counter_add_CLR(7) <= (U2/latch3 AND NOT add(7));
    U3/counter_add_PRE(7) <= (U2/latch3 AND add(7));

    madd(8) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(8))
    	OR (NOT N_PZ_30394 AND NOT add(8))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(0))));

    FDCPE_U3/add_latched0: FDCPE port map (U3/add_latched(0),add(8),U2/latch3,'0','0','1');

    madd(9) <= NOT (((NOT N_PZ_30322 AND NOT mem_pointer(9))
    	OR (NOT N_PZ_30394 AND NOT add(9))
    	OR (N_PZ_30322 AND lword AND iack AND am(5) AND am(0) AND
    	NOT am(2) AND am(4) AND am(3) AND NOT brdsel24 AND am(1) AND
    	NOT U3/add_latched(1))));

    FDCPE_U3/add_latched1: FDCPE port map (U3/add_latched(1),add(9),U2/latch3,'0','0','1');

    mdat_I(0) <= NOT (((NOT db(0).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(0))));

    N_PZ_30353 <= (NOT write AND N_PZ_30322 AND N_PZ_30489);

    FDCPE_dout_reg_in0: FDCPE port map (dout_reg_in(0),dout_reg_in_2(0),clk,reset,'0','1');

    FDCPE_dout_reg_in_20: FDCPE port map (dout_reg_in_2(0),dout(0).PIN,clk,reset,'0','1');

    _n0088_MC.GLB <= ((estado_FFD2 AND NOT estado_FFD3)
    	OR (NOT estado_FFD3 AND NOT estado_FFD1 AND NOT write AND N_PZ_30489));

    mdat_I(10) <= NOT (((NOT db(10).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(10))));

    FDCPE_dout_reg_in10: FDCPE port map (dout_reg_in(10),dout_reg_in_2(10),clk,reset,'0','1');

    FDCPE_dout_reg_in_210: FDCPE port map (dout_reg_in_2(10),dout(10).PIN,clk,reset,'0','1');

    mdat_I(11) <= NOT (((NOT db(11).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(11))));

    FDCPE_dout_reg_in11: FDCPE port map (dout_reg_in(11),dout_reg_in_2(11),clk,reset,'0','1');

    FDCPE_dout_reg_in_211: FDCPE port map (dout_reg_in_2(11),dout(11).PIN,clk,reset,'0','1');

    mdat_I(12) <= NOT (((NOT db(12).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(12))));

    FDCPE_dout_reg_in12: FDCPE port map (dout_reg_in(12),dout_reg_in_2(12),clk,reset,'0','1');

    FDCPE_dout_reg_in_212: FDCPE port map (dout_reg_in_2(12),dout(12).PIN,clk,reset,'0','1');

    mdat_I(13) <= NOT (((NOT db(13).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(13))));

    FDCPE_dout_reg_in13: FDCPE port map (dout_reg_in(13),dout_reg_in_2(13),clk,reset,'0','1');

    FDCPE_dout_reg_in_213: FDCPE port map (dout_reg_in_2(13),dout(13).PIN,clk,reset,'0','1');

    mdat_I(14) <= NOT (((NOT db(14).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(14))));

    FDCPE_dout_reg_in14: FDCPE port map (dout_reg_in(14),dout_reg_in_2(14),clk,reset,'0','1');

    FDCPE_dout_reg_in_214: FDCPE port map (dout_reg_in_2(14),dout(14).PIN,clk,reset,'0','1');

    mdat_I(15) <= NOT (((NOT db(15).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(15))));

    FDCPE_dout_reg_in15: FDCPE port map (dout_reg_in(15),dout_reg_in_2(15),clk,reset,'0','1');

    FDCPE_dout_reg_in_215: FDCPE port map (dout_reg_in_2(15),dout(15).PIN,clk,reset,'0','1');

    mdat_I(1) <= NOT (((NOT db(1).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(1))));

    FDCPE_dout_reg_in1: FDCPE port map (dout_reg_in(1),dout_reg_in_2(1),clk,reset,'0','1');

    FDCPE_dout_reg_in_21: FDCPE port map (dout_reg_in_2(1),dout(1).PIN,clk,reset,'0','1');

    mdat_I(2) <= NOT (((NOT db(2).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(2))));

    FDCPE_dout_reg_in2: FDCPE port map (dout_reg_in(2),dout_reg_in_2(2),clk,reset,'0','1');

    FDCPE_dout_reg_in_22: FDCPE port map (dout_reg_in_2(2),dout(2).PIN,clk,reset,'0','1');

    mdat_I(3) <= NOT (((NOT db(3).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(3))));

    FDCPE_dout_reg_in3: FDCPE port map (dout_reg_in(3),dout_reg_in_2(3),clk,reset,'0','1');

    FDCPE_dout_reg_in_23: FDCPE port map (dout_reg_in_2(3),dout(3).PIN,clk,reset,'0','1');

    mdat_I(4) <= NOT (((NOT db(4).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(4))));

    FDCPE_dout_reg_in4: FDCPE port map (dout_reg_in(4),dout_reg_in_2(4),clk,reset,'0','1');

    FDCPE_dout_reg_in_24: FDCPE port map (dout_reg_in_2(4),dout(4).PIN,clk,reset,'0','1');

    mdat_I(5) <= NOT (((NOT db(5).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(5))));

    FDCPE_dout_reg_in5: FDCPE port map (dout_reg_in(5),dout_reg_in_2(5),clk,reset,'0','1');

    FDCPE_dout_reg_in_25: FDCPE port map (dout_reg_in_2(5),dout(5).PIN,clk,reset,'0','1');

    mdat_I(6) <= NOT (((NOT db(6).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(6))));

    FDCPE_dout_reg_in6: FDCPE port map (dout_reg_in(6),dout_reg_in_2(6),clk,reset,'0','1');

    FDCPE_dout_reg_in_26: FDCPE port map (dout_reg_in_2(6),dout(6).PIN,clk,reset,'0','1');

    mdat_I(7) <= NOT (((NOT db(7).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(7))));

    FDCPE_dout_reg_in7: FDCPE port map (dout_reg_in(7),dout_reg_in_2(7),clk,reset,'0','1');

    FDCPE_dout_reg_in_27: FDCPE port map (dout_reg_in_2(7),dout(7).PIN,clk,reset,'0','1');

    mdat_I(8) <= NOT (((NOT db(8).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(8))));

    FDCPE_dout_reg_in8: FDCPE port map (dout_reg_in(8),dout_reg_in_2(8),clk,reset,'0','1');

    FDCPE_dout_reg_in_28: FDCPE port map (dout_reg_in_2(8),dout(8).PIN,clk,reset,'0','1');

    mdat_I(9) <= NOT (((NOT db(9).PIN AND N_PZ_30353)
    	OR (NOT N_PZ_30353 AND NOT dout_reg_in(9))));

    FDCPE_dout_reg_in9: FDCPE port map (dout_reg_in(9),dout_reg_in_2(9),clk,reset,'0','1');

    FDCPE_dout_reg_in_29: FDCPE port map (dout_reg_in_2(9),dout(9).PIN,clk,reset,'0','1');

    FDCPE_mem_done_p: FDCPE port map (mem_done_p,mem_done_p_D,clk,reset,'0','1');
    mem_done_p_D <= ((estado_FFD2 AND estado_FFD3 AND NOT estado_FFD1)
    	OR (NOT ena_ceros_mem AND NOT ena_gol_test AND mem_done_p));

    mspare_0 <= '0';

    mspare_1 <= '0';

    mspare_2 <= '0';

    mspare_3 <= '0';

    oe <= NOT (((cspare(11))
    	OR (write AND N_PZ_30489)));

    tp6 <= (estado_FFD2 AND estado_FFD3 AND estado_FFD1);

    tp8 <= clk_slow;

    FDCPE_trigger_led: FDCPE port map (trigger_led,NOT ULED/q1,clk_slow,'0',reset,'1');

    FTCPE_ULED/q1: FTCPE port map (ULED/q1,ULED/q1_T,clk,ULED/q3,'0','1');
    ULED/q1_T <= (enw1.COMB AND NOT ULED/q1);

    FDCPE_ULED/q3: FDCPE port map (ULED/q3,NOT trigger_led,clk_slow,reset,'0','1');

    vspare_1 <= '0';

    we <= NOT (((N_PZ_30322 AND U1/q2)
    	OR (N_PZ_30322 AND U2/b2)
    	OR (estado_FFD2 AND NOT estado_FFD3 AND NOT we_fifo)));

    FDDCPE_we_fifo: FDDCPE port map (we_fifo,we_fifo_D,clk,'0',reset,'1');
    we_fifo_D <= NOT ((txena_reg_in AND NOT clk));

    N_PZ_30373 <= (NOT add(5) AND NOT add(4) AND NOT add(3))
    	XOR (NOT add(5) AND NOT add(4) AND NOT add(3) AND write AND N_PZ_30322 AND
    	N_PZ_30489);

    db(9) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(9).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(9) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(9) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(9) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(9) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND N_PZ_30373 AND
    	U4/ena_lfsr(2)));FDCPE_U4/ena_lfsr2: FDCPE port map (U4/ena_lfsr(2),db(9).PIN,clk,reset,'0',N_PZ_30413);

    db(10) <= ((write AND N_PZ_30322 AND N_PZ_30489 AND mdat(10).PIN)
    	OR (add(2) AND add(1) AND NOT add(0) AND num_cycles(10) AND
    	N_PZ_30373)
    	OR (add(2) AND NOT add(1) AND add(0) AND mevent_count(10) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND add(1) AND add(0) AND mword_count(10) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND add(0) AND mem_pointer(10) AND
    	N_PZ_30373)
    	OR (NOT add(2) AND NOT add(1) AND NOT add(0) AND N_PZ_30373 AND
    	U4/ena_lfsr(3)));FDCPE_U4/ena_lfsr3: FDCPE port map (U4/ena_lfsr(3),db(10).PIN,clk,reset,'0',N_PZ_30413);

    FDCPE_is_trigger_1: FDCPE port map (is_trigger_1,is_trigger,clk,reset,'0','1');

    FDCPE_txena_reg_out: FDCPE port map (txena_reg_out,txena_out,clk,reset,'0','1');

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FDDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     FTDCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ****************************  Device Pin Out ****************************

    Device : XC2C512-7-PQ208

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 VCC                             105 VCCIO-1.8
      2 add<15>                         106 mspare_0
      3 add<14>                         107 trigger_led
      4 add<13>                         108 led<1>
      5 add<12>                         109 led<0>
      6 add<11>                         110 KPR
      7 add<10>                         111 mem_done_p
      8 add<17>                         112 tp6
      9 add<6>                          113 madd<0>
     10 add<7>                          114 vspare_1
     11 VCCAUX                          115 dout<0>
     12 add<8>                          116 dout<10>
     13 GND                             117 dout<11>
     14 db<0>                           118 dtack_mem
     15 db<1>                           119 dout<13>
     16 add<2>                          120 dout<14>
     17 add<3>                          121 dout<15>
     18 add<4>                          122 dout<4>
     19 db<12>                          123 dout<5>
     20 db<5>                           124 VCC
     21 db<13>                          125 dout<6>
     22 db<6>                           126 cspare<1>
     23 db<7>                           127 cspare<0>
     24 GND                             128 cspare<9>
     25 db<8>                           129 GND
     26 VCCIO-1.8                       130 GND
     27 KPR                             131 cspare<8>
     28 KPR                             132 VCCIO-1.8
     29 cspare<2>                       133 VCCIO-1.8
     30 cspare<3>                       134 mspare_1
     31 KPR                             135 vspare_0
     32 KPR                             136 KPR
     33 VCCIO-1.8                       137 madd<5>
     34 cspare<6>                       138 madd<7>
     35 cspare<7>                       139 madd<9>
     36 mspare_3                        140 madd<8>
     37 KPR                             141 GND
     38 KPR                             142 KPR
     39 cspare<10>                      143 madd<2>
     40 cspare<11>                      144 madd<1>
     41 KPR                             145 oe
     42 GND                             146 g245_mem
     43 KPR                             147 mdat<9>
     44 dsdly<0>                        148 mdat<8>
     45 KPR                             149 mdat<7>
     46 clk                             150 mdat<6>
     47 iack                            151 mdat<5>
     48 etr                             152 mdat<4>
     49 enw_x                           153 mdat<3>
     50 ds1                             154 mdat<2>
     51 tp5                             155 we
     52 GND                             156 GND
     53 VCC                             157 VCCIO-1.8
     54 txena                           158 cspare<5>
     55 dsdly<1>                        159 cspare<4>
     56 is_trigger                      160 KPR
     57 lword                           161 tp8
     58 KPR                             162 mdat<0>
     59 VCCIO-1.8                       163 mdat<10>
     60 db<9>                           164 mdat<11>
     61 db<4>                           165 mdat<12>
     62 KPR                             166 mdat<13>
     63 KPR                             167 mdat<14>
     64 KPR                             168 mdat<15>
     65 KPR                             169 mdat<1>
     66 KPR                             170 madd<12>
     67 KPR                             171 madd<11>
     68 GND                             172 VCCIO-1.8
     69 KPR                             173 madd<10>
     70 KPR                             174 add<0>
     71 KPR                             175 add<1>
     72 KPR                             176 TDO
     73 KPR                             177 GND
     74 madd<17>                        178 KPR
     75 madd<16>                        179 madd<3>
     76 madd<15>                        180 madd<4>
     77 madd<14>                        181 VCCIO-1.8
     78 madd<13>                        182 madd<6>
     79 VCCIO-1.8                       183 ds0
     80 KPR                             184 cs
     81 GND                             185 clk_slow
     82 KPR                             186 brdsel24
     83 KPR                             187 add<5>
     84 KPR                             188 db<2>
     85 KPR                             189 db<15>
     86 KPR                             190 GND
     87 KPR                             191 db<14>
     88 KPR                             192 as
     89 dout<9>                         193 write
     90 dout<8>                         194 am<1>
     91 dout<7>                         195 KPR
     92 VCCIO-1.8                       196 db<11>
     93 GND                             197 db<3>
     94 TDI                             198 db<10>
     95 dout<3>                         199 am<5>
     96 TMS                             200 am<4>
     97 dout<2>                         201 am<3>
     98 TCK                             202 am<2>
     99 dout<1>                         203 am<0>
    100 dout<12>                        204 VCCIO-1.8
    101 mspare_2                        205 add<9>
    102 tp7                             206 reset
    103 ds_out                          207 GND
    104 GND                             208 add<16>

    Legend :  NC  = Not Connected, unbonded pin
            PGND  = Unused I/O configured as additional Ground pin
             KPR  = Unused I/O with weak keeper (leave unconnected)
             WPU  = Unused I/O with weak pull up (leave unconnected)
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
          VCCAUX  = Power supply for JTAG pins
       VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
       VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
       VCCIO-1.8  = I/O supply voltage for LVCMOS18
       VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
            VREF  = Reference voltage for indicated input standard
           *VREF  = Reference voltage pin selected by software
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc2c512-7-PQ208
    Optimization Method                         : DENSITY
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : ON
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Set Unused I/O Pin Termination              : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Enable Input Registers                      : ON
    Function Block Fan-in Limit                 : 38
    Use DATA_GATE Attribute                     : ON
    Set Tristate Outputs to Termination Mode    : KEEPER
    Default Voltage Standard for All Outputs    : LVCMOS18
    Input Limit                                 : 23
    Pterm Limit                                 : 32