library ieee;
use ieee.std_logic_1164.all;

---
-- ver esquema
-- VME INTERFACE A16:D16 SYNCH (ROS)
---
entity vmeifc is
     port (
     clk: in std_logic;
     iack, ack_int, dtack_int, ds0, ds1: in std_logic;
     write, brd_sel, lword: in std_logic;
     add_mod: in std_logic_vector (5 downto 0);
     etr, enw, dtack, g245: out std_logic 
     );
end vmeifc;

architecture arch of vmeifc is
component ffrp port (
     d, clk, ce, cr, pr: in std_logic;
     q: out std_logic);
end component;

signal ds_rst, q1, q2, q4, q5, q8,q9,q44,q444: std_logic;
signal q6, q7: std_logic;
signal md, acc, d_lec, d_esc, ena_d: std_logic;
signal one, zero, not_ds0, dssync: std_logic;
begin
one <= '1';
zero <= '0';
-- interface (A16, short non-privileed access, MOD=$29)
md <= '1' when add_mod="101001" else '0'; --10 1001

acc <= not brd_sel and lword and iack and md;
d_lec <= acc and     write and dssync; --ds_lec;
d_esc <= acc and not write and dssync; --ds_esc;
--Nicola vme ena_d <= q2 or q5;
ena_d <= q2 or q7;

--Nicola vme g245 <= not (ack_int or q1 or q5);
--Nicola vme etr <= not q5;
g245 <= not (ack_int or q1 or q5);
etr <= not q5;

enw <= q2 and not q4;
dtack <= q444 or dtack_int;
--dtack <= q4 or dtack_int;

--not_ds0 <= not ds0; LINCO ago 07
not_ds0 <= not (ds0 or ds1);
--ds_rst <= ds0 or ds1; LINCO ago 07
ds_rst <= ds0 and ds1;

--WRITE
fq1:  ffrp port map (clk => clk, d => one,     ce => d_esc, cr => ds_rst, pr => zero, q => q1);
--fq2:  ffrp port map (clk => clk, d => q1,      ce => one,   cr => ds_rst, pr => zero, q => q2);
-- asi esta en el esquematico 
fq2:  ffrp port map (clk => clk, d => q1,      ce => d_esc,   cr => ds_rst, pr => zero, q => q2);

--necesito registrar el enw porque es una patata en la placa, así que se me retrasa 1 ciclo, retraso el dtack
fq4:  ffrp port map (clk => clk, d => ena_d,   ce => one,   cr => zero,   pr => zero, q => q4);
fq44:  ffrp port map (clk => clk, d => q4,   ce => one,   cr => zero,   pr => zero, q => q44);
fq444:  ffrp port map (clk => clk, d => q44,   ce => one,   cr => zero,   pr => zero, q => q444);


--READ
fq5:  ffrp port map (clk => clk, d => one,     ce => d_lec, cr => ds_rst, pr => zero, q => q5);
--problem Nicola vme, retraso el dtack
fq6:  ffrp port map (clk => clk, d => q5,     ce => one, cr => ds_rst, pr => zero, q => q6);
--fq7:  ffrp port map (clk => clk, d => q6,     ce => one, cr => ds_rst, pr => zero, q => q7);
fq7:  ffrp port map (clk => clk, d => q6,     ce => one, cr => ds_rst, pr => zero, q => q9);
fq9:  ffrp port map (clk => clk, d => q9,     ce => one, cr => ds_rst, pr => zero, q => q7);


--DSSYNC
fq8:  ffrp port map (clk => clk, d => not_ds0, ce => one,   cr => zero,   pr => zero, q => q8);
fds:  ffrp port map (clk => clk, d => q8,      ce => one,   cr => ds0,    pr => zero, q => dssync);
  
end arch;
	
