    cpldfit:  version G.35                              Xilinx Inc.
                                      Fitter Report
    Design Name: rosvme                              Date: 12- 4-2009,  5:41PM
    Device Used: XC2C384-7-PQ208
    Fitting Status: Successful

    ****************************  Resource Summary  ****************************

    Macrocells     Product Terms    Registers      Pins           Function Block
    Used           Used             Used           Used           Inputs Used
    223/384 ( 58%) 540 /1344 ( 40%) 142/384 ( 37%) 163/173 ( 94%) 648/960 ( 67%)

    PIN RESOURCES:

    Signal Type    Required     Mapped  |  Pin Type            Used   Remaining
    ------------------------------------|---------------------------------------
    Input         :   61          61    |  I/O              :   154        9
    Output        :   83          83    |  GCK/IO           :     3        0
    Bidirectional :   16          16    |  GTS/IO           :     4        0
    GCK           :    2           2    |  GSR/IO           :     1        0
    GTS           :    0           0    |  CDR/IO           :     1        0
    GSR           :    1           1    |  DGE/IO           :     0        1
                     ----        ----
            Total    163         163

    MACROCELL RESOURCES:

    Total Macrocells Available                   384
    Registered Macrocells                        142
    Non-registered Macrocell driving I/O          67

    GLOBAL RESOURCES:

    Signal 'clk_slow' mapped onto global clock net GCK0.
    Signal 'clk' mapped onto global clock net GCK1.
    Signal '_n0009_MC.GLB' mapped onto global output enable net GTS0.
    Signal 'sysreset' mapped onto global set/reset net GSR.

    End of Resource Summary
    ****************************  Errors and Warnings  *************************

    WARNING:Cpld:987 - An internal tristate buffer 'fl_tdo_aux' is detected.  The
       logic is being translated to a mux implementation.
    *************** Summary of Required Resources ******************

    ** LOGIC **
    Signal              Total Signals Loc     Slew Pin  Pin       Pin     Reg     I/O      I/O       Reg Init
    Name                Pt    Used            Rate #    Type      Use     Use     STD      Style     State
    N_PZ_1002           2       6     FB12_15           (b)       (b)
    N_PZ_1032           2       5     FB1_16       199  I/O       I
    N_PZ_1042           7       8     FB7_14       45   I/O       I
    N_PZ_930            1       2     FB7_13            (b)       (b)
    N_PZ_941            1       10    FB5_10            (b)       (b)
    N_PZ_944            1       3     FB4_9             (b)       (b)
    N_PZ_945            1       3     FB4_8             (b)       (b)
    N_PZ_953            1       12    FB5_11            (b)       (b)
    N_PZ_957            2       6     FB12_14           (b)       (b)
    N_PZ_966            1       2     FB7_12       46   GCK/I/O   GCK/I
    N_PZ_971            7       8     FB3_13       192  I/O       I
    U1/dssync           2       2     FB11_6            (b)       (b)     DFF                        RESET
    U1/q1               2       14    FB10_11           (b)       (b)     TFF                        RESET
    U1/q2               3       14    FB10_10           (b)       (b)     DEFF                       RESET
    U1/q4               1       2     FB7_8             (b)       (b)     DFF                        RESET
    U1/q44              1       1     FB5_9             (b)       (b)     DFF                        RESET
    U1/q444             1       1     FB7_10            (b)       (b)     DFF                        RESET
    U1/q6               2       3     FB10_9            (b)       (b)     DFF                        RESET
    U1/q7               2       3     FB10_7            (b)       (b)     DFF                        RESET
    U1/q8               1       2     FB10_8            (b)       (b)     DFF                        RESET
    U1/q9               2       3     FB10_6            (b)       (b)     DFF                        RESET
    U3/r3               0       0     FB1_1        2    I/O       I       DFF                        RESET
    U3/r4               2       2     FB3_16            (b)       (b)     DEFF                       RESET
    U3/r5               2       2     FB11_11           (b)       (b)     DFF                        RESET
    U3/r6               2       2     FB11_8            (b)       (b)     DFF                        RESET
    U3/r7               2       2     FB10_16      71   I/O       I       DFF                        RESET
    U3/r8               3       4     FB10_14      69   I/O       I       DFF/S                      SET
    U5/_n0041           2       16    FB7_15       44   GCK/I/O   GCK
    U5/_n007019         6       16    FB1_5             (b)       (b)
    U5/bits_to_send<0>  5       7     FB3_12       193  I/O       I       TFF                        RESET
    U5/bits_to_send<1>  5       8     FB14_11           (b)       (b)     TFF                        RESET
    U5/bits_to_send<2>  5       9     FB15_14           (b)       (b)     TFF                        RESET
    U5/bits_to_send<3>  5       10    FB15_11           (b)       (b)     TFF                        RESET
    U5/cclk_counter<0>  1       1     FB3_9             (b)       (b)     TFF                        RESET
    U5/cclk_counter<1>  2       2     FB3_8             (b)       (b)     TFF                        RESET
    U5/cclk_counter<2>  2       3     FB3_7             (b)       (b)     TFF                        RESET
    U5/cclk_counter<3>  2       4     FB3_6             (b)       (b)     TFF                        RESET
    U5/cclk_counter<4>  2       5     FB3_15       191  I/O       I       TFF                        RESET
    U5/cuenta_prgm_0_0  3       7     FB15_10           (b)       (b)     TFF                        RESET
    U5/cuenta_prgm_0_1  4       7     FB15_8            (b)       (b)     TFF                        RESET
    U5/cuenta_prgm_0_2  5       7     FB15_7            (b)       (b)     TFF                        RESET
    U5/cuenta_prgm_0_3  5       7     FB15_6            (b)       (b)     DFF                        RESET
    U5/cuenta_prgm_0_4  3       7     FB15_9            (b)       (b)     DFF                        RESET
    U5/ena_evres        3       14    FB16_12      145  I/O       (b)     DEFF                       RESET
    U5/flash_enable<0>  3       7     FB1_9             (b)       (b)     DFF                        RESET
    U5/flash_enable<1>  3       7     FB1_8             (b)       (b)     DFF                        RESET
    U5/flash_enable<2>  3       7     FB1_7             (b)       (b)     DFF                        RESET
    U5/flash_enable<3>  3       7     FB1_6             (b)       (b)     DFF                        RESET
    U5/flash_enable<4>  5       11    FB1_11            (b)       (b)     DFF                        RESET
    U5/flash_tck        3       5     FB12_13           (b)       (b)     DFF                        RESET
    U5/flash_tdi_reg    3       5     FB4_11            (b)       (b)     DEFF                       RESET
    U5/flash_tms        3       3     FB4_7             (b)       (b)     DEFF                       RESET
    U5/gol_notready_reg 3       5     FB4_10            (b)       (b)     DFF                        RESET
    U5/int_ena_mdone    4       16    FB2_6             (b)       (b)     TFF                        RESET
    U5/int_ena_rosw     4       16    FB2_15       9    GTS/I/O   I       TFF                        RESET
    U5/int_ena_sff      4       16    FB2_13       8    I/O       I       TFF                        RESET
    U5/int_ena_spaf     4       16    FB2_4        6    I/O       I       TFF                        RESET
    U5/int_vect<0>      3       15    FB2_14            (b)       (b)     DEFF                       RESET
    U5/int_vect<2>      3       15    FB2_12            (b)       (b)     DEFF                       RESET
    U5/int_vect<3>      3       15    FB2_11            (b)       (b)     DEFF                       RESET
    U5/int_vect<4>      3       15    FB2_10            (b)       (b)     DEFF                       RESET
    U5/int_vect<6>      3       15    FB2_9             (b)       (b)     DEFF                       RESET
    U5/int_vect<7>      3       15    FB15_16      171  I/O       (b)     DEFF                       RESET
    U5/jtag_end         5       6     FB12_10           (b)       (b)     DFF                        RESET
    U5/jtag_num_bits<0> 3       3     FB11_10           (b)       (b)     DEFF                       RESET
    U5/jtag_num_bits<1> 3       3     FB11_7            (b)       (b)     DEFF                       RESET
    U5/jtag_num_bits<2> 3       3     FB11_9            (b)       (b)     DEFF                       RESET
    U5/jtag_num_bits<3> 3       3     FB11_14           (b)       (b)     DEFF                       RESET
    U5/jtag_shift       4       5     FB12_11           (b)       (b)     DFF                        RESET
    U5/jtag_start       3       4     FB13_15           (b)       (b)     DFF                        RESET
    U5/local_reset      2       14    FB7_16       43   I/O       I
    U5/mem_d0           1       1     FB1_2        208  I/O       I       DFF                        RESET
    U5/mem_done_reg     3       5     FB3_11            (b)       (b)     DFF                        RESET
    U5/not_sel_tim_reg  3       5     FB14_15           (b)       (b)     DFF                        RESET
    U5/qpll_error_reg   3       5     FB13_4       161  I/O       I       DFF                        RESET
    U5/qpll_hasunlock_reg                    3       5     FB8_14            (b)       (b)     DFF                        RESET
    U5/reset_1          2       14    FB7_6             (b)       (b)     DFF                        RESET
    U5/reset_2          1       1     FB7_9             (b)       (b)     DFF                        RESET
    U5/ros_w0           1       1     FB1_4        205  I/O       I       DFF                        RESET
    U5/ros_waiting_reg  3       5     FB3_10            (b)       (b)     DFF                        RESET
    U5/s_reset_1        3       16    FB6_15            (b)       (b)     DFF                        RESET
    U5/s_reset_2        1       1     FB7_7             (b)       (b)     DFF                        RESET
    U5/state_FFD1       5       6     FB1_3        206  GSR/I/O   GSR/I   DFF                        RESET
    U5/state_FFD2       4       5     FB1_15       200  I/O       I       DFF                        RESET
    U5/state_FFD3       3       9     FB12_8            (b)       (b)     DFF                        RESET
    U5/tdi_bits<0>      4       6     FB13_5            (b)       (b)     DFF                        RESET
    U5/tdi_bits<1>      4       6     FB13_6            (b)       (b)     DFF                        RESET
    U5/tdi_bits<2>      4       6     FB13_7            (b)       (b)     DFF                        RESET
    U5/tdi_bits<3>      4       6     FB13_8            (b)       (b)     DFF                        RESET
    U5/tdi_bits<4>      4       6     FB13_9            (b)       (b)     DFF                        RESET
    U5/tdi_bits<5>      4       6     FB13_10           (b)       (b)     DFF                        RESET
    U5/tdi_bits<6>      4       6     FB13_11           (b)       (b)     DFF                        RESET
    U5/tdi_bits<7>      3       5     FB13_14           (b)       (b)     DFF                        RESET
    U5/tdo_bits<0>      3       5     FB9_8             (b)       (b)     DFF                        RESET
    U5/tdo_bits<1>      3       5     FB9_9             (b)       (b)     DFF                        RESET
    U5/tdo_bits<2>      3       5     FB9_10            (b)       (b)     DFF                        RESET
    U5/tdo_bits<3>      3       5     FB9_11            (b)       (b)     DFF                        RESET
    U5/tdo_bits<4>      3       5     FB9_16            (b)       (b)     DFF                        RESET
    U5/tdo_bits<5>      3       5     FB13_2            (b)       (b)     DFF                        RESET
    U5/tdo_bits<6>      3       5     FB13_1            (b)       (b)     DFF                        RESET
    U5/tdo_bits<7>      3       5     FB13_12      162  I/O       I       DFF                        RESET
    U5/tdo_reg          5       7     FB12_9            (b)       (b)     DFF                        RESET
    ULED1/q1            2       3     FB11_2            (b)       (b)     TFF                        RESET
    ULED1/q3            2       2     FB11_15           (b)       (b)     DFF                        RESET
    ULED2/q1            4       6     FB14_12           (b)       (b)     TFF                        RESET
    ULED2/q3            2       2     FB11_13           (b)       (b)     DFF                        RESET
    ULED3/q1            2       4     FB7_11            (b)       (b)     TFF                        RESET
    ULED3/q3            2       2     FB11_16           (b)       (b)     DFF                        RESET
    ack_int             3       4     FB10_3            (b)       (b)     DFF                        RESET
    add_f_p<10>         0       0     FB3_2   FAST 197  I/O       O               LVCMOS33 OD
    add_f_p<11>         0       0     FB3_3   FAST 196  I/O       O               LVCMOS33 OD
    add_f_p<12>         0       0     FB3_1   FAST 198  I/O       O               LVCMOS33 OD
    add_f_p<13>         0       0     FB3_4   FAST 195  I/O       O               LVCMOS33 OD
    add_f_p<14>         0       0     FB3_5   FAST 194  I/O       O               LVCMOS33 OD
    add_f_p<15>         0       0     FB9_3   FAST 39   I/O       O               LVCMOS33 OD
    add_f_p<9>          0       0     FB9_4   FAST 38   I/O       O               LVCMOS33 OD
    add_hold            1       2     FB16_3  FAST 147  I/O       O               LVCMOS33
    cclk<0>             1       2     FB7_1   FAST 51   CDR/I/O   O       DFF     LVCMOS33           RESET
    cclk<1>             1       2     FB7_2   FAST 50   I/O       O       DFF     LVCMOS33           RESET
    cclk<2>             1       2     FB7_3   FAST 49   I/O       O       DFF     LVCMOS33           RESET
    cclk<3>             1       2     FB7_4   FAST 48   I/O       O       DFF     LVCMOS33           RESET
    cclk<4>             1       2     FB7_5   FAST 47   I/O       O       DFF     LVCMOS33           RESET
    cscr_p<0>           1       4     FB13_13 FAST 163  I/O       O               LVCMOS33
    cscr_p<1>           1       4     FB13_16 FAST 164  I/O       O               LVCMOS33
    cscr_p<2>           1       4     FB15_2  FAST 165  I/O       O               LVCMOS33
    cscr_p<3>           1       4     FB15_3  FAST 166  I/O       O               LVCMOS33
    cscr_p<4>           1       4     FB15_5  FAST 167  I/O       O               LVCMOS33
    cscr_p<5>           1       4     FB15_12 FAST 168  I/O       O               LVCMOS33
    cscr_p<6>           1       4     FB15_13 FAST 169  I/O       O               LVCMOS33
    cspare_8            0       0     FB1_12  FAST 203  I/O       O               LVCMOS33 OD
    cspare_9            0       0     FB2_3   FAST 5    GTS/I/O   O               LVCMOS33 OD
    db<0>               12      19    FB4_1   FAST 12   I/O       I/O     DEFF/S  LVCMOS33           SET
    db<10>              8       16    FB5_12  FAST 187  I/O       I/O     DEFF    LVCMOS33           RESET
    db<11>              6       14    FB24_2  FAST 84   I/O       I/O     DEFF    LVCMOS33           RESET
    db<12>              6       14    FB8_4   FAST 57   I/O       I/O     DEFF/S  LVCMOS33           SET
    db<13>              5       19    FB9_2   FAST 40   I/O       I/O     DEFF    LVCMOS33           RESET
    db<14>              5       13    FB8_3   FAST 56   I/O       I/O     DEFF    LVCMOS33           RESET
    db<15>              1       8     FB4_4   FAST 15   I/O       I/O             LVCMOS33
    db<1>               10      17    FB5_4   FAST 189  I/O       I/O             LVCMOS33
    db<2>               12      19    FB6_1   FAST 22   I/O       I/O     DEFF/S  LVCMOS33           SET
    db<3>               9       16    FB8_1   FAST 54   I/O       I/O             LVCMOS33
    db<4>               9       16    FB6_16  FAST 25   I/O       I/O             LVCMOS33
    db<5>               10      23    FB9_1   FAST 41   I/O       I/O     DEFF/S  LVCMOS33           SET
    db<6>               10      17    FB8_2   FAST 55   GCK/I/O   I/O     DEFF    LVCMOS33           RESET
    db<7>               9       16    FB4_5   FAST 16   I/O       I/O     DEFF    LVCMOS33           RESET
    db<8>               6       13    FB4_3   FAST 14   I/O       I/O             LVCMOS33
    db<9>               8       22    FB5_5   FAST 188  I/O       I/O     DEFF    LVCMOS33           RESET
    dtack_int           3       4     FB10_15      70   I/O       I       DFF                        RESET
    dtack_led           2       2     FB14_4  FAST 154  I/O       O       DFF/S   LVCMOS33           SET
    dtack_p             2       4     FB16_16 FAST 143  I/O       O               LVCMOS33
    ena_evres_prgm      3       3     FB8_16            (b)       (b)     DEFF                       RESET
    enw_vf              1       1     FB17_13 FAST 179  I/O       O               LVCMOS33
    enw_x               1       2     FB18_13 FAST 136  I/O       O               LVCMOS33
    etr_vf              1       1     FB10_1  FAST 62   I/O       O               LVCMOS33
    etr_x               2       14    FB10_2  FAST 63   I/O       O       TFF/S   LVCMOS33           SET
    fl_tck_r            1       1     FB20_1       102  I/O       I       DFF                        RESET
    fl_tdi_r            1       1     FB20_2       101  I/O       I       DFF                        RESET
    fl_tdo              13      13    FB12_1  FAST 72   I/O       O       DFF     LVCMOS33           RESET
    fl_tms_r            1       1     FB20_3       100  I/O       I       DFF                        RESET
    fl_vme<1>           3       5     FB8_5        58   DGE/I/O   (b)     DEFF/S                     SET
    flash_ena_5_rosmem  5       11    FB1_10            (b)       (b)     DFF                        RESET
    flash_tck_p<0>      4       11    FB12_2  FAST 73   I/O       O               LVCMOS33
    flash_tck_p<1>      6       10    FB12_3  FAST 74   I/O       O               LVCMOS33
    flash_tck_p<2>      4       11    FB12_4  FAST 75   I/O       O               LVCMOS33
    flash_tck_p<3>      4       11    FB12_5  FAST 76   I/O       O               LVCMOS33
    flash_tck_p<4>      4       11    FB12_12 FAST 77   I/O       O               LVCMOS33
    flash_tck_p<5>      4       11    FB12_16 FAST 78   I/O       O               LVCMOS33
    flash_tdi_p         3       10    FB16_1  FAST 149  I/O       O               LVCMOS33
    flash_tms_p         3       10    FB16_2  FAST 148  I/O       O               LVCMOS33
    fpga_init<0>        3       3     FB1_13  FAST 202  I/O       O       DEFF    LVCMOS33           RESET
    fpga_init<1>        3       3     FB4_12  FAST 17   I/O       O       DEFF    LVCMOS33           RESET
    fpga_init<2>        3       3     FB4_14  FAST 19   I/O       O       DEFF    LVCMOS33           RESET
    fpga_init<3>        3       3     FB5_14  FAST 185  I/O       O       DEFF    LVCMOS33           RESET
    fpga_init<4>        3       3     FB6_3   FAST 23   I/O       O       DEFF    LVCMOS33           RESET
    g245_p              1       5     FB10_5  FAST 65   I/O       O               LVCMOS33
    gol_off             3       3     FB4_15  FAST 20   I/O       O       DEFF/S  LVCMOS33           SET
    gol_reset           2       3     FB17_1  FAST 173  I/O       O               LVCMOS33
    i2c_ce_1wire        3       3     FB4_13  FAST 18   I/O       O       DEFF    LVCMOS33           RESET
    i2c_ce_gol          3       5     FB1_14  FAST 201  I/O       O       DFF     LVCMOS33           RESET
    i2c_ce_p            1       8     FB2_2   FAST 4    I/O       O               LVCMOS33
    i2c_rd              1       2     FB23_4  FAST 127  I/O       O               LVCMOS33
    i2c_reset           1       2     FB17_2  FAST 174  I/O       O               LVCMOS33
    i2c_wr              1       3     FB18_5  FAST 138  I/O       O               LVCMOS33
    iackout             1       2     FB16_4  FAST 146  I/O       O               LVCMOS33
    int_lev<1>          3       15    FB2_8             (b)       (b)     DEFF                       RESET
    int_lev<2>          3       15    FB2_7             (b)       (b)     DEFF                       RESET
    int_rst             13      18    FB3_14            (b)       (b)     DFF                        RESET
    intrpt_led          2       2     FB14_5  FAST 153  I/O       O       DFF/S   LVCMOS33           SET
    irq<1>              1       4     FB11_1  FAST 31   I/O       O               LVCMOS33
    irq<2>              1       4     FB11_3  FAST 30   I/O       O               LVCMOS33
    irq<3>              1       4     FB11_4  FAST 29   I/O       O               LVCMOS33
    irq<4>              1       4     FB11_5  FAST 28   I/O       O               LVCMOS33
    irq<5>              1       4     FB11_12 FAST 27   I/O       O               LVCMOS33
    irq<6>              1       4     FB18_2  FAST 142  I/O       O               LVCMOS33
    irq<7>              1       4     FB18_3  FAST 140  I/O       O               LVCMOS33
    ldpreg              1       13    FB10_4  FAST 64   I/O       O               LVCMOS33
    mrs                 2       14    FB14_1  FAST 159  I/O       O               LVCMOS33
    mspare_0            0       0     FB18_4  FAST 139  I/O       O               LVCMOS33 OD
    mspare_1            0       0     FB8_13  FAST 60   I/O       O               LVCMOS33 OD
    mspare_2            0       0     FB18_12 FAST 137  I/O       O               LVCMOS33 OD
    mspare_3            0       0     FB18_15 FAST 134  I/O       O               LVCMOS33 OD
    on_244              0       0     FB2_16  FAST 10   I/O       O               LVCMOS33
    prgm_fpga<0>        4       9     FB15_4            (b)       (b)     DFF/S                      SET
    prgm_fpga<1>        4       9     FB15_1            (b)       (b)     DFF/S                      SET
    prgm_fpga<2>        4       9     FB17_15           (b)       (b)     DFF/S                      SET
    prgm_fpga<3>        4       9     FB17_11           (b)       (b)     DFF/S                      SET
    prgm_fpga<4>        4       9     FB17_10           (b)       (b)     DFF/S                      SET
    prgm_fpga_p<0>      1       2     FB9_5   FAST 37   I/O       O               LVCMOS33 OD
    prgm_fpga_p<1>      1       2     FB9_12  FAST 36   I/O       O               LVCMOS33 OD
    prgm_fpga_p<2>      1       2     FB9_13  FAST 35   I/O       O               LVCMOS33 OD
    prgm_fpga_p<3>      1       2     FB9_14  FAST 34   I/O       O               LVCMOS33 OD
    prgm_fpga_p<4>      1       2     FB9_15  FAST 32   I/O       O               LVCMOS33 OD
    prs                 4       17    FB14_2  FAST 158  I/O       O               LVCMOS33
    qpll_reset          2       3     FB2_1   FAST 3    GTS/I/O   O               LVCMOS33
    reset_p             1       2     FB17_3  FAST 175  I/O       O               LVCMOS33
    sel_tim_clk<0>      3       14    FB23_12 FAST 128  I/O       O       DEFF    LVCMOS33           RESET
    sel_tim_clk<1>      3       14    FB23_14 FAST 131  I/O       O       DEFF    LVCMOS33           RESET
    spare_led           2       2     FB14_13 FAST 152  I/O       O       DFF     LVCMOS33           RESET
    tp2                 2       14    FB19_1  FAST 103  I/O       O       TFF/S   LVCMOS33           SET
    tp3                 1       2     FB14_3  FAST 155  I/O       O               LVCMOS33
    tp4                 1       1     FB13_3  FAST 160  I/O       O               LVCMOS33
    vspare_0            1       2     FB15_15 FAST 170  I/O       O               LVCMOS33
    vspare_1            0       0     FB16_14 FAST 144  I/O       O               LVCMOS33 OD

    ** INPUTS **
    Signal                            Loc          Pin  Pin       Pin     Reg     I/O      I/O
    Name                                           #    Type      Use     Use     STD      Style
    add_mod<0>                        FB10_15      70   I/O       I               LVCMOS33
    add_mod<1>                        FB10_16      71   I/O       I               LVCMOS33
    add_mod<2>                        FB14_14      151  I/O       I               LVCMOS33
    add_mod<3>                        FB14_16      150  I/O       I               LVCMOS33
    add_mod<4>                        FB19_4       107  I/O       I               LVCMOS33
    add_mod<5>                        FB19_5       108  I/O       I               LVCMOS33
    add_p<0>                          FB10_12      66   I/O       I               LVCMOS33
    add_p<1>                          FB10_13      67   I/O       I               LVCMOS33
    add_p<2>                          FB10_14      69   I/O       I               LVCMOS33
    add_p<3>                          FB2_13       8    I/O       I               LVCMOS33
    add_p<4>                          FB2_5        7    GTS/I/O   I               LVCMOS33
    add_p<5>                          FB2_4        6    I/O       I               LVCMOS33
    add_p<6>                          FB13_12      162  I/O       I               LVCMOS33
    add_p<7>                          FB13_4       161  I/O       I               LVCMOS33
    add_p<8>                          FB2_15       9    GTS/I/O   I               LVCMOS33
    as                                FB19_12      109  I/O       I               LVCMOS33
    brd_sel_16                        FB19_13      110  I/O       I               LVCMOS33
    brd_sel_24                        FB19_14      111  I/O       I               LVCMOS33
    clk                               FB7_12       46   GCK/I/O   GCK/I           LVCMOS33
    clk_slow                          FB7_15       44   GCK/I/O   GCK             LVCMOS33
    ds0                               FB1_1        2    I/O       I               LVCMOS33
    ds1                               FB19_15      112  I/O       I               LVCMOS33
    dtack_mem                         FB19_16      113  I/O       I               LVCMOS33
    evcnt_res                         FB3_12       193  I/O       I               LVCMOS33
    fl_switch<0>                      FB5_15       184  I/O       I               LVCMOS33
    fl_switch<1>                      FB5_16       183  I/O       I               LVCMOS33
    fl_switch<2>                      FB8_15       61   I/O       I               LVCMOS33
    fl_tck                            FB20_1       102  I/O       I               LVCMOS33
    fl_tdi                            FB20_2       101  I/O       I               LVCMOS33
    fl_tms                            FB20_3       100  I/O       I               LVCMOS33
    flash_tdo_p<0>                    FB20_4       99   I/O       I               LVCMOS33
    flash_tdo_p<1>                    FB20_5       97   I/O       I               LVCMOS33
    flash_tdo_p<2>                    FB20_13      95   I/O       I               LVCMOS33
    flash_tdo_p<3>                    FB21_1       114  I/O       I               LVCMOS33
    flash_tdo_p<4>                    FB21_2       115  I/O       I               LVCMOS33
    flash_tdo_p<5>                    FB21_3       116  I/O       I               LVCMOS33
    fpga_done<0>                      FB7_14       45   I/O       I               LVCMOS33 PU
    fpga_done<1>                      FB7_16       43   I/O       I               LVCMOS33 PU
    fpga_done<2>                      FB3_13       192  I/O       I               LVCMOS33 PU
    fpga_done<3>                      FB3_15       191  I/O       I               LVCMOS33 PU
    fpga_done<4>                      FB21_4       117  I/O       I               LVCMOS33 PU
    g245_mem                          FB21_5       118  I/O       I               LVCMOS33
    gol_ready                         FB21_12      119  I/O       I               LVCMOS33
    i2c_int_p                         FB17_16      182  I/O       I               LVCMOS33
    iack                              FB21_13      120  I/O       I               LVCMOS33
    iackin                            FB21_14      121  I/O       I               LVCMOS33
    lword                             FB21_15      122  I/O       I               LVCMOS33
    mem_done                          FB1_2        208  I/O       I               LVCMOS33
    qpll_error                        FB21_16      123  I/O       I               LVCMOS33
    qpll_locked                       FB22_2       91   I/O       I               LVCMOS33
    ros_waiting                       FB1_4        205  I/O       I               LVCMOS33
    sel_tim_p                         FB17_14      180  I/O       I               LVCMOS33
    sff<0>                            FB1_15       200  I/O       I               LVCMOS33
    sff<1>                            FB1_16       199  I/O       I               LVCMOS33
    sff<2>                            FB4_16       21   I/O       I               LVCMOS33
    sff<3>                            FB22_3       90   I/O       I               LVCMOS33
    sff<4>                            FB22_4       89   I/O       I               LVCMOS33
    spaf<0>                           FB22_12      88   I/O       I               LVCMOS33
    spaf<1>                           FB22_13      87   I/O       I               LVCMOS33
    spaf<2>                           FB22_14      86   I/O       I               LVCMOS33
    spaf<3>                           FB22_15      85   I/O       I               LVCMOS33
    spaf<4>                           FB23_2       125  I/O       I               LVCMOS33
    sysreset                          FB1_3        206  GSR/I/O   GSR/I           LVCMOS33
    write                             FB23_3       126  I/O       I               LVCMOS33

    End of Resources

    Legend:
    I/O Style - OD    - OpenDrain
              - PU    - Pullup
              - KPR   - Keeper
              - S     - SchmittTrigger
              - DG    - DataGate
    Reg Use   - LATCH - Transparent latch
              - DFF   - D-flip-flop
              - DEFF  - D-flip-flop with clock enable
              - TFF   - T-flip-flop
              - TDFF  - Dual-edge-triggered T-flip-flop
              - DDFF  - Dual-edge-triggered flip-flop
              - DDEFF - Dual-edge-triggered flip-flop with clock enable
              /S (after any above flop/latch type) indicates initial state is Set

    *********************Function Block Resource Summary***********************
    Function    # of        FB Inputs   Signals     Total       O/IO      IO
    Block       Macrocells  Used        Used        Pt Used     Req       Avail
    FB1          16          32          32           36         3/0        9
    FB2          15          33          33           35         4/0        8
    FB3          16          37          37           35         5/0        8
    FB4          13          39          39           41         4/4        9
    FB5           7          39          39           30         1/3        7
    FB6           4          39          39           26         1/2        3
    FB7          16          36          36           23         5/0        9
    FB8           8          39          39           35         1/4        7
    FB9          14          39          39           30         7/2        9
    FB10         14          40          40           23         4/0        9
    FB11         16          20          20           28         5/0        5
    FB12         14          37          37           56         7/0        7
    FB13         16          33          33           37         3/0        5
    FB14          9          40          40           21         6/0        8
    FB15         16          38          38           39         6/0        7
    FB16          7          35          35           13         6/0        7
    FB17          7          19          19           13         4/0        7
    FB18          7           7           7            4         7/0        8
    FB19          1          14          14            2         1/0        9
    FB20          3           1           1            1         0/0        6
    FB21          0           0           0            0         0/0       10
    FB22          0           0           0            0         0/0        7
    FB23          3          17          17            6         3/0        5
    FB24          1          14          14            6         0/1        4
                ----                                -----       -----     -----
                223                                  540        83/16     173
    *********************************** FB1 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  32
    Number of function block inputs used/remaining:               32/8
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   36/20
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U3/r3                             0       FB1_1   2     I/O      I
    U5/mem_d0                         1       FB1_2   208   I/O      I
    U5/state_FFD1                     5       FB1_3   206   GSR/I/O  GSR/I
    U5/ros_w0                         1       FB1_4   205   I/O      I
    U5/_n007019                       6       FB1_5         (b)      (b)
    U5/flash_enable<3>                3       FB1_6         (b)      (b)
    U5/flash_enable<2>                3       FB1_7         (b)      (b)
    U5/flash_enable<1>                3       FB1_8         (b)      (b)
    U5/flash_enable<0>                3       FB1_9         (b)      (b)
    flash_ena_5_rosmem                5       FB1_10        (b)      (b)
    U5/flash_enable<4>                5       FB1_11        (b)      (b)
    cspare_8                          0       FB1_12  203   I/O      O
    fpga_init<0>                      3       FB1_13  202   I/O      O
    i2c_ce_gol                        3       FB1_14  201   I/O      O
    U5/state_FFD2                     4       FB1_15  200   I/O      I
    N_PZ_1032                         2       FB1_16  199   I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_1032         12: U5/jtag_start     23: db<4>.PIN
      2: N_PZ_941          13: U5/local_reset    24: db<5>.PIN
      3: N_PZ_944          14: U5/state_FFD1     25: flash_ena_5_rosmem
      4: N_PZ_953          15: U5/state_FFD2     26: flash_tdo_p<0>
      5: N_PZ_957          16: U5/state_FFD3     27: flash_tdo_p<1>
      6: U5/cclk_counter<4>
                           17: add_p<0>          28: flash_tdo_p<2>
      7: U5/flash_enable<0>
                           18: add_p<1>          29: flash_tdo_p<3>
      8: U5/flash_enable<1>
                           19: db<0>.PIN         30: flash_tdo_p<4>
      9: U5/flash_enable<2>
                           20: db<1>.PIN         31: flash_tdo_p<5>
     10: U5/flash_enable<3>
                           21: db<2>.PIN         32: i2c_ce_gol
     11: U5/flash_enable<4>
                           22: db<3>.PIN

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U5/state_FFD1     .....X.....XXXXX........................ 6       6
    U5/_n007019       ....XXXXXXX..XX.........XXXXXXX......... 16      16
    U5/flash_enable<3>
                      XX.......X..X...XX...X.................. 7       7
    U5/flash_enable<2>
                      XX......X...X...XX..X................... 7       7
    U5/flash_enable<1>
                      XX.....X....X...XX.X.................... 7       7
    U5/flash_enable<0>
                      XX....X.....X...XXX..................... 7       7
    flash_ena_5_rosmem
                      .X..........X...XXXXXXXXX............... 11      11
    U5/flash_enable<4>
                      .X........X.X...XXXXXXXX................ 11      11
    cspare_8          ........................................ 0       0
    fpga_init<0>      ..X.........X.....X..................... 3       3
    i2c_ce_gol        ...X........X.....XX...........X........ 5       5
    U5/state_FFD2     .....X......XXXX........................ 5       5
    N_PZ_1032         .X........X.....XX......X............... 5       5
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB2 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  33
    Number of function block inputs used/remaining:               33/7
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   35/21
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    qpll_reset                        2       FB2_1   3     GTS/I/O  O
    i2c_ce_p                          1       FB2_2   4     I/O      O
    cspare_9                          0       FB2_3   5     GTS/I/O  O
    U5/int_ena_spaf                   4       FB2_4   6     I/O      I
    (unused)                          0       FB2_5   7     GTS/I/O  I
    U5/int_ena_mdone                  4       FB2_6         (b)      (b)
    int_lev<2>                        3       FB2_7         (b)      (b)
    int_lev<1>                        3       FB2_8         (b)      (b)
    U5/int_vect<6>                    3       FB2_9         (b)      (b)
    U5/int_vect<4>                    3       FB2_10        (b)      (b)
    U5/int_vect<3>                    3       FB2_11        (b)      (b)
    U5/int_vect<2>                    3       FB2_12        (b)      (b)
    U5/int_ena_sff                    4       FB2_13  8     I/O      I
    U5/int_vect<0>                    3       FB2_14        (b)      (b)
    U5/int_ena_rosw                   4       FB2_15  9     GTS/I/O  I
    on_244                            0       FB2_16  10    I/O      O

    Signals Used by Logic in Function Block
      1: N_PZ_930          12: add_p<1>          23: db<11>.PIN
      2: N_PZ_953          13: add_p<2>          24: db<12>.PIN
      3: U1/q2             14: add_p<3>          25: db<14>.PIN
      4: U1/q4             15: add_p<4>          26: db<1>.PIN
      5: U5/int_ena_mdone  16: add_p<5>          27: db<2>.PIN
      6: U5/int_ena_rosw   17: add_p<6>          28: db<3>.PIN
      7: U5/int_ena_sff    18: add_p<7>          29: db<6>.PIN
      8: U5/int_ena_spaf   19: add_p<8>          30: db<7>.PIN
      9: U5/local_reset    20: brd_sel_16        31: db<8>.PIN
     10: ack_int           21: db<0>.PIN         32: int_rst
     11: add_p<0>          22: db<10>.PIN        33: tp2

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    qpll_reset        XX............................X......... 3       3
    i2c_ce_p          ............XXXXXXXX.................... 8       8
    cspare_9          ........................................ 0       0
    U5/int_ena_spaf   ..XX...XX.XXXXXXXXXXX..........X........ 16      16
    U5/int_ena_mdone  ..XXX...X.XXXXXXXXXX......X....X........ 16      16
    int_lev<2>        ..XX....X.XXXXXXXXXX.........X.X........ 15      15
    int_lev<1>        ..XX....X.XXXXXXXXXX........X..X........ 15      15
    U5/int_vect<6>    ..XX....X.XXXXXXXXXX....X......X........ 15      15
    U5/int_vect<4>    ..XX....X.XXXXXXXXXX...X.......X........ 15      15
    U5/int_vect<3>    ..XX....X.XXXXXXXXXX..X........X........ 15      15
    U5/int_vect<2>    ..XX....X.XXXXXXXXXX.X.........X........ 15      15
    U5/int_ena_sff    ..XX..X.X.XXXXXXXXXX.....X.....X........ 16      16
    U5/int_vect<0>    ..XX....X.XXXXXXXXXX..........XX........ 15      15
    U5/int_ena_rosw   ..XX.X..X.XXXXXXXXXX.......X...X........ 16      16
    on_244            ........................................ 0       0
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB3 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   35/21
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    add_f_p<12>                       0       FB3_1   198   I/O      O
    add_f_p<10>                       0       FB3_2   197   I/O      O
    add_f_p<11>                       0       FB3_3   196   I/O      O
    add_f_p<13>                       0       FB3_4   195   I/O      O
    add_f_p<14>                       0       FB3_5   194   I/O      O
    U5/cclk_counter<3>                2       FB3_6         (b)      (b)
    U5/cclk_counter<2>                2       FB3_7         (b)      (b)
    U5/cclk_counter<1>                2       FB3_8         (b)      (b)
    U5/cclk_counter<0>                1       FB3_9         (b)      (b)
    U5/ros_waiting_reg                3       FB3_10        (b)      (b)
    U5/mem_done_reg                   3       FB3_11        (b)      (b)
    U5/bits_to_send<0>                5       FB3_12  193   I/O      I
    N_PZ_971                          7       FB3_13  192   I/O      I
    int_rst                           13      FB3_14        (b)      (b)
    U5/cclk_counter<4>                2       FB3_15  191   I/O      I
    U3/r4                             2       FB3_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: U3/r3             14: U5/mem_d0         26: mem_done
      2: U5/bits_to_send<0>
                           15: U5/mem_done_reg   27: ros_waiting
      3: U5/cclk_counter<0>
                           16: U5/ros_w0         28: sff<0>
      4: U5/cclk_counter<1>
                           17: U5/ros_waiting_reg
                                                 29: sff<1>
      5: U5/cclk_counter<2>
                           18: U5/state_FFD1     30: sff<2>
      6: U5/cclk_counter<3>
                           19: U5/state_FFD2     31: sff<3>
      7: U5/cclk_counter<4>
                           20: U5/state_FFD3     32: sff<4>
      8: U5/int_ena_mdone  21: db<10>            33: spaf<0>
      9: U5/int_ena_rosw   22: db<11>            34: spaf<1>
     10: U5/int_ena_sff    23: db<12>            35: spaf<2>
     11: U5/int_ena_spaf   24: dtack_int         36: spaf<3>
     12: U5/jtag_num_bits<0>
                           25: int_rst           37: spaf<4>
     13: U5/local_reset

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    add_f_p<12>       ........................................ 0       0
    add_f_p<10>       ........................................ 0       0
    add_f_p<11>       ........................................ 0       0
    add_f_p<13>       ........................................ 0       0
    add_f_p<14>       ........................................ 0       0
    U5/cclk_counter<3>
                      ..XXX.......X........................... 4       4
    U5/cclk_counter<2>
                      ..XX........X........................... 3       3
    U5/cclk_counter<1>
                      ..X.........X........................... 2       2
    U5/cclk_counter<0>
                      ............X........................... 1       1
    U5/ros_waiting_reg
                      ............X..XX.......X.X............. 5       5
    U5/mem_done_reg   ............XXX.........XX.............. 5       5
    U5/bits_to_send<0>
                      .X....X....XX....XXX.................... 7       7
    N_PZ_971          ..XXXXX.............XXX................. 8       8
    int_rst           .......XXXX...X.X......XX..XXXXXXXXXX... 18      18
    U5/cclk_counter<4>
                      ..XXXX......X........................... 5       5
    U3/r4             X.......................X............... 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB4 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  39
    Number of function block inputs used/remaining:               39/1
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   41/15
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<0>                             12      FB4_1   12    I/O      I/O
    (unused)                          0       FB4_2         (b)
    db<8>                             6       FB4_3   14    I/O      I/O
    db<15>                            1       FB4_4   15    I/O      I/O
    db<7>                             9       FB4_5   16    I/O      I/O
    (unused)                          0       FB4_6         (b)
    U5/flash_tms                      3       FB4_7         (b)      (b)
    N_PZ_945                          1       FB4_8         (b)      (b)
    N_PZ_944                          1       FB4_9         (b)      (b)
    U5/gol_notready_reg               3       FB4_10        (b)      (b)
    U5/flash_tdi_reg                  3       FB4_11        (b)      (b)
    fpga_init<1>                      3       FB4_12  17    I/O      O
    i2c_ce_1wire                      3       FB4_13  18    I/O      O
    fpga_init<2>                      3       FB4_14  19    I/O      O
    gol_off                           3       FB4_15  20    I/O      O
    (unused)                          0       FB4_16  21    I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_941          14: U5/local_reset    27: db<1>.PIN
      2: N_PZ_944          15: U5/tdi_bits<0>    28: db<2>.PIN
      3: N_PZ_945          16: U5/tdi_bits<7>    29: db<7>
      4: N_PZ_953          17: U5/tdo_bits<0>    30: db<7>.PIN
      5: U5/ena_evres      18: U5/tdo_bits<7>    31: db<8>.PIN
      6: U5/flash_enable<0>
                           19: ack_int           32: fpga_init<0>
      7: U5/flash_tdi_reg  20: add_p<0>          33: gol_ready
      8: U5/flash_tms      21: add_p<1>          34: i2c_ce_gol
      9: U5/gol_notready_reg
                           22: add_p<2>          35: int_lev<2>
     10: U5/int_ena_spaf   23: add_p<3>          36: ros_waiting
     11: U5/int_vect<0>    24: add_p<4>          37: sff<2>
     12: U5/int_vect<7>    25: add_p<5>          38: sff<3>
     13: U5/jtag_end       26: db<0>             39: spaf<0>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<0>             X....X...XX..XX.X.XXXXXXXX.....X.X.X..X. 19      19
    db<8>             ....X.XX..X.X.....XXXXXXX............X.. 13      13
    db<15>            ...........X......XXXXXXX............... 8       8
    db<7>             X.......X..X.X.X.XXXXXXXX...X.....X.X... 16      16
    U5/flash_tms      ..X..........X................X......... 3       3
    N_PZ_945          X..................XX................... 3       3
    N_PZ_944          X..................XX................... 3       3
    U5/gol_notready_reg
                      ...X....X....X...............X..X....... 5       5
    U5/flash_tdi_reg  X............X.....XX.........X......... 5       5
    fpga_init<1>      .X...........X............X............. 3       3
    i2c_ce_1wire      ...X.........X............X............. 3       3
    fpga_init<2>      .X...........X.............X............ 3       3
    gol_off           ...X.........X.............X............ 3       3
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB5 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  39
    Number of function block inputs used/remaining:               39/1
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   30/26
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB5_1         (b)
    (unused)                          0       FB5_2         (b)
    (unused)                          0       FB5_3         (b)
    db<1>                             10      FB5_4   189   I/O      I/O
    db<9>                             8       FB5_5   188   I/O      I/O
    (unused)                          0       FB5_6         (b)
    (unused)                          0       FB5_7         (b)
    (unused)                          0       FB5_8         (b)
    U1/q44                            1       FB5_9         (b)      (b)
    N_PZ_941                          1       FB5_10        (b)      (b)
    N_PZ_953                          1       FB5_11        (b)      (b)
    db<10>                            8       FB5_12  187   I/O      I/O
    (unused)                          0       FB5_13  186   I/O
    fpga_init<3>                      3       FB5_14  185   I/O      O
    (unused)                          0       FB5_15  184   I/O      I
    (unused)                          0       FB5_16  183   I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_944          14: ack_int           27: db<9>
      2: N_PZ_957          15: add_p<0>          28: fl_vme<1>
      3: U1/q2             16: add_p<1>          29: flash_tdo_p<0>
      4: U1/q4             17: add_p<2>          30: flash_tdo_p<1>
      5: U5/flash_enable<1>
                           18: add_p<3>          31: fpga_init<1>
      6: U5/int_ena_sff    19: add_p<4>          32: i2c_ce_1wire
      7: U5/int_vect<2>    20: add_p<5>          33: int_rst
      8: U5/jtag_num_bits<0>
                           21: add_p<6>          34: mem_done
      9: U5/jtag_num_bits<1>
                           22: add_p<7>          35: sel_tim_clk<0>
     10: U5/local_reset    23: add_p<8>          36: sel_tim_clk<1>
     11: U5/not_sel_tim_reg
                           24: brd_sel_16        37: sel_tim_p
     12: U5/tdi_bits<1>    25: db<10>            38: sff<4>
     13: U5/tdo_bits<1>    26: db<3>.PIN         39: spaf<1>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<1>             ....XX.....XXXXXXXXX......XX..XX.X....X. 17      17
    db<9>             .XXX...X.X...XXXXXXXXXXX..X.X...X.X.XX.. 22      22
    U1/q44            ...X.................................... 1       1
    N_PZ_941          ..XX............XXXXXXXX................ 10      10
    N_PZ_953          ..XX..........XXXXXXXXXX................ 12      12
    db<10>            XX....X.XXX..XXXXXXX....X....X.....X.... 16      16
    fpga_init<3>      X........X...............X.............. 3       3
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB6 ***********************************
    This function block is part of I/O Bank number:               2
    Number of signals used by logic mapping into function block:  39
    Number of function block inputs used/remaining:               39/1
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   26/30
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<2>                             12      FB6_1   22    I/O      I/O
    (unused)                          0       FB6_2         (b)
    fpga_init<4>                      3       FB6_3   23    I/O      O
    (unused)                          0       FB6_4         (b)
    (unused)                          0       FB6_5         (b)
    (unused)                          0       FB6_6         (b)
    (unused)                          0       FB6_7         (b)
    (unused)                          0       FB6_8         (b)
    (unused)                          0       FB6_9         (b)
    (unused)                          0       FB6_10        (b)
    (unused)                          0       FB6_11        (b)
    (unused)                          0       FB6_12        (b)
    (unused)                          0       FB6_13        (b)
    (unused)                          0       FB6_14        (b)
    U5/s_reset_1                      3       FB6_15        (b)      (b)
    db<4>                             9       FB6_16  25    I/O      I/O

    Signals Used by Logic in Function Block
      1: N_PZ_941          14: U5/tdi_bits<4>    27: brd_sel_16
      2: N_PZ_944          15: U5/tdo_bits<2>    28: db<15>.PIN
      3: U1/q2             16: U5/tdo_bits<4>    29: db<2>
      4: U1/q4             17: ack_int           30: db<4>.PIN
      5: U5/ena_evres      18: add_p<0>          31: evcnt_res
      6: U5/flash_enable<2>
                           19: add_p<1>          32: fpga_done<0>
      7: U5/flash_enable<4>
                           20: add_p<2>          33: fpga_done<2>
      8: U5/int_ena_mdone  21: add_p<3>          34: fpga_init<2>
      9: U5/int_vect<2>    22: add_p<4>          35: fpga_init<4>
     10: U5/int_vect<4>    23: add_p<5>          36: gol_off
     11: U5/local_reset    24: add_p<6>          37: int_rst
     12: U5/qpll_error_reg 25: add_p<7>          38: spaf<2>
     13: U5/tdi_bits<2>    26: add_p<8>          39: spaf<4>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<2>             X....X.XX.X.X.X.XXXXXXX.....X..X.X.X.X.. 19      19
    fpga_init<4>      .X........X..................X.......... 3       3
    U5/s_reset_1      ..XXX.....X......XXXXXXXXXXX..X......... 16      16
    db<4>             ......X..X.X.X.XXXXXXXX.........X.X.X.X. 16      16
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB7 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  36
    Number of function block inputs used/remaining:               36/4
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   23/33
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    cclk<0>                           1       FB7_1   51    CDR/I/O  O
    cclk<1>                           1       FB7_2   50    I/O      O
    cclk<2>                           1       FB7_3   49    I/O      O
    cclk<3>                           1       FB7_4   48    I/O      O
    cclk<4>                           1       FB7_5   47    I/O      O
    U5/reset_1                        2       FB7_6         (b)      (b)
    U5/s_reset_2                      1       FB7_7         (b)      (b)
    U1/q4                             1       FB7_8         (b)      (b)
    U5/reset_2                        1       FB7_9         (b)      (b)
    U1/q444                           1       FB7_10        (b)      (b)
    ULED3/q1                          2       FB7_11        (b)      (b)
    N_PZ_966                          1       FB7_12  46    GCK/I/O  GCK/I
    N_PZ_930                          1       FB7_13        (b)      (b)
    N_PZ_1042                         7       FB7_14  45    I/O      I
    U5/_n0041                         2       FB7_15  44    GCK/I/O  GCK
    U5/local_reset                    2       FB7_16  43    I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_971          13: add_p<1>          25: db<5>
      2: U1/q2             14: add_p<2>          26: ena_evres_prgm
      3: U1/q4             15: add_p<3>          27: evcnt_res
      4: U1/q44            16: add_p<4>          28: fpga_done<0>
      5: U1/q7             17: add_p<5>          29: fpga_done<1>
      6: U3/r4             18: add_p<6>          30: fpga_done<2>
      7: U5/reset_1        19: add_p<7>          31: fpga_done<3>
      8: U5/reset_2        20: add_p<8>          32: fpga_done<4>
      9: U5/s_reset_1      21: brd_sel_16        33: iack
     10: ULED3/q1          22: db<14>            34: int_lev<1>
     11: ULED3/q3          23: db<14>.PIN        35: int_lev<2>
     12: add_p<0>          24: db<15>.PIN        36: sysreset

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    cclk<0>           X..........................X............ 2       2
    cclk<1>           X...........................X........... 2       2
    cclk<2>           X............................X.......... 2       2
    cclk<3>           X.............................X......... 2       2
    cclk<4>           X..............................X........ 2       2
    U5/reset_1        .XX........XXXXXXXXXX.X............X.... 14      14
    U5/s_reset_2      ........X............................... 1       1
    U1/q4             .X..X................................... 2       2
    U5/reset_2        ......X................................. 1       1
    U1/q444           ...X.................................... 1       1
    ULED3/q1          .XX......XX............................. 4       4
    N_PZ_966          .........................XX............. 2       2
    N_PZ_930          ......XX................................ 2       2
    N_PZ_1042         .....X.....XXX..........X.......XXX..... 8       8
    U5/_n0041         .XX........XXXXXXXXXXX.X.XX............. 16      16
    U5/local_reset    .XX........XXXXXXXXXX.X............X.... 14      14
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB8 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  39
    Number of function block inputs used/remaining:               39/1
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   35/21
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<3>                             9       FB8_1   54    I/O      I/O
    db<6>                             10      FB8_2   55    GCK/I/O  I/O
    db<14>                            5       FB8_3   56    I/O      I/O
    db<12>                            6       FB8_4   57    I/O      I/O
    fl_vme<1>                         3       FB8_5   58    DGE/I/O  (b)
    (unused)                          0       FB8_6         (b)
    (unused)                          0       FB8_7         (b)
    (unused)                          0       FB8_8         (b)
    (unused)                          0       FB8_9         (b)
    (unused)                          0       FB8_10        (b)
    (unused)                          0       FB8_11        (b)
    (unused)                          0       FB8_12        (b)
    mspare_1                          0       FB8_13  60    I/O      O
    U5/qpll_hasunlock_reg             3       FB8_14        (b)      (b)
    (unused)                          0       FB8_15  61    I/O      I
    ena_evres_prgm                    3       FB8_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_941          14: U5/tdi_bits<6>    27: db<1>.PIN
      2: N_PZ_944          15: U5/tdo_bits<3>    28: db<6>
      3: N_PZ_953          16: U5/tdo_bits<6>    29: db<6>.PIN
      4: N_PZ_957          17: ack_int           30: flash_tdo_p<3>
      5: U5/flash_enable<3>
                           18: add_p<0>          31: flash_tdo_p<5>
      6: U5/int_ena_rosw   19: add_p<1>          32: fpga_done<1>
      7: U5/int_vect<3>    20: add_p<2>          33: fpga_done<4>
      8: U5/int_vect<4>    21: add_p<3>          34: fpga_init<3>
      9: U5/int_vect<6>    22: add_p<4>          35: gol_ready
     10: U5/jtag_num_bits<3>
                           23: add_p<5>          36: int_lev<1>
     11: U5/local_reset    24: db<12>            37: qpll_locked
     12: U5/qpll_hasunlock_reg
                           25: db<13>.PIN        38: sff<1>
     13: U5/tdi_bits<3>    26: db<14>            39: spaf<3>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<3>             ....XXX.....X.X.XXXXXXX........X.XX...X. 16      16
    db<6>             X.......X.XX.X.XXXXXXXX....X....X..X.X.. 17      17
    db<14>            .X.X....X.X.....XXXXXXX..X....X......... 13      13
    db<12>            .X.X...X.XX.....XXXXXXXX.....X.......... 14      14
    fl_vme<1>         X.........X......XX.......X............. 5       5
    mspare_1          ........................................ 0       0
    U5/qpll_hasunlock_reg
                      ..X.......XX................X.......X... 5       5
    ena_evres_prgm    .X........X.............X............... 3       3
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB9 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  39
    Number of function block inputs used/remaining:               39/1
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   30/26
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    db<5>                             10      FB9_1   41    I/O      I/O
    db<13>                            5       FB9_2   40    I/O      I/O
    add_f_p<15>                       0       FB9_3   39    I/O      O
    add_f_p<9>                        0       FB9_4   38    I/O      O
    prgm_fpga_p<0>                    1       FB9_5   37    I/O      O
    (unused)                          0       FB9_6         (b)
    (unused)                          0       FB9_7         (b)
    U5/tdo_bits<0>                    3       FB9_8         (b)      (b)
    U5/tdo_bits<1>                    3       FB9_9         (b)      (b)
    U5/tdo_bits<2>                    3       FB9_10        (b)      (b)
    U5/tdo_bits<3>                    3       FB9_11        (b)      (b)
    prgm_fpga_p<1>                    1       FB9_12  36    I/O      O
    prgm_fpga_p<2>                    1       FB9_13  35    I/O      O
    prgm_fpga_p<3>                    1       FB9_14  34    I/O      O
    prgm_fpga_p<4>                    1       FB9_15  32    I/O      O
    U5/tdo_bits<4>                    3       FB9_16        (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_957          14: U5/tdo_bits<5>    27: db<5>
      2: N_PZ_966          15: ack_int           28: ena_evres_prgm
      3: U1/q2             16: add_p<0>          29: flash_ena_5_rosmem
      4: U1/q4             17: add_p<1>          30: flash_tdo_p<4>
      5: U5/jtag_shift     18: add_p<2>          31: fpga_done<3>
      6: U5/jtag_start     19: add_p<3>          32: int_rst
      7: U5/local_reset    20: add_p<4>          33: prgm_fpga<0>
      8: U5/tdi_bits<5>    21: add_p<5>          34: prgm_fpga<1>
      9: U5/tdo_bits<0>    22: add_p<6>          35: prgm_fpga<2>
     10: U5/tdo_bits<1>    23: add_p<7>          36: prgm_fpga<3>
     11: U5/tdo_bits<2>    24: add_p<8>          37: prgm_fpga<4>
     12: U5/tdo_bits<3>    25: brd_sel_16        38: qpll_locked
     13: U5/tdo_bits<4>    26: db<13>            39: sff<0>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<5>             ..XX..XX.....XXXXXXXXXXXXXX.X.XX.....XX. 23      23
    db<13>            X.XX..X.......XXXXXXXXXXXX.X.X.X........ 19      19
    add_f_p<15>       ........................................ 0       0
    add_f_p<9>        ........................................ 0       0
    prgm_fpga_p<0>    .X..............................X....... 2       2
    U5/tdo_bits<0>    ....XXX.XX.............................. 5       5
    U5/tdo_bits<1>    ....XXX..XX............................. 5       5
    U5/tdo_bits<2>    ....XXX...XX............................ 5       5
    U5/tdo_bits<3>    ....XXX....XX........................... 5       5
    prgm_fpga_p<1>    .X...............................X...... 2       2
    prgm_fpga_p<2>    .X................................X..... 2       2
    prgm_fpga_p<3>    .X.................................X.... 2       2
    prgm_fpga_p<4>    .X..................................X... 2       2
    U5/tdo_bits<4>    ....XXX.....XX.......................... 5       5
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB10 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  40
    Number of function block inputs used/remaining:               40/0
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   23/33
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    etr_vf                            1       FB10_1  62    I/O      O
    etr_x                             2       FB10_2  63    I/O      O
    ack_int                           3       FB10_3        (b)      (b)
    ldpreg                            1       FB10_4  64    I/O      O
    g245_p                            1       FB10_5  65    I/O      O
    U1/q9                             2       FB10_6        (b)      (b)
    U1/q7                             2       FB10_7        (b)      (b)
    U1/q8                             1       FB10_8        (b)      (b)
    U1/q6                             2       FB10_9        (b)      (b)
    U1/q2                             3       FB10_10       (b)      (b)
    U1/q1                             2       FB10_11       (b)      (b)
    (unused)                          0       FB10_12 66    I/O      I
    (unused)                          0       FB10_13 67    I/O      I
    U3/r8                             3       FB10_14 69    I/O      I
    dtack_int                         3       FB10_15 70    I/O      I
    U3/r7                             2       FB10_16 71    I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_1042         15: add_mod<3>        28: brd_sel_16
      2: U1/dssync         16: add_mod<4>        29: brd_sel_24
      3: U1/q1             17: add_mod<5>        30: db<11>.PIN
      4: U1/q2             18: add_p<0>          31: ds0
      5: U1/q4             19: add_p<1>          32: ds1
      6: U1/q6             20: add_p<2>          33: dtack_int
      7: U1/q9             21: add_p<3>          34: etr_x
      8: U3/r6             22: add_p<4>          35: flash_ena_5_rosmem
      9: U3/r7             23: add_p<5>          36: g245_mem
     10: U3/r8             24: add_p<6>          37: iack
     11: ack_int           25: add_p<7>          38: lword
     12: add_mod<0>        26: add_p<8>          39: tp2
     13: add_mod<1>        27: as                40: write
     14: add_mod<2>

    Signal                     1         2         3         4         5 Signals FB
    Name             0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
    etr_vf            ............................X..................... 1       1
    etr_x             .X.........XXXXXX..........X..XX.X..XX.X.......... 14      14
    ack_int           X......X..X...................X................... 4       4
    ldpreg            ...XX............XXXXXXXXX.X.X.................... 13      13
    g245_p            ..X.......X.......................XX..X........... 5       5
    U1/q9             .....X........................XX.................. 3       3
    U1/q7             ......X.......................XX.................. 3       3
    U1/q8             ..............................XX.................. 2       2
    U1/q6             ..............................XX......X........... 3       3
    U1/q2             .XX........XXXXXX..........X..XX....XX.X.......... 14      14
    U1/q1             .XX........XXXXXX..........X..XX....XX.X.......... 14      14
    U3/r8             X.......XX................X....................... 4       4
    dtack_int         X.......X.....................X.X................. 4       4
    U3/r7             .......X......................X................... 2       2
                     0----+----1----+----2----+----3----+----4----+----5
                               0         0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB11 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  20
    Number of function block inputs used/remaining:               20/20
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   28/28
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    irq<1>                            1       FB11_1  31    I/O      O
    ULED1/q1                          2       FB11_2        (b)      (b)
    irq<2>                            1       FB11_3  30    I/O      O
    irq<3>                            1       FB11_4  29    I/O      O
    irq<4>                            1       FB11_5  28    I/O      O
    U1/dssync                         2       FB11_6        (b)      (b)
    U5/jtag_num_bits<1>               3       FB11_7        (b)      (b)
    U3/r6                             2       FB11_8        (b)      (b)
    U5/jtag_num_bits<2>               3       FB11_9        (b)      (b)
    U5/jtag_num_bits<0>               3       FB11_10       (b)      (b)
    U3/r5                             2       FB11_11       (b)      (b)
    irq<5>                            1       FB11_12 27    I/O      O
    ULED2/q3                          2       FB11_13       (b)      (b)
    U5/jtag_num_bits<3>               3       FB11_14       (b)      (b)
    ULED1/q3                          2       FB11_15       (b)      (b)
    ULED3/q3                          2       FB11_16       (b)      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_930           8: db<10>.PIN        15: iackin
      2: N_PZ_945           9: db<11>.PIN        16: int_lev<1>
      3: U1/q8             10: db<12>.PIN        17: int_lev<2>
      4: U3/r5             11: db<5>             18: int_rst
      5: U5/local_reset    12: db<9>.PIN         19: intrpt_led
      6: ULED1/q1          13: ds0               20: spare_led
      7: ULED1/q3          14: dtack_led

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    irq<1>            ..........X....XXX...................... 4       4
    ULED1/q1          .....XX..........X...................... 3       3
    irq<2>            ..........X....XXX...................... 4       4
    irq<3>            ..........X....XXX...................... 4       4
    irq<4>            ..........X....XXX...................... 4       4
    U1/dssync         ..X.........X........................... 2       2
    U5/jtag_num_bits<1>
                      .X..X..X................................ 3       3
    U3/r6             ...X........X........................... 2       2
    U5/jtag_num_bits<2>
                      .X..X...X............................... 3       3
    U5/jtag_num_bits<0>
                      .X..X......X............................ 3       3
    U3/r5             ............X.X......................... 2       2
    irq<5>            ..........X....XXX...................... 4       4
    ULED2/q3          X............X.......................... 2       2
    U5/jtag_num_bits<3>
                      .X..X....X.............................. 3       3
    ULED1/q3          X.................X..................... 2       2
    ULED3/q3          X..................X.................... 2       2
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB12 ***********************************
    This function block is part of I/O Bank number:               1
    Number of signals used by logic mapping into function block:  37
    Number of function block inputs used/remaining:               37/3
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   56/0
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    fl_tdo                            13      FB12_1  72    I/O      O
    flash_tck_p<0>                    4       FB12_2  73    I/O      O
    flash_tck_p<1>                    6       FB12_3  74    I/O      O
    flash_tck_p<2>                    4       FB12_4  75    I/O      O
    flash_tck_p<3>                    4       FB12_5  76    I/O      O
    (unused)                          0       FB12_6        (b)
    (unused)                          0       FB12_7        (b)
    U5/state_FFD3                     3       FB12_8        (b)      (b)
    U5/tdo_reg                        5       FB12_9        (b)      (b)
    U5/jtag_end                       5       FB12_10       (b)      (b)
    U5/jtag_shift                     4       FB12_11       (b)      (b)
    flash_tck_p<4>                    4       FB12_12 77    I/O      O
    U5/flash_tck                      3       FB12_13       (b)      (b)
    N_PZ_957                          2       FB12_14       (b)      (b)
    N_PZ_1002                         2       FB12_15       (b)      (b)
    flash_tck_p<5>                    4       FB12_16 78    I/O      O

    Signals Used by Logic in Function Block
      1: N_PZ_930          14: U5/flash_tck      26: fl_switch<0>
      2: N_PZ_957          15: U5/jtag_end       27: fl_switch<1>
      3: U5/_n007019       16: U5/jtag_shift     28: fl_switch<2>
      4: U5/bits_to_send<0>
                           17: U5/jtag_start     29: fl_tck_r
      5: U5/bits_to_send<1>
                           18: U5/local_reset    30: fl_vme<1>
      6: U5/bits_to_send<2>
                           19: U5/state_FFD1     31: flash_ena_5_rosmem
      7: U5/bits_to_send<3>
                           20: U5/state_FFD2     32: flash_tdo_p<0>
      8: U5/cclk_counter<4>
                           21: U5/state_FFD3     33: flash_tdo_p<1>
      9: U5/flash_enable<0>
                           22: U5/tdo_reg        34: flash_tdo_p<2>
     10: U5/flash_enable<1>
                           23: db<0>             35: flash_tdo_p<3>
     11: U5/flash_enable<2>
                           24: db<2>             36: flash_tdo_p<4>
     12: U5/flash_enable<3>
                           25: db<6>             37: flash_tdo_p<5>
     13: U5/flash_enable<4>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    fl_tdo            X.....................XX.XXX.X.XXXXXX... 13      13
    flash_tck_p<0>    .X......X....X........XXXXXXXX.......... 11      11
    flash_tck_p<1>    .........X...X........XXXXXXXX.......... 10      10
    flash_tck_p<2>    .X........X..X........XXXXXXXX.......... 11      11
    flash_tck_p<3>    .X.........X.X........XXXXXXXX.......... 11      11
    U5/state_FFD3     ...XXXXX.........XXXX................... 9       9
    U5/tdo_reg        ..X....X.........XXXXX.................. 7       7
    U5/jtag_end       ..............X.XXXXX................... 6       6
    U5/jtag_shift     ...............X.XXXX................... 5       5
    flash_tck_p<4>    .X..........XX........XXXXXXXX.......... 11      11
    U5/flash_tck      .............X...XXXX................... 5       5
    N_PZ_957          ......................XX.XXX.X.......... 6       6
    N_PZ_1002         ......................XX.XXX.X.......... 6       6
    flash_tck_p<5>    .X...........X........XXXXXXXXX......... 11      11
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB13 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  33
    Number of function block inputs used/remaining:               33/7
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   37/19
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    U5/tdo_bits<6>                    3       FB13_1        (b)      (b)
    U5/tdo_bits<5>                    3       FB13_2        (b)      (b)
    tp4                               1       FB13_3  160   I/O      O
    U5/qpll_error_reg                 3       FB13_4  161   I/O      I
    U5/tdi_bits<0>                    4       FB13_5        (b)      (b)
    U5/tdi_bits<1>                    4       FB13_6        (b)      (b)
    U5/tdi_bits<2>                    4       FB13_7        (b)      (b)
    U5/tdi_bits<3>                    4       FB13_8        (b)      (b)
    U5/tdi_bits<4>                    4       FB13_9        (b)      (b)
    U5/tdi_bits<5>                    4       FB13_10       (b)      (b)
    U5/tdi_bits<6>                    4       FB13_11       (b)      (b)
    U5/tdo_bits<7>                    3       FB13_12 162   I/O      I
    cscr_p<0>                         1       FB13_13 163   I/O      O
    U5/tdi_bits<7>                    3       FB13_14       (b)      (b)
    U5/jtag_start                     3       FB13_15       (b)      (b)
    cscr_p<1>                         1       FB13_16 164   I/O      O

    Signals Used by Logic in Function Block
      1: N_PZ_945          12: U5/tdi_bits<4>    23: brd_sel_16
      2: N_PZ_953          13: U5/tdi_bits<5>    24: clk
      3: U5/jtag_end       14: U5/tdi_bits<6>    25: db<0>.PIN
      4: U5/jtag_shift     15: U5/tdi_bits<7>    26: db<1>.PIN
      5: U5/jtag_start     16: U5/tdo_bits<5>    27: db<2>.PIN
      6: U5/local_reset    17: U5/tdo_bits<6>    28: db<3>.PIN
      7: U5/qpll_error_reg 18: U5/tdo_bits<7>    29: db<4>.PIN
      8: U5/tdi_bits<0>    19: U5/tdo_reg        30: db<5>.PIN
      9: U5/tdi_bits<1>    20: add_p<6>          31: db<6>.PIN
     10: U5/tdi_bits<2>    21: add_p<7>          32: db<7>.PIN
     11: U5/tdi_bits<3>    22: add_p<8>          33: qpll_error

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    U5/tdo_bits<6>    ...XXX..........XX...................... 5       5
    U5/tdo_bits<5>    ...XXX.........XX....................... 5       5
    tp4               .......................X................ 1       1
    U5/qpll_error_reg
                      .X...XX.....................X...X....... 5       5
    U5/tdi_bits<0>    X..X.X.XX...............X............... 6       6
    U5/tdi_bits<1>    X..X.X..XX...............X.............. 6       6
    U5/tdi_bits<2>    X..X.X...XX...............X............. 6       6
    U5/tdi_bits<3>    X..X.X....XX...............X............ 6       6
    U5/tdi_bits<4>    X..X.X.....XX...............X........... 6       6
    U5/tdi_bits<5>    X..X.X......XX...............X.......... 6       6
    U5/tdi_bits<6>    X..X.X.......XX...............X......... 6       6
    U5/tdo_bits<7>    ...XXX...........XX..................... 5       5
    cscr_p<0>         ...................XXXX................. 4       4
    U5/tdi_bits<7>    X..X.X........X................X........ 5       5
    U5/jtag_start     X.X.XX.................................. 4       4
    cscr_p<1>         ...................XXXX................. 4       4
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB14 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  40
    Number of function block inputs used/remaining:               40/0
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   21/35
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    mrs                               2       FB14_1  159   I/O      O
    prs                               4       FB14_2  158   I/O      O
    tp3                               1       FB14_3  155   I/O      O
    dtack_led                         2       FB14_4  154   I/O      O
    intrpt_led                        2       FB14_5  153   I/O      O
    (unused)                          0       FB14_6        (b)
    (unused)                          0       FB14_7        (b)
    (unused)                          0       FB14_8        (b)
    (unused)                          0       FB14_9        (b)
    (unused)                          0       FB14_10       (b)
    U5/bits_to_send<1>                5       FB14_11       (b)      (b)
    ULED2/q1                          4       FB14_12       (b)      (b)
    spare_led                         2       FB14_13 152   I/O      O
    (unused)                          0       FB14_14 151   I/O      I
    U5/not_sel_tim_reg                3       FB14_15       (b)      (b)
    (unused)                          0       FB14_16 150   I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_930          15: U5/state_FFD1     28: add_p<6>
      2: N_PZ_953          16: U5/state_FFD2     29: add_p<7>
      3: U1/q2             17: U5/state_FFD3     30: add_p<8>
      4: U1/q4             18: ULED1/q1          31: brd_sel_16
      5: U1/q444           19: ULED2/q1          32: db<10>.PIN
      6: U5/bits_to_send<0>
                           20: ULED2/q3          33: db<12>.PIN
      7: U5/bits_to_send<1>
                           21: ULED3/q1          34: db<13>.PIN
      8: U5/cclk_counter<4>
                           22: add_p<0>          35: db<15>.PIN
      9: U5/ena_evres      23: add_p<1>          36: dtack_int
     10: U5/jtag_num_bits<1>
                           24: add_p<2>          37: dtack_mem
     11: U5/local_reset    25: add_p<3>          38: evcnt_res
     12: U5/not_sel_tim_reg
                           26: add_p<4>          39: flash_ena_5_rosmem
     13: U5/reset_1        27: add_p<5>          40: sel_tim_p
     14: U5/reset_2

    Signal                     1         2         3         4         5 Signals FB
    Name             0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
    mrs               ..XX......X..........XXXXXXXXXX..X................ 14      14
    prs               ..XX....X.X..........XXXXXXXXXX.X.X..X............ 17      17
    tp3               ............XX.................................... 2       2
    dtack_led         X.................X............................... 2       2
    intrpt_led        X................X................................ 2       2
    U5/bits_to_send<1>
                      .....XXX.XX...XXX................................. 8       8
    ULED2/q1          ....X.............XX...............XX.X........... 6       6
    spare_led         X...................X............................. 2       2
    U5/not_sel_tim_reg
                      .X........XX...................X.......X.......... 5       5
                     0----+----1----+----2----+----3----+----4----+----5
                               0         0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB15 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  38
    Number of function block inputs used/remaining:               38/2
    Number of function block control terms used/remaining:        2/2
    Number of PLA product terms used/remaining:                   39/17
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    prgm_fpga<1>                      4       FB15_1        (b)      (b)
    cscr_p<2>                         1       FB15_2  165   I/O      O
    cscr_p<3>                         1       FB15_3  166   I/O      O
    prgm_fpga<0>                      4       FB15_4        (b)      (b)
    cscr_p<4>                         1       FB15_5  167   I/O      O
    U5/cuenta_prgm_0_3                5       FB15_6        (b)      (b)
    U5/cuenta_prgm_0_2                5       FB15_7        (b)      (b)
    U5/cuenta_prgm_0_1                4       FB15_8        (b)      (b)
    U5/cuenta_prgm_0_4                3       FB15_9        (b)      (b)
    U5/cuenta_prgm_0_0                3       FB15_10       (b)      (b)
    U5/bits_to_send<3>                5       FB15_11       (b)      (b)
    cscr_p<5>                         1       FB15_12 168   I/O      O
    cscr_p<6>                         1       FB15_13 169   I/O      O
    U5/bits_to_send<2>                5       FB15_14       (b)      (b)
    vspare_0                          1       FB15_15 170   I/O      O
    U5/int_vect<7>                    3       FB15_16 171   I/O      (b)

    Signals Used by Logic in Function Block
      1: N_PZ_944          14: U5/cuenta_prgm_0_4
                                                 27: add_p<4>
      2: U1/q2             15: U5/jtag_num_bits<2>
                                                 28: add_p<5>
      3: U1/q4             16: U5/jtag_num_bits<3>
                                                 29: add_p<6>
      4: U5/_n0041         17: U5/local_reset    30: add_p<7>
      5: U5/bits_to_send<0>
                           18: U5/s_reset_1      31: add_p<8>
      6: U5/bits_to_send<1>
                           19: U5/s_reset_2      32: brd_sel_16
      7: U5/bits_to_send<2>
                           20: U5/state_FFD1     33: db<15>.PIN
      8: U5/bits_to_send<3>
                           21: U5/state_FFD2     34: db<5>.PIN
      9: U5/cclk_counter<4>
                           22: U5/state_FFD3     35: db<6>.PIN
     10: U5/cuenta_prgm_0_0
                           23: add_p<0>          36: int_rst
     11: U5/cuenta_prgm_0_1
                           24: add_p<1>          37: prgm_fpga<0>
     12: U5/cuenta_prgm_0_2
                           25: add_p<2>          38: prgm_fpga<1>
     13: U5/cuenta_prgm_0_3
                           26: add_p<3>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    prgm_fpga<1>      X..X.....XXXXX....................X..X.. 9       9
    cscr_p<2>         ............................XXXX........ 4       4
    cscr_p<3>         ............................XXXX........ 4       4
    prgm_fpga<0>      X..X.....XXXXX...................X..X... 9       9
    cscr_p<4>         ............................XXXX........ 4       4
    U5/cuenta_prgm_0_3
                      X..X.....XXXXX.......................... 7       7
    U5/cuenta_prgm_0_2
                      X..X.....XXXXX.......................... 7       7
    U5/cuenta_prgm_0_1
                      X..X.....XXXXX.......................... 7       7
    U5/cuenta_prgm_0_4
                      X..X.....XXXXX.......................... 7       7
    U5/cuenta_prgm_0_0
                      X..X.....XXXXX.......................... 7       7
    U5/bits_to_send<3>
                      ....XXXXX......XX..XXX.................. 10      10
    cscr_p<5>         ............................XXXX........ 4       4
    cscr_p<6>         ............................XXXX........ 4       4
    U5/bits_to_send<2>
                      ....XXX.X.....X.X..XXX.................. 9       9
    vspare_0          .................XX..................... 2       2
    U5/int_vect<7>    .XX.............X.....XXXXXXXXXXX..X.... 15      15
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB16 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  35
    Number of function block inputs used/remaining:               35/5
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   13/43
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    flash_tdi_p                       3       FB16_1  149   I/O      O
    flash_tms_p                       3       FB16_2  148   I/O      O
    add_hold                          1       FB16_3  147   I/O      O
    iackout                           1       FB16_4  146   I/O      O
    (unused)                          0       FB16_5        (b)
    (unused)                          0       FB16_6        (b)
    (unused)                          0       FB16_7        (b)
    (unused)                          0       FB16_8        (b)
    (unused)                          0       FB16_9        (b)
    (unused)                          0       FB16_10       (b)
    (unused)                          0       FB16_11       (b)
    U5/ena_evres                      3       FB16_12 145   I/O      (b)
    (unused)                          0       FB16_13       (b)
    vspare_1                          0       FB16_14 144   I/O      O
    (unused)                          0       FB16_15       (b)
    dtack_p                           2       FB16_16 143   I/O      O

    Signals Used by Logic in Function Block
      1: N_PZ_1002         13: add_p<3>          25: ds1
      2: U1/q2             14: add_p<4>          26: dtack_int
      3: U1/q4             15: add_p<5>          27: dtack_mem
      4: U1/q444           16: add_p<6>          28: fl_switch<0>
      5: U3/r8             17: add_p<7>          29: fl_switch<1>
      6: U5/flash_tdi_reg  18: add_p<8>          30: fl_switch<2>
      7: U5/flash_tms      19: brd_sel_16        31: fl_tdi_r
      8: U5/local_reset    20: db<0>             32: fl_tms_r
      9: U5/tdi_bits<0>    21: db<2>             33: fl_vme<1>
     10: add_p<0>          22: db<7>             34: flash_ena_5_rosmem
     11: add_p<1>          23: db<8>.PIN         35: iackin
     12: add_p<2>          24: ds0

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    flash_tdi_p       X....X..X..........XX......XXXX.X....... 10      10
    flash_tms_p       X.....X............XXX.....XXX.XX....... 10      10
    add_hold          .......................XX............... 2       2
    iackout           ....X.............................X..... 2       2
    U5/ena_evres      .XX....X.XXXXXXXXXX...X................. 14      14
    vspare_1          ........................................ 0       0
    dtack_p           ...X.....................XX......X...... 4       4
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB17 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  19
    Number of function block inputs used/remaining:               19/21
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   13/43
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    gol_reset                         2       FB17_1  173   I/O      O
    i2c_reset                         1       FB17_2  174   I/O      O
    reset_p                           1       FB17_3  175   I/O      O
    (unused)                          0       FB17_4        (b)
    (unused)                          0       FB17_5        (b)
    (unused)                          0       FB17_6        (b)
    (unused)                          0       FB17_7        (b)
    (unused)                          0       FB17_8        (b)
    (unused)                          0       FB17_9        (b)
    prgm_fpga<4>                      4       FB17_10       (b)      (b)
    prgm_fpga<3>                      4       FB17_11       (b)      (b)
    (unused)                          0       FB17_12 178   I/O
    enw_vf                            1       FB17_13 179   I/O      O
    (unused)                          0       FB17_14 180   I/O      I
    prgm_fpga<2>                      4       FB17_15       (b)      (b)
    (unused)                          0       FB17_16 182   I/O      I

    Signals Used by Logic in Function Block
      1: N_PZ_930           8: U5/cuenta_prgm_0_3
                                                 14: db<8>.PIN
      2: N_PZ_944           9: U5/cuenta_prgm_0_4
                                                 15: db<9>.PIN
      3: N_PZ_953          10: U5/reset_1        16: i2c_int_p
      4: U5/_n0041         11: U5/reset_2        17: prgm_fpga<2>
      5: U5/cuenta_prgm_0_0
                           12: db<11>.PIN        18: prgm_fpga<3>
      6: U5/cuenta_prgm_0_1
                           13: db<7>.PIN         19: prgm_fpga<4>
      7: U5/cuenta_prgm_0_2

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    gol_reset         X.X........X............................ 3       3
    i2c_reset         .........XX............................. 2       2
    reset_p           .........XX............................. 2       2
    prgm_fpga<4>      .X.XXXXXX.....X...X..................... 9       9
    prgm_fpga<3>      .X.XXXXXX....X...X...................... 9       9
    enw_vf            ...............X........................ 1       1
    prgm_fpga<2>      .X.XXXXXX...X...X....................... 9       9
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB18 ***********************************
    This function block is part of I/O Bank number:               4
    Number of signals used by logic mapping into function block:  7
    Number of function block inputs used/remaining:               7/33
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   4/52
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB18_1        (b)
    irq<6>                            1       FB18_2  142   I/O      O
    irq<7>                            1       FB18_3  140   I/O      O
    mspare_0                          0       FB18_4  139   I/O      O
    i2c_wr                            1       FB18_5  138   I/O      O
    (unused)                          0       FB18_6        (b)
    (unused)                          0       FB18_7        (b)
    (unused)                          0       FB18_8        (b)
    (unused)                          0       FB18_9        (b)
    (unused)                          0       FB18_10       (b)
    (unused)                          0       FB18_11       (b)
    mspare_2                          0       FB18_12 137   I/O      O
    enw_x                             1       FB18_13 136   I/O      O
    (unused)                          0       FB18_14 135   I/O
    mspare_3                          0       FB18_15 134   I/O      O
    (unused)                          0       FB18_16       (b)

    Signals Used by Logic in Function Block
      1: U1/q2              4: i2c_ce_p           6: int_lev<2>
      2: U1/q4              5: int_lev<1>         7: int_rst
      3: db<5>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    irq<6>            ..X.XXX................................. 4       4
    irq<7>            ..X.XXX................................. 4       4
    mspare_0          ........................................ 0       0
    i2c_wr            XX.X.................................... 3       3
    mspare_2          ........................................ 0       0
    enw_x             XX...................................... 2       2
    mspare_3          ........................................ 0       0
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB19 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  14
    Number of function block inputs used/remaining:               14/26
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   2/54
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    tp2                               2       FB19_1  103   I/O      O
    (unused)                          0       FB19_2        (b)
    (unused)                          0       FB19_3  106   I/O
    (unused)                          0       FB19_4  107   I/O      I
    (unused)                          0       FB19_5  108   I/O      I
    (unused)                          0       FB19_6        (b)
    (unused)                          0       FB19_7        (b)
    (unused)                          0       FB19_8        (b)
    (unused)                          0       FB19_9        (b)
    (unused)                          0       FB19_10       (b)
    (unused)                          0       FB19_11       (b)
    (unused)                          0       FB19_12 109   I/O      I
    (unused)                          0       FB19_13 110   I/O      I
    (unused)                          0       FB19_14 111   I/O      I
    (unused)                          0       FB19_15 112   I/O      I
    (unused)                          0       FB19_16 113   I/O      I

    Signals Used by Logic in Function Block
      1: U1/dssync          6: add_mod<4>        11: iack
      2: add_mod<0>         7: add_mod<5>        12: lword
      3: add_mod<1>         8: brd_sel_16        13: tp2
      4: add_mod<2>         9: ds0               14: write
      5: add_mod<3>        10: ds1

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    tp2               XXXXXXXXXXXXXX.......................... 14      14
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB20 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  1
    Number of function block inputs used/remaining:               1/39
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   1/55
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    fl_tck_r                          1       FB20_1  102   I/O      I
    fl_tdi_r                          1       FB20_2  101   I/O      I
    fl_tms_r                          1       FB20_3  100   I/O      I
    (unused)                          0       FB20_4  99    I/O      I
    (unused)                          0       FB20_5  97    I/O      I
    (unused)                          0       FB20_6        (b)
    (unused)                          0       FB20_7        (b)
    (unused)                          0       FB20_8        (b)
    (unused)                          0       FB20_9        (b)
    (unused)                          0       FB20_10       (b)
    (unused)                          0       FB20_11       (b)
    (unused)                          0       FB20_12       (b)
    (unused)                          0       FB20_13 95    I/O      I
    (unused)                          0       FB20_14       (b)
    (unused)                          0       FB20_15       (b)
    (unused)                          0       FB20_16       (b)

    Signals Used by Logic in Function Block
      1: N_PZ_930

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB21 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB21_1  114   I/O      I
    (unused)                          0       FB21_2  115   I/O      I
    (unused)                          0       FB21_3  116   I/O      I
    (unused)                          0       FB21_4  117   I/O      I
    (unused)                          0       FB21_5  118   I/O      I
    (unused)                          0       FB21_6        (b)
    (unused)                          0       FB21_7        (b)
    (unused)                          0       FB21_8        (b)
    (unused)                          0       FB21_9        (b)
    (unused)                          0       FB21_10       (b)
    (unused)                          0       FB21_11       (b)
    (unused)                          0       FB21_12 119   I/O      I
    (unused)                          0       FB21_13 120   I/O      I
    (unused)                          0       FB21_14 121   I/O      I
    (unused)                          0       FB21_15 122   I/O      I
    (unused)                          0       FB21_16 123   I/O      I
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB22 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  0
    Number of function block inputs used/remaining:               0/40
    Number of function block control terms used/remaining:        0/4
    Number of PLA product terms used/remaining:                   0/56
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB22_1        (b)
    (unused)                          0       FB22_2  91    I/O      I
    (unused)                          0       FB22_3  90    I/O      I
    (unused)                          0       FB22_4  89    I/O      I
    (unused)                          0       FB22_5        (b)
    (unused)                          0       FB22_6        (b)
    (unused)                          0       FB22_7        (b)
    (unused)                          0       FB22_8        (b)
    (unused)                          0       FB22_9        (b)
    (unused)                          0       FB22_10       (b)
    (unused)                          0       FB22_11       (b)
    (unused)                          0       FB22_12 88    I/O      I
    (unused)                          0       FB22_13 87    I/O      I
    (unused)                          0       FB22_14 86    I/O      I
    (unused)                          0       FB22_15 85    I/O      I
    (unused)                          0       FB22_16       (b)
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB23 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  17
    Number of function block inputs used/remaining:               17/23
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   6/50
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB23_1        (b)
    (unused)                          0       FB23_2  125   I/O      I
    (unused)                          0       FB23_3  126   I/O      I
    i2c_rd                            1       FB23_4  127   I/O      O
    (unused)                          0       FB23_5        (b)
    (unused)                          0       FB23_6        (b)
    (unused)                          0       FB23_7        (b)
    (unused)                          0       FB23_8        (b)
    (unused)                          0       FB23_9        (b)
    (unused)                          0       FB23_10       (b)
    (unused)                          0       FB23_11       (b)
    sel_tim_clk<0>                    3       FB23_12 128   I/O      O
    (unused)                          0       FB23_13       (b)
    sel_tim_clk<1>                    3       FB23_14 131   I/O      O
    (unused)                          0       FB23_15       (b)
    (unused)                          0       FB23_16       (b)

    Signals Used by Logic in Function Block
      1: U1/q2              7: add_p<3>          13: brd_sel_16
      2: U1/q4              8: add_p<4>          14: db<10>.PIN
      3: U5/local_reset     9: add_p<5>          15: db<9>.PIN
      4: add_p<0>          10: add_p<6>          16: i2c_ce_p
      5: add_p<1>          11: add_p<7>          17: tp2
      6: add_p<2>          12: add_p<8>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    i2c_rd            ...............XX....................... 2       2
    sel_tim_clk<0>    XXXXXXXXXXXXX.X......................... 14      14
    sel_tim_clk<1>    XXXXXXXXXXXXXX.......................... 14      14
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    *********************************** FB24 ***********************************
    This function block is part of I/O Bank number:               3
    Number of signals used by logic mapping into function block:  14
    Number of function block inputs used/remaining:               14/26
    Number of function block control terms used/remaining:        1/3
    Number of PLA product terms used/remaining:                   6/50
    Signal                            Total   Loc     Pin   Pin      Pin
    Name                              Pt               #    Type     Use
    (unused)                          0       FB24_1        (b)
    db<11>                            6       FB24_2  84    I/O      I/O
    (unused)                          0       FB24_3        (b)
    (unused)                          0       FB24_4  83    I/O
    (unused)                          0       FB24_5  82    I/O
    (unused)                          0       FB24_6        (b)
    (unused)                          0       FB24_7        (b)
    (unused)                          0       FB24_8        (b)
    (unused)                          0       FB24_9        (b)
    (unused)                          0       FB24_10       (b)
    (unused)                          0       FB24_11       (b)
    (unused)                          0       FB24_12       (b)
    (unused)                          0       FB24_13       (b)
    (unused)                          0       FB24_14 80    I/O
    (unused)                          0       FB24_15       (b)
    (unused)                          0       FB24_16       (b)

    Signals Used by Logic in Function Block
      1: N_PZ_944           6: ack_int           11: add_p<4>
      2: N_PZ_957           7: add_p<0>          12: add_p<5>
      3: U5/int_vect<3>     8: add_p<1>          13: db<11>
      4: U5/jtag_num_bits<2>
                            9: add_p<2>          14: flash_tdo_p<2>
      5: U5/local_reset    10: add_p<3>

    Signal                     1         2         3         4 Signals FB
    Name             0----+----0----+----0----+----0----+----0 Used    Inputs
    db<11>            XXXXXXXXXXXXXX.......................... 14      14
                     0----+----1----+----2----+----3----+----4
                               0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    ;;-----------------------------------------------------------------;;
    ; Implemented Equations.

    add_f_p(10) <= NOT ('0');

    add_f_p(11) <= NOT ('0');

    add_f_p(12) <= NOT ('0');

    add_f_p(13) <= NOT ('0');

    add_f_p(14) <= NOT ('0');

    add_f_p(15) <= NOT ('0');

    add_f_p(9) <= NOT ('0');

    add_hold <= NOT ((ds0 AND ds1));

    FDCPE_cclk0: FDCPE port map (cclk(0),cclk_D(0),clk,'0','0','1');
    cclk_D(0) <= (fpga_done(0) AND N_PZ_971);

    N_PZ_971 <= ((U5/cclk_freq(1) AND U5/cclk_freq(2) AND
    	U5/cclk_counter(4))
    	OR (U5/cclk_freq(0) AND U5/cclk_freq(2) AND
    	U5/cclk_counter(4))
    	OR (U5/cclk_freq(1) AND U5/cclk_freq(0) AND
    	NOT U5/cclk_freq(2) AND U5/cclk_counter(1))
    	OR (U5/cclk_freq(1) AND NOT U5/cclk_freq(0) AND
    	NOT U5/cclk_freq(2) AND U5/cclk_counter(2))
    	OR (NOT U5/cclk_freq(1) AND U5/cclk_freq(0) AND
    	NOT U5/cclk_freq(2) AND U5/cclk_counter(3))
    	OR (NOT U5/cclk_freq(1) AND NOT U5/cclk_freq(0) AND
    	U5/cclk_freq(2) AND U5/cclk_counter(0))
    	OR (NOT U5/cclk_freq(1) AND NOT U5/cclk_freq(0) AND
    	NOT U5/cclk_freq(2) AND U5/cclk_counter(4)));

    db(11) <= ((U5/cclk_freq(1) AND NOT add_p(1) AND NOT add_p(0) AND
    	NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(2))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(3))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(2)));FDCPE_U5/cclk_freq1: FDCPE port map (U5/cclk_freq(1),db(11).PIN,clk,U5/local_reset,'0',N_PZ_944);

    N_PZ_944 <= (NOT add_p(1) AND NOT add_p(0) AND N_PZ_941);

    N_PZ_941 <= (NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND
    	NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4);

    FDCPE_U1/q2: FDCPE port map (U1/q2,U1/q1,clk,U1/q2_CLR,'0',U1/q2_CE);
    U1/q2_CLR <= (ds0 AND ds1);
    U1/q2_CE <= (NOT brd_sel_16 AND iack AND lword AND add_mod(0) AND NOT write AND
    	NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND add_mod(5) AND
    	add_mod(3) AND U1/dssync);

    FTCPE_U1/q1: FTCPE port map (U1/q1,U1/q1_T,clk,U1/q1_CLR,'0','1');
    U1/q1_T <= (NOT brd_sel_16 AND NOT U1/q1 AND iack AND lword AND add_mod(0) AND
    	NOT write AND NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND
    	add_mod(5) AND add_mod(3) AND U1/dssync);
    U1/q1_CLR <= (ds0 AND ds1);

    FDCPE_U1/dssync: FDCPE port map (U1/dssync,U1/q8,clk,ds0,'0','1');

    FDCPE_U1/q8: FDCPE port map (U1/q8,U1/q8_D,clk,'0','0','1');
    U1/q8_D <= (NOT ds0 AND NOT ds1);

    FDCPE_U1/q4: FDCPE port map (U1/q4,U1/q4_D,clk,'0','0','1');
    U1/q4_D <= NOT ((NOT U1/q2 AND NOT U1/q7));

    FDCPE_U1/q7: FDCPE port map (U1/q7,U1/q9,clk,U1/q7_CLR,'0','1');
    U1/q7_CLR <= (ds0 AND ds1);

    FDCPE_U1/q9: FDCPE port map (U1/q9,U1/q6,clk,U1/q9_CLR,'0','1');
    U1/q9_CLR <= (ds0 AND ds1);

    FDCPE_U1/q6: FDCPE port map (U1/q6,NOT tp2,clk,U1/q6_CLR,'0','1');
    U1/q6_CLR <= (ds0 AND ds1);

    FTCPE_tp2: FTCPE port map (tp2,tp2_T,clk,'0',tp2_PRE,'1');
    tp2_T <= (NOT brd_sel_16 AND iack AND lword AND add_mod(0) AND write AND
    	NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND add_mod(5) AND
    	add_mod(3) AND U1/dssync AND tp2);
    tp2_PRE <= (ds0 AND ds1);

    U5/local_reset <= ((sysreset)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(14).PIN));

    _n0009_MC.GLB <= ((ack_int)
    	OR (add_p(5) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND NOT tp2)
    	OR (NOT add_p(4) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND NOT tp2)
    	OR (add_p(3) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND NOT tp2)
    	OR (add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND NOT tp2));

    FDCPE_ack_int: FDCPE port map (ack_int,ack_int_D,clk,ds0,'0','1');
    ack_int_D <= ((ack_int AND NOT U3/r6)
    	OR (U3/r6 AND N_PZ_1042));

    FDCPE_U3/r6: FDCPE port map (U3/r6,U3/r5,clk,ds0,'0','1');

    FDCPE_U3/r5: FDCPE port map (U3/r5,NOT iackin,clk,ds0,'0','1');

    N_PZ_1042 <= (NOT iack AND U3/r4)
    	XOR ((add_p(1) AND NOT iack AND U3/r4 AND NOT int_lev(1))
    	OR (NOT add_p(1) AND NOT iack AND U3/r4 AND int_lev(1))
    	OR (add_p(0) AND NOT iack AND U3/r4 AND NOT int_lev(0))
    	OR (NOT add_p(0) AND NOT iack AND U3/r4 AND int_lev(0))
    	OR (add_p(2) AND NOT iack AND U3/r4 AND NOT int_lev(2))
    	OR (NOT add_p(2) AND NOT iack AND U3/r4 AND int_lev(2)));

    FDCPE_U3/r4: FDCPE port map (U3/r4,int_rst,clk,sysreset,'0',U3/r3);

    FDCPE_int_rst: FDCPE port map (int_rst,int_rst_D,clk,sysreset,'0','1');
    int_rst_D <= ((int_rst AND NOT dtack_int)
    	OR (sff(4) AND NOT dtack_int AND U5/int_ena_sff)
    	OR (NOT dtack_int AND U5/int_ena_sff AND sff(3))
    	OR (NOT dtack_int AND U5/int_ena_sff AND sff(2))
    	OR (NOT dtack_int AND U5/int_ena_sff AND sff(1))
    	OR (NOT dtack_int AND U5/int_ena_sff AND sff(0))
    	OR (NOT dtack_int AND spaf(4) AND U5/int_ena_spaf)
    	OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(3))
    	OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(2))
    	OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(1))
    	OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(0))
    	OR (NOT dtack_int AND U5/int_ena_mdone AND U5/mem_done_reg)
    	OR (NOT dtack_int AND U5/int_ena_rosw AND U5/ros_waiting_reg));

    FDCPE_dtack_int: FDCPE port map (dtack_int,dtack_int_D,clk,ds0,'0','1');
    dtack_int_D <= ((N_PZ_1042 AND U3/r7)
    	OR (dtack_int AND NOT U3/r7));

    FDCPE_U3/r7: FDCPE port map (U3/r7,U3/r6,clk,ds0,'0','1');

    FTCPE_U5/int_ena_sff: FTCPE port map (U5/int_ena_sff,U5/int_ena_sff_T,clk,U5/local_reset,'0','1');
    U5/int_ena_sff_T <= ((int_rst AND U5/int_ena_sff)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_sff AND NOT db(1).PIN)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_sff AND
    	db(1).PIN));

    FTCPE_U5/int_ena_spaf: FTCPE port map (U5/int_ena_spaf,U5/int_ena_spaf_T,clk,U5/local_reset,'0','1');
    U5/int_ena_spaf_T <= ((int_rst AND U5/int_ena_spaf)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_spaf AND NOT db(0).PIN)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_spaf AND
    	db(0).PIN));

    FTCPE_U5/int_ena_mdone: FTCPE port map (U5/int_ena_mdone,U5/int_ena_mdone_T,clk,U5/local_reset,'0','1');
    U5/int_ena_mdone_T <= ((int_rst AND U5/int_ena_mdone)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_mdone AND NOT db(2).PIN)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_mdone AND
    	db(2).PIN));

    FDCPE_U5/mem_done_reg: FDCPE port map (U5/mem_done_reg,U5/mem_done_reg_D,clk,U5/local_reset,'0','1');
    U5/mem_done_reg_D <= ((mem_done AND NOT U5/mem_d0)
    	OR (NOT int_rst AND U5/mem_done_reg AND mem_done AND
    	U5/mem_d0));

    FDCPE_U5/mem_d0: FDCPE port map (U5/mem_d0,mem_done,clk,U5/local_reset,'0','1');

    FTCPE_U5/int_ena_rosw: FTCPE port map (U5/int_ena_rosw,U5/int_ena_rosw_T,clk,U5/local_reset,'0','1');
    U5/int_ena_rosw_T <= ((int_rst AND U5/int_ena_rosw)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_rosw AND NOT db(3).PIN)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_rosw AND
    	db(3).PIN));

    FDCPE_U5/ros_waiting_reg: FDCPE port map (U5/ros_waiting_reg,U5/ros_waiting_reg_D,clk,U5/local_reset,'0','1');
    U5/ros_waiting_reg_D <= ((ros_waiting AND NOT U5/ros_w0)
    	OR (NOT int_rst AND U5/ros_waiting_reg AND ros_waiting AND
    	U5/ros_w0));

    FDCPE_U5/ros_w0: FDCPE port map (U5/ros_w0,ros_waiting,clk,U5/local_reset,'0','1');

    FDCPE_U3/r3: FDCPE port map (U3/r3,ds0,clk,sysreset,'0','1');

    db(5) <= ((ack_int AND U5/int_vect(5))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(5))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_lev(0))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND flash_ena_5_rosmem)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(0))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND qpll_locked)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(5))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(3)));FDCPE_int_lev0: FDCPE port map (int_lev(0),db(5).PIN,clk,'0',U5/local_reset,int_lev_CE(0));
    int_lev_CE(0) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_int_lev1: FDCPE port map (int_lev(1),db(6).PIN,clk,U5/local_reset,'0',int_lev_CE(1));
    int_lev_CE(1) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_int_lev2: FDCPE port map (int_lev(2),db(7).PIN,clk,U5/local_reset,'0',int_lev_CE(2));
    int_lev_CE(2) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    db(10) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(1))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(2))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/not_sel_tim_reg)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/cclk_freq(0))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sel_tim_clk(1))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(1)));FDCPE_U5/cclk_freq0: FDCPE port map (U5/cclk_freq(0),db(10).PIN,clk,U5/local_reset,'0',N_PZ_944);

    db(12) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(3))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(4))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/cclk_freq(2))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(3)));FDCPE_U5/cclk_freq2: FDCPE port map (U5/cclk_freq(2),db(12).PIN,clk,'0',U5/local_reset,N_PZ_944);

    FTCPE_U5/cclk_counter0: FTCPE port map (U5/cclk_counter(0),'0',clk,U5/local_reset,'0','1');

    FTCPE_U5/cclk_counter4: FTCPE port map (U5/cclk_counter(4),U5/cclk_counter_T(4),clk,U5/local_reset,'0','1');
    U5/cclk_counter_T(4) <= (U5/cclk_counter(0) AND U5/cclk_counter(1) AND
    	U5/cclk_counter(2) AND U5/cclk_counter(3));

    FTCPE_U5/cclk_counter1: FTCPE port map (U5/cclk_counter(1),U5/cclk_counter(0),clk,U5/local_reset,'0','1');

    FTCPE_U5/cclk_counter2: FTCPE port map (U5/cclk_counter(2),U5/cclk_counter_T(2),clk,U5/local_reset,'0','1');
    U5/cclk_counter_T(2) <= (U5/cclk_counter(0) AND U5/cclk_counter(1));

    FTCPE_U5/cclk_counter3: FTCPE port map (U5/cclk_counter(3),U5/cclk_counter_T(3),clk,U5/local_reset,'0','1');
    U5/cclk_counter_T(3) <= (U5/cclk_counter(0) AND U5/cclk_counter(1) AND
    	U5/cclk_counter(2));

    FDCPE_cclk1: FDCPE port map (cclk(1),cclk_D(1),clk,'0','0','1');
    cclk_D(1) <= (N_PZ_971 AND fpga_done(1));

    FDCPE_cclk2: FDCPE port map (cclk(2),cclk_D(2),clk,'0','0','1');
    cclk_D(2) <= (N_PZ_971 AND fpga_done(2));

    FDCPE_cclk3: FDCPE port map (cclk(3),cclk_D(3),clk,'0','0','1');
    cclk_D(3) <= (N_PZ_971 AND fpga_done(3));

    FDCPE_cclk4: FDCPE port map (cclk(4),cclk_D(4),clk,'0','0','1');
    cclk_D(4) <= (N_PZ_971 AND fpga_done(4));

    cscr_p(0) <= (NOT brd_sel_16 AND NOT add_p(8) AND NOT add_p(7) AND NOT add_p(6));

    cscr_p(1) <= (NOT brd_sel_16 AND NOT add_p(8) AND NOT add_p(7) AND add_p(6));

    cscr_p(2) <= (NOT brd_sel_16 AND NOT add_p(8) AND add_p(7) AND NOT add_p(6));

    cscr_p(3) <= (NOT brd_sel_16 AND NOT add_p(8) AND add_p(7) AND add_p(6));

    cscr_p(4) <= (NOT brd_sel_16 AND add_p(8) AND NOT add_p(7) AND NOT add_p(6));

    cscr_p(5) <= (NOT brd_sel_16 AND add_p(8) AND NOT add_p(7) AND add_p(6));

    cscr_p(6) <= (NOT brd_sel_16 AND add_p(8) AND add_p(7) AND NOT add_p(6));

    cspare_8 <= NOT ('0');

    cspare_9 <= NOT ('0');

    db_I(15) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(7));

    FDCPE_U5/int_vect7: FDCPE port map (U5/int_vect(7),db(15).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(7));
    U5/int_vect_CE(7) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    db_I(1) <= ((ack_int AND U5/int_vect(1))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(1))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_sff)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(1))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(1))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND i2c_ce_1wire)
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fl_vme(1))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(1))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(1))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND mem_done));

    FDCPE_i2c_ce_1wire: FDCPE port map (i2c_ce_1wire,db(1).PIN,clk,U5/local_reset,'0',N_PZ_953);

    N_PZ_953 <= (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4);

    FDCPE_fpga_init1: FDCPE port map (fpga_init(1),db(1).PIN,clk,U5/local_reset,'0',N_PZ_944);

    FDCPE_U5/flash_enable1: FDCPE port map (U5/flash_enable(1),U5/flash_enable_D(1),clk,U5/local_reset,'0','1');
    U5/flash_enable_D(1) <= ((U5/flash_enable(1) AND N_PZ_1032)
    	OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(1).PIN));

    N_PZ_1032 <= (NOT flash_ena_5_rosmem AND NOT U5/flash_enable(4))
    	XOR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND
    	NOT flash_ena_5_rosmem AND NOT U5/flash_enable(4));

    FDCPE_flash_ena_5_rosmem: FDCPE port map (flash_ena_5_rosmem,flash_ena_5_rosmem_D,clk,U5/local_reset,'0','1');
    flash_ena_5_rosmem_D <= ((NOT add_p(1) AND flash_ena_5_rosmem)
    	OR (add_p(0) AND flash_ena_5_rosmem)
    	OR (NOT N_PZ_941 AND flash_ena_5_rosmem)
    	OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND NOT db(1).PIN AND
    	NOT db(0).PIN AND NOT db(2).PIN AND NOT db(3).PIN AND NOT db(4).PIN AND db(5).PIN));

    FDCPE_U5/flash_enable4: FDCPE port map (U5/flash_enable(4),U5/flash_enable_D(4),clk,U5/local_reset,'0','1');
    U5/flash_enable_D(4) <= ((NOT add_p(1) AND U5/flash_enable(4))
    	OR (add_p(0) AND U5/flash_enable(4))
    	OR (NOT N_PZ_941 AND U5/flash_enable(4))
    	OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND NOT db(1).PIN AND
    	NOT db(0).PIN AND NOT db(2).PIN AND NOT db(3).PIN AND db(4).PIN AND NOT db(5).PIN));

    FDCPE_fl_vme1: FDCPE port map (fl_vme(1),db(1).PIN,clk,'0',U5/local_reset,fl_vme_CE(1));
    fl_vme_CE(1) <= (NOT add_p(1) AND add_p(0) AND N_PZ_941);

    db(9) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(0))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(1))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(4))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT sel_tim_p)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sel_tim_clk(0))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(0)));FDCPE_U5/int_vect1: FDCPE port map (U5/int_vect(1),db(9).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(1));
    U5/int_vect_CE(1) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_U5/tdi_bits1: FDCPE port map (U5/tdi_bits(1),U5/tdi_bits_D(1),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(1) <= ((db(1).PIN AND N_PZ_945)
    	OR (U5/tdi_bits(1) AND NOT N_PZ_945 AND NOT U5/jtag_shift)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(2) AND U5/jtag_shift));

    N_PZ_945 <= (add_p(1) AND add_p(0) AND N_PZ_941);

    FDCPE_U5/tdi_bits2: FDCPE port map (U5/tdi_bits(2),U5/tdi_bits_D(2),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(2) <= ((db(2).PIN AND N_PZ_945)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(2) AND NOT U5/jtag_shift)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(3) AND U5/jtag_shift));

    FDCPE_U5/tdi_bits3: FDCPE port map (U5/tdi_bits(3),U5/tdi_bits_D(3),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(3) <= ((db(3).PIN AND N_PZ_945)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(3) AND NOT U5/jtag_shift)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(4) AND U5/jtag_shift));

    FDCPE_U5/tdi_bits4: FDCPE port map (U5/tdi_bits(4),U5/tdi_bits_D(4),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(4) <= ((db(4).PIN AND N_PZ_945)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(4) AND NOT U5/jtag_shift)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(5) AND U5/jtag_shift));

    FDCPE_U5/tdi_bits5: FDCPE port map (U5/tdi_bits(5),U5/tdi_bits_D(5),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(5) <= ((db(5).PIN AND N_PZ_945)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(5) AND NOT U5/jtag_shift)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(6) AND U5/jtag_shift));

    FDCPE_U5/tdi_bits6: FDCPE port map (U5/tdi_bits(6),U5/tdi_bits_D(6),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(6) <= ((db(6).PIN AND N_PZ_945)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(6) AND NOT U5/jtag_shift)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(7) AND U5/jtag_shift));

    FDCPE_U5/tdi_bits7: FDCPE port map (U5/tdi_bits(7),U5/tdi_bits_D(7),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(7) <= ((db(7).PIN AND N_PZ_945)
    	OR (NOT N_PZ_945 AND U5/tdi_bits(7) AND NOT U5/jtag_shift));

    FDCPE_U5/jtag_shift: FDCPE port map (U5/jtag_shift,U5/jtag_shift_D,clk,U5/local_reset,'0','1');
    U5/jtag_shift_D <= NOT (((NOT U5/jtag_shift AND NOT U5/state_FFD3)
    	OR (U5/state_FFD3 AND NOT U5/state_FFD2)
    	OR (U5/state_FFD2 AND U5/state_FFD1)));

    FDCPE_U5/state_FFD3: FDCPE port map (U5/state_FFD3,U5/state_FFD3_D,clk,U5/local_reset,'0','1');
    U5/state_FFD3_D <= ((NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
    	U5/state_FFD2 AND NOT U5/state_FFD1)
    	OR (U5/state_FFD3 AND U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	NOT U5/bits_to_send(0) AND NOT U5/bits_to_send(1) AND NOT U5/bits_to_send(2) AND
    	NOT U5/bits_to_send(3)));

    FDCPE_U5/state_FFD2: FDCPE port map (U5/state_FFD2,U5/state_FFD2_D,clk,U5/local_reset,'0','1');
    U5/state_FFD2_D <= NOT (((U5/cclk_counter(4) AND NOT U5/state_FFD2)
    	OR (U5/state_FFD3 AND U5/state_FFD1)
    	OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1)));

    FDCPE_U5/state_FFD1: FDCPE port map (U5/state_FFD1,U5/state_FFD1_D,clk,U5/local_reset,'0','1');
    U5/state_FFD1_D <= ((NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
    	U5/state_FFD1)
    	OR (U5/state_FFD3 AND U5/state_FFD2 AND NOT U5/state_FFD1)
    	OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/state_FFD1)
    	OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/jtag_start));

    FDCPE_U5/jtag_start: FDCPE port map (U5/jtag_start,U5/jtag_start_D,clk,U5/local_reset,'0','1');
    U5/jtag_start_D <= ((N_PZ_945)
    	OR (U5/jtag_start AND NOT U5/jtag_end));

    FDCPE_U5/jtag_end: FDCPE port map (U5/jtag_end,U5/jtag_end_D,clk,U5/local_reset,'0','1');
    U5/jtag_end_D <= NOT (((U5/state_FFD3 AND NOT U5/state_FFD2)
    	OR (NOT U5/state_FFD3 AND NOT U5/jtag_end)
    	OR (NOT U5/state_FFD1 AND NOT U5/jtag_end)
    	OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND U5/jtag_start)));

    FTCPE_U5/bits_to_send0: FTCPE port map (U5/bits_to_send(0),U5/bits_to_send_T(0),clk,U5/local_reset,'0','1');
    U5/bits_to_send_T(0) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND
    	U5/bits_to_send(0))
    	OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
    	U5/state_FFD2 AND NOT U5/state_FFD1)
    	OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	U5/bits_to_send(0) AND NOT U5/jtag_num_bits(0))
    	OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	NOT U5/bits_to_send(0) AND U5/jtag_num_bits(0)));

    FDCPE_U5/jtag_num_bits0: FDCPE port map (U5/jtag_num_bits(0),db(9).PIN,clk,U5/local_reset,'0',N_PZ_945);

    FTCPE_U5/bits_to_send1: FTCPE port map (U5/bits_to_send(1),U5/bits_to_send_T(1),clk,U5/local_reset,'0','1');
    U5/bits_to_send_T(1) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND
    	U5/bits_to_send(1))
    	OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	U5/bits_to_send(1) AND NOT U5/jtag_num_bits(1))
    	OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
    	U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/bits_to_send(0))
    	OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	NOT U5/bits_to_send(1) AND U5/jtag_num_bits(1)));

    FDCPE_U5/jtag_num_bits1: FDCPE port map (U5/jtag_num_bits(1),db(10).PIN,clk,U5/local_reset,'0',N_PZ_945);

    FTCPE_U5/bits_to_send2: FTCPE port map (U5/bits_to_send(2),U5/bits_to_send_T(2),clk,U5/local_reset,'0','1');
    U5/bits_to_send_T(2) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND
    	U5/bits_to_send(2))
    	OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	U5/bits_to_send(2) AND NOT U5/jtag_num_bits(2))
    	OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	NOT U5/bits_to_send(2) AND U5/jtag_num_bits(2))
    	OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
    	U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/bits_to_send(0) AND
    	NOT U5/bits_to_send(1)));

    FDCPE_U5/jtag_num_bits2: FDCPE port map (U5/jtag_num_bits(2),db(11).PIN,clk,U5/local_reset,'0',N_PZ_945);

    FTCPE_U5/bits_to_send3: FTCPE port map (U5/bits_to_send(3),U5/bits_to_send_T(3),clk,U5/local_reset,'0','1');
    U5/bits_to_send_T(3) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND
    	U5/bits_to_send(3))
    	OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	U5/bits_to_send(3) AND NOT U5/jtag_num_bits(3))
    	OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
    	NOT U5/bits_to_send(3) AND U5/jtag_num_bits(3))
    	OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
    	U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/bits_to_send(0) AND
    	NOT U5/bits_to_send(1) AND NOT U5/bits_to_send(2)));

    FDCPE_U5/jtag_num_bits3: FDCPE port map (U5/jtag_num_bits(3),db(12).PIN,clk,U5/local_reset,'0',N_PZ_945);

    FDCPE_U5/tdo_bits1: FDCPE port map (U5/tdo_bits(1),U5/tdo_bits_D(1),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(1) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(2))
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(1)));

    FDCPE_U5/tdo_bits2: FDCPE port map (U5/tdo_bits(2),U5/tdo_bits_D(2),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(2) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(3))
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(2)));

    FDCPE_U5/tdo_bits3: FDCPE port map (U5/tdo_bits(3),U5/tdo_bits_D(3),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(3) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(4))
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(3)));

    FDCPE_U5/tdo_bits4: FDCPE port map (U5/tdo_bits(4),U5/tdo_bits_D(4),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(4) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(5))
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(4)));

    FDCPE_U5/tdo_bits5: FDCPE port map (U5/tdo_bits(5),U5/tdo_bits_D(5),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(5) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(6))
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(5)));

    FDCPE_U5/tdo_bits6: FDCPE port map (U5/tdo_bits(6),U5/tdo_bits_D(6),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(6) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(7))
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(6)));

    FDCPE_U5/tdo_bits7: FDCPE port map (U5/tdo_bits(7),U5/tdo_bits_D(7),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(7) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_reg)
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(7)));

    FDCPE_U5/tdo_reg: FDCPE port map (U5/tdo_reg,U5/tdo_reg_D,clk,U5/local_reset,'0','1');
    U5/tdo_reg_D <= NOT (((U5/state_FFD3 AND NOT U5/state_FFD2)
    	OR (U5/state_FFD3 AND NOT U5/tdo_reg)
    	OR (NOT U5/tdo_reg AND NOT U5/_n007019)
    	OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
    	U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/_n007019)));

    U5/_n007019 <= ((NOT U5/cclk_counter(4) AND U5/flash_enable(1) AND
    	U5/state_FFD2 AND NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(1))
    	OR (NOT U5/cclk_counter(4) AND flash_ena_5_rosmem AND
    	U5/state_FFD2 AND NOT U5/state_FFD1 AND flash_tdo_p(5) AND N_PZ_957)
    	OR (NOT U5/cclk_counter(4) AND U5/flash_enable(4) AND
    	U5/state_FFD2 AND NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(4))
    	OR (NOT U5/cclk_counter(4) AND U5/state_FFD2 AND
    	NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(0) AND U5/flash_enable(0))
    	OR (NOT U5/cclk_counter(4) AND U5/state_FFD2 AND
    	NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(2) AND U5/flash_enable(2))
    	OR (NOT U5/cclk_counter(4) AND U5/state_FFD2 AND
    	NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(3) AND U5/flash_enable(3)));

    N_PZ_957 <= ((fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2))
    	OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2)));

    db(0) <= ((ack_int AND U5/int_vect(0))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(0))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_spaf)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(0))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(0))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND i2c_ce_gol)
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fl_vme(0))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(0))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(0))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND ros_waiting));FDCPE_fl_vme0: FDCPE port map (fl_vme(0),db(0).PIN,clk,'0',U5/local_reset,fl_vme_CE(0));
    fl_vme_CE(0) <= (NOT add_p(1) AND add_p(0) AND N_PZ_941);

    db(2) <= ((ack_int AND U5/int_vect(2))
    	OR (NOT fpga_done(0) AND NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND
    	NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(2))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_mdone)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(2))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(2))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND gol_off)
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fl_vme(2))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(2))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(2)));FDCPE_fl_vme2: FDCPE port map (fl_vme(2),db(2).PIN,clk,'0',U5/local_reset,fl_vme_CE(2));
    fl_vme_CE(2) <= (NOT add_p(1) AND add_p(0) AND N_PZ_941);

    FDCPE_U5/flash_enable0: FDCPE port map (U5/flash_enable(0),U5/flash_enable_D(0),clk,U5/local_reset,'0','1');
    U5/flash_enable_D(0) <= ((N_PZ_1032 AND U5/flash_enable(0))
    	OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(0).PIN));

    FDCPE_U5/flash_enable2: FDCPE port map (U5/flash_enable(2),U5/flash_enable_D(2),clk,U5/local_reset,'0','1');
    U5/flash_enable_D(2) <= ((N_PZ_1032 AND U5/flash_enable(2))
    	OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(2).PIN));

    FDCPE_U5/flash_enable3: FDCPE port map (U5/flash_enable(3),U5/flash_enable_D(3),clk,U5/local_reset,'0','1');
    U5/flash_enable_D(3) <= ((N_PZ_1032 AND U5/flash_enable(3))
    	OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(3).PIN));

    db_I(3) <= ((ack_int AND U5/int_vect(3))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(3))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_rosw)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(3))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(3))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND gol_ready)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(3))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(3))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(1)));

    FDCPE_fpga_init3: FDCPE port map (fpga_init(3),db(3).PIN,clk,U5/local_reset,'0',N_PZ_944);

    FDCPE_U5/int_vect3: FDCPE port map (U5/int_vect(3),db(11).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(3));
    U5/int_vect_CE(3) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    db_I(4) <= ((ack_int AND U5/int_vect(4))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(4))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_rst)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(4))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(4))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/qpll_error_reg)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(4))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(4))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(2)));

    FDCPE_fpga_init4: FDCPE port map (fpga_init(4),db(4).PIN,clk,U5/local_reset,'0',N_PZ_944);

    FDCPE_U5/int_vect4: FDCPE port map (U5/int_vect(4),db(12).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(4));
    U5/int_vect_CE(4) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_U5/qpll_error_reg: FDCPE port map (U5/qpll_error_reg,U5/qpll_error_reg_D,clk,U5/local_reset,'0','1');
    U5/qpll_error_reg_D <= NOT (((N_PZ_953 AND NOT db(4).PIN)
    	OR (NOT N_PZ_953 AND NOT U5/qpll_error_reg AND NOT qpll_error)));

    db_I(8) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tms)
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(0))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tdi_reg)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(3))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/jtag_end)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/ena_evres));

    FDCPE_U5/ena_evres: FDCPE port map (U5/ena_evres,db(8).PIN,clk,U5/local_reset,'0',U5/ena_evres_CE);
    U5/ena_evres_CE <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4);

    FDCPE_U5/flash_tdi_reg: FDCPE port map (U5/flash_tdi_reg,db(8).PIN,clk,U5/local_reset,'0',U5/flash_tdi_reg_CE);
    U5/flash_tdi_reg_CE <= (add_p(1) AND NOT add_p(0) AND N_PZ_941);

    FDCPE_U5/flash_tms: FDCPE port map (U5/flash_tms,db(8).PIN,clk,U5/local_reset,'0',N_PZ_945);

    FDCPE_U5/int_vect0: FDCPE port map (U5/int_vect(0),db(8).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(0));
    U5/int_vect_CE(0) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_dtack_led: FDCPE port map (dtack_led,NOT ULED2/q1,clk_slow,'0',NOT N_PZ_930,'1');

    FTCPE_ULED2/q1: FTCPE port map (ULED2/q1,ULED2/q1_T,clk,ULED2/q3,'0','1');
    ULED2/q1_T <= ((dtack_int AND NOT ULED2/q1)
    	OR (NOT ULED2/q1 AND U1/q444)
    	OR (NOT flash_ena_5_rosmem AND NOT ULED2/q1 AND dtack_mem));

    FDCPE_U1/q444: FDCPE port map (U1/q444,U1/q44,clk,'0','0','1');

    FDCPE_U1/q44: FDCPE port map (U1/q44,U1/q4,clk,'0','0','1');

    FDCPE_ULED2/q3: FDCPE port map (ULED2/q3,NOT dtack_led,clk_slow,NOT N_PZ_930,'0','1');

    N_PZ_930 <= (NOT U5/reset_1 AND NOT U5/reset_2);

    FDCPE_U5/reset_1: FDCPE port map (U5/reset_1,U5/reset_1_D,clk,'0','0','1');
    U5/reset_1_D <= ((sysreset)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(14).PIN));

    FDCPE_U5/reset_2: FDCPE port map (U5/reset_2,U5/reset_1,clk,'0','0','1');

    dtack_p <= NOT (((NOT dtack_int AND flash_ena_5_rosmem AND NOT U1/q444)
    	OR (NOT dtack_int AND NOT dtack_mem AND NOT U1/q444)));

    enw_vf <= i2c_int_p;

    enw_x <= (U1/q2 AND NOT U1/q4);

    etr_vf <= brd_sel_24;

    FTCPE_etr_x: FTCPE port map (etr_x,etr_x_T,clk,'0',etr_x_PRE,'1');
    etr_x_T <= (NOT brd_sel_16 AND iack AND lword AND add_mod(0) AND write AND
    	NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND add_mod(5) AND
    	add_mod(3) AND U1/dssync AND etr_x);
    etr_x_PRE <= (ds0 AND ds1);

    FDCPE_fl_tdo: FDCPE port map (fl_tdo,fl_tdo_D,clk,NOT N_PZ_930,'0','1');
    fl_tdo_D <= NOT (((fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND
    	NOT flash_tdo_p(3))
    	OR (fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND
    	NOT flash_tdo_p(2))
    	OR (NOT fl_vme(1) AND NOT flash_tdo_p(5) AND fl_vme(0) AND
    	fl_vme(2))
    	OR (NOT fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND
    	NOT flash_tdo_p(1))
    	OR (NOT fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND
    	NOT flash_tdo_p(4))
    	OR (NOT fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND
    	NOT flash_tdo_p(0))
    	OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND
    	fl_switch(0) AND fl_vme(0) AND NOT flash_tdo_p(3))
    	OR (NOT flash_tdo_p(5) AND fl_switch(2) AND NOT fl_switch(1) AND
    	fl_switch(0) AND fl_vme(0) AND fl_vme(2))
    	OR (fl_vme(1) AND fl_switch(2) AND NOT fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(4))
    	OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(2))
    	OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
    	fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(1))
    	OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(0))));

    flash_tck_p(0) <= ((N_PZ_957 AND U5/flash_enable(0) AND U5/flash_tck_reg)
    	OR (N_PZ_957 AND U5/flash_enable(0) AND U5/flash_tck)
    	OR (NOT fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r)
    	OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));

    FDCPE_fl_tck_r: FDCPE port map (fl_tck_r,fl_tck,clk,NOT N_PZ_930,'0','1');

    db(6) <= ((ack_int AND U5/int_vect(6))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(6))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_lev(1))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tck_reg)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(1))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/qpll_hasunlock_reg)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(6))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(4)));FDCPE_U5/flash_tck_reg: FDCPE port map (U5/flash_tck_reg,db(6).PIN,clk,U5/local_reset,'0',U5/flash_tck_reg_CE);
    U5/flash_tck_reg_CE <= (add_p(1) AND NOT add_p(0) AND N_PZ_941);

    FDCPE_U5/flash_tck: FDCPE port map (U5/flash_tck,U5/flash_tck_D,clk,U5/local_reset,'0','1');
    U5/flash_tck_D <= ((NOT U5/state_FFD3 AND U5/state_FFD2 AND NOT U5/state_FFD1)
    	OR (U5/state_FFD3 AND U5/state_FFD2 AND U5/state_FFD1 AND
    	U5/flash_tck));

    flash_tck_p(1) <= ((NOT fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r)
    	OR (U5/flash_enable(1) AND fl_vme(1) AND NOT fl_vme(0) AND
    	fl_vme(2) AND U5/flash_tck_reg)
    	OR (U5/flash_enable(1) AND fl_vme(1) AND NOT fl_vme(0) AND
    	fl_vme(2) AND U5/flash_tck)
    	OR (U5/flash_enable(1) AND fl_vme(1) AND fl_switch(2) AND
    	fl_switch(1) AND NOT fl_switch(0) AND fl_vme(2) AND U5/flash_tck_reg)
    	OR (U5/flash_enable(1) AND fl_vme(1) AND fl_switch(2) AND
    	fl_switch(1) AND NOT fl_switch(0) AND fl_vme(2) AND U5/flash_tck)
    	OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
    	fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));

    flash_tck_p(2) <= ((N_PZ_957 AND U5/flash_enable(2) AND U5/flash_tck_reg)
    	OR (N_PZ_957 AND U5/flash_enable(2) AND U5/flash_tck)
    	OR (fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r)
    	OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));

    flash_tck_p(3) <= ((N_PZ_957 AND U5/flash_enable(3) AND U5/flash_tck_reg)
    	OR (N_PZ_957 AND U5/flash_enable(3) AND U5/flash_tck)
    	OR (fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r)
    	OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND
    	fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));

    flash_tck_p(4) <= ((U5/flash_enable(4) AND N_PZ_957 AND U5/flash_tck_reg)
    	OR (U5/flash_enable(4) AND N_PZ_957 AND U5/flash_tck)
    	OR (NOT fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND fl_tck_r)
    	OR (fl_vme(1) AND fl_switch(2) AND NOT fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));

    flash_tck_p(5) <= ((flash_ena_5_rosmem AND N_PZ_957 AND U5/flash_tck_reg)
    	OR (flash_ena_5_rosmem AND N_PZ_957 AND U5/flash_tck)
    	OR (NOT fl_vme(1) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r)
    	OR (fl_vme(1) AND fl_switch(2) AND NOT fl_switch(1) AND
    	fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));

    flash_tdi_p <= NOT (((NOT fl_tdi_r AND NOT N_PZ_1002)
    	OR (fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND
    	NOT U5/flash_tdi_reg AND NOT U5/tdi_bits(0))
    	OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(2) AND NOT U5/flash_tdi_reg AND NOT U5/tdi_bits(0))));

    FDCPE_U5/tdi_bits0: FDCPE port map (U5/tdi_bits(0),U5/tdi_bits_D(0),clk,U5/local_reset,'0','1');
    U5/tdi_bits_D(0) <= ((db(0).PIN AND N_PZ_945)
    	OR (U5/tdi_bits(1) AND NOT N_PZ_945 AND U5/jtag_shift)
    	OR (NOT N_PZ_945 AND NOT U5/jtag_shift AND U5/tdi_bits(0)));

    FDCPE_fl_tdi_r: FDCPE port map (fl_tdi_r,fl_tdi,clk,NOT N_PZ_930,'0','1');

    N_PZ_1002 <= ((fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2))
    	OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(2)));

    flash_tms_p <= NOT (((NOT N_PZ_1002 AND NOT fl_tms_r)
    	OR (fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND
    	NOT U5/flash_tms AND NOT U5/flash_tms_reg)
    	OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND
    	NOT fl_switch(0) AND fl_vme(2) AND NOT U5/flash_tms AND NOT U5/flash_tms_reg)));

    db(7) <= ((ack_int AND U5/int_vect(7))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(7))
    	OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_lev(2))
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tms_reg)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(2))
    	OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/gol_notready_reg)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(7)));FDCPE_U5/flash_tms_reg: FDCPE port map (U5/flash_tms_reg,db(7).PIN,clk,U5/local_reset,'0',U5/flash_tms_reg_CE);
    U5/flash_tms_reg_CE <= (add_p(1) AND NOT add_p(0) AND N_PZ_941);

    FDCPE_fl_tms_r: FDCPE port map (fl_tms_r,fl_tms,clk,NOT N_PZ_930,'0','1');

    FDCPE_fpga_init0: FDCPE port map (fpga_init(0),db(0).PIN,clk,U5/local_reset,'0',N_PZ_944);

    FDCPE_fpga_init2: FDCPE port map (fpga_init(2),db(2).PIN,clk,U5/local_reset,'0',N_PZ_944);

    g245_p <= (NOT U1/q1 AND tp2 AND NOT ack_int AND NOT flash_ena_5_rosmem AND
    	g245_mem);

    FDCPE_gol_off: FDCPE port map (gol_off,db(2).PIN,clk,'0',U5/local_reset,N_PZ_953);

    gol_reset <= NOT (((NOT N_PZ_930)
    	OR (N_PZ_953 AND db(11).PIN)));

    FDCPE_i2c_ce_gol: FDCPE port map (i2c_ce_gol,i2c_ce_gol_D,clk,U5/local_reset,'0','1');
    i2c_ce_gol_D <= ((NOT N_PZ_953 AND i2c_ce_gol)
    	OR (NOT db(1).PIN AND db(0).PIN AND N_PZ_953));

    i2c_ce_p <= NOT ((NOT add_p(5) AND add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND
    	NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6)));

    i2c_rd <= NOT ((NOT tp2 AND NOT i2c_ce_p));

    i2c_reset <= (NOT U5/reset_1 AND NOT U5/reset_2);

    i2c_wr <= NOT ((U1/q2 AND NOT U1/q4 AND NOT i2c_ce_p));

    iackout <= (iackin AND U3/r8);

    FDCPE_U3/r8: FDCPE port map (U3/r8,U3/r8_D,clk,'0',as,'1');
    U3/r8_D <= ((N_PZ_1042 AND U3/r7)
    	OR (NOT U3/r7 AND U3/r8));

    FDCPE_intrpt_led: FDCPE port map (intrpt_led,NOT ULED1/q1,clk_slow,'0',NOT N_PZ_930,'1');

    FTCPE_ULED1/q1: FTCPE port map (ULED1/q1,ULED1/q1_T,clk,ULED1/q3,'0','1');
    ULED1/q1_T <= (int_rst AND NOT ULED1/q1);

    FDCPE_ULED1/q3: FDCPE port map (ULED1/q3,NOT intrpt_led,clk_slow,NOT N_PZ_930,'0','1');

    irq(1) <= (int_rst AND int_lev(0) AND NOT int_lev(1) AND NOT int_lev(2));

    irq(2) <= (int_rst AND NOT int_lev(0) AND int_lev(1) AND NOT int_lev(2));

    irq(3) <= (int_rst AND int_lev(0) AND int_lev(1) AND NOT int_lev(2));

    irq(4) <= (int_rst AND NOT int_lev(0) AND NOT int_lev(1) AND int_lev(2));

    irq(5) <= (int_rst AND int_lev(0) AND NOT int_lev(1) AND int_lev(2));

    irq(6) <= (int_rst AND NOT int_lev(0) AND int_lev(1) AND int_lev(2));

    irq(7) <= (int_rst AND int_lev(0) AND int_lev(1) AND int_lev(2));

    ldpreg <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(11).PIN);

    mrs <= ((U5/local_reset)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(13).PIN));

    mspare_0 <= NOT ('0');

    mspare_1 <= NOT ('0');

    mspare_2 <= NOT ('0');

    mspare_3 <= NOT ('0');

    on_244 <= '0';

    prgm_fpga_p(0) <= (NOT prgm_fpga(0) AND NOT N_PZ_966);

    FDCPE_prgm_fpga0: FDCPE port map (prgm_fpga(0),prgm_fpga_D(0),clk,'0',U5/_n0041,'1');
    prgm_fpga_D(0) <= NOT (((N_PZ_944 AND NOT db(5).PIN)
    	OR (NOT N_PZ_944 AND NOT prgm_fpga(0))
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
    	U5/cuenta_prgm_0_4)));

    FTCPE_U5/cuenta_prgm_0_0: FTCPE port map (U5/cuenta_prgm_0_0,U5/cuenta_prgm_0_0_T,clk,U5/_n0041,'0','1');
    U5/cuenta_prgm_0_0_T <= NOT (((N_PZ_944 AND NOT U5/cuenta_prgm_0_0)
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
    	U5/cuenta_prgm_0_4)));

    FTCPE_U5/cuenta_prgm_0_1: FTCPE port map (U5/cuenta_prgm_0_1,U5/cuenta_prgm_0_1_T,clk,U5/_n0041,'0','1');
    U5/cuenta_prgm_0_1_T <= NOT (((N_PZ_944 AND NOT U5/cuenta_prgm_0_1)
    	OR (NOT N_PZ_944 AND NOT U5/cuenta_prgm_0_0)
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_1 AND
    	U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND U5/cuenta_prgm_0_4)));

    FTCPE_U5/cuenta_prgm_0_2: FTCPE port map (U5/cuenta_prgm_0_2,U5/cuenta_prgm_0_2_T,clk,U5/_n0041,'0','1');
    U5/cuenta_prgm_0_2_T <= NOT (((N_PZ_944 AND NOT U5/cuenta_prgm_0_2)
    	OR (NOT N_PZ_944 AND NOT U5/cuenta_prgm_0_0)
    	OR (NOT N_PZ_944 AND NOT U5/cuenta_prgm_0_1)
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_2 AND
    	U5/cuenta_prgm_0_3 AND U5/cuenta_prgm_0_4)));

    FDCPE_U5/cuenta_prgm_0_3: FDCPE port map (U5/cuenta_prgm_0_3,U5/cuenta_prgm_0_3_D,clk,U5/_n0041,'0','1');
    U5/cuenta_prgm_0_3_D <= NOT (NOT U5/cuenta_prgm_0_3
    	XOR ((N_PZ_944 AND U5/cuenta_prgm_0_3)
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND NOT U5/cuenta_prgm_0_3)
    	OR (U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND
    	U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND NOT U5/cuenta_prgm_0_4)));

    FDCPE_U5/cuenta_prgm_0_4: FDCPE port map (U5/cuenta_prgm_0_4,U5/cuenta_prgm_0_4_D,clk,U5/_n0041,'0','1');
    U5/cuenta_prgm_0_4_D <= ((NOT N_PZ_944 AND U5/cuenta_prgm_0_4)
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3));

    U5/_n0041 <= ((evcnt_res AND ena_evres_prgm)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(15).PIN AND U5/ena_rst_prgm));

    FDCPE_ena_evres_prgm: FDCPE port map (ena_evres_prgm,db(13).PIN,clk,U5/local_reset,'0',N_PZ_944);

    db(14) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(6))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/ena_rst_prgm)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND flash_tdo_p(5) AND N_PZ_957));FDCPE_U5/ena_rst_prgm: FDCPE port map (U5/ena_rst_prgm,db(14).PIN,clk,U5/local_reset,'0',N_PZ_944);

    N_PZ_966 <= (evcnt_res AND ena_evres_prgm);

    prgm_fpga_p(1) <= (NOT N_PZ_966 AND NOT prgm_fpga(1));

    FDCPE_prgm_fpga1: FDCPE port map (prgm_fpga(1),prgm_fpga_D(1),clk,'0',U5/_n0041,'1');
    prgm_fpga_D(1) <= NOT (((N_PZ_944 AND NOT db(6).PIN)
    	OR (NOT N_PZ_944 AND NOT prgm_fpga(1))
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
    	U5/cuenta_prgm_0_4)));

    prgm_fpga_p(2) <= (NOT N_PZ_966 AND NOT prgm_fpga(2));

    FDCPE_prgm_fpga2: FDCPE port map (prgm_fpga(2),prgm_fpga_D(2),clk,'0',U5/_n0041,'1');
    prgm_fpga_D(2) <= NOT (((N_PZ_944 AND NOT db(7).PIN)
    	OR (NOT N_PZ_944 AND NOT prgm_fpga(2))
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
    	U5/cuenta_prgm_0_4)));

    prgm_fpga_p(3) <= (NOT N_PZ_966 AND NOT prgm_fpga(3));

    FDCPE_prgm_fpga3: FDCPE port map (prgm_fpga(3),prgm_fpga_D(3),clk,'0',U5/_n0041,'1');
    prgm_fpga_D(3) <= NOT (((N_PZ_944 AND NOT db(8).PIN)
    	OR (NOT N_PZ_944 AND NOT prgm_fpga(3))
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
    	U5/cuenta_prgm_0_4)));

    prgm_fpga_p(4) <= (NOT N_PZ_966 AND NOT prgm_fpga(4));

    FDCPE_prgm_fpga4: FDCPE port map (prgm_fpga(4),prgm_fpga_D(4),clk,'0',U5/_n0041,'1');
    prgm_fpga_D(4) <= NOT (((N_PZ_944 AND NOT db(9).PIN)
    	OR (NOT N_PZ_944 AND NOT prgm_fpga(4))
    	OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND
    	U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
    	U5/cuenta_prgm_0_4)));

    prs <= ((U5/local_reset)
    	OR (U5/ena_evres AND evcnt_res)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(15).PIN)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(12).PIN));

    qpll_reset <= NOT (((NOT N_PZ_930)
    	OR (N_PZ_953 AND db(8).PIN)));

    reset_p <= NOT ((NOT U5/reset_1 AND NOT U5/reset_2));

    FDCPE_sel_tim_clk0: FDCPE port map (sel_tim_clk(0),db(9).PIN,clk,U5/local_reset,'0',sel_tim_clk_CE(0));
    sel_tim_clk_CE(0) <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4);

    FDCPE_sel_tim_clk1: FDCPE port map (sel_tim_clk(1),db(10).PIN,clk,U5/local_reset,'0',sel_tim_clk_CE(1));
    sel_tim_clk_CE(1) <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4);

    FDCPE_spare_led: FDCPE port map (spare_led,ULED3/q1,clk_slow,NOT N_PZ_930,'0','1');

    FTCPE_ULED3/q1: FTCPE port map (ULED3/q1,ULED3/q1_T,clk,ULED3/q3,'0','1');
    ULED3/q1_T <= (U1/q2 AND NOT U1/q4 AND NOT ULED3/q1);

    FDCPE_ULED3/q3: FDCPE port map (ULED3/q3,spare_led,clk_slow,NOT N_PZ_930,'0','1');

    tp3 <= NOT ((NOT U5/reset_1 AND NOT U5/reset_2));

    tp4 <= clk;

    vspare_0 <= NOT ((NOT U5/s_reset_1 AND NOT U5/s_reset_2));

    FDCPE_U5/s_reset_1: FDCPE port map (U5/s_reset_1,U5/s_reset_1_D,clk,'0','0','1');
    U5/s_reset_1_D <= ((U5/local_reset)
    	OR (U5/ena_evres AND evcnt_res)
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND db(15).PIN));

    FDCPE_U5/s_reset_2: FDCPE port map (U5/s_reset_2,U5/s_reset_1,clk,'0','0','1');

    vspare_1 <= NOT ('0');

    FDCPE_U5/int_vect2: FDCPE port map (U5/int_vect(2),db(10).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(2));
    U5/int_vect_CE(2) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_U5/not_sel_tim_reg: FDCPE port map (U5/not_sel_tim_reg,U5/not_sel_tim_reg_D,clk,U5/local_reset,'0','1');
    U5/not_sel_tim_reg_D <= NOT (((N_PZ_953 AND NOT db(10).PIN)
    	OR (NOT N_PZ_953 AND NOT U5/not_sel_tim_reg AND sel_tim_p)));

    FDCPE_U5/int_vect6: FDCPE port map (U5/int_vect(6),db(14).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(6));
    U5/int_vect_CE(6) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_U5/qpll_hasunlock_reg: FDCPE port map (U5/qpll_hasunlock_reg,U5/qpll_hasunlock_reg_D,clk,U5/local_reset,'0','1');
    U5/qpll_hasunlock_reg_D <= NOT (((NOT db(6).PIN AND N_PZ_953)
    	OR (NOT N_PZ_953 AND NOT U5/qpll_hasunlock_reg AND qpll_locked)));

    FDCPE_U5/gol_notready_reg: FDCPE port map (U5/gol_notready_reg,U5/gol_notready_reg_D,clk,U5/local_reset,'0','1');
    U5/gol_notready_reg_D <= NOT (((NOT db(7).PIN AND N_PZ_953)
    	OR (NOT N_PZ_953 AND gol_ready AND NOT U5/gol_notready_reg)));

    db(13) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(5))
    	OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND ena_evres_prgm)
    	OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(4)));FDCPE_U5/int_vect5: FDCPE port map (U5/int_vect(5),db(13).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(5));
    U5/int_vect_CE(5) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
    	NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
    	add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);

    FDCPE_U5/tdo_bits0: FDCPE port map (U5/tdo_bits(0),U5/tdo_bits_D(0),clk,U5/local_reset,'0','1');
    U5/tdo_bits_D(0) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(1))
    	OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(0)));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FDDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     FTDCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ****************************  Device Pin Out ****************************

    Device : XC2C384-7-PQ208

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 VCC                             105 VCCIO-3.3
      2 ds0                             106 PGND
      3 qpll_reset                      107 add_mod<4>
      4 i2c_ce_p                        108 add_mod<5>
      5 cspare_9                        109 as
      6 add_p<5>                        110 brd_sel_16
      7 add_p<4>                        111 brd_sel_24
      8 add_p<3>                        112 ds1
      9 add_p<8>                        113 dtack_mem
     10 on_244                          114 flash_tdo_p<3>
     11 VCCAUX                          115 flash_tdo_p<4>
     12 db<0>                           116 flash_tdo_p<5>
     13 GND                             117 fpga_done<4>
     14 db<8>                           118 g245_mem
     15 db<15>                          119 gol_ready
     16 db<7>                           120 iack
     17 fpga_init<1>                    121 iackin
     18 i2c_ce_1wire                    122 lword
     19 fpga_init<2>                    123 qpll_error
     20 gol_off                         124 VCC
     21 sff<2>                          125 spaf<4>
     22 db<2>                           126 write
     23 fpga_init<4>                    127 i2c_rd
     24 GND                             128 sel_tim_clk<0>
     25 db<4>                           129 GND
     26 VCCIO-3.3                       130 GND
     27 irq<5>                          131 sel_tim_clk<1>
     28 irq<4>                          132 VCCIO-3.3
     29 irq<3>                          133 VCCIO-3.3
     30 irq<2>                          134 mspare_3
     31 irq<1>                          135 PGND
     32 prgm_fpga_p<4>                  136 enw_x
     33 VCCIO-3.3                       137 mspare_2
     34 prgm_fpga_p<3>                  138 i2c_wr
     35 prgm_fpga_p<2>                  139 mspare_0
     36 prgm_fpga_p<1>                  140 irq<7>
     37 prgm_fpga_p<0>                  141 GND
     38 add_f_p<9>                      142 irq<6>
     39 add_f_p<15>                     143 dtack_p
     40 db<13>                          144 vspare_1
     41 db<5>                           145 PGND
     42 GND                             146 iackout
     43 fpga_done<1>                    147 add_hold
     44 clk_slow                        148 flash_tms_p
     45 fpga_done<0>                    149 flash_tdi_p
     46 clk                             150 add_mod<3>
     47 cclk<4>                         151 add_mod<2>
     48 cclk<3>                         152 spare_led
     49 cclk<2>                         153 intrpt_led
     50 cclk<1>                         154 dtack_led
     51 cclk<0>                         155 tp3
     52 GND                             156 GND
     53 VCC                             157 VCCIO-3.3
     54 db<3>                           158 prs
     55 db<6>                           159 mrs
     56 db<14>                          160 tp4
     57 db<12>                          161 add_p<7>
     58 PGND                            162 add_p<6>
     59 VCCIO-3.3                       163 cscr_p<0>
     60 mspare_1                        164 cscr_p<1>
     61 fl_switch<2>                    165 cscr_p<2>
     62 etr_vf                          166 cscr_p<3>
     63 etr_x                           167 cscr_p<4>
     64 ldpreg                          168 cscr_p<5>
     65 g245_p                          169 cscr_p<6>
     66 add_p<0>                        170 vspare_0
     67 add_p<1>                        171 PGND
     68 GND                             172 VCCIO-3.3
     69 add_p<2>                        173 gol_reset
     70 add_mod<0>                      174 i2c_reset
     71 add_mod<1>                      175 reset_p
     72 fl_tdo                          176 TDO
     73 flash_tck_p<0>                  177 GND
     74 flash_tck_p<1>                  178 PGND
     75 flash_tck_p<2>                  179 enw_vf
     76 flash_tck_p<3>                  180 sel_tim_p
     77 flash_tck_p<4>                  181 VCCIO-3.3
     78 flash_tck_p<5>                  182 i2c_int_p
     79 VCCIO-3.3                       183 fl_switch<1>
     80 PGND                            184 fl_switch<0>
     81 GND                             185 fpga_init<3>
     82 PGND                            186 PGND
     83 PGND                            187 db<10>
     84 db<11>                          188 db<9>
     85 spaf<3>                         189 db<1>
     86 spaf<2>                         190 GND
     87 spaf<1>                         191 fpga_done<3>
     88 spaf<0>                         192 fpga_done<2>
     89 sff<4>                          193 evcnt_res
     90 sff<3>                          194 add_f_p<14>
     91 qpll_locked                     195 add_f_p<13>
     92 VCCIO-3.3                       196 add_f_p<11>
     93 GND                             197 add_f_p<10>
     94 TDI                             198 add_f_p<12>
     95 flash_tdo_p<2>                  199 sff<1>
     96 TMS                             200 sff<0>
     97 flash_tdo_p<1>                  201 i2c_ce_gol
     98 TCK                             202 fpga_init<0>
     99 flash_tdo_p<0>                  203 cspare_8
    100 fl_tms                          204 VCCIO-3.3
    101 fl_tdi                          205 ros_waiting
    102 fl_tck                          206 sysreset
    103 tp2                             207 GND
    104 GND                             208 mem_done

    Legend :  NC  = Not Connected, unbonded pin
            PGND  = Unused I/O configured as additional Ground pin
             KPR  = Unused I/O with weak keeper (leave unconnected)
             WPU  = Unused I/O with weak pull up (leave unconnected)
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
          VCCAUX  = Power supply for JTAG pins
       VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
       VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
       VCCIO-1.8  = I/O supply voltage for LVCMOS18
       VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
            VREF  = Reference voltage for indicated input standard
           *VREF  = Reference voltage pin selected by software
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc2c384-7-PQ208
    Optimization Method                         : DENSITY
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : FPGA
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : ON
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Set Unused I/O Pin Termination              : GROUND
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Enable Input Registers                      : ON
    Function Block Fan-in Limit                 : 40
    Use DATA_GATE Attribute                     : ON
    Set Tristate Outputs to Termination Mode    : FLOAT
    Default Voltage Standard for All Outputs    : LVCMOS33
    Input Limit                                 : 40
    Pterm Limit                                 : 56