<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE Document [


<!ELEMENT Document (Net*, Globals*, Lb+)>
<!ATTLIST Document
	Version CDATA #REQUIRED
	Module CDATA #REQUIRED
	Date CDATA #REQUIRED
	Device CDATA #REQUIRED
>

<!ELEMENT Globals (InBuf*, GlblBuf*, ClkDiv*, SDot*)>

<!ELEMENT Net (Activity?)>
<!ATTLIST Net
	NNm CDATA #REQUIRED
	IoT (in | out | bidi | none) #REQUIRED
	Loc CDATA #IMPLIED
	ClkT (G | U) #IMPLIED
	SNm CDATA #IMPLIED
>

<!ELEMENT Activity EMPTY>
<!ATTLIST Activity
	Freq CDATA #IMPLIED
	DutyCycle CDATA #IMPLIED
>



<!ELEMENT InBuf (IPort, OPort*)>
<!ATTLIST InBuf
	Nm CDATA #REQUIRED
	IOS (LVTTL | LVCMOS15 | LVCMOS18 | LVCMOS25 | LVCMOS33 | HSTL_I | SSTL2_I | SSTL3_I | STRIG) #REQUIRED
	DataGate (Y | N) #REQUIRED
>

<!ELEMENT GlblBuf (IPort)>
<!ATTLIST GlblBuf
	Nm CDATA #REQUIRED
	GType (GOE | GSR | GCK | GCK2 | CDRST | GDGATE) #REQUIRED
>

<!ELEMENT ClkDiv (IPort, OPort)>
<!ATTLIST ClkDiv
	Nm CDATA #REQUIRED
	DivideBy (2 | 4 | 6 | 8 | 10 | 12 | 14 | 16) #REQUIRED
>

<!ELEMENT SDot (IPort, OPort)>
<!ATTLIST SDot
	Nm CDATA #REQUIRED
>


<!ELEMENT Lb (LbT*, Mc*, SDot*)>
<!ATTLIST Lb
	Nm CDATA #REQUIRED
>

<!ELEMENT LbT (OPort, IPort+)>
<!ATTLIST LbT
	Nm CDATA #REQUIRED
	PtT (XBR_A | XBR_B | XBR_C | XBR_CT | XBR_CT_X) #REQUIRED
>

<!ELEMENT Mc (RMux*, ClkMux?, XorMux?, OeMux?, FbMux*, InBuf?, OutBuf?, DFlop?, Or?, SDot*)>
<!ATTLIST Mc
	Nm CDATA #REQUIRED
>

<!ELEMENT Or (OPort, IPort+)>
<!ATTLIST Or
	Nm CDATA #REQUIRED
>

<!ELEMENT ClkMux (IPort, OPort)>
<!ATTLIST ClkMux
	Nm CDATA #REQUIRED
	Rate (1 | 2) #IMPLIED
>

<!ELEMENT RMux (IPort)>
<!ATTLIST RMux
	Nm CDATA #REQUIRED
>

<!ELEMENT OeMux (IPort)>
<!ATTLIST OeMux
	Nm CDATA #REQUIRED
>

<!ELEMENT XorMux (IPort)>
<!ATTLIST XorMux
	Nm CDATA #REQUIRED
>

<!ELEMENT FbMux (IPort)>
<!ATTLIST FbMux
	Nm CDATA #REQUIRED
>

<!ELEMENT OutBuf (IPort, OPort, CntlPort*)>
<!ATTLIST OutBuf
	Nm CDATA #REQUIRED
	IOS (LVTTL | LVCMOS15 | LVCMOS18 | LVCMOS25 | LVCMOS33 | HSTL_I | SSTL2_I | SSTL3_I | STRIG) #REQUIRED
>

<!ELEMENT DFlop (FlopPort+)>
<!ATTLIST DFlop
	Nm CDATA #REQUIRED
>


<!ELEMENT FlopPort EMPTY>
<!ATTLIST FlopPort
	NNm CDATA #REQUIRED
	Port (D | CLK | Q | RST | PST | CE) #REQUIRED
>

<!ELEMENT IPort EMPTY>
<!ATTLIST IPort
	NNm CDATA #REQUIRED
>

<!ELEMENT OPort EMPTY>
<!ATTLIST OPort
	NNm CDATA #REQUIRED
>

<!ELEMENT CntlPort EMPTY>
<!ATTLIST CntlPort
	NNm CDATA #REQUIRED
>
]>
<Document Date="Dec 04 17:41:36 2009" Device="XC2C384-7PQ208" Module="rosvme" Version="2"><Net IoT="none" NNm="FB3_10_Q" SNm="U5/ros_waiting_reg_MC.Q"/><Net IoT="none" NNm="FB3_14_Q" SNm="int_rst_MC.Q"/><Net IoT="in" Loc="FB1_1" NNm="ds0" SNm="ds0"/><Net IoT="in" Loc="FB19_15" NNm="ds1" SNm="ds1"/><Net IoT="none" NNm="FB4_11_Q" SNm="U5/flash_tdi_reg_MC.Q"/><Net IoT="none" NNm="FB14_4_Q" SNm="dtack_led_MC.UIM"/><Net IoT="none" NNm="FB9_1_Q" SNm="int_lev&lt;0&gt;"/><Net IoT="none" NNm="FB2_6_Q" SNm="U5/int_ena_mdone_MC.Q"/><Net IoT="none" NNm="FB1_1_I" SNm="U3/r3_MC.D"/><Net IoT="none" NNm="FB19_15_I" SNm="ds1_II/UIM"/><Net IoT="none" NNm="FB1_4_Q" SNm="U5/ros_w0_MC.Q"/><Net IoT="out" Loc="FB19_1" NNm="tp2" SNm="tp2"/><Net IoT="out" Loc="FB1_12" NNm="cspare_8" SNm="cspare_8"/><Net IoT="out" Loc="FB14_3" NNm="tp3" SNm="tp3"/><Net IoT="out" Loc="FB2_3" NNm="cspare_9" SNm="cspare_9"/><Net IoT="out" Loc="FB13_3" NNm="tp4" SNm="tp4"/><Net IoT="out" Loc="FB18_4" NNm="mspare_0" SNm="mspare_0"/><Net IoT="out" Loc="FB8_13" NNm="mspare_1" SNm="mspare_1"/><Net IoT="out" Loc="FB18_12" NNm="mspare_2" SNm="mspare_2"/><Net IoT="out" Loc="FB18_15" NNm="mspare_3" SNm="mspare_3"/><Net IoT="none" NNm="FB10_PT0" SNm="FB10_PT0"/><Net IoT="none" NNm="FB1_PT10" SNm="FB1_PT10"/><Net IoT="none" NNm="FB10_PT1" SNm="FB10_PT1"/><Net IoT="none" NNm="FB11_PT0" SNm="FB11_PT0"/><Net IoT="none" NNm="FB1_PT11" SNm="FB1_PT11"/><Net IoT="none" NNm="FB1_PT20" SNm="FB1_PT20"/><Net IoT="none" NNm="FB2_PT10" SNm="FB2_PT10"/><Net IoT="none" NNm="FB10_PT2" SNm="FB10_PT2"/><Net IoT="none" NNm="FB11_PT1" SNm="FB11_PT1"/><Net IoT="none" NNm="FB12_PT0" SNm="FB12_PT0"/><Net IoT="none" NNm="FB1_PT12" SNm="FB1_PT12"/><Net IoT="none" NNm="FB1_PT21" SNm="FB1_PT21"/><Net IoT="none" NNm="FB1_PT30" SNm="FB1_PT30"/><Net IoT="none" NNm="FB2_PT11" SNm="FB2_PT11"/><Net IoT="none" NNm="FB2_PT20" SNm="FB2_PT20"/><Net IoT="none" NNm="FB3_PT10" SNm="FB3_PT10"/><Net IoT="none" NNm="FB10_PT3" SNm="FB10_PT3"/><Net IoT="none" NNm="FB11_PT2" SNm="FB11_PT2"/><Net IoT="none" NNm="FB12_PT1" SNm="FB12_PT1"/><Net IoT="none" NNm="FB13_PT0" SNm="FB13_PT0"/><Net IoT="none" NNm="FB14_13_Q" SNm="spare_led_MC.UIM"/><Net IoT="none" NNm="FB1_PT13" SNm="FB1_PT13"/><Net IoT="none" NNm="FB1_PT22" SNm="FB1_PT22"/><Net IoT="none" NNm="FB1_PT31" SNm="FB1_PT31"/><Net IoT="none" NNm="FB2_PT12" SNm="FB2_PT12"/><Net IoT="none" NNm="FB2_PT21" SNm="FB2_PT21"/><Net IoT="none" NNm="FB3_PT11" SNm="FB3_PT11"/><Net IoT="none" NNm="FB3_PT20" SNm="FB3_PT20"/><Net IoT="none" NNm="FB4_PT10" SNm="FB4_PT10"/><Net IoT="none" NNm="FB10_PT4" SNm="FB10_PT4"/><Net IoT="none" NNm="FB11_PT3" SNm="FB11_PT3"/><Net IoT="none" NNm="FB12_PT2" SNm="FB12_PT2"/><Net IoT="none" NNm="FB13_PT1" SNm="FB13_PT1"/><Net IoT="none" NNm="FB14_PT0" SNm="FB14_PT0"/><Net IoT="none" NNm="FB23_PT0" SNm="FB23_PT0"/><Net IoT="none" NNm="FB10_PT5" SNm="FOOBAR10__ctinst/5"/><Net IoT="out" Loc="FB18_13" NNm="enw_x" SNm="enw_x"/><Net IoT="out" Loc="FB15_15" NNm="vspare_0" SNm="vspare_0"/><Net IoT="none" NNm="FB1_PT14" SNm="FB1_PT14"/><Net IoT="none" NNm="FB1_PT23" SNm="FB1_PT23"/><Net IoT="none" NNm="FB1_PT32" SNm="FB1_PT32"/><Net IoT="none" NNm="FB2_PT13" SNm="i2c_ce_p_MC.UIM"/><Net IoT="none" NNm="FB2_PT22" SNm="FB2_PT22"/><Net IoT="none" NNm="FB2_PT31" SNm="FB2_PT31"/><Net IoT="none" NNm="FB2_PT40" SNm="FB2_PT40"/><Net IoT="none" NNm="FB3_PT12" SNm="FB3_PT12"/><Net IoT="none" NNm="FB3_PT21" SNm="FB3_PT21"/><Net IoT="none" NNm="FB3_PT30" SNm="FB3_PT30"/><Net IoT="none" NNm="FB4_PT11" SNm="FB4_PT11"/><Net IoT="none" NNm="FB4_PT20" SNm="FB4_PT20"/><Net IoT="none" NNm="FB5_PT10" SNm="FB5_PT10"/><Net IoT="none" NNm="FB12_PT3" SNm="FB12_PT3"/><Net IoT="none" NNm="FB13_PT2" SNm="FB13_PT2"/><Net IoT="none" NNm="FB14_PT1" SNm="FB14_PT1"/><Net IoT="none" NNm="FB15_PT0" SNm="FB15_PT0"/><Net IoT="none" NNm="FB23_PT1" SNm="FB23_PT1"/><Net IoT="none" NNm="FB24_PT0" SNm="FB24_PT0"/><Net IoT="none" NNm="FB11_PT5" SNm="FOOBAR11__ctinst/5"/><Net IoT="out" Loc="FB10_2" NNm="etr_x" SNm="etr_x"/><Net IoT="none" NNm="FB20_PT5" SNm="FOOBAR20__ctinst/5"/><Net IoT="none" NNm="FB10_PT6" SNm="FOOBAR10__ctinst/6"/><Net IoT="out" Loc="FB16_14" NNm="vspare_1" SNm="vspare_1"/><Net IoT="none" NNm="FB1_PT15" SNm="FB1_PT15"/><Net IoT="none" NNm="FB1_PT24" SNm="FB1_PT24"/><Net IoT="none" NNm="FB1_PT33" SNm="FB1_PT33"/><Net IoT="none" NNm="FB2_PT14" SNm="FB2_PT14"/><Net IoT="none" NNm="FB2_PT23" SNm="FB2_PT23"/><Net IoT="none" NNm="FB3_PT13" SNm="FB3_PT13"/><Net IoT="none" NNm="FB3_PT22" SNm="FB3_PT22"/><Net IoT="none" NNm="FB3_PT31" SNm="U5/cclk_counter&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB4_PT12" SNm="FB4_PT12"/><Net IoT="none" NNm="FB4_PT21" SNm="FB4_PT21"/><Net IoT="none" NNm="FB4_PT30" SNm="FB4_PT30"/><Net IoT="none" NNm="FB5_PT11" SNm="FB5_PT11"/><Net IoT="none" NNm="FB5_PT20" SNm="FB5_PT20"/><Net IoT="none" NNm="FB6_PT10" SNm="FB6_PT10"/><Net IoT="none" NNm="FB12_PT4" SNm="FB12_PT4"/><Net IoT="none" NNm="FB13_PT3" SNm="FB13_PT3"/><Net IoT="none" NNm="FB14_PT2" SNm="FB14_PT2"/><Net IoT="none" NNm="FB15_PT1" SNm="FB15_PT1"/><Net IoT="none" NNm="FB16_PT0" SNm="FB16_PT0"/><Net IoT="none" NNm="FB24_PT1" SNm="FB24_PT1"/><Net IoT="none" NNm="FB12_PT5" SNm="FOOBAR12__ctinst/5"/><Net IoT="none" NNm="FB1_PT16" SNm="FB1_PT16"/><Net IoT="none" NNm="FB1_PT25" SNm="FB1_PT25"/><Net IoT="none" NNm="FB2_PT15" SNm="FB2_PT15"/><Net IoT="none" NNm="FB2_PT24" SNm="FB2_PT24"/><Net IoT="none" NNm="FB3_PT14" SNm="FB3_PT14"/><Net IoT="none" NNm="FB3_PT23" SNm="FB3_PT23"/><Net IoT="none" NNm="FB3_PT32" SNm="FB3_PT32"/><Net IoT="none" NNm="FB4_PT13" SNm="FB4_PT13"/><Net IoT="none" NNm="FB4_PT22" SNm="FB4_PT22"/><Net IoT="none" NNm="FB4_PT31" SNm="N_PZ_945"/><Net IoT="none" NNm="FB4_PT40" SNm="FB4_PT40"/><Net IoT="none" NNm="FB5_PT12" SNm="FB5_PT12"/><Net IoT="none" NNm="FB5_PT21" SNm="FB5_PT21"/><Net IoT="none" NNm="FB6_PT11" SNm="FB6_PT11"/><Net IoT="none" NNm="FB6_PT20" SNm="FB6_PT20"/><Net IoT="none" NNm="FB7_PT10" SNm="cclk&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB10_PT7" SNm="FB10_PT7"/><Net IoT="none" NNm="FB13_PT4" SNm="FB13_PT4"/><Net IoT="none" NNm="FB14_PT3" SNm="FB14_PT3"/><Net IoT="none" NNm="FB15_PT2" SNm="FB15_PT2"/><Net IoT="none" NNm="FB16_PT1" SNm="FB16_PT1"/><Net IoT="none" NNm="FB17_PT0" SNm="FB17_PT0"/><Net IoT="none" NNm="FB24_PT2" SNm="FB24_PT2"/><Net IoT="none" NNm="FB13_PT5" SNm="FOOBAR13__ctinst/5"/><Net IoT="none" NNm="FB1_PT17" SNm="FB1_PT17"/><Net IoT="none" NNm="FB1_PT26" SNm="FB1_PT26"/><Net IoT="none" NNm="FB2_PT16" SNm="FB2_PT16"/><Net IoT="none" NNm="FB2_PT25" SNm="FB2_PT25"/><Net IoT="none" NNm="FB2_PT34" SNm="FB2_PT34"/><Net IoT="none" NNm="FB2_PT43" SNm="FB2_PT43"/><Net IoT="none" NNm="FB3_PT15" SNm="FB3_PT15"/><Net IoT="none" NNm="FB3_PT24" SNm="FB3_PT24"/><Net IoT="none" NNm="FB4_PT14" SNm="FB4_PT14"/><Net IoT="none" NNm="FB4_PT23" SNm="FB4_PT23"/><Net IoT="none" NNm="FB4_PT32" SNm="FB4_PT32"/><Net IoT="none" NNm="FB5_PT13" SNm="FB5_PT13"/><Net IoT="none" NNm="FB5_PT22" SNm="FB5_PT22"/><Net IoT="none" NNm="FB5_PT40" SNm="N_PZ_953"/><Net IoT="none" NNm="FB6_PT12" SNm="FB6_PT12"/><Net IoT="none" NNm="FB6_PT21" SNm="FB6_PT21"/><Net IoT="none" NNm="FB8_PT10" SNm="FB8_PT10"/><Net IoT="none" NNm="FB12_PT6" SNm="FB12_PT6"/><Net IoT="none" NNm="FB14_PT4" SNm="FB14_PT4"/><Net IoT="none" NNm="FB15_PT3" SNm="FB15_PT3"/><Net IoT="none" NNm="FB16_PT2" SNm="FB16_PT2"/><Net IoT="none" NNm="FB17_PT1" SNm="FB17_PT1"/><Net IoT="none" NNm="FB24_PT3" SNm="FB24_PT3"/><Net IoT="out" Loc="FB13_13" NNm="cscr_p&lt;0&gt;" SNm="cscr_p&lt;0&gt;"/><Net IoT="none" NNm="FB8_5_Q" SNm="fl_vme&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB14_PT5" SNm="FOOBAR14__ctinst/5"/><Net IoT="none" NNm="FB23_PT5" SNm="FOOBAR23__ctinst/5"/><Net IoT="none" NNm="FB1_PT18" SNm="FB1_PT18"/><Net IoT="none" NNm="FB1_PT27" SNm="FB1_PT27"/><Net IoT="none" NNm="FB2_PT17" SNm="FB2_PT17"/><Net IoT="none" NNm="FB2_PT26" SNm="FB2_PT26"/><Net IoT="none" NNm="FB3_PT16" SNm="FB3_PT16"/><Net IoT="none" NNm="FB3_PT25" SNm="U5/cclk_counter&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB3_PT52" SNm="U5/cclk_counter&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB4_PT15" SNm="FB4_PT15"/><Net IoT="none" NNm="FB4_PT24" SNm="FB4_PT24"/><Net IoT="none" NNm="FB4_PT33" SNm="FB4_PT33"/><Net IoT="none" NNm="FB5_PT14" SNm="FB5_PT14"/><Net IoT="none" NNm="FB5_PT23" SNm="FB5_PT23"/><Net IoT="none" NNm="FB6_PT13" SNm="FB6_PT13"/><Net IoT="none" NNm="FB6_PT22" SNm="FB6_PT22"/><Net IoT="none" NNm="FB8_PT11" SNm="FB8_PT11"/><Net IoT="none" NNm="FB8_PT20" SNm="FB8_PT20"/><Net IoT="none" NNm="FB9_PT10" SNm="FB9_PT10"/><Net IoT="none" NNm="FB12_PT7" SNm="FB12_PT7"/><Net IoT="none" NNm="FB13_PT6" SNm="FB13_PT6"/><Net IoT="none" NNm="FB15_PT4" SNm="FB15_PT4"/><Net IoT="none" NNm="FB16_PT3" SNm="FB16_PT3"/><Net IoT="none" NNm="FB17_PT2" SNm="FB17_PT2"/><Net IoT="none" NNm="FB24_PT5" SNm="FOOBAR24__ctinst/5"/><Net IoT="out" Loc="FB13_16" NNm="cscr_p&lt;1&gt;" SNm="cscr_p&lt;1&gt;"/><Net IoT="none" NNm="FB14_PT6" SNm="FOOBAR14__ctinst/6"/><Net IoT="none" NNm="FB15_PT5" SNm="FOOBAR15__ctinst/5"/><Net IoT="none" NNm="FB1_PT19" SNm="FB1_PT19"/><Net IoT="none" NNm="FB1_PT28" SNm="FB1_PT28"/><Net IoT="none" NNm="FB1_PT46" SNm="FB1_PT46"/><Net IoT="none" NNm="FB1_PT55" SNm="FB1_PT55"/><Net IoT="none" NNm="FB2_PT18" SNm="FB2_PT18"/><Net IoT="none" NNm="FB2_PT27" SNm="FB2_PT27"/><Net IoT="none" NNm="FB3_PT17" SNm="FB3_PT17"/><Net IoT="none" NNm="FB3_PT26" SNm="FB3_PT26"/><Net IoT="none" NNm="FB4_PT16" SNm="FB4_PT16"/><Net IoT="none" NNm="FB4_PT25" SNm="FB4_PT25"/><Net IoT="none" NNm="FB4_PT34" SNm="N_PZ_944"/><Net IoT="none" NNm="FB4_PT43" SNm="FB4_PT43"/><Net IoT="none" NNm="FB4_PT52" SNm="FB4_PT52"/><Net IoT="none" NNm="FB5_PT15" SNm="FB5_PT15"/><Net IoT="none" NNm="FB5_PT24" SNm="FB5_PT24"/><Net IoT="none" NNm="FB6_PT14" SNm="FB6_PT14"/><Net IoT="none" NNm="FB6_PT23" SNm="FB6_PT23"/><Net IoT="none" NNm="FB7_PT13" SNm="cclk&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB7_PT22" SNm="cclk&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB7_PT31" SNm="U1/q4_MC.D"/><Net IoT="none" NNm="FB7_PT40" SNm="ULED3/q1_MC.D"/><Net IoT="none" NNm="FB8_PT12" SNm="FB8_PT12"/><Net IoT="none" NNm="FB8_PT21" SNm="FB8_PT21"/><Net IoT="none" NNm="FB8_PT30" SNm="FB8_PT30"/><Net IoT="none" NNm="FB9_PT11" SNm="FB9_PT11"/><Net IoT="none" NNm="FB9_PT20" SNm="FB9_PT20"/><Net IoT="none" NNm="FB12_PT8" SNm="FB12_PT8"/><Net IoT="none" NNm="FB13_PT7" SNm="FB13_PT7"/><Net IoT="none" NNm="FB16_PT4" SNm="FB16_PT4"/><Net IoT="none" NNm="FB17_PT3" SNm="FB17_PT3"/><Net IoT="out" Loc="FB15_2" NNm="cscr_p&lt;2&gt;" SNm="cscr_p&lt;2&gt;"/><Net IoT="none" NNm="FB16_PT5" SNm="FOOBAR16__ctinst/5"/><Net IoT="none" NNm="FB15_PT6" SNm="FOOBAR15__ctinst/6"/><Net IoT="none" NNm="FB1_PT29" SNm="FB1_PT29"/><Net IoT="none" NNm="FB2_PT19" SNm="FB2_PT19"/><Net IoT="none" NNm="FB2_PT28" SNm="FB2_PT28"/><Net IoT="none" NNm="FB2_PT37" SNm="FB2_PT37"/><Net IoT="none" NNm="FB3_PT18" SNm="FB3_PT18"/><Net IoT="none" NNm="FB3_PT27" SNm="FB3_PT27"/><Net IoT="none" NNm="FB4_PT17" SNm="FB4_PT17"/><Net IoT="none" NNm="FB4_PT26" SNm="FB4_PT26"/><Net IoT="none" NNm="FB4_PT35" SNm="FB4_PT35"/><Net IoT="none" NNm="FB5_PT16" SNm="FB5_PT16"/><Net IoT="none" NNm="FB5_PT34" SNm="U1/q44_MC.D"/><Net IoT="none" NNm="FB5_PT43" SNm="FB5_PT43"/><Net IoT="none" NNm="FB6_PT15" SNm="FB6_PT15"/><Net IoT="none" NNm="FB6_PT24" SNm="FB6_PT24"/><Net IoT="none" NNm="FB8_PT13" SNm="FB8_PT13"/><Net IoT="none" NNm="FB8_PT22" SNm="FB8_PT22"/><Net IoT="none" NNm="FB8_PT31" SNm="FB8_PT31"/><Net IoT="none" NNm="FB9_PT12" SNm="FB9_PT12"/><Net IoT="none" NNm="FB9_PT21" SNm="FB9_PT21"/><Net IoT="none" NNm="FB12_PT9" SNm="FB12_PT9"/><Net IoT="none" NNm="FB13_PT8" SNm="FB13_PT8"/><Net IoT="none" NNm="FB14_PT7" SNm="FB14_PT7"/><Net IoT="none" NNm="FB17_PT4" SNm="FB17_PT4"/><Net IoT="in" Loc="FB21_15" NNm="lword" SNm="lword"/><Net IoT="out" Loc="FB15_3" NNm="cscr_p&lt;3&gt;" SNm="cscr_p&lt;3&gt;"/><Net IoT="none" NNm="FB3_PT19" SNm="FB3_PT19"/><Net IoT="none" NNm="FB3_PT28" SNm="U5/cclk_counter&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB3_PT55" SNm="FB3_PT55"/><Net IoT="none" NNm="FB4_PT18" SNm="FB4_PT18"/><Net IoT="none" NNm="FB4_PT27" SNm="FB4_PT27"/><Net IoT="none" NNm="FB5_PT17" SNm="FB5_PT17"/><Net IoT="none" NNm="FB6_PT16" SNm="FB6_PT16"/><Net IoT="none" NNm="FB6_PT25" SNm="FB6_PT25"/><Net IoT="none" NNm="FB8_PT14" SNm="FB8_PT14"/><Net IoT="none" NNm="FB8_PT23" SNm="FB8_PT23"/><Net IoT="none" NNm="FB8_PT32" SNm="FB8_PT32"/><Net IoT="none" NNm="FB9_PT13" SNm="FB9_PT13"/><Net IoT="none" NNm="FB9_PT22" SNm="prgm_fpga_p&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB13_PT9" SNm="FB13_PT9"/><Net IoT="none" NNm="FB14_PT8" SNm="FB14_PT8"/><Net IoT="none" NNm="FB15_PT7" SNm="FB15_PT7"/><Net IoT="none" NNm="FB16_PT6" SNm="FB16_PT6"/><Net IoT="none" NNm="FB17_PT5" SNm="FB17_PT5"/><Net IoT="out" Loc="FB15_5" NNm="cscr_p&lt;4&gt;" SNm="cscr_p&lt;4&gt;"/><Net IoT="none" NNm="FB17_PT6" SNm="FOOBAR17__ctinst/6"/><Net IoT="none" NNm="FB3_PT29" SNm="FB3_PT29"/><Net IoT="none" NNm="FB4_PT19" SNm="db&lt;15&gt;_MC.Q"/><Net IoT="none" NNm="FB4_PT28" SNm="FB4_PT28"/><Net IoT="none" NNm="FB4_PT46" SNm="FB4_PT46"/><Net IoT="none" NNm="FB5_PT18" SNm="FB5_PT18"/><Net IoT="none" NNm="FB6_PT17" SNm="FB6_PT17"/><Net IoT="none" NNm="FB7_PT16" SNm="cclk&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB7_PT34" SNm="U5/reset_2_MC.D"/><Net IoT="none" NNm="FB7_PT43" SNm="N_PZ_966"/><Net IoT="none" NNm="FB8_PT15" SNm="FB8_PT15"/><Net IoT="none" NNm="FB8_PT24" SNm="FB8_PT24"/><Net IoT="none" NNm="FB8_PT33" SNm="FB8_PT33"/><Net IoT="none" NNm="FB9_PT14" SNm="FB9_PT14"/><Net IoT="none" NNm="FB9_PT23" SNm="FB9_PT23"/><Net IoT="none" NNm="FB14_PT9" SNm="FB14_PT9"/><Net IoT="none" NNm="FB15_PT8" SNm="FB15_PT8"/><Net IoT="none" NNm="FB16_PT7" SNm="FB16_PT7"/><Net IoT="out" Loc="FB15_12" NNm="cscr_p&lt;5&gt;" SNm="cscr_p&lt;5&gt;"/><Net IoT="none" NNm="FB2_PT49" SNm="FB2_PT49"/><Net IoT="none" NNm="FB4_PT29" SNm="FB4_PT29"/><Net IoT="none" NNm="FB5_PT19" SNm="FB5_PT19"/><Net IoT="none" NNm="FB5_PT37" SNm="N_PZ_941"/><Net IoT="none" NNm="FB6_PT18" SNm="FB6_PT18"/><Net IoT="none" NNm="FB8_PT16" SNm="FB8_PT16"/><Net IoT="none" NNm="FB8_PT25" SNm="FB8_PT25"/><Net IoT="none" NNm="FB9_PT15" SNm="FB9_PT15"/><Net IoT="none" NNm="FB9_PT24" SNm="FB9_PT24"/><Net IoT="none" NNm="FB15_PT9" SNm="FB15_PT9"/><Net IoT="none" NNm="FB16_PT8" SNm="FB16_PT8"/><Net IoT="none" NNm="FB17_PT7" SNm="FB17_PT7"/><Net IoT="in" Loc="FB23_3" NNm="write" SNm="write"/><Net IoT="none" NNm="FB19_PT6" SNm="FOOBAR19__ctinst/6"/><Net IoT="out" Loc="FB15_13" NNm="cscr_p&lt;6&gt;" SNm="cscr_p&lt;6&gt;"/><Net IoT="out" Loc="FB12_2" NNm="flash_tck_p&lt;0&gt;" SNm="flash_tck_p&lt;0&gt;"/><Net IoT="none" NNm="FB6_PT19" SNm="FB6_PT19"/><Net IoT="none" NNm="FB8_PT17" SNm="FB8_PT17"/><Net IoT="none" NNm="FB8_PT26" SNm="FB8_PT26"/><Net IoT="none" NNm="FB9_PT16" SNm="FB9_PT16"/><Net IoT="none" NNm="FB9_PT25" SNm="FB9_PT25"/><Net IoT="none" NNm="FB9_PT43" SNm="prgm_fpga_p&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB9_PT52" SNm="prgm_fpga_p&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB16_PT9" SNm="FB16_PT9"/><Net IoT="none" NNm="FB17_PT8" SNm="FB17_PT8"/><Net IoT="none" NNm="FB1_10_Q" SNm="flash_ena_5_rosmem_MC.Q"/><Net IoT="out" Loc="FB12_3" NNm="flash_tck_p&lt;1&gt;" SNm="flash_tck_p&lt;1&gt;"/><Net IoT="none" NNm="FB11_2_Q" SNm="ULED1/q1_MC.Q"/><Net IoT="none" NNm="FB4_PT49" SNm="FB4_PT49"/><Net IoT="none" NNm="FB7_PT19" SNm="cclk&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB7_PT28" SNm="U5/s_reset_2_MC.D"/><Net IoT="none" NNm="FB7_PT37" SNm="U1/q444_MC.D"/><Net IoT="none" NNm="FB7_PT46" SNm="N_PZ_930"/><Net IoT="none" NNm="FB8_PT18" SNm="FB8_PT18"/><Net IoT="none" NNm="FB8_PT27" SNm="FB8_PT27"/><Net IoT="none" NNm="FB9_PT17" SNm="FB9_PT17"/><Net IoT="none" NNm="FB17_PT9" SNm="FB17_PT9"/><Net IoT="none" NNm="FB14_12_Q" SNm="ULED2/q1_MC.Q"/><Net IoT="out" Loc="FB12_4" NNm="flash_tck_p&lt;2&gt;" SNm="flash_tck_p&lt;2&gt;"/><Net IoT="none" NNm="FB8_3_Q" SNm="U5/ena_rst_prgm"/><Net IoT="none" NNm="FB5_PT49" SNm="FB5_PT49"/><Net IoT="none" NNm="FB8_PT19" SNm="FB8_PT19"/><Net IoT="none" NNm="FB8_PT28" SNm="FB8_PT28"/><Net IoT="none" NNm="FB8_PT55" SNm="FB8_PT55"/><Net IoT="none" NNm="FB9_PT18" SNm="FB9_PT18"/><Net IoT="out" Loc="FB12_5" NNm="flash_tck_p&lt;3&gt;" SNm="flash_tck_p&lt;3&gt;"/><Net IoT="none" NNm="FB11_15_Q" SNm="ULED1/q3_MC.Q"/><Net IoT="none" NNm="FB7_11_Q" SNm="ULED3/q1_MC.Q"/><Net IoT="none" NNm="FB8_PT29" SNm="FB8_PT29"/><Net IoT="none" NNm="FB9_PT19" SNm="FB9_PT19"/><Net IoT="none" NNm="FB9_PT46" SNm="prgm_fpga_p&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB11_13_Q" SNm="ULED2/q3_MC.Q"/><Net IoT="out" Loc="FB12_12" NNm="flash_tck_p&lt;4&gt;" SNm="flash_tck_p&lt;4&gt;"/><Net IoT="out" Loc="FB9_5" NNm="prgm_fpga_p&lt;0&gt;" SNm="prgm_fpga_p&lt;0&gt;"/><Net IoT="none" NNm="FB7_PT49" SNm="FB7_PT49"/><Net IoT="out" Loc="FB16_3" NNm="add_hold" SNm="add_hold"/><Net IoT="in" Loc="FB20_4" NNm="flash_tdo_p&lt;0&gt;" SNm="flash_tdo_p&lt;0&gt;"/><Net IoT="out" Loc="FB12_16" NNm="flash_tck_p&lt;5&gt;" SNm="flash_tck_p&lt;5&gt;"/><Net IoT="out" Loc="FB9_12" NNm="prgm_fpga_p&lt;1&gt;" SNm="prgm_fpga_p&lt;1&gt;"/><Net IoT="none" NNm="FB11_16_Q" SNm="ULED3/q3_MC.Q"/><Net IoT="in" Loc="FB20_5" NNm="flash_tdo_p&lt;1&gt;" SNm="flash_tdo_p&lt;1&gt;"/><Net IoT="out" Loc="FB9_13" NNm="prgm_fpga_p&lt;2&gt;" SNm="prgm_fpga_p&lt;2&gt;"/><Net IoT="none" NNm="FB9_PT49" SNm="prgm_fpga_p&lt;3&gt;_MC.Q"/><Net IoT="in" Loc="FB20_13" NNm="flash_tdo_p&lt;2&gt;" SNm="flash_tdo_p&lt;2&gt;"/><Net IoT="out" Loc="FB9_14" NNm="prgm_fpga_p&lt;3&gt;" SNm="prgm_fpga_p&lt;3&gt;"/><Net IoT="none" NNm="FB5_5_Q" SNm="U5/int_vect&lt;1&gt;"/><Net IoT="in" Loc="FB21_1" NNm="flash_tdo_p&lt;3&gt;" SNm="flash_tdo_p&lt;3&gt;"/><Net IoT="out" Loc="FB23_4" NNm="i2c_rd" SNm="i2c_rd"/><Net IoT="out" Loc="FB9_15" NNm="prgm_fpga_p&lt;4&gt;" SNm="prgm_fpga_p&lt;4&gt;"/><Net IoT="out" Loc="FB23_12" NNm="sel_tim_clk&lt;0&gt;" SNm="sel_tim_clk&lt;0&gt;"/><Net IoT="in" Loc="FB21_2" NNm="flash_tdo_p&lt;4&gt;" SNm="flash_tdo_p&lt;4&gt;"/><Net IoT="out" Loc="FB23_14" NNm="sel_tim_clk&lt;1&gt;" SNm="sel_tim_clk&lt;1&gt;"/><Net IoT="none" NNm="FB21_15_I" SNm="lword_II/UIM"/><Net IoT="in" Loc="FB21_3" NNm="flash_tdo_p&lt;5&gt;" SNm="flash_tdo_p&lt;5&gt;"/><Net IoT="none" NNm="FB9_2_Q" SNm="U5/int_vect&lt;5&gt;"/><Net IoT="none" NNm="FB1_14_Q" SNm="i2c_ce_gol_MC.UIM"/><Net IoT="out" Loc="FB14_5" NNm="intrpt_led" SNm="intrpt_led"/><Net IoT="none" NNm="FB23_3_I" SNm="write_II/UIM"/><Net IoT="none" NNm="FB2_13_Q" SNm="U5/int_ena_sff_MC.Q"/><Net IoT="in" Loc="FB7_12" NNm="clk" SNm="clk" ClkT="G"/><Net IoT="none" NNm="FB1_9_Q" SNm="U5/flash_enable&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB1_8_Q" SNm="U5/flash_enable&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB1_3_Q" SNm="U5/state_FFD1_MC.Q"/><Net IoT="none" NNm="FB8_14_Q" SNm="U5/qpll_hasunlock_reg_MC.Q"/><Net IoT="none" NNm="FB1_15_Q" SNm="U5/state_FFD2_MC.Q"/><Net IoT="none" NNm="FB20_4_I" SNm="flash_tdo_p&lt;0&gt;_II/UIM"/><Net IoT="none" NNm="FB1_7_Q" SNm="U5/flash_enable&lt;2&gt;_MC.Q"/><Net IoT="out" Loc="FB2_1" NNm="qpll_reset" SNm="qpll_reset"/><Net IoT="none" NNm="FB12_8_Q" SNm="U5/state_FFD3_MC.Q"/><Net IoT="none" NNm="FB20_5_I" SNm="flash_tdo_p&lt;1&gt;_II/UIM"/><Net IoT="none" NNm="FB1_6_Q" SNm="U5/flash_enable&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB1_11_Q" SNm="U5/flash_enable&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB20_13_I" SNm="flash_tdo_p&lt;2&gt;_II/UIM"/><Net IoT="none" NNm="FB21_1_I" SNm="flash_tdo_p&lt;3&gt;_II/UIM"/><Net IoT="none" NNm="FB6_15_Q" SNm="U5/s_reset_1_MC.Q"/><Net IoT="none" NNm="FB21_2_I" SNm="flash_tdo_p&lt;4&gt;_II/UIM"/><Net IoT="none" NNm="FB7_7_Q" SNm="U5/s_reset_2_MC.Q"/><Net IoT="none" NNm="FB21_3_I" SNm="flash_tdo_p&lt;5&gt;_II/UIM"/><Net IoT="in" Loc="FB21_16" NNm="qpll_error" SNm="qpll_error"/><Net IoT="none" NNm="FB20_2_Q" SNm="fl_tdi_r_MC.Q"/><Net IoT="in" Loc="FB1_2" NNm="mem_done" SNm="mem_done"/><Net IoT="none" NNm="FB20_1_Q" SNm="fl_tck_r_MC.Q"/><Net IoT="out" Loc="FB18_5" NNm="i2c_wr" SNm="i2c_wr"/><Net IoT="none" NNm="FB7_12_I" SNm="clk_II/FCLK"/><Net IoT="out" Loc="FB7_1" NNm="cclk&lt;0&gt;" SNm="cclk&lt;0&gt;"/><Net IoT="out" Loc="FB7_2" NNm="cclk&lt;1&gt;" SNm="cclk&lt;1&gt;"/><Net IoT="out" Loc="FB7_3" NNm="cclk&lt;2&gt;" SNm="cclk&lt;2&gt;"/><Net IoT="none" NNm="FB11_6_Q" SNm="U1/dssync_MC.Q"/><Net IoT="out" Loc="FB7_4" NNm="cclk&lt;3&gt;" SNm="cclk&lt;3&gt;"/><Net IoT="none" NNm="FB2_1_OR" SNm="qpll_reset_MC.Q"/><Net IoT="out" Loc="FB7_5" NNm="cclk&lt;4&gt;" SNm="cclk&lt;4&gt;"/><Net IoT="none" NNm="FB1_3_OR" SNm="U5/state_FFD1_MC.D"/><Net IoT="none" NNm="FB4_15_Q" SNm="gol_off_MC.UIM"/><Net IoT="none" NNm="FB1_5_OR" SNm="U5/_n007019"/><Net IoT="none" NNm="FB2_4_OR" SNm="U5/int_ena_spaf_MC.D"/><Net IoT="none" NNm="FB10_PT10" SNm="etr_vf_MC.Q"/><Net IoT="none" NNm="FB1_6_OR" SNm="U5/flash_enable&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB2_5_OR" SNm="_n0009_MC.GLB"/><Net IoT="none" NNm="FB4_3_OR" SNm="db&lt;8&gt;_MC.Q"/><Net IoT="none" NNm="FB10_PT11" SNm="FB10_PT11"/><Net IoT="none" NNm="FB11_PT10" SNm="irq&lt;1&gt;_MC.Q"/><Net IoT="in" Loc="FB7_14" NNm="fpga_done&lt;0&gt;" SNm="fpga_done&lt;0&gt;"/><Net IoT="none" NNm="FB1_7_OR" SNm="U5/flash_enable&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB2_6_OR" SNm="U5/int_ena_mdone_MC.D"/><Net IoT="none" NNm="FB11_PT11" SNm="FB11_PT11"/><Net IoT="none" NNm="FB12_PT10" SNm="FB12_PT10"/><Net IoT="in" Loc="FB7_16" NNm="fpga_done&lt;1&gt;" SNm="fpga_done&lt;1&gt;"/><Net IoT="none" NNm="FB1_8_OR" SNm="U5/flash_enable&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB2_7_OR" SNm="int_lev&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB5_4_OR" SNm="db&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB6_3_OR" SNm="fpga_init&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB8_1_OR" SNm="db&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB10_PT13" SNm="etr_x_MC.D"/><Net IoT="none" NNm="FB10_PT22" SNm="g245_p_MC.Q"/><Net IoT="none" NNm="FB10_PT31" SNm="U1/q8_MC.D"/><Net IoT="none" NNm="FB10_PT40" SNm="U1/q1_MC.D"/><Net IoT="none" NNm="FB12_PT11" SNm="FB12_PT11"/><Net IoT="none" NNm="FB12_PT20" SNm="FB12_PT20"/><Net IoT="none" NNm="FB13_PT10" SNm="FB13_PT10"/><Net IoT="in" Loc="FB3_13" NNm="fpga_done&lt;2&gt;" SNm="fpga_done&lt;2&gt;"/><Net IoT="none" NNm="FB21_16_I" SNm="qpll_error_II/UIM"/><Net IoT="out" Loc="FB14_1" NNm="mrs" SNm="mrs"/><Net IoT="none" NNm="FB1_9_OR" SNm="U5/flash_enable&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB2_8_OR" SNm="int_lev&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB10_PT14" SNm="FB10_PT14"/><Net IoT="none" NNm="FB10_PT50" SNm="FB10_PT50"/><Net IoT="none" NNm="FB11_PT13" SNm="ULED1/q1_MC.D"/><Net IoT="none" NNm="FB11_PT22" SNm="irq&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB11_PT31" SNm="U3/r6_MC.D"/><Net IoT="none" NNm="FB11_PT40" SNm="U3/r5_MC.D"/><Net IoT="none" NNm="FB12_PT12" SNm="FB12_PT12"/><Net IoT="none" NNm="FB12_PT21" SNm="FB12_PT21"/><Net IoT="none" NNm="FB12_PT30" SNm="FB12_PT30"/><Net IoT="none" NNm="FB13_PT11" SNm="FB13_PT11"/><Net IoT="none" NNm="FB13_PT20" SNm="FB13_PT20"/><Net IoT="none" NNm="FB14_PT10" SNm="FB14_PT10"/><Net IoT="none" NNm="FB1_2_I" SNm="U5/mem_d0_MC.D"/><Net IoT="in" Loc="FB3_15" NNm="fpga_done&lt;3&gt;" SNm="fpga_done&lt;3&gt;"/><Net IoT="none" NNm="FB2_9_OR" SNm="U5/int_vect&lt;6&gt;_MC.D"/><Net IoT="none" NNm="FB4_7_OR" SNm="U5/flash_tms_MC.D"/><Net IoT="none" NNm="FB11_PT23" SNm="FB11_PT23"/><Net IoT="none" NNm="FB11_PT50" SNm="FB11_PT50"/><Net IoT="none" NNm="FB12_PT13" SNm="FB12_PT13"/><Net IoT="none" NNm="FB12_PT22" SNm="FB12_PT22"/><Net IoT="none" NNm="FB12_PT31" SNm="FB12_PT31"/><Net IoT="none" NNm="FB12_PT40" SNm="FB12_PT40"/><Net IoT="none" NNm="FB13_PT12" SNm="FB13_PT12"/><Net IoT="none" NNm="FB13_PT21" SNm="FB13_PT21"/><Net IoT="none" NNm="FB13_PT30" SNm="FB13_PT30"/><Net IoT="none" NNm="FB14_PT11" SNm="FB14_PT11"/><Net IoT="none" NNm="FB15_PT10" SNm="FB15_PT10"/><Net IoT="in" Loc="FB21_4" NNm="fpga_done&lt;4&gt;" SNm="fpga_done&lt;4&gt;"/><Net IoT="none" NNm="FB10_PT25" SNm="U1/q9_MC.D"/><Net IoT="none" NNm="FB10_PT34" SNm="U1/q6_MC.D"/><Net IoT="none" NNm="FB12_PT14" SNm="FB12_PT14"/><Net IoT="none" NNm="FB12_PT23" SNm="FB12_PT23"/><Net IoT="none" NNm="FB12_PT32" SNm="FB12_PT32"/><Net IoT="none" NNm="FB12_PT41" SNm="FB12_PT41"/><Net IoT="none" NNm="FB12_PT50" SNm="FB12_PT50"/><Net IoT="none" NNm="FB13_PT13" SNm="FB13_PT13"/><Net IoT="none" NNm="FB13_PT22" SNm="FB13_PT22"/><Net IoT="none" NNm="FB13_PT31" SNm="FB13_PT31"/><Net IoT="none" NNm="FB14_PT12" SNm="FB14_PT12"/><Net IoT="none" NNm="FB15_PT11" SNm="FB15_PT11"/><Net IoT="none" NNm="FB15_PT20" SNm="FB15_PT20"/><Net IoT="in" Loc="FB22_12" NNm="spaf&lt;0&gt;" SNm="spaf&lt;0&gt;"/><Net IoT="out" Loc="FB14_2" NNm="prs" SNm="prs"/><Net IoT="none" NNm="FB7_6_OR" SNm="U5/reset_1_MC.D"/><Net IoT="none" NNm="FB8_5_OR" SNm="fl_vme&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB10_PT53" SNm="FB10_PT53"/><Net IoT="none" NNm="FB11_PT16" SNm="irq&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB11_PT25" SNm="U1/dssync_MC.D"/><Net IoT="none" NNm="FB11_PT34" SNm="FB11_PT34"/><Net IoT="none" NNm="FB11_PT43" SNm="irq&lt;5&gt;_MC.Q"/><Net IoT="none" NNm="FB11_PT52" SNm="ULED1/q3_MC.D"/><Net IoT="none" NNm="FB12_PT15" SNm="FB12_PT15"/><Net IoT="none" NNm="FB12_PT24" SNm="FB12_PT24"/><Net IoT="none" NNm="FB12_PT33" SNm="FB12_PT33"/><Net IoT="none" NNm="FB12_PT42" SNm="FB12_PT42"/><Net IoT="none" NNm="FB12_PT51" SNm="FB12_PT51"/><Net IoT="none" NNm="FB13_PT14" SNm="FB13_PT14"/><Net IoT="none" NNm="FB13_PT23" SNm="FB13_PT23"/><Net IoT="none" NNm="FB13_PT32" SNm="FB13_PT32"/><Net IoT="none" NNm="FB14_PT13" SNm="FB14_PT13"/><Net IoT="none" NNm="FB14_PT22" SNm="intrpt_led_MC.D"/><Net IoT="none" NNm="FB15_PT12" SNm="FB15_PT12"/><Net IoT="none" NNm="FB15_PT21" SNm="FB15_PT21"/><Net IoT="none" NNm="FB15_PT30" SNm="FB15_PT30"/><Net IoT="in" Loc="FB22_13" NNm="spaf&lt;1&gt;" SNm="spaf&lt;1&gt;"/><Net IoT="none" NNm="FB11_PT44" SNm="FB11_PT44"/><Net IoT="none" NNm="FB11_PT53" SNm="FB11_PT53"/><Net IoT="none" NNm="FB12_PT16" SNm="FB12_PT16"/><Net IoT="none" NNm="FB12_PT25" SNm="FB12_PT25"/><Net IoT="none" NNm="FB12_PT34" SNm="FB12_PT34"/><Net IoT="none" NNm="FB12_PT43" SNm="FB12_PT43"/><Net IoT="none" NNm="FB12_PT52" SNm="FB12_PT52"/><Net IoT="none" NNm="FB13_PT15" SNm="FB13_PT15"/><Net IoT="none" NNm="FB13_PT24" SNm="FB13_PT24"/><Net IoT="none" NNm="FB13_PT33" SNm="FB13_PT33"/><Net IoT="none" NNm="FB14_PT14" SNm="FB14_PT14"/><Net IoT="none" NNm="FB14_PT41" SNm="FB14_PT41"/><Net IoT="none" NNm="FB15_PT13" SNm="cscr_p&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB15_PT22" SNm="cscr_p&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB15_PT31" SNm="FB15_PT31"/><Net IoT="none" NNm="FB24_PT13" SNm="FB24_PT13"/><Net IoT="none" NNm="FB10_11_Q" SNm="U1/q1_MC.Q"/><Net IoT="in" Loc="FB22_14" NNm="spaf&lt;2&gt;" SNm="spaf&lt;2&gt;"/><Net IoT="none" NNm="FB10_PT19" SNm="ldpreg_MC.Q"/><Net IoT="none" NNm="FB10_PT28" SNm="U1/q7_MC.D"/><Net IoT="none" NNm="FB10_PT37" SNm="FB10_PT37"/><Net IoT="none" NNm="FB10_PT55" SNm="U3/r7_MC.D"/><Net IoT="none" NNm="FB12_PT17" SNm="FB12_PT17"/><Net IoT="none" NNm="FB12_PT26" SNm="FB12_PT26"/><Net IoT="none" NNm="FB12_PT35" SNm="FB12_PT35"/><Net IoT="none" NNm="FB12_PT44" SNm="FB12_PT44"/><Net IoT="none" NNm="FB12_PT53" SNm="FB12_PT53"/><Net IoT="none" NNm="FB13_PT16" SNm="tp4_MC.Q"/><Net IoT="none" NNm="FB13_PT25" SNm="FB13_PT25"/><Net IoT="none" NNm="FB13_PT34" SNm="FB13_PT34"/><Net IoT="none" NNm="FB15_PT14" SNm="FB15_PT14"/><Net IoT="none" NNm="FB15_PT23" SNm="FB15_PT23"/><Net IoT="none" NNm="FB19_PT10" SNm="tp2_MC.D"/><Net IoT="none" NNm="FB10_10_Q" SNm="U1/q2_MC.Q"/><Net IoT="in" Loc="FB22_15" NNm="spaf&lt;3&gt;" SNm="spaf&lt;3&gt;"/><Net IoT="none" NNm="FB20_3_Q" SNm="fl_tms_r_MC.Q"/><Net IoT="none" NNm="FB11_PT19" SNm="irq&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB11_PT28" SNm="FB11_PT28"/><Net IoT="none" NNm="FB11_PT37" SNm="FB11_PT37"/><Net IoT="none" NNm="FB11_PT46" SNm="ULED2/q3_MC.D"/><Net IoT="none" NNm="FB11_PT55" SNm="ULED3/q3_MC.D"/><Net IoT="none" NNm="FB12_PT18" SNm="FB12_PT18"/><Net IoT="none" NNm="FB12_PT27" SNm="FB12_PT27"/><Net IoT="none" NNm="FB12_PT36" SNm="FB12_PT36"/><Net IoT="none" NNm="FB12_PT45" SNm="FB12_PT45"/><Net IoT="none" NNm="FB12_PT54" SNm="FB12_PT54"/><Net IoT="none" NNm="FB13_PT17" SNm="FB13_PT17"/><Net IoT="none" NNm="FB13_PT26" SNm="FB13_PT26"/><Net IoT="none" NNm="FB14_PT16" SNm="tp3_MC.Q"/><Net IoT="none" NNm="FB15_PT15" SNm="FB15_PT15"/><Net IoT="none" NNm="FB15_PT24" SNm="FB15_PT24"/><Net IoT="none" NNm="FB17_PT13" SNm="reset_p_MC.Q"/><Net IoT="none" NNm="FB23_PT43" SNm="FB23_PT43"/><Net IoT="in" Loc="FB23_2" NNm="spaf&lt;4&gt;" SNm="spaf&lt;4&gt;"/><Net IoT="none" NNm="FB9_8_OR" SNm="U5/tdo_bits&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB11_PT29" SNm="FB11_PT29"/><Net IoT="none" NNm="FB11_PT38" SNm="FB11_PT38"/><Net IoT="none" NNm="FB12_PT19" SNm="FB12_PT19"/><Net IoT="none" NNm="FB12_PT28" SNm="FB12_PT28"/><Net IoT="none" NNm="FB12_PT37" SNm="FB12_PT37"/><Net IoT="none" NNm="FB12_PT46" SNm="FB12_PT46"/><Net IoT="none" NNm="FB12_PT55" SNm="FB12_PT55"/><Net IoT="none" NNm="FB13_PT18" SNm="FB13_PT18"/><Net IoT="none" NNm="FB13_PT27" SNm="FB13_PT27"/><Net IoT="none" NNm="FB14_PT44" SNm="FB14_PT44"/><Net IoT="none" NNm="FB15_PT16" SNm="cscr_p&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB15_PT25" SNm="FB15_PT25"/><Net IoT="none" NNm="FB15_PT43" SNm="cscr_p&lt;5&gt;_MC.Q"/><Net IoT="none" NNm="FB15_PT52" SNm="vspare_0_MC.Q"/><Net IoT="none" NNm="FB18_PT13" SNm="irq&lt;6&gt;_MC.Q"/><Net IoT="none" NNm="FB18_PT22" SNm="i2c_wr_MC.Q"/><Net IoT="none" NNm="FB7_8_Q" SNm="U1/q4_MC.Q"/><Net IoT="none" NNm="FB9_9_OR" SNm="U5/tdo_bits&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB12_PT29" SNm="FB12_PT29"/><Net IoT="none" NNm="FB12_PT38" SNm="FB12_PT38"/><Net IoT="none" NNm="FB12_PT47" SNm="FB12_PT47"/><Net IoT="none" NNm="FB13_PT19" SNm="FB13_PT19"/><Net IoT="none" NNm="FB13_PT28" SNm="FB13_PT28"/><Net IoT="none" NNm="FB13_PT46" SNm="cscr_p&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB13_PT55" SNm="cscr_p&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB15_PT17" SNm="FB15_PT17"/><Net IoT="none" NNm="FB15_PT26" SNm="FB15_PT26"/><Net IoT="none" NNm="FB15_PT53" SNm="FB15_PT53"/><Net IoT="none" NNm="FB16_PT16" SNm="add_hold_MC.Q"/><Net IoT="none" NNm="FB16_PT43" SNm="FB16_PT43"/><Net IoT="none" NNm="FB11_PT49" SNm="FB11_PT49"/><Net IoT="none" NNm="FB12_PT39" SNm="FB12_PT39"/><Net IoT="none" NNm="FB12_PT48" SNm="FB12_PT48"/><Net IoT="none" NNm="FB13_PT29" SNm="FB13_PT29"/><Net IoT="none" NNm="FB14_PT19" SNm="dtack_led_MC.D"/><Net IoT="none" NNm="FB14_PT46" SNm="spare_led_MC.D"/><Net IoT="none" NNm="FB15_PT18" SNm="FB15_PT18"/><Net IoT="none" NNm="FB15_PT27" SNm="FB15_PT27"/><Net IoT="none" NNm="FB17_PT16" SNm="FB17_PT16"/><Net IoT="none" NNm="FB23_PT19" SNm="i2c_rd_MC.Q"/><Net IoT="none" NNm="FB10_9_Q" SNm="U1/q6_MC.Q"/><Net IoT="none" NNm="FB1_1_Q" SNm="U3/r3_MC.Q"/><Net IoT="none" NNm="FB12_PT49" SNm="FB12_PT49"/><Net IoT="none" NNm="FB15_PT19" SNm="FB15_PT19"/><Net IoT="none" NNm="FB15_PT28" SNm="FB15_PT28"/><Net IoT="none" NNm="FB15_PT46" SNm="cscr_p&lt;6&gt;_MC.Q"/><Net IoT="none" NNm="FB15_PT55" SNm="FB15_PT55"/><Net IoT="none" NNm="FB18_PT16" SNm="irq&lt;7&gt;_MC.Q"/><Net IoT="none" NNm="FB7_14_I" SNm="fpga_done&lt;0&gt;_II/UIM"/><Net IoT="none" NNm="FB10_7_Q" SNm="U1/q7_MC.Q"/><Net IoT="none" NNm="FB3_16_Q" SNm="U3/r4_MC.Q"/><Net IoT="none" NNm="FB15_PT29" SNm="FB15_PT29"/><Net IoT="none" NNm="FB15_PT38" SNm="FB15_PT38"/><Net IoT="none" NNm="FB15_PT47" SNm="FB15_PT47"/><Net IoT="none" NNm="FB16_PT19" SNm="iackout_MC.Q"/><Net IoT="none" NNm="FB10_8_Q" SNm="U1/q8_MC.Q"/><Net IoT="none" NNm="FB11_11_Q" SNm="U3/r5_MC.Q"/><Net IoT="none" NNm="FB7_16_I" SNm="fpga_done&lt;1&gt;_II/UIM"/><Net IoT="out" Loc="FB1_13" NNm="fpga_init&lt;0&gt;" SNm="fpga_init&lt;0&gt;"/><Net IoT="none" NNm="FB17_PT46" SNm="enw_vf_MC.Q"/><Net IoT="none" NNm="FB23_PT49" SNm="FB23_PT49"/><Net IoT="none" NNm="FB10_6_Q" SNm="U1/q9_MC.Q"/><Net IoT="none" NNm="FB11_8_Q" SNm="U3/r6_MC.Q"/><Net IoT="none" NNm="FB3_13_I" SNm="fpga_done&lt;2&gt;_II/UIM"/><Net IoT="out" Loc="FB4_12" NNm="fpga_init&lt;1&gt;" SNm="fpga_init&lt;1&gt;"/><Net IoT="none" NNm="FB18_PT46" SNm="enw_x_MC.Q"/><Net IoT="in" Loc="FB7_15" NNm="clk_slow" SNm="clk_slow" ClkT="G"/><Net IoT="none" NNm="FB10_16_Q" SNm="U3/r7_MC.Q"/><Net IoT="none" NNm="FB3_15_I" SNm="fpga_done&lt;3&gt;_II/UIM"/><Net IoT="out" Loc="FB4_14" NNm="fpga_init&lt;2&gt;" SNm="fpga_init&lt;2&gt;"/><Net IoT="none" NNm="FB15_4_Q" SNm="prgm_fpga&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB21_4_I" SNm="fpga_done&lt;4&gt;_II/UIM"/><Net IoT="out" Loc="FB5_14" NNm="fpga_init&lt;3&gt;" SNm="fpga_init&lt;3&gt;"/><Net IoT="none" NNm="FB10_14_Q" SNm="U3/r8_MC.Q"/><Net IoT="none" NNm="FB15_1_Q" SNm="prgm_fpga&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB22_12_I" SNm="spaf&lt;0&gt;_II/UIM"/><Net IoT="out" Loc="FB6_3" NNm="fpga_init&lt;4&gt;" SNm="fpga_init&lt;4&gt;"/><Net IoT="none" NNm="FB17_15_Q" SNm="prgm_fpga&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB22_13_I" SNm="spaf&lt;1&gt;_II/UIM"/><Net IoT="none" NNm="FB17_11_Q" SNm="prgm_fpga&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB4_10_Q" SNm="U5/gol_notready_reg_MC.Q"/><Net IoT="none" NNm="FB22_14_I" SNm="spaf&lt;2&gt;_II/UIM"/><Net IoT="none" NNm="FB3_9_Q" SNm="U5/cclk_counter&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB17_10_Q" SNm="prgm_fpga&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB22_15_I" SNm="spaf&lt;3&gt;_II/UIM"/><Net IoT="none" NNm="FB3_8_Q" SNm="U5/cclk_counter&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB3_12_Q" SNm="U5/bits_to_send&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB23_2_I" SNm="spaf&lt;4&gt;_II/UIM"/><Net IoT="none" NNm="FB3_7_Q" SNm="U5/cclk_counter&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB14_11_Q" SNm="U5/bits_to_send&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB3_6_Q" SNm="U5/cclk_counter&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB15_14_Q" SNm="U5/bits_to_send&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB3_15_Q" SNm="U5/cclk_counter&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB15_11_Q" SNm="U5/bits_to_send&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB12_13_Q" SNm="U5/flash_tck_MC.Q"/><Net IoT="none" NNm="FB7_6_Q" SNm="U5/reset_1_MC.Q"/><Net IoT="none" NNm="FB7_9_Q" SNm="U5/reset_2_MC.Q"/><Net IoT="out" Loc="FB4_13" NNm="i2c_ce_1wire" SNm="i2c_ce_1wire"/><Net IoT="in" Loc="FB21_14" NNm="iackin" SNm="iackin"/><Net IoT="bidi" Loc="FB4_1" NNm="db&lt;0&gt;" SNm="db&lt;0&gt;"/><Net IoT="in" Loc="FB5_15" NNm="fl_switch&lt;0&gt;" SNm="fl_switch&lt;0&gt;"/><Net IoT="bidi" Loc="FB5_4" NNm="db&lt;1&gt;" SNm="db&lt;1&gt;"/><Net IoT="in" Loc="FB5_16" NNm="fl_switch&lt;1&gt;" SNm="fl_switch&lt;1&gt;"/><Net IoT="none" NNm="FB15_10_Q" SNm="U5/cuenta_prgm_0_0_MC.Q"/><Net IoT="out" Loc="FB9_4" NNm="add_f_p&lt;9&gt;" SNm="add_f_p&lt;9&gt;"/><Net IoT="bidi" Loc="FB6_1" NNm="db&lt;2&gt;" SNm="db&lt;2&gt;"/><Net IoT="in" Loc="FB8_15" NNm="fl_switch&lt;2&gt;" SNm="fl_switch&lt;2&gt;"/><Net IoT="none" NNm="FB15_8_Q" SNm="U5/cuenta_prgm_0_1_MC.Q"/><Net IoT="bidi" Loc="FB8_1" NNm="db&lt;3&gt;" SNm="db&lt;3&gt;"/><Net IoT="none" NNm="FB15_7_Q" SNm="U5/cuenta_prgm_0_2_MC.Q"/><Net IoT="in" Loc="FB20_2" NNm="fl_tdi" SNm="fl_tdi"/><Net IoT="none" NNm="FB1_1_MC_CLK" SNm="FB1_1_MC_CLK"/><Net IoT="in" Loc="FB10_15" NNm="add_mod&lt;0&gt;" SNm="add_mod&lt;0&gt;"/><Net IoT="bidi" Loc="FB6_16" NNm="db&lt;4&gt;" SNm="db&lt;4&gt;"/><Net IoT="none" NNm="FB16_12_Q" SNm="U5/ena_evres_MC.Q"/><Net IoT="none" NNm="FB15_6_Q" SNm="U5/cuenta_prgm_0_3_MC.Q"/><Net IoT="in" Loc="FB20_1" NNm="fl_tck" SNm="fl_tck"/><Net IoT="none" NNm="FB1_2_MC_CLK" SNm="FB1_2_MC_CLK"/><Net IoT="in" Loc="FB10_16" NNm="add_mod&lt;1&gt;" SNm="add_mod&lt;1&gt;"/><Net IoT="bidi" Loc="FB9_1" NNm="db&lt;5&gt;" SNm="db&lt;5&gt;"/><Net IoT="none" NNm="FB15_9_Q" SNm="U5/cuenta_prgm_0_4_MC.Q"/><Net IoT="none" NNm="FB1_3_MC_CLK" SNm="FB1_3_MC_CLK"/><Net IoT="in" Loc="FB14_14" NNm="add_mod&lt;2&gt;" SNm="add_mod&lt;2&gt;"/><Net IoT="bidi" Loc="FB8_2" NNm="db&lt;6&gt;" SNm="db&lt;6&gt;"/><Net IoT="none" NNm="FB1_4_MC_CLK" SNm="FB1_4_MC_CLK"/><Net IoT="none" NNm="FB4_1_MC_CLK" SNm="FB4_1_MC_CLK"/><Net IoT="in" Loc="FB14_16" NNm="add_mod&lt;3&gt;" SNm="add_mod&lt;3&gt;"/><Net IoT="bidi" Loc="FB4_5" NNm="db&lt;7&gt;" SNm="db&lt;7&gt;"/><Net IoT="none" NNm="FB2_4_MC_CLK" SNm="FB2_4_MC_CLK"/><Net IoT="in" Loc="FB19_4" NNm="add_mod&lt;4&gt;" SNm="add_mod&lt;4&gt;"/><Net IoT="bidi" Loc="FB4_3" NNm="db&lt;8&gt;" SNm="db&lt;8&gt;"/><Net IoT="none" NNm="FB1_6_MC_CLK" SNm="FB1_6_MC_CLK"/><Net IoT="none" NNm="FB6_1_MC_CLK" SNm="FB6_1_MC_CLK"/><Net IoT="in" Loc="FB19_5" NNm="add_mod&lt;5&gt;" SNm="add_mod&lt;5&gt;"/><Net IoT="bidi" Loc="FB5_5" NNm="db&lt;9&gt;" SNm="db&lt;9&gt;"/><Net IoT="in" Loc="FB17_16" NNm="i2c_int_p" SNm="i2c_int_p"/><Net IoT="out" Loc="FB12_1" NNm="fl_tdo" SNm="fl_tdo"/><Net IoT="none" NNm="FB8_2_Q" SNm="U5/flash_tck_reg"/><Net IoT="none" NNm="FB1_7_MC_CLK" SNm="FB1_7_MC_CLK"/><Net IoT="none" NNm="FB2_6_MC_CLK" SNm="FB2_6_MC_CLK"/><Net IoT="none" NNm="FB7_1_MC_CLK" SNm="FB7_1_MC_CLK"/><Net IoT="none" NNm="FB1_8_MC_CLK" SNm="FB1_8_MC_CLK"/><Net IoT="none" NNm="FB1_10_OR" SNm="flash_ena_5_rosmem_MC.D"/><Net IoT="none" NNm="FB2_7_MC_CLK" SNm="FB2_7_MC_CLK"/><Net IoT="none" NNm="FB3_6_MC_CLK" SNm="FB3_6_MC_CLK"/><Net IoT="none" NNm="FB4_5_MC_CLK" SNm="FB4_5_MC_CLK"/><Net IoT="none" NNm="FB6_3_MC_CLK" SNm="FB6_3_MC_CLK"/><Net IoT="none" NNm="FB7_2_MC_CLK" SNm="FB7_2_MC_CLK"/><Net IoT="none" NNm="FB1_9_MC_CLK" SNm="FB1_9_MC_CLK"/><Net IoT="none" NNm="FB1_11_OR" SNm="U5/flash_enable&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB2_8_MC_CLK" SNm="FB2_8_MC_CLK"/><Net IoT="none" NNm="FB2_10_OR" SNm="U5/int_vect&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB3_7_MC_CLK" SNm="FB3_7_MC_CLK"/><Net IoT="none" NNm="FB5_5_MC_CLK" SNm="FB5_5_MC_CLK"/><Net IoT="none" NNm="FB7_3_MC_CLK" SNm="FB7_3_MC_CLK"/><Net IoT="none" NNm="FB8_2_MC_CLK" SNm="FB8_2_MC_CLK"/><Net IoT="none" NNm="FB9_1_MC_CLK" SNm="FB9_1_MC_CLK"/><Net IoT="none" NNm="FB2_9_MC_CLK" SNm="FB2_9_MC_CLK"/><Net IoT="none" NNm="FB2_11_OR" SNm="U5/int_vect&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB3_8_MC_CLK" SNm="FB3_8_MC_CLK"/><Net IoT="none" NNm="FB3_10_OR" SNm="U5/ros_waiting_reg_MC.D"/><Net IoT="none" NNm="FB4_7_MC_CLK" SNm="FB4_7_MC_CLK"/><Net IoT="none" NNm="FB7_4_MC_CLK" SNm="FB7_4_MC_CLK"/><Net IoT="none" NNm="FB8_3_MC_CLK" SNm="FB8_3_MC_CLK"/><Net IoT="none" NNm="FB9_2_MC_CLK" SNm="FB9_2_MC_CLK"/><Net IoT="none" NNm="FB10_3_OR" SNm="ack_int_MC.D"/><Net IoT="none" NNm="FB12_1_OR" SNm="fl_tdo_MC.D"/><Net IoT="none" NNm="FB21_14_I" SNm="iackin_II/UIM"/><Net IoT="none" NNm="FB4_1_I" SNm="fl_vme&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB5_15_I" SNm="fl_switch&lt;0&gt;_II/UIM"/><Net IoT="none" NNm="FB4_7_Q" SNm="U5/flash_tms_MC.Q"/><Net IoT="none" NNm="FB1_13_OR" SNm="fpga_init&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB2_12_OR" SNm="U5/int_vect&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB3_9_MC_CLK" SNm="FB3_9_MC_CLK"/><Net IoT="none" NNm="FB3_11_OR" SNm="U5/mem_done_reg_MC.D"/><Net IoT="none" NNm="FB4_10_OR" SNm="U5/gol_notready_reg_MC.D"/><Net IoT="none" NNm="FB7_5_MC_CLK" SNm="FB7_5_MC_CLK"/><Net IoT="none" NNm="FB8_4_MC_CLK" SNm="FB8_4_MC_CLK"/><Net IoT="none" NNm="FB12_2_OR" SNm="flash_tck_p&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB13_1_OR" SNm="U5/tdo_bits&lt;6&gt;_MC.D"/><Net IoT="none" NNm="FB5_4_I" SNm="db&lt;1&gt;_II/UIM"/><Net IoT="none" NNm="FB5_16_I" SNm="fl_switch&lt;1&gt;_II/UIM"/><Net IoT="none" NNm="FB1_14_OR" SNm="i2c_ce_gol_MC.D"/><Net IoT="none" NNm="FB2_13_OR" SNm="U5/int_ena_sff_MC.D"/><Net IoT="none" NNm="FB3_12_OR" SNm="U5/bits_to_send&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB4_11_OR" SNm="U5/flash_tdi_reg_MC.D"/><Net IoT="none" NNm="FB7_6_MC_CLK" SNm="FB7_6_MC_CLK"/><Net IoT="none" NNm="FB8_5_MC_CLK" SNm="FB8_5_MC_CLK"/><Net IoT="none" NNm="FB12_3_OR" SNm="flash_tck_p&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB13_2_OR" SNm="U5/tdo_bits&lt;5&gt;_MC.D"/><Net IoT="none" NNm="FB14_1_OR" SNm="mrs_MC.Q"/><Net IoT="none" NNm="FB6_1_I" SNm="fl_vme&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB8_15_I" SNm="fl_switch&lt;2&gt;_II/UIM"/><Net IoT="out" Loc="FB10_4" NNm="ldpreg" SNm="ldpreg"/><Net IoT="none" NNm="FB1_15_OR" SNm="U5/state_FFD2_MC.D"/><Net IoT="none" NNm="FB2_14_OR" SNm="U5/int_vect&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB3_13_OR" SNm="N_PZ_971"/><Net IoT="none" NNm="FB4_12_OR" SNm="fpga_init&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB5_9_MC_CLK" SNm="FB5_9_MC_CLK"/><Net IoT="none" NNm="FB7_7_MC_CLK" SNm="FB7_7_MC_CLK"/><Net IoT="none" NNm="FB12_4_OR" SNm="flash_tck_p&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB14_2_OR" SNm="prs_MC.Q"/><Net IoT="none" NNm="FB15_1_OR" SNm="prgm_fpga&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB8_1_I" SNm="db&lt;3&gt;_II/UIM"/><Net IoT="out" Loc="FB16_1" NNm="flash_tdi_p" SNm="flash_tdi_p"/><Net IoT="none" NNm="FB5_12_Q" SNm="U5/cclk_freq&lt;0&gt;"/><Net IoT="none" NNm="FB1_16_OR" SNm="N_PZ_1032"/><Net IoT="none" NNm="FB2_15_OR" SNm="U5/int_ena_rosw_MC.D"/><Net IoT="none" NNm="FB3_14_OR" SNm="int_rst_MC.D"/><Net IoT="none" NNm="FB4_13_OR" SNm="i2c_ce_1wire_MC.D"/><Net IoT="none" NNm="FB7_8_MC_CLK" SNm="FB7_8_MC_CLK"/><Net IoT="none" NNm="FB12_5_OR" SNm="flash_tck_p&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB13_4_OR" SNm="U5/qpll_error_reg_MC.D"/><Net IoT="none" NNm="FB16_1_OR" SNm="flash_tdi_p_MC.Q"/><Net IoT="none" NNm="FB10_15_I" SNm="add_mod&lt;0&gt;_II/UIM"/><Net IoT="none" NNm="FB6_16_I" SNm="db&lt;4&gt;_II/UIM"/><Net IoT="none" NNm="FB24_2_Q" SNm="U5/cclk_freq&lt;1&gt;"/><Net IoT="none" NNm="FB4_14_OR" SNm="fpga_init&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB7_9_MC_CLK" SNm="FB7_9_MC_CLK"/><Net IoT="none" NNm="FB11_7_OR" SNm="U5/jtag_num_bits&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB13_5_OR" SNm="U5/tdi_bits&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB16_2_OR" SNm="flash_tms_p_MC.Q"/><Net IoT="none" NNm="FB17_1_OR" SNm="gol_reset_MC.Q"/><Net IoT="none" NNm="FB10_16_I" SNm="add_mod&lt;1&gt;_II/UIM"/><Net IoT="none" NNm="FB9_1_I" SNm="int_lev&lt;0&gt;_MC.D"/><Net IoT="out" Loc="FB17_2" NNm="i2c_reset" SNm="i2c_reset"/><Net IoT="none" NNm="FB8_4_Q" SNm="U5/cclk_freq&lt;2&gt;"/><Net IoT="none" NNm="FB3_16_OR" SNm="U3/r4_MC.D"/><Net IoT="none" NNm="FB4_15_OR" SNm="gol_off_MC.D"/><Net IoT="none" NNm="FB5_14_OR" SNm="fpga_init&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB9_8_MC_CLK" SNm="FB9_8_MC_CLK"/><Net IoT="none" NNm="FB9_10_OR" SNm="U5/tdo_bits&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB13_6_OR" SNm="U5/tdi_bits&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB15_4_OR" SNm="prgm_fpga&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB14_14_I" SNm="add_mod&lt;2&gt;_II/UIM"/><Net IoT="none" NNm="FB8_2_I" SNm="U5/flash_tck_reg_MC.D"/><Net IoT="none" NNm="FB9_9_MC_CLK" SNm="FB9_9_MC_CLK"/><Net IoT="none" NNm="FB9_11_OR" SNm="U5/tdo_bits&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB11_9_OR" SNm="U5/jtag_num_bits&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB12_8_OR" SNm="U5/state_FFD3_MC.D"/><Net IoT="none" NNm="FB13_7_OR" SNm="U5/tdi_bits&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB14_16_I" SNm="add_mod&lt;3&gt;_II/UIM"/><Net IoT="in" Loc="FB1_3" NNm="sysreset" SNm="sysreset"/><Net IoT="none" NNm="FB4_5_I" SNm="U5/flash_tms_reg_MC.D"/><Net IoT="none" NNm="FB6_15_OR" SNm="U5/s_reset_1_MC.D"/><Net IoT="none" NNm="FB7_14_OR" SNm="N_PZ_1042"/><Net IoT="none" NNm="FB12_9_OR" SNm="U5/tdo_reg_MC.D"/><Net IoT="none" NNm="FB13_8_OR" SNm="U5/tdi_bits&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB15_6_OR" SNm="U5/cuenta_prgm_0_3_MC.D"/><Net IoT="none" NNm="FB19_4_I" SNm="add_mod&lt;4&gt;_II/UIM"/><Net IoT="none" NNm="FB4_3_I" SNm="db&lt;8&gt;_II/UIM"/><Net IoT="none" NNm="FB19_1_Q" SNm="tp2_MC.UIM"/><Net IoT="none" NNm="FB6_16_OR" SNm="db&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB7_15_OR" SNm="U5/_n0041"/><Net IoT="none" NNm="FB8_14_OR" SNm="U5/qpll_hasunlock_reg_MC.D"/><Net IoT="none" NNm="FB13_9_OR" SNm="U5/tdi_bits&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB15_7_OR" SNm="U5/cuenta_prgm_0_2_MC.D"/><Net IoT="none" NNm="FB19_5_I" SNm="add_mod&lt;5&gt;_II/UIM"/><Net IoT="none" NNm="FB5_5_I" SNm="U5/int_vect&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB17_16_I" SNm="i2c_int_p_II/UIM"/><Net IoT="out" Loc="FB17_13" NNm="enw_vf" SNm="enw_vf"/><Net IoT="in" Loc="FB20_3" NNm="fl_tms" SNm="fl_tms"/><Net IoT="none" NNm="FB7_16_OR" SNm="U5/local_reset"/><Net IoT="none" NNm="FB15_8_OR" SNm="U5/cuenta_prgm_0_1_MC.D"/><Net IoT="out" Loc="FB10_1" NNm="etr_vf" SNm="etr_vf"/><Net IoT="none" NNm="FB8_16_OR" SNm="ena_evres_prgm_MC.D"/><Net IoT="none" NNm="FB15_9_OR" SNm="U5/cuenta_prgm_0_4_MC.D"/><Net IoT="none" NNm="FB9_16_OR" SNm="U5/tdo_bits&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB4_5_Q" SNm="U5/flash_tms_reg"/><Net IoT="in" Loc="FB22_2" NNm="qpll_locked" SNm="qpll_locked"/><Net IoT="none" NNm="FB5_9_Q" SNm="U1/q44_MC.Q"/><Net IoT="none" NNm="FB1_3_I" SNm="sysreset_II/FSR"/><Net IoT="none" NNm="FB10_2_Q" SNm="etr_x_MC.UIM"/><Net IoT="out" Loc="FB16_2" NNm="flash_tms_p" SNm="flash_tms_p"/><Net IoT="none" NNm="FB4_1_Q" SNm="fl_vme&lt;0&gt;"/><Net IoT="none" NNm="FB6_1_Q" SNm="fl_vme&lt;2&gt;"/><Net IoT="in" Loc="FB21_13" NNm="iack" SNm="iack"/><Net IoT="out" Loc="FB3_2" NNm="add_f_p&lt;10&gt;" SNm="add_f_p&lt;10&gt;"/><Net IoT="none" NNm="FB22_2_I" SNm="qpll_locked_II/UIM"/><Net IoT="out" Loc="FB3_3" NNm="add_f_p&lt;11&gt;" SNm="add_f_p&lt;11&gt;"/><Net IoT="out" Loc="FB3_1" NNm="add_f_p&lt;12&gt;" SNm="add_f_p&lt;12&gt;"/><Net IoT="out" Loc="FB3_4" NNm="add_f_p&lt;13&gt;" SNm="add_f_p&lt;13&gt;"/><Net IoT="none" NNm="FB13_4_Q" SNm="U5/qpll_error_reg_MC.Q"/><Net IoT="out" Loc="FB14_4" NNm="dtack_led" SNm="dtack_led"/><Net IoT="out" Loc="FB3_5" NNm="add_f_p&lt;14&gt;" SNm="add_f_p&lt;14&gt;"/><Net IoT="none" NNm="FB3_11_Q" SNm="U5/mem_done_reg_MC.Q"/><Net IoT="none" NNm="FB2_8_Q" SNm="int_lev&lt;1&gt;_MC.Q"/><Net IoT="out" Loc="FB9_3" NNm="add_f_p&lt;15&gt;" SNm="add_f_p&lt;15&gt;"/><Net IoT="none" NNm="FB2_7_Q" SNm="int_lev&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB12_9_Q" SNm="U5/tdo_reg_MC.Q"/><Net IoT="bidi" Loc="FB5_12" NNm="db&lt;10&gt;" SNm="db&lt;10&gt;"/><Net IoT="in" Loc="FB21_5" NNm="g245_mem" SNm="g245_mem"/><Net IoT="in" Loc="FB19_14" NNm="brd_sel_24" SNm="brd_sel_24"/><Net IoT="bidi" Loc="FB24_2" NNm="db&lt;11&gt;" SNm="db&lt;11&gt;"/><Net IoT="none" NNm="FB7_15_I" SNm="clk_slow_II/FCLK"/><Net IoT="in" Loc="FB10_12" NNm="add_p&lt;0&gt;" SNm="add_p&lt;0&gt;"/><Net IoT="in" Loc="FB19_13" NNm="brd_sel_16" SNm="brd_sel_16"/><Net IoT="bidi" Loc="FB8_4" NNm="db&lt;12&gt;" SNm="db&lt;12&gt;"/><Net IoT="none" NNm="FB23_12_Q" SNm="sel_tim_clk&lt;0&gt;_MC.UIM"/><Net IoT="none" NNm="FB1_10_MC_CLK" SNm="FB1_10_MC_CLK"/><Net IoT="in" Loc="FB10_13" NNm="add_p&lt;1&gt;" SNm="add_p&lt;1&gt;"/><Net IoT="none" NNm="FB2_4_Q" SNm="U5/int_ena_spaf_MC.Q"/><Net IoT="bidi" Loc="FB9_2" NNm="db&lt;13&gt;" SNm="db&lt;13&gt;"/><Net IoT="none" NNm="FB23_14_Q" SNm="sel_tim_clk&lt;1&gt;_MC.UIM"/><Net IoT="none" NNm="FB1_11_MC_CLK" SNm="FB1_11_MC_CLK"/><Net IoT="none" NNm="FB2_10_MC_CLK" SNm="FB2_10_MC_CLK"/><Net IoT="none" NNm="FB10_2_MC_CLK" SNm="FB10_2_MC_CLK"/><Net IoT="none" NNm="FB20_1_MC_CLK" SNm="FB20_1_MC_CLK"/><Net IoT="in" Loc="FB10_14" NNm="add_p&lt;2&gt;" SNm="add_p&lt;2&gt;"/><Net IoT="none" NNm="FB21_13_I" SNm="iack_II/UIM"/><Net IoT="bidi" Loc="FB8_3" NNm="db&lt;14&gt;" SNm="db&lt;14&gt;"/><Net IoT="none" NNm="FB2_11_MC_CLK" SNm="FB2_11_MC_CLK"/><Net IoT="none" NNm="FB3_10_MC_CLK" SNm="FB3_10_MC_CLK"/><Net IoT="none" NNm="FB10_3_MC_CLK" SNm="FB10_3_MC_CLK"/><Net IoT="none" NNm="FB11_2_MC_CLK" SNm="FB11_2_MC_CLK"/><Net IoT="none" NNm="FB12_1_MC_CLK" SNm="FB12_1_MC_CLK"/><Net IoT="none" NNm="FB20_2_MC_CLK" SNm="FB20_2_MC_CLK"/><Net IoT="in" Loc="FB2_13" NNm="add_p&lt;3&gt;" SNm="add_p&lt;3&gt;"/><Net IoT="bidi" Loc="FB4_4" NNm="db&lt;15&gt;" SNm="db&lt;15&gt;"/><Net IoT="none" NNm="FB1_13_MC_CLK" SNm="FB1_13_MC_CLK"/><Net IoT="none" NNm="FB2_12_MC_CLK" SNm="FB2_12_MC_CLK"/><Net IoT="none" NNm="FB3_11_MC_CLK" SNm="FB3_11_MC_CLK"/><Net IoT="none" NNm="FB4_10_MC_CLK" SNm="FB4_10_MC_CLK"/><Net IoT="none" NNm="FB13_1_MC_CLK" SNm="FB13_1_MC_CLK"/><Net IoT="none" NNm="FB20_3_MC_CLK" SNm="FB20_3_MC_CLK"/><Net IoT="in" Loc="FB2_5" NNm="add_p&lt;4&gt;" SNm="add_p&lt;4&gt;"/><Net IoT="in" Loc="FB19_16" NNm="dtack_mem" SNm="dtack_mem"/><Net IoT="none" NNm="FB14_5_Q" SNm="intrpt_led_MC.UIM"/><Net IoT="none" NNm="FB1_14_MC_CLK" SNm="FB1_14_MC_CLK"/><Net IoT="none" NNm="FB2_13_MC_CLK" SNm="FB2_13_MC_CLK"/><Net IoT="none" NNm="FB3_12_MC_CLK" SNm="FB3_12_MC_CLK"/><Net IoT="none" NNm="FB4_11_MC_CLK" SNm="FB4_11_MC_CLK"/><Net IoT="none" NNm="FB13_2_MC_CLK" SNm="FB13_2_MC_CLK"/><Net IoT="in" Loc="FB2_4" NNm="add_p&lt;5&gt;" SNm="add_p&lt;5&gt;"/><Net IoT="none" NNm="FB1_15_MC_CLK" SNm="FB1_15_MC_CLK"/><Net IoT="none" NNm="FB2_14_MC_CLK" SNm="FB2_14_MC_CLK"/><Net IoT="none" NNm="FB4_12_MC_CLK" SNm="FB4_12_MC_CLK"/><Net IoT="none" NNm="FB10_6_MC_CLK" SNm="FB10_6_MC_CLK"/><Net IoT="none" NNm="FB15_1_MC_CLK" SNm="FB15_1_MC_CLK"/><Net IoT="in" Loc="FB13_12" NNm="add_p&lt;6&gt;" SNm="add_p&lt;6&gt;"/><Net IoT="in" Loc="FB1_4" NNm="ros_waiting" SNm="ros_waiting"/><Net IoT="none" NNm="FB2_15_MC_CLK" SNm="FB2_15_MC_CLK"/><Net IoT="none" NNm="FB3_14_MC_CLK" SNm="FB3_14_MC_CLK"/><Net IoT="none" NNm="FB4_13_MC_CLK" SNm="FB4_13_MC_CLK"/><Net IoT="none" NNm="FB5_12_MC_CLK" SNm="FB5_12_MC_CLK"/><Net IoT="none" NNm="FB7_10_MC_CLK" SNm="FB7_10_MC_CLK"/><Net IoT="none" NNm="FB10_7_MC_CLK" SNm="FB10_7_MC_CLK"/><Net IoT="none" NNm="FB11_6_MC_CLK" SNm="FB11_6_MC_CLK"/><Net IoT="none" NNm="FB13_4_MC_CLK" SNm="FB13_4_MC_CLK"/><Net IoT="none" NNm="FB24_2_MC_CLK" SNm="FB24_2_MC_CLK"/><Net IoT="in" Loc="FB13_4" NNm="add_p&lt;7&gt;" SNm="add_p&lt;7&gt;"/><Net IoT="none" NNm="FB3_15_MC_CLK" SNm="FB3_15_MC_CLK"/><Net IoT="none" NNm="FB4_14_MC_CLK" SNm="FB4_14_MC_CLK"/><Net IoT="none" NNm="FB7_11_MC_CLK" SNm="FB7_11_MC_CLK"/><Net IoT="none" NNm="FB10_8_MC_CLK" SNm="FB10_8_MC_CLK"/><Net IoT="none" NNm="FB10_10_OR" SNm="U1/q2_MC.D"/><Net IoT="none" NNm="FB11_7_MC_CLK" SNm="FB11_7_MC_CLK"/><Net IoT="none" NNm="FB13_5_MC_CLK" SNm="FB13_5_MC_CLK"/><Net IoT="none" NNm="FB14_4_MC_CLK" SNm="FB14_4_MC_CLK"/><Net IoT="in" Loc="FB2_15" NNm="add_p&lt;8&gt;" SNm="add_p&lt;8&gt;"/><Net IoT="none" NNm="FB3_16_MC_CLK" SNm="FB3_16_MC_CLK"/><Net IoT="none" NNm="FB4_15_MC_CLK" SNm="FB4_15_MC_CLK"/><Net IoT="none" NNm="FB5_14_MC_CLK" SNm="FB5_14_MC_CLK"/><Net IoT="none" NNm="FB9_10_MC_CLK" SNm="FB9_10_MC_CLK"/><Net IoT="none" NNm="FB10_9_MC_CLK" SNm="FB10_9_MC_CLK"/><Net IoT="none" NNm="FB11_8_MC_CLK" SNm="FB11_8_MC_CLK"/><Net IoT="none" NNm="FB11_10_OR" SNm="U5/jtag_num_bits&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB13_6_MC_CLK" SNm="FB13_6_MC_CLK"/><Net IoT="none" NNm="FB14_5_MC_CLK" SNm="FB14_5_MC_CLK"/><Net IoT="none" NNm="FB15_4_MC_CLK" SNm="FB15_4_MC_CLK"/><Net IoT="none" NNm="FB9_11_MC_CLK" SNm="FB9_11_MC_CLK"/><Net IoT="none" NNm="FB11_9_MC_CLK" SNm="FB11_9_MC_CLK"/><Net IoT="none" NNm="FB12_8_MC_CLK" SNm="FB12_8_MC_CLK"/><Net IoT="none" NNm="FB12_10_OR" SNm="U5/jtag_end_MC.D"/><Net IoT="none" NNm="FB13_7_MC_CLK" SNm="FB13_7_MC_CLK"/><Net IoT="none" NNm="FB19_1_MC_CLK" SNm="FB19_1_MC_CLK"/><Net IoT="none" NNm="FB6_15_MC_CLK" SNm="FB6_15_MC_CLK"/><Net IoT="none" NNm="FB12_9_MC_CLK" SNm="FB12_9_MC_CLK"/><Net IoT="none" NNm="FB12_11_OR" SNm="U5/jtag_shift_MC.D"/><Net IoT="none" NNm="FB13_8_MC_CLK" SNm="FB13_8_MC_CLK"/><Net IoT="none" NNm="FB13_10_OR" SNm="U5/tdi_bits&lt;5&gt;_MC.D"/><Net IoT="none" NNm="FB15_6_MC_CLK" SNm="FB15_6_MC_CLK"/><Net IoT="none" NNm="FB5_12_I" SNm="U5/cclk_freq&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB21_5_I" SNm="g245_mem_II/UIM"/><Net IoT="none" NNm="FB8_14_MC_CLK" SNm="FB8_14_MC_CLK"/><Net IoT="none" NNm="FB10_14_OR" SNm="U3/r8_MC.D"/><Net IoT="none" NNm="FB12_12_OR" SNm="flash_tck_p&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB13_9_MC_CLK" SNm="FB13_9_MC_CLK"/><Net IoT="none" NNm="FB13_11_OR" SNm="U5/tdi_bits&lt;6&gt;_MC.D"/><Net IoT="none" NNm="FB15_7_MC_CLK" SNm="FB15_7_MC_CLK"/><Net IoT="none" NNm="FB24_2_I" SNm="U5/cclk_freq&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB19_14_I" SNm="brd_sel_24_II/UIM"/><Net IoT="none" NNm="FB10_15_OR" SNm="dtack_int_MC.D"/><Net IoT="none" NNm="FB11_14_OR" SNm="U5/jtag_num_bits&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB12_13_OR" SNm="U5/flash_tck_MC.D"/><Net IoT="none" NNm="FB13_12_OR" SNm="U5/tdo_bits&lt;7&gt;_MC.D"/><Net IoT="none" NNm="FB14_11_OR" SNm="U5/bits_to_send&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB15_8_MC_CLK" SNm="FB15_8_MC_CLK"/><Net IoT="none" NNm="FB15_10_OR" SNm="U5/cuenta_prgm_0_0_MC.D"/><Net IoT="none" NNm="FB10_12_I" SNm="add_p&lt;0&gt;_II/UIM"/><Net IoT="none" NNm="FB19_13_I" SNm="brd_sel_16_II/UIM"/><Net IoT="none" NNm="FB8_4_I" SNm="U5/cclk_freq&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB8_16_MC_CLK" SNm="FB8_16_MC_CLK"/><Net IoT="none" NNm="FB12_14_OR" SNm="N_PZ_957"/><Net IoT="none" NNm="FB14_12_OR" SNm="ULED2/q1_MC.D"/><Net IoT="none" NNm="FB15_9_MC_CLK" SNm="FB15_9_MC_CLK"/><Net IoT="none" NNm="FB15_11_OR" SNm="U5/bits_to_send&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB23_12_OR" SNm="sel_tim_clk&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB10_13_I" SNm="add_p&lt;1&gt;_II/UIM"/><Net IoT="none" NNm="FB9_2_I" SNm="U5/int_vect&lt;5&gt;_MC.D"/><Net IoT="out" Loc="FB14_13" NNm="spare_led" SNm="spare_led"/><Net IoT="none" NNm="FB9_16_MC_CLK" SNm="FB9_16_MC_CLK"/><Net IoT="none" NNm="FB12_15_OR" SNm="N_PZ_1002"/><Net IoT="none" NNm="FB13_14_OR" SNm="U5/tdi_bits&lt;7&gt;_MC.D"/><Net IoT="none" NNm="FB17_10_OR" SNm="prgm_fpga&lt;4&gt;_MC.D"/><Net IoT="none" NNm="FB10_14_I" SNm="add_p&lt;2&gt;_II/UIM"/><Net IoT="none" NNm="FB8_3_I" SNm="U5/ena_rst_prgm_MC.D"/><Net IoT="none" NNm="FB12_16_OR" SNm="flash_tck_p&lt;5&gt;_MC.Q"/><Net IoT="none" NNm="FB13_15_OR" SNm="U5/jtag_start_MC.D"/><Net IoT="none" NNm="FB16_12_OR" SNm="U5/ena_evres_MC.D"/><Net IoT="none" NNm="FB17_11_OR" SNm="prgm_fpga&lt;3&gt;_MC.D"/><Net IoT="none" NNm="FB23_14_OR" SNm="sel_tim_clk&lt;1&gt;_MC.D"/><Net IoT="none" NNm="FB2_13_I" SNm="add_p&lt;3&gt;_II/UIM"/><Net IoT="none" NNm="FB10_15_Q" SNm="dtack_int_MC.Q"/><Net IoT="none" NNm="FB4_4_I" SNm="db&lt;15&gt;_II/UIM"/><Net IoT="none" NNm="FB14_15_OR" SNm="U5/not_sel_tim_reg_MC.D"/><Net IoT="none" NNm="FB15_14_OR" SNm="U5/bits_to_send&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB2_5_I" SNm="add_p&lt;4&gt;_II/UIM"/><Net IoT="none" NNm="FB19_16_I" SNm="dtack_mem_II/UIM"/><Net IoT="none" NNm="FB2_4_I" SNm="add_p&lt;5&gt;_II/UIM"/><Net IoT="none" NNm="FB15_16_OR" SNm="U5/int_vect&lt;7&gt;_MC.D"/><Net IoT="none" NNm="FB13_12_I" SNm="add_p&lt;6&gt;_II/UIM"/><Net IoT="none" NNm="FB1_4_I" SNm="U5/ros_w0_MC.D"/><Net IoT="none" NNm="FB16_16_OR" SNm="dtack_p_MC.Q"/><Net IoT="none" NNm="FB17_15_OR" SNm="prgm_fpga&lt;2&gt;_MC.D"/><Net IoT="none" NNm="FB13_4_I" SNm="add_p&lt;7&gt;_II/UIM"/><Net IoT="none" NNm="FB7_1_Q" SNm="cclk&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB2_15_I" SNm="add_p&lt;8&gt;_II/UIM"/><Net IoT="none" NNm="FB7_2_Q" SNm="cclk&lt;1&gt;_MC.Q"/><Net IoT="in" Loc="FB21_12" NNm="gol_ready" SNm="gol_ready"/><Net IoT="none" NNm="FB13_5_Q" SNm="U5/tdi_bits&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB7_3_Q" SNm="cclk&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB13_6_Q" SNm="U5/tdi_bits&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB7_4_Q" SNm="cclk&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB13_7_Q" SNm="U5/tdi_bits&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB7_5_Q" SNm="cclk&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB13_8_Q" SNm="U5/tdi_bits&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB13_9_Q" SNm="U5/tdi_bits&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB20_2_I" SNm="fl_tdi_r_MC.D"/><Net IoT="none" NNm="FB13_10_Q" SNm="U5/tdi_bits&lt;5&gt;_MC.Q"/><Net IoT="none" NNm="FB20_1_I" SNm="fl_tck_r_MC.D"/><Net IoT="none" NNm="FB13_11_Q" SNm="U5/tdi_bits&lt;6&gt;_MC.Q"/><Net IoT="in" Loc="FB17_14" NNm="sel_tim_p" SNm="sel_tim_p"/><Net IoT="none" NNm="FB9_8_Q" SNm="U5/tdo_bits&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB13_14_Q" SNm="U5/tdi_bits&lt;7&gt;_MC.Q"/><Net IoT="none" NNm="FB9_9_Q" SNm="U5/tdo_bits&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB9_10_Q" SNm="U5/tdo_bits&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB9_11_Q" SNm="U5/tdo_bits&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB9_16_Q" SNm="U5/tdo_bits&lt;4&gt;_MC.Q"/><Net IoT="none" NNm="FB2_14_Q" SNm="U5/int_vect&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB7_10_Q" SNm="U1/q444_MC.Q"/><Net IoT="none" NNm="FB13_2_Q" SNm="U5/tdo_bits&lt;5&gt;_MC.Q"/><Net IoT="none" NNm="FB13_1_Q" SNm="U5/tdo_bits&lt;6&gt;_MC.Q"/><Net IoT="none" NNm="FB2_12_Q" SNm="U5/int_vect&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB2_15_Q" SNm="U5/int_ena_rosw_MC.Q"/><Net IoT="none" NNm="FB13_12_Q" SNm="U5/tdo_bits&lt;7&gt;_MC.Q"/><Net IoT="none" NNm="FB21_12_I" SNm="gol_ready_II/UIM"/><Net IoT="none" NNm="FB2_11_Q" SNm="U5/int_vect&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB2_10_Q" SNm="U5/int_vect&lt;4&gt;_MC.Q"/><Net IoT="out" Loc="FB17_1" NNm="gol_reset" SNm="gol_reset"/><Net IoT="out" Loc="FB1_14" NNm="i2c_ce_gol" SNm="i2c_ce_gol"/><Net IoT="none" NNm="FB2_9_Q" SNm="U5/int_vect&lt;6&gt;_MC.Q"/><Net IoT="none" NNm="FB15_16_Q" SNm="U5/int_vect&lt;7&gt;_MC.Q"/><Net IoT="in" Loc="FB3_12" NNm="evcnt_res" SNm="evcnt_res"/><Net IoT="none" NNm="FB17_14_I" SNm="sel_tim_p_II/UIM"/><Net IoT="none" NNm="FB1_13_Q" SNm="fpga_init&lt;0&gt;_MC.UIM"/><Net IoT="none" NNm="FB11_10_Q" SNm="U5/jtag_num_bits&lt;0&gt;_MC.Q"/><Net IoT="none" NNm="FB4_12_Q" SNm="fpga_init&lt;1&gt;_MC.UIM"/><Net IoT="none" NNm="FB11_7_Q" SNm="U5/jtag_num_bits&lt;1&gt;_MC.Q"/><Net IoT="none" NNm="FB4_14_Q" SNm="fpga_init&lt;2&gt;_MC.UIM"/><Net IoT="none" NNm="FB20_3_I" SNm="fl_tms_r_MC.D"/><Net IoT="none" NNm="FB11_9_Q" SNm="U5/jtag_num_bits&lt;2&gt;_MC.Q"/><Net IoT="none" NNm="FB5_14_Q" SNm="fpga_init&lt;3&gt;_MC.UIM"/><Net IoT="none" NNm="FB11_14_Q" SNm="U5/jtag_num_bits&lt;3&gt;_MC.Q"/><Net IoT="none" NNm="FB6_3_Q" SNm="fpga_init&lt;4&gt;_MC.UIM"/><Net IoT="out" Loc="FB10_5" NNm="g245_p" SNm="g245_p"/><Net IoT="none" NNm="FB8_16_Q" SNm="ena_evres_prgm_MC.Q"/><Net IoT="in" Loc="FB19_12" NNm="as" SNm="as"/><Net IoT="none" NNm="FB10_10_MC_CLK" SNm="FB10_10_MC_CLK"/><Net IoT="none" NNm="FB10_11_MC_CLK" SNm="FB10_11_MC_CLK"/><Net IoT="none" NNm="FB11_10_MC_CLK" SNm="FB11_10_MC_CLK"/><Net IoT="none" NNm="FB11_11_MC_CLK" SNm="FB11_11_MC_CLK"/><Net IoT="none" NNm="FB12_10_MC_CLK" SNm="FB12_10_MC_CLK"/><Net IoT="out" Loc="FB2_16" NNm="on_244" SNm="on_244"/><Net IoT="none" NNm="FB12_11_MC_CLK" SNm="FB12_11_MC_CLK"/><Net IoT="none" NNm="FB13_10_MC_CLK" SNm="FB13_10_MC_CLK"/><Net IoT="out" Loc="FB16_16" NNm="dtack_p" SNm="dtack_p"/><Net IoT="none" NNm="FB10_14_MC_CLK" SNm="FB10_14_MC_CLK"/><Net IoT="none" NNm="FB11_13_MC_CLK" SNm="FB11_13_MC_CLK"/><Net IoT="none" NNm="FB13_11_MC_CLK" SNm="FB13_11_MC_CLK"/><Net IoT="none" NNm="FB3_12_I" SNm="evcnt_res_II/UIM"/><Net IoT="none" NNm="FB10_15_MC_CLK" SNm="FB10_15_MC_CLK"/><Net IoT="none" NNm="FB11_14_MC_CLK" SNm="FB11_14_MC_CLK"/><Net IoT="none" NNm="FB12_13_MC_CLK" SNm="FB12_13_MC_CLK"/><Net IoT="none" NNm="FB13_12_MC_CLK" SNm="FB13_12_MC_CLK"/><Net IoT="none" NNm="FB14_11_MC_CLK" SNm="FB14_11_MC_CLK"/><Net IoT="none" NNm="FB15_10_MC_CLK" SNm="FB15_10_MC_CLK"/><Net IoT="none" NNm="FB10_16_MC_CLK" SNm="FB10_16_MC_CLK"/><Net IoT="none" NNm="FB11_15_MC_CLK" SNm="FB11_15_MC_CLK"/><Net IoT="none" NNm="FB14_12_MC_CLK" SNm="FB14_12_MC_CLK"/><Net IoT="none" NNm="FB15_11_MC_CLK" SNm="FB15_11_MC_CLK"/><Net IoT="none" NNm="FB23_12_MC_CLK" SNm="FB23_12_MC_CLK"/><Net IoT="none" NNm="FB10_3_Q" SNm="ack_int_MC.Q"/><Net IoT="none" NNm="FB11_16_MC_CLK" SNm="FB11_16_MC_CLK"/><Net IoT="none" NNm="FB13_14_MC_CLK" SNm="FB13_14_MC_CLK"/><Net IoT="none" NNm="FB14_13_MC_CLK" SNm="FB14_13_MC_CLK"/><Net IoT="none" NNm="FB17_10_MC_CLK" SNm="FB17_10_MC_CLK"/><Net IoT="none" NNm="FB13_15_MC_CLK" SNm="FB13_15_MC_CLK"/><Net IoT="none" NNm="FB16_12_MC_CLK" SNm="FB16_12_MC_CLK"/><Net IoT="none" NNm="FB17_11_MC_CLK" SNm="FB17_11_MC_CLK"/><Net IoT="none" NNm="FB23_14_MC_CLK" SNm="FB23_14_MC_CLK"/><Net IoT="none" NNm="PT_GND" SNm="U5/cclk_counter&lt;0&gt;_MC.D"/><Net IoT="none" NNm="FB14_15_MC_CLK" SNm="FB14_15_MC_CLK"/><Net IoT="none" NNm="FB15_14_MC_CLK" SNm="FB15_14_MC_CLK"/><Net IoT="out" Loc="FB4_15" NNm="gol_off" SNm="gol_off"/><Net IoT="none" NNm="FB4_13_Q" SNm="i2c_ce_1wire_MC.UIM"/><Net IoT="none" NNm="FB15_16_MC_CLK" SNm="FB15_16_MC_CLK"/><Net IoT="none" NNm="FB12_11_Q" SNm="U5/jtag_shift_MC.Q"/><Net IoT="none" NNm="FB17_15_MC_CLK" SNm="FB17_15_MC_CLK"/><Net IoT="none" NNm="FB19_12_I" SNm="as_II/UIM"/><Net IoT="none" NNm="FB12_1_Q" SNm="fl_tdo_MC.Q"/><Net IoT="in" Loc="FB1_15" NNm="sff&lt;0&gt;" SNm="sff&lt;0&gt;"/><Net IoT="in" Loc="FB1_16" NNm="sff&lt;1&gt;" SNm="sff&lt;1&gt;"/><Net IoT="in" Loc="FB4_16" NNm="sff&lt;2&gt;" SNm="sff&lt;2&gt;"/><Net IoT="in" Loc="FB22_3" NNm="sff&lt;3&gt;" SNm="sff&lt;3&gt;"/><Net IoT="none" NNm="FB1_2_Q" SNm="U5/mem_d0_MC.Q"/><Net IoT="none" NNm="FB1_PT0" SNm="FB1_PT0"/><Net IoT="in" Loc="FB22_4" NNm="sff&lt;4&gt;" SNm="sff&lt;4&gt;"/><Net IoT="none" NNm="FB1_PT1" SNm="FB1_PT1"/><Net IoT="none" NNm="FB2_PT0" SNm="FB2_PT0"/><Net IoT="none" NNm="FB1_PT2" SNm="FB1_PT2"/><Net IoT="none" NNm="FB2_PT1" SNm="FB2_PT1"/><Net IoT="none" NNm="FB3_PT0" SNm="FB3_PT0"/><Net IoT="none" NNm="FB13_15_Q" SNm="U5/jtag_start_MC.Q"/><Net IoT="none" NNm="FB1_PT3" SNm="FB1_PT3"/><Net IoT="none" NNm="FB2_PT2" SNm="FB2_PT2"/><Net IoT="none" NNm="FB3_PT1" SNm="FB3_PT1"/><Net IoT="none" NNm="FB4_PT0" SNm="FB4_PT0"/><Net IoT="none" NNm="FB1_PT4" SNm="FB1_PT4"/><Net IoT="none" NNm="FB2_PT3" SNm="FB2_PT3"/><Net IoT="none" NNm="FB3_PT2" SNm="FB3_PT2"/><Net IoT="none" NNm="FB4_PT1" SNm="FB4_PT1"/><Net IoT="none" NNm="FB5_PT0" SNm="FB5_PT0"/><Net IoT="none" NNm="FB1_PT5" SNm="FOOBAR1__ctinst/5"/><Net IoT="out" Loc="FB16_4" NNm="iackout" SNm="iackout"/><Net IoT="none" NNm="FB2_PT4" SNm="FB2_PT4"/><Net IoT="none" NNm="FB3_PT3" SNm="FB3_PT3"/><Net IoT="none" NNm="FB4_PT2" SNm="FB4_PT2"/><Net IoT="none" NNm="FB5_PT1" SNm="FB5_PT1"/><Net IoT="none" NNm="FB6_PT0" SNm="FB6_PT0"/><Net IoT="none" NNm="FB2_PT5" SNm="FOOBAR2__ctinst/5"/><Net IoT="none" NNm="FB1_PT6" SNm="FB1_PT6"/><Net IoT="none" NNm="FB3_PT4" SNm="FB3_PT4"/><Net IoT="none" NNm="FB4_PT3" SNm="FB4_PT3"/><Net IoT="none" NNm="FB5_PT2" SNm="FB5_PT2"/><Net IoT="none" NNm="FB6_PT1" SNm="FB6_PT1"/><Net IoT="none" NNm="FB7_PT0" SNm="FB7_PT0"/><Net IoT="none" NNm="FB3_PT5" SNm="FOOBAR3__ctinst/5"/><Net IoT="out" Loc="FB17_3" NNm="reset_p" SNm="reset_p"/><Net IoT="none" NNm="FB1_PT7" SNm="FB1_PT7"/><Net IoT="none" NNm="FB2_PT6" SNm="FB2_PT6"/><Net IoT="none" NNm="FB4_PT4" SNm="FB4_PT4"/><Net IoT="none" NNm="FB5_PT3" SNm="FB5_PT3"/><Net IoT="none" NNm="FB6_PT2" SNm="FB6_PT2"/><Net IoT="none" NNm="FB7_PT1" SNm="FB7_PT1"/><Net IoT="none" NNm="FB8_PT0" SNm="FB8_PT0"/><Net IoT="none" NNm="FB4_PT5" SNm="FOOBAR4__ctinst/5"/><Net IoT="none" NNm="FB1_PT8" SNm="FB1_PT8"/><Net IoT="none" NNm="FB2_PT7" SNm="FB2_PT7"/><Net IoT="none" NNm="FB3_PT6" SNm="FB3_PT6"/><Net IoT="none" NNm="FB5_PT4" SNm="FB5_PT4"/><Net IoT="none" NNm="FB6_PT3" SNm="FB6_PT3"/><Net IoT="none" NNm="FB7_PT2" SNm="FB7_PT2"/><Net IoT="none" NNm="FB8_PT1" SNm="FB8_PT1"/><Net IoT="none" NNm="FB9_PT0" SNm="FB9_PT0"/><Net IoT="none" NNm="FB5_PT5" SNm="FOOBAR5__ctinst/5"/><Net IoT="none" NNm="FB4_PT6" SNm="FOOBAR4__ctinst/6"/><Net IoT="out" Loc="FB2_2" NNm="i2c_ce_p" SNm="i2c_ce_p"/><Net IoT="none" NNm="FB1_PT9" SNm="FB1_PT9"/><Net IoT="none" NNm="FB2_PT8" SNm="FB2_PT8"/><Net IoT="none" NNm="FB3_PT7" SNm="FB3_PT7"/><Net IoT="none" NNm="FB6_PT4" SNm="FB6_PT4"/><Net IoT="none" NNm="FB7_PT3" SNm="FB7_PT3"/><Net IoT="none" NNm="FB8_PT2" SNm="FB8_PT2"/><Net IoT="none" NNm="FB9_PT1" SNm="FB9_PT1"/><Net IoT="none" NNm="FB1_15_I" SNm="sff&lt;0&gt;_II/UIM"/><Net IoT="none" NNm="FB6_PT5" SNm="FOOBAR6__ctinst/5"/><Net IoT="none" NNm="FB2_PT9" SNm="FB2_PT9"/><Net IoT="none" NNm="FB3_PT8" SNm="FB3_PT8"/><Net IoT="none" NNm="FB4_PT7" SNm="FB4_PT7"/><Net IoT="none" NNm="FB5_PT6" SNm="FB5_PT6"/><Net IoT="none" NNm="FB7_PT4" SNm="FB7_PT4"/><Net IoT="none" NNm="FB8_PT3" SNm="FB8_PT3"/><Net IoT="none" NNm="FB9_PT2" SNm="FB9_PT2"/><Net IoT="none" NNm="FB1_16_I" SNm="sff&lt;1&gt;_II/UIM"/><Net IoT="none" NNm="FB12_10_Q" SNm="U5/jtag_end_MC.Q"/><Net IoT="none" NNm="FB6_PT6" SNm="FOOBAR6__ctinst/6"/><Net IoT="out" Loc="FB11_1" NNm="irq&lt;1&gt;" SNm="irq&lt;1&gt;"/><Net IoT="none" NNm="FB7_PT5" SNm="FOOBAR7__ctinst/5"/><Net IoT="none" NNm="FB3_PT9" SNm="FB3_PT9"/><Net IoT="none" NNm="FB4_PT8" SNm="FB4_PT8"/><Net IoT="none" NNm="FB5_PT7" SNm="FB5_PT7"/><Net IoT="none" NNm="FB8_PT4" SNm="FB8_PT4"/><Net IoT="none" NNm="FB9_PT3" SNm="FB9_PT3"/><Net IoT="none" NNm="FB4_16_I" SNm="sff&lt;2&gt;_II/UIM"/><Net IoT="none" NNm="FB8_PT5" SNm="FOOBAR8__ctinst/5"/><Net IoT="out" Loc="FB11_3" NNm="irq&lt;2&gt;" SNm="irq&lt;2&gt;"/><Net IoT="none" NNm="FB14_15_Q" SNm="U5/not_sel_tim_reg_MC.Q"/><Net IoT="none" NNm="FB4_PT9" SNm="FB4_PT9"/><Net IoT="none" NNm="FB5_PT8" SNm="FB5_PT8"/><Net IoT="none" NNm="FB6_PT7" SNm="FB6_PT7"/><Net IoT="none" NNm="FB7_PT6" SNm="FB7_PT6"/><Net IoT="none" NNm="FB9_PT4" SNm="FB9_PT4"/><Net IoT="none" NNm="FB22_3_I" SNm="sff&lt;3&gt;_II/UIM"/><Net IoT="none" NNm="FB8_PT6" SNm="FOOBAR8__ctinst/6"/><Net IoT="none" NNm="FB9_PT5" SNm="FOOBAR9__ctinst/5"/><Net IoT="out" Loc="FB11_4" NNm="irq&lt;3&gt;" SNm="irq&lt;3&gt;"/><Net IoT="none" NNm="FB5_PT9" SNm="FB5_PT9"/><Net IoT="none" NNm="FB6_PT8" SNm="FB6_PT8"/><Net IoT="none" NNm="FB7_PT7" SNm="FB7_PT7"/><Net IoT="none" NNm="FB22_4_I" SNm="sff&lt;4&gt;_II/UIM"/><Net IoT="none" NNm="FB9_PT6" SNm="FOOBAR9__ctinst/6"/><Net IoT="out" Loc="FB11_5" NNm="irq&lt;4&gt;" SNm="irq&lt;4&gt;"/><Net IoT="none" NNm="FB6_PT9" SNm="FB6_PT9"/><Net IoT="none" NNm="FB7_PT8" SNm="FB7_PT8"/><Net IoT="none" NNm="FB8_PT7" SNm="FB8_PT7"/><Net IoT="out" Loc="FB11_12" NNm="irq&lt;5&gt;" SNm="irq&lt;5&gt;"/><Net IoT="none" NNm="FB7_PT9" SNm="FB7_PT9"/><Net IoT="none" NNm="FB8_PT8" SNm="FB8_PT8"/><Net IoT="none" NNm="FB9_PT7" SNm="FB9_PT7"/><Net IoT="out" Loc="FB18_2" NNm="irq&lt;6&gt;" SNm="irq&lt;6&gt;"/><Net IoT="none" NNm="FB8_PT9" SNm="FB8_PT9"/><Net IoT="none" NNm="FB9_PT8" SNm="FB9_PT8"/><Net IoT="out" Loc="FB18_3" NNm="irq&lt;7&gt;" SNm="irq&lt;7&gt;"/><Net IoT="none" NNm="FB9_PT9" SNm="FB9_PT9"/><Globals><GlblBuf Nm="GCK1" GType="GCK"><IPort NNm="FB7_12_I"/></GlblBuf><GlblBuf Nm="GCK0" GType="GCK"><IPort NNm="FB7_15_I"/></GlblBuf><GlblBuf Nm="GOE0" GType="GOE"><IPort NNm="FB2_5_OR"/></GlblBuf><GlblBuf Nm="GSR" GType="GSR"><IPort NNm="FB1_3_I"/></GlblBuf></Globals><Lb Nm="FB1"><LbT Nm="FB1_PT0" PtT="XBR_CT_X"><OPort NNm="FB1_PT0"/><IPort NNm="FB5_4_I"/><IPort NNm="FB4_1_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB1_PT1" PtT="XBR_CT_X"><OPort NNm="FB1_PT1"/><IPort NNm="FB5_PT40"/><IPort NNm="FB1_14_Q"/></LbT><LbT Nm="FB1_PT2" PtT="XBR_CT_X"><OPort NNm="FB1_PT2"/><IPort NNm="FB4_1_I"/></LbT><LbT Nm="FB1_PT3" PtT="XBR_CT_X"><OPort NNm="FB1_PT3"/><IPort NNm="FB10_13_I"/><IPort NNm="FB1_11_Q"/></LbT><LbT Nm="FB1_PT4" PtT="XBR_CT"><OPort NNm="FB1_PT4"/><IPort NNm="FB10_12_I"/><IPort NNm="FB1_11_Q"/></LbT><LbT Nm="FB1_PT5" PtT="XBR_CT"><OPort NNm="FB1_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB1_PT6" PtT="XBR_CT"><OPort NNm="FB1_PT6"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_4_I"/><IPort NNm="FB4_1_I"/><IPort NNm="FB6_1_I"/><IPort NNm="FB8_1_I"/><IPort NNm="FB6_16_I"/><IPort NNm="FB9_1_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT7" PtT="XBR_CT"><OPort NNm="FB1_PT7"/><IPort NNm="FB1_11_Q"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT8" PtT="XBR_A"><OPort NNm="FB1_PT8"/><IPort NNm="FB10_13_I"/><IPort NNm="FB1_10_Q"/></LbT><LbT Nm="FB1_PT9" PtT="XBR_B"><OPort NNm="FB1_PT9"/><IPort NNm="FB10_12_I"/><IPort NNm="FB1_10_Q"/></LbT><LbT Nm="FB1_PT10" PtT="XBR_C"><OPort NNm="FB1_PT10"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_4_I"/><IPort NNm="FB4_1_I"/><IPort NNm="FB6_1_I"/><IPort NNm="FB8_1_I"/><IPort NNm="FB6_16_I"/><IPort NNm="FB9_1_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT11" PtT="XBR_A"><OPort NNm="FB1_PT11"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT12" PtT="XBR_B"><OPort NNm="FB1_PT12"/><IPort NNm="FB1_9_Q"/><IPort NNm="FB1_16_OR"/></LbT><LbT Nm="FB1_PT13" PtT="XBR_C"><OPort NNm="FB1_PT13"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB4_1_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT14" PtT="XBR_A"><OPort NNm="FB1_PT14"/><IPort NNm="FB1_8_Q"/><IPort NNm="FB1_16_OR"/></LbT><LbT Nm="FB1_PT15" PtT="XBR_B"><OPort NNm="FB1_PT15"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_4_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT16" PtT="XBR_C"><OPort NNm="FB1_PT16"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB1_16_OR"/></LbT><LbT Nm="FB1_PT17" PtT="XBR_A"><OPort NNm="FB1_PT17"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB6_1_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT18" PtT="XBR_B"><OPort NNm="FB1_PT18"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB1_16_OR"/></LbT><LbT Nm="FB1_PT19" PtT="XBR_C"><OPort NNm="FB1_PT19"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB8_1_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT20" PtT="XBR_A"><OPort NNm="FB1_PT20"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB21_3_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB1_PT21" PtT="XBR_B"><OPort NNm="FB1_PT21"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB1_11_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB21_2_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB1_PT22" PtT="XBR_C"><OPort NNm="FB1_PT22"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB20_4_I"/><IPort NNm="FB1_9_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB1_PT23" PtT="XBR_A"><OPort NNm="FB1_PT23"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB1_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB20_5_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB1_PT24" PtT="XBR_B"><OPort NNm="FB1_PT24"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB20_13_I"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB1_PT25" PtT="XBR_C"><OPort NNm="FB1_PT25"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB21_1_I"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB1_PT26" PtT="XBR_A"><OPort NNm="FB1_PT26"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB1_11_Q"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB1_PT27" PtT="XBR_B"><OPort NNm="FB1_PT27"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB1_PT28" PtT="XBR_C"><OPort NNm="FB1_PT28"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB1_PT29" PtT="XBR_A"><OPort NNm="FB1_PT29"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB1_PT30" PtT="XBR_B"><OPort NNm="FB1_PT30"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB13_15_Q"/></LbT><LbT Nm="FB1_PT31" PtT="XBR_C"><OPort NNm="FB1_PT31"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB1_PT32" PtT="XBR_A"><OPort NNm="FB1_PT32"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB1_PT33" PtT="XBR_B"><OPort NNm="FB1_PT33"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB1_PT46" PtT="XBR_C"><OPort NNm="FB1_PT46"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB1_PT55" PtT="XBR_C"><OPort NNm="FB1_PT55"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB1_11_Q"/></LbT><Mc Nm="FB1_1"><RMux Nm="FB1_1_RST"><IPort NNm="FB1_3_I"/></RMux><ClkMux Nm="FB1_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_1_MC_CLK"/></ClkMux><FbMux Nm="FB1_1_N"><IPort NNm="FB1_1_Q"/></FbMux><FbMux Nm="FB1_1_P"><IPort NNm="FB1_1_I"/></FbMux><InBuf Nm="FB1_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="ds0"/><OPort NNm="FB1_1_I"/></InBuf><DFlop Nm="FB1_1_FF"><FlopPort NNm="FB1_1_I" Port="D"/><FlopPort NNm="FB1_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_1_Q" Port="Q"/><FlopPort NNm="FB1_3_I" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_2"><RMux Nm="FB1_2_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_2_MC_CLK"/></ClkMux><FbMux Nm="FB1_2_N"><IPort NNm="FB1_2_Q"/></FbMux><FbMux Nm="FB1_2_P"><IPort NNm="FB1_2_I"/></FbMux><InBuf Nm="FB1_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="mem_done"/><OPort NNm="FB1_2_I"/></InBuf><DFlop Nm="FB1_2_FF"><FlopPort NNm="FB1_2_I" Port="D"/><FlopPort NNm="FB1_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_2_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_3"><RMux Nm="FB1_3_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_3_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_3_MC_CLK"/></ClkMux><FbMux Nm="FB1_3_N"><IPort NNm="FB1_3_Q"/></FbMux><InBuf Nm="FB1_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sysreset"/><OPort NNm="FB1_3_I"/></InBuf><DFlop Nm="FB1_3_FF"><FlopPort NNm="FB1_3_OR" Port="D"/><FlopPort NNm="FB1_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_3_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_3_OR"><OPort NNm="FB1_3_OR"/><IPort NNm="FB1_PT33"/><IPort NNm="FB1_PT32"/><IPort NNm="FB1_PT31"/><IPort NNm="FB1_PT30"/></Or></Mc><Mc Nm="FB1_4"><RMux Nm="FB1_4_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_4_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_4_MC_CLK"/></ClkMux><FbMux Nm="FB1_4_N"><IPort NNm="FB1_4_Q"/></FbMux><FbMux Nm="FB1_4_P"><IPort NNm="FB1_4_I"/></FbMux><InBuf Nm="FB1_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="ros_waiting"/><OPort NNm="FB1_4_I"/></InBuf><DFlop Nm="FB1_4_FF"><FlopPort NNm="FB1_4_I" Port="D"/><FlopPort NNm="FB1_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_4_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_5"><FbMux Nm="FB1_5_N"><IPort NNm="FB1_5_OR"/></FbMux><Or Nm="FB1_5_OR"><OPort NNm="FB1_5_OR"/><IPort NNm="FB1_PT23"/><IPort NNm="FB1_PT20"/><IPort NNm="FB1_PT21"/><IPort NNm="FB1_PT22"/><IPort NNm="FB1_PT24"/><IPort NNm="FB1_PT25"/></Or></Mc><Mc Nm="FB1_6"><RMux Nm="FB1_6_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_6_MC_CLK"/></ClkMux><FbMux Nm="FB1_6_N"><IPort NNm="FB1_6_Q"/></FbMux><DFlop Nm="FB1_6_FF"><FlopPort NNm="FB1_6_OR" Port="D"/><FlopPort NNm="FB1_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_6_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_6_OR"><OPort NNm="FB1_6_OR"/><IPort NNm="FB1_PT18"/><IPort NNm="FB1_PT19"/></Or></Mc><Mc Nm="FB1_7"><RMux Nm="FB1_7_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_7_MC_CLK"/></ClkMux><FbMux Nm="FB1_7_N"><IPort NNm="FB1_7_Q"/></FbMux><DFlop Nm="FB1_7_FF"><FlopPort NNm="FB1_7_OR" Port="D"/><FlopPort NNm="FB1_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_7_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_7_OR"><OPort NNm="FB1_7_OR"/><IPort NNm="FB1_PT16"/><IPort NNm="FB1_PT17"/></Or></Mc><Mc Nm="FB1_8"><RMux Nm="FB1_8_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_8_MC_CLK"/></ClkMux><FbMux Nm="FB1_8_N"><IPort NNm="FB1_8_Q"/></FbMux><DFlop Nm="FB1_8_FF"><FlopPort NNm="FB1_8_OR" Port="D"/><FlopPort NNm="FB1_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_8_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_8_OR"><OPort NNm="FB1_8_OR"/><IPort NNm="FB1_PT14"/><IPort NNm="FB1_PT15"/></Or></Mc><Mc Nm="FB1_9"><RMux Nm="FB1_9_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_9_MC_CLK"/></ClkMux><FbMux Nm="FB1_9_N"><IPort NNm="FB1_9_Q"/></FbMux><DFlop Nm="FB1_9_FF"><FlopPort NNm="FB1_9_OR" Port="D"/><FlopPort NNm="FB1_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_9_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_9_OR"><OPort NNm="FB1_9_OR"/><IPort NNm="FB1_PT12"/><IPort NNm="FB1_PT13"/></Or></Mc><Mc Nm="FB1_10"><RMux Nm="FB1_10_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_10_MC_CLK"/></ClkMux><FbMux Nm="FB1_10_N"><IPort NNm="FB1_10_Q"/></FbMux><DFlop Nm="FB1_10_FF"><FlopPort NNm="FB1_10_OR" Port="D"/><FlopPort NNm="FB1_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_10_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_10_OR"><OPort NNm="FB1_10_OR"/><IPort NNm="FB1_PT8"/><IPort NNm="FB1_PT9"/><IPort NNm="FB1_PT11"/><IPort NNm="FB1_PT10"/></Or></Mc><Mc Nm="FB1_11"><RMux Nm="FB1_11_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_11_MC_CLK"/></ClkMux><FbMux Nm="FB1_11_N"><IPort NNm="FB1_11_Q"/></FbMux><DFlop Nm="FB1_11_FF"><FlopPort NNm="FB1_11_OR" Port="D"/><FlopPort NNm="FB1_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_11_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_11_OR"><OPort NNm="FB1_11_OR"/><IPort NNm="FB1_PT3"/><IPort NNm="FB1_PT4"/><IPort NNm="FB1_PT7"/><IPort NNm="FB1_PT6"/></Or></Mc><Mc Nm="FB1_12"><InBuf Nm="FB1_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cspare_8"/></InBuf><OutBuf Nm="FB1_12_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="cspare_8"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB1_13"><RMux Nm="FB1_13_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_13_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_13_MC_CLK"/></ClkMux><FbMux Nm="FB1_13_N"><IPort NNm="FB1_13_Q"/></FbMux><InBuf Nm="FB1_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_init&lt;0&gt;"/></InBuf><OutBuf Nm="FB1_13_O" IOS="LVCMOS33"><IPort NNm="FB1_13_Q"/><OPort NNm="fpga_init&lt;0&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_13_FF"><FlopPort NNm="FB1_13_OR" Port="D"/><FlopPort NNm="FB1_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_13_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB1_PT46" Port="CE"/></DFlop><Or Nm="FB1_13_OR"><OPort NNm="FB1_13_OR"/><IPort NNm="FB1_PT2"/></Or></Mc><Mc Nm="FB1_14"><RMux Nm="FB1_14_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_14_MC_CLK"/></ClkMux><FbMux Nm="FB1_14_N"><IPort NNm="FB1_14_Q"/></FbMux><InBuf Nm="FB1_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="i2c_ce_gol"/></InBuf><OutBuf Nm="FB1_14_O" IOS="LVCMOS33"><IPort NNm="FB1_14_Q"/><OPort NNm="i2c_ce_gol"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_14_FF"><FlopPort NNm="FB1_14_OR" Port="D"/><FlopPort NNm="FB1_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_14_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_14_OR"><OPort NNm="FB1_14_OR"/><IPort NNm="FB1_PT1"/><IPort NNm="FB1_PT0"/></Or></Mc><Mc Nm="FB1_15"><RMux Nm="FB1_15_RST"><IPort NNm="FB1_PT5"/></RMux><ClkMux Nm="FB1_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB1_15_MC_CLK"/></ClkMux><FbMux Nm="FB1_15_N"><IPort NNm="FB1_15_Q"/></FbMux><FbMux Nm="FB1_15_P"><IPort NNm="FB1_15_I"/></FbMux><InBuf Nm="FB1_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sff&lt;0&gt;"/><OPort NNm="FB1_15_I"/></InBuf><DFlop Nm="FB1_15_FF"><FlopPort NNm="FB1_15_OR" Port="D"/><FlopPort NNm="FB1_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_15_Q" Port="Q"/><FlopPort NNm="FB1_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_15_OR"><OPort NNm="FB1_15_OR"/><IPort NNm="FB1_PT29"/><IPort NNm="FB1_PT27"/><IPort NNm="FB1_PT28"/></Or></Mc><Mc Nm="FB1_16"><XorMux Nm="FB1_16_AND"><IPort NNm="FB1_16_OR"/></XorMux><FbMux Nm="FB1_16_N"><IPort NNm="FB1_16_OR"/></FbMux><FbMux Nm="FB1_16_P"><IPort NNm="FB1_16_I"/></FbMux><InBuf Nm="FB1_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sff&lt;1&gt;"/><OPort NNm="FB1_16_I"/></InBuf><Or Nm="FB1_16_OR"><OPort NNm="FB1_16_OR"/><IPort NNm="FB1_PT26"/><IPort NNm="FB1_PT55"/></Or></Mc></Lb><Lb Nm="FB2"><LbT Nm="FB2_PT0" PtT="XBR_CT_X"><OPort NNm="FB2_PT0"/><IPort NNm="FB4_3_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB2_PT1" PtT="XBR_CT_X"><OPort NNm="FB2_PT1"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB2_PT2" PtT="XBR_CT_X"><OPort NNm="FB2_PT2"/><IPort NNm="FB2_4_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB19_1_Q"/></LbT><LbT Nm="FB2_PT3" PtT="XBR_CT_X"><OPort NNm="FB2_PT3"/><IPort NNm="FB2_5_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB19_1_Q"/></LbT><LbT Nm="FB2_PT4" PtT="XBR_CT"><OPort NNm="FB2_PT4"/><IPort NNm="FB2_13_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB19_1_Q"/></LbT><LbT Nm="FB2_PT5" PtT="XBR_CT"><OPort NNm="FB2_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB2_PT6" PtT="XBR_CT"><OPort NNm="FB2_PT6"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB19_1_Q"/></LbT><LbT Nm="FB2_PT7" PtT="XBR_CT"><OPort NNm="FB2_PT7"/><IPort NNm="FB10_3_Q"/></LbT><LbT Nm="FB2_PT8" PtT="XBR_A"><OPort NNm="FB2_PT8"/><IPort NNm="FB4_3_I"/></LbT><LbT Nm="FB2_PT9" PtT="XBR_B"><OPort NNm="FB2_PT9"/><IPort NNm="FB5_12_I"/></LbT><LbT Nm="FB2_PT10" PtT="XBR_C"><OPort NNm="FB2_PT10"/><IPort NNm="FB24_2_I"/></LbT><LbT Nm="FB2_PT11" PtT="XBR_A"><OPort NNm="FB2_PT11"/><IPort NNm="FB8_4_I"/></LbT><LbT Nm="FB2_PT12" PtT="XBR_B"><OPort NNm="FB2_PT12"/><IPort NNm="FB8_3_I"/></LbT><LbT Nm="FB2_PT13" PtT="XBR_C"><OPort NNm="FB2_PT13"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><LbT Nm="FB2_PT14" PtT="XBR_A"><OPort NNm="FB2_PT14"/><IPort NNm="FB8_2_I"/></LbT><LbT Nm="FB2_PT15" PtT="XBR_B"><OPort NNm="FB2_PT15"/><IPort NNm="FB4_5_I"/></LbT><LbT Nm="FB2_PT16" PtT="XBR_C"><OPort NNm="FB2_PT16"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_6_Q"/></LbT><LbT Nm="FB2_PT17" PtT="XBR_A"><OPort NNm="FB2_PT17"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB2_6_Q"/><IPort NNm="FB6_1_I"/></LbT><LbT Nm="FB2_PT18" PtT="XBR_B"><OPort NNm="FB2_PT18"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_6_Q"/><IPort NNm="FB6_1_I"/></LbT><LbT Nm="FB2_PT19" PtT="XBR_C"><OPort NNm="FB2_PT19"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_15_Q"/></LbT><LbT Nm="FB2_PT20" PtT="XBR_A"><OPort NNm="FB2_PT20"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB2_15_Q"/><IPort NNm="FB8_1_I"/></LbT><LbT Nm="FB2_PT21" PtT="XBR_B"><OPort NNm="FB2_PT21"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_15_Q"/><IPort NNm="FB8_1_I"/></LbT><LbT Nm="FB2_PT22" PtT="XBR_C"><OPort NNm="FB2_PT22"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_13_Q"/></LbT><LbT Nm="FB2_PT23" PtT="XBR_A"><OPort NNm="FB2_PT23"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB2_13_Q"/><IPort NNm="FB5_4_I"/></LbT><LbT Nm="FB2_PT24" PtT="XBR_B"><OPort NNm="FB2_PT24"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_13_Q"/><IPort NNm="FB5_4_I"/></LbT><LbT Nm="FB2_PT25" PtT="XBR_C"><OPort NNm="FB2_PT25"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_4_Q"/></LbT><LbT Nm="FB2_PT26" PtT="XBR_A"><OPort NNm="FB2_PT26"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB2_4_Q"/><IPort NNm="FB4_1_I"/></LbT><LbT Nm="FB2_PT27" PtT="XBR_B"><OPort NNm="FB2_PT27"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_4_Q"/><IPort NNm="FB4_1_I"/></LbT><LbT Nm="FB2_PT28" PtT="XBR_C"><OPort NNm="FB2_PT28"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB2_PT31" PtT="XBR_C"><OPort NNm="FB2_PT31"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB2_PT34" PtT="XBR_C"><OPort NNm="FB2_PT34"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB2_PT37" PtT="XBR_C"><OPort NNm="FB2_PT37"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB2_PT40" PtT="XBR_C"><OPort NNm="FB2_PT40"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB2_PT43" PtT="XBR_C"><OPort NNm="FB2_PT43"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB2_PT49" PtT="XBR_C"><OPort NNm="FB2_PT49"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><Mc Nm="FB2_1"><InBuf Nm="FB2_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="qpll_reset"/></InBuf><OutBuf Nm="FB2_1_O" IOS="LVCMOS33"><IPort NNm="FB2_1_OR"/><OPort NNm="qpll_reset"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB2_1_OR"><OPort NNm="FB2_1_OR"/><IPort NNm="FB2_PT1"/><IPort NNm="FB2_PT0"/></Or></Mc><Mc Nm="FB2_2"><XorMux Nm="FB2_2_AND"><IPort NNm="FB2_PT13"/></XorMux><FbMux Nm="FB2_2_N"><IPort NNm="FB2_PT13"/></FbMux><InBuf Nm="FB2_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="i2c_ce_p"/></InBuf><OutBuf Nm="FB2_2_O" IOS="LVCMOS33"><IPort NNm="FB2_PT13"/><OPort NNm="i2c_ce_p"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB2_3"><InBuf Nm="FB2_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cspare_9"/></InBuf><OutBuf Nm="FB2_3_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="cspare_9"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB2_4"><RMux Nm="FB2_4_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_4_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_4_MC_CLK"/></ClkMux><FbMux Nm="FB2_4_N"><IPort NNm="FB2_4_Q"/></FbMux><FbMux Nm="FB2_4_P"><IPort NNm="FB2_4_I"/></FbMux><InBuf Nm="FB2_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;5&gt;"/><OPort NNm="FB2_4_I"/></InBuf><DFlop Nm="FB2_4_FF"><FlopPort NNm="FB2_4_OR" Port="D"/><FlopPort NNm="FB2_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_4_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB2_4_OR"><OPort NNm="FB2_4_OR"/><IPort NNm="FB2_PT25"/><IPort NNm="FB2_PT26"/><IPort NNm="FB2_PT27"/></Or></Mc><Mc Nm="FB2_5"><FbMux Nm="FB2_5_P"><IPort NNm="FB2_5_I"/></FbMux><InBuf Nm="FB2_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;4&gt;"/><OPort NNm="FB2_5_I"/></InBuf><Or Nm="FB2_5_OR"><OPort NNm="FB2_5_OR"/><IPort NNm="FB2_PT7"/><IPort NNm="FB2_PT2"/><IPort NNm="FB2_PT3"/><IPort NNm="FB2_PT4"/><IPort NNm="FB2_PT6"/></Or></Mc><Mc Nm="FB2_6"><RMux Nm="FB2_6_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_6_MC_CLK"/></ClkMux><FbMux Nm="FB2_6_N"><IPort NNm="FB2_6_Q"/></FbMux><DFlop Nm="FB2_6_FF"><FlopPort NNm="FB2_6_OR" Port="D"/><FlopPort NNm="FB2_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_6_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB2_6_OR"><OPort NNm="FB2_6_OR"/><IPort NNm="FB2_PT16"/><IPort NNm="FB2_PT17"/><IPort NNm="FB2_PT18"/></Or></Mc><Mc Nm="FB2_7"><RMux Nm="FB2_7_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_7_MC_CLK"/></ClkMux><FbMux Nm="FB2_7_N"><IPort NNm="FB2_7_Q"/></FbMux><DFlop Nm="FB2_7_FF"><FlopPort NNm="FB2_7_OR" Port="D"/><FlopPort NNm="FB2_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_7_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB2_PT28" Port="CE"/></DFlop><Or Nm="FB2_7_OR"><OPort NNm="FB2_7_OR"/><IPort NNm="FB2_PT15"/></Or></Mc><Mc Nm="FB2_8"><RMux Nm="FB2_8_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_8_MC_CLK"/></ClkMux><FbMux Nm="FB2_8_N"><IPort NNm="FB2_8_Q"/></FbMux><DFlop Nm="FB2_8_FF"><FlopPort NNm="FB2_8_OR" Port="D"/><FlopPort NNm="FB2_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_8_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB2_PT28" Port="CE"/></DFlop><Or Nm="FB2_8_OR"><OPort NNm="FB2_8_OR"/><IPort NNm="FB2_PT14"/></Or></Mc><Mc Nm="FB2_9"><RMux Nm="FB2_9_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_9_MC_CLK"/></ClkMux><FbMux Nm="FB2_9_N"><IPort NNm="FB2_9_Q"/></FbMux><DFlop Nm="FB2_9_FF"><FlopPort NNm="FB2_9_OR" Port="D"/><FlopPort NNm="FB2_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_9_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB2_PT28" Port="CE"/></DFlop><Or Nm="FB2_9_OR"><OPort NNm="FB2_9_OR"/><IPort NNm="FB2_PT12"/></Or></Mc><Mc Nm="FB2_10"><RMux Nm="FB2_10_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_10_MC_CLK"/></ClkMux><FbMux Nm="FB2_10_N"><IPort NNm="FB2_10_Q"/></FbMux><DFlop Nm="FB2_10_FF"><FlopPort NNm="FB2_10_OR" Port="D"/><FlopPort NNm="FB2_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_10_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB2_PT28" Port="CE"/></DFlop><Or Nm="FB2_10_OR"><OPort NNm="FB2_10_OR"/><IPort NNm="FB2_PT11"/></Or></Mc><Mc Nm="FB2_11"><RMux Nm="FB2_11_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_11_MC_CLK"/></ClkMux><FbMux Nm="FB2_11_N"><IPort NNm="FB2_11_Q"/></FbMux><DFlop Nm="FB2_11_FF"><FlopPort NNm="FB2_11_OR" Port="D"/><FlopPort NNm="FB2_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_11_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB2_PT28" Port="CE"/></DFlop><Or Nm="FB2_11_OR"><OPort NNm="FB2_11_OR"/><IPort NNm="FB2_PT10"/></Or></Mc><Mc Nm="FB2_12"><RMux Nm="FB2_12_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_12_MC_CLK"/></ClkMux><FbMux Nm="FB2_12_N"><IPort NNm="FB2_12_Q"/></FbMux><DFlop Nm="FB2_12_FF"><FlopPort NNm="FB2_12_OR" Port="D"/><FlopPort NNm="FB2_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_12_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB2_PT28" Port="CE"/></DFlop><Or Nm="FB2_12_OR"><OPort NNm="FB2_12_OR"/><IPort NNm="FB2_PT9"/></Or></Mc><Mc Nm="FB2_13"><RMux Nm="FB2_13_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_13_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_13_MC_CLK"/></ClkMux><FbMux Nm="FB2_13_N"><IPort NNm="FB2_13_Q"/></FbMux><FbMux Nm="FB2_13_P"><IPort NNm="FB2_13_I"/></FbMux><InBuf Nm="FB2_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;3&gt;"/><OPort NNm="FB2_13_I"/></InBuf><DFlop Nm="FB2_13_FF"><FlopPort NNm="FB2_13_OR" Port="D"/><FlopPort NNm="FB2_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_13_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB2_13_OR"><OPort NNm="FB2_13_OR"/><IPort NNm="FB2_PT22"/><IPort NNm="FB2_PT23"/><IPort NNm="FB2_PT24"/></Or></Mc><Mc Nm="FB2_14"><RMux Nm="FB2_14_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_14_MC_CLK"/></ClkMux><FbMux Nm="FB2_14_N"><IPort NNm="FB2_14_Q"/></FbMux><DFlop Nm="FB2_14_FF"><FlopPort NNm="FB2_14_OR" Port="D"/><FlopPort NNm="FB2_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_14_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB2_PT28" Port="CE"/></DFlop><Or Nm="FB2_14_OR"><OPort NNm="FB2_14_OR"/><IPort NNm="FB2_PT8"/></Or></Mc><Mc Nm="FB2_15"><RMux Nm="FB2_15_RST"><IPort NNm="FB2_PT5"/></RMux><ClkMux Nm="FB2_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB2_15_MC_CLK"/></ClkMux><FbMux Nm="FB2_15_N"><IPort NNm="FB2_15_Q"/></FbMux><FbMux Nm="FB2_15_P"><IPort NNm="FB2_15_I"/></FbMux><InBuf Nm="FB2_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;8&gt;"/><OPort NNm="FB2_15_I"/></InBuf><DFlop Nm="FB2_15_FF"><FlopPort NNm="FB2_15_OR" Port="D"/><FlopPort NNm="FB2_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_15_Q" Port="Q"/><FlopPort NNm="FB2_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB2_15_OR"><OPort NNm="FB2_15_OR"/><IPort NNm="FB2_PT19"/><IPort NNm="FB2_PT20"/><IPort NNm="FB2_PT21"/></Or></Mc><Mc Nm="FB2_16"><InBuf Nm="FB2_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="on_244"/></InBuf><OutBuf Nm="FB2_16_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="on_244"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc></Lb><Lb Nm="FB3"><LbT Nm="FB3_PT0" PtT="XBR_CT_X"><OPort NNm="FB3_PT0"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB3_PT1" PtT="XBR_CT_X"><OPort NNm="FB3_PT1"/><IPort NNm="FB22_4_I"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_13_Q"/></LbT><LbT Nm="FB3_PT2" PtT="XBR_CT_X"><OPort NNm="FB3_PT2"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_13_Q"/><IPort NNm="FB22_3_I"/></LbT><LbT Nm="FB3_PT3" PtT="XBR_CT_X"><OPort NNm="FB3_PT3"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_13_Q"/><IPort NNm="FB4_16_I"/></LbT><LbT Nm="FB3_PT4" PtT="XBR_CT"><OPort NNm="FB3_PT4"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_13_Q"/><IPort NNm="FB1_16_I"/></LbT><LbT Nm="FB3_PT5" PtT="XBR_CT"><OPort NNm="FB3_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB3_PT6" PtT="XBR_CT"><OPort NNm="FB3_PT6"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_13_Q"/><IPort NNm="FB1_15_I"/></LbT><LbT Nm="FB3_PT7" PtT="XBR_CT"><OPort NNm="FB3_PT7"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB23_2_I"/><IPort NNm="FB2_4_Q"/></LbT><LbT Nm="FB3_PT8" PtT="XBR_A"><OPort NNm="FB3_PT8"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_4_Q"/><IPort NNm="FB22_15_I"/></LbT><LbT Nm="FB3_PT9" PtT="XBR_B"><OPort NNm="FB3_PT9"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_4_Q"/><IPort NNm="FB22_14_I"/></LbT><LbT Nm="FB3_PT10" PtT="XBR_C"><OPort NNm="FB3_PT10"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_4_Q"/><IPort NNm="FB22_13_I"/></LbT><LbT Nm="FB3_PT11" PtT="XBR_A"><OPort NNm="FB3_PT11"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_4_Q"/><IPort NNm="FB22_12_I"/></LbT><LbT Nm="FB3_PT12" PtT="XBR_B"><OPort NNm="FB3_PT12"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_6_Q"/><IPort NNm="FB3_11_Q"/></LbT><LbT Nm="FB3_PT13" PtT="XBR_C"><OPort NNm="FB3_PT13"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB2_15_Q"/><IPort NNm="FB3_10_Q"/></LbT><LbT Nm="FB3_PT14" PtT="XBR_A"><OPort NNm="FB3_PT14"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB10_15_Q"/></LbT><LbT Nm="FB3_PT15" PtT="XBR_B"><OPort NNm="FB3_PT15"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB3_11_Q"/><IPort NNm="FB1_2_I"/><IPort NNm="FB1_2_Q"/></LbT><LbT Nm="FB3_PT16" PtT="XBR_C"><OPort NNm="FB3_PT16"/><IPort NNm="FB1_2_I"/><IPort NNm="FB1_2_Q"/></LbT><LbT Nm="FB3_PT17" PtT="XBR_A"><OPort NNm="FB3_PT17"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB3_10_Q"/><IPort NNm="FB1_4_I"/><IPort NNm="FB1_4_Q"/></LbT><LbT Nm="FB3_PT18" PtT="XBR_B"><OPort NNm="FB3_PT18"/><IPort NNm="FB1_4_I"/><IPort NNm="FB1_4_Q"/></LbT><LbT Nm="FB3_PT19" PtT="XBR_C"><OPort NNm="FB3_PT19"/><IPort NNm="FB3_9_Q"/><IPort NNm="FB5_12_Q"/><IPort NNm="FB24_2_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB3_PT20" PtT="XBR_A"><OPort NNm="FB3_PT20"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB24_2_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB3_PT21" PtT="XBR_B"><OPort NNm="FB3_PT21"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB5_12_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB3_PT22" PtT="XBR_C"><OPort NNm="FB3_PT22"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB5_12_Q"/><IPort NNm="FB24_2_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB3_PT23" PtT="XBR_A"><OPort NNm="FB3_PT23"/><IPort NNm="FB3_8_Q"/><IPort NNm="FB5_12_Q"/><IPort NNm="FB24_2_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB3_PT24" PtT="XBR_B"><OPort NNm="FB3_PT24"/><IPort NNm="FB3_7_Q"/><IPort NNm="FB5_12_Q"/><IPort NNm="FB24_2_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB3_PT25" PtT="XBR_C"><OPort NNm="FB3_PT25"/><IPort NNm="FB3_9_Q"/><IPort NNm="FB3_8_Q"/><IPort NNm="FB3_7_Q"/></LbT><LbT Nm="FB3_PT26" PtT="XBR_A"><OPort NNm="FB3_PT26"/><IPort NNm="FB3_6_Q"/><IPort NNm="FB5_12_Q"/><IPort NNm="FB24_2_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB3_PT27" PtT="XBR_B"><OPort NNm="FB3_PT27"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB3_12_Q"/></LbT><LbT Nm="FB3_PT28" PtT="XBR_C"><OPort NNm="FB3_PT28"/><IPort NNm="FB3_9_Q"/><IPort NNm="FB3_8_Q"/></LbT><LbT Nm="FB3_PT29" PtT="XBR_A"><OPort NNm="FB3_PT29"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB3_12_Q"/><IPort NNm="FB11_10_Q"/></LbT><LbT Nm="FB3_PT30" PtT="XBR_B"><OPort NNm="FB3_PT30"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB3_12_Q"/><IPort NNm="FB11_10_Q"/></LbT><LbT Nm="FB3_PT31" PtT="XBR_C"><OPort NNm="FB3_PT31"/><IPort NNm="FB3_9_Q"/></LbT><LbT Nm="FB3_PT32" PtT="XBR_A"><OPort NNm="FB3_PT32"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB3_PT52" PtT="XBR_C"><OPort NNm="FB3_PT52"/><IPort NNm="FB3_9_Q"/><IPort NNm="FB3_8_Q"/><IPort NNm="FB3_7_Q"/><IPort NNm="FB3_6_Q"/></LbT><LbT Nm="FB3_PT55" PtT="XBR_C"><OPort NNm="FB3_PT55"/><IPort NNm="FB1_1_Q"/></LbT><Mc Nm="FB3_1"><InBuf Nm="FB3_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_f_p&lt;12&gt;"/></InBuf><OutBuf Nm="FB3_1_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="add_f_p&lt;12&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB3_2"><InBuf Nm="FB3_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_f_p&lt;10&gt;"/></InBuf><OutBuf Nm="FB3_2_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="add_f_p&lt;10&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB3_3"><InBuf Nm="FB3_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_f_p&lt;11&gt;"/></InBuf><OutBuf Nm="FB3_3_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="add_f_p&lt;11&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB3_4"><InBuf Nm="FB3_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_f_p&lt;13&gt;"/></InBuf><OutBuf Nm="FB3_4_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="add_f_p&lt;13&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB3_5"><InBuf Nm="FB3_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_f_p&lt;14&gt;"/></InBuf><OutBuf Nm="FB3_5_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="add_f_p&lt;14&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB3_6"><RMux Nm="FB3_6_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_6_MC_CLK"/></ClkMux><XorMux Nm="FB3_6_AND"><IPort NNm="FB3_PT25"/></XorMux><FbMux Nm="FB3_6_N"><IPort NNm="FB3_6_Q"/></FbMux><DFlop Nm="FB3_6_FF"><FlopPort NNm="FB3_PT25" Port="D"/><FlopPort NNm="FB3_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_6_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB3_7"><RMux Nm="FB3_7_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_7_MC_CLK"/></ClkMux><XorMux Nm="FB3_7_AND"><IPort NNm="FB3_PT28"/></XorMux><FbMux Nm="FB3_7_N"><IPort NNm="FB3_7_Q"/></FbMux><DFlop Nm="FB3_7_FF"><FlopPort NNm="FB3_PT28" Port="D"/><FlopPort NNm="FB3_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_7_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB3_8"><RMux Nm="FB3_8_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_8_MC_CLK"/></ClkMux><XorMux Nm="FB3_8_AND"><IPort NNm="FB3_PT31"/></XorMux><FbMux Nm="FB3_8_N"><IPort NNm="FB3_8_Q"/></FbMux><DFlop Nm="FB3_8_FF"><FlopPort NNm="FB3_PT31" Port="D"/><FlopPort NNm="FB3_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_8_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB3_9"><RMux Nm="FB3_9_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_9_MC_CLK"/></ClkMux><FbMux Nm="FB3_9_N"><IPort NNm="FB3_9_Q"/></FbMux><DFlop Nm="FB3_9_FF"><FlopPort NNm="PT_GND" Port="D"/><FlopPort NNm="FB3_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_9_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB3_10"><RMux Nm="FB3_10_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_10_MC_CLK"/></ClkMux><FbMux Nm="FB3_10_N"><IPort NNm="FB3_10_Q"/></FbMux><DFlop Nm="FB3_10_FF"><FlopPort NNm="FB3_10_OR" Port="D"/><FlopPort NNm="FB3_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_10_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB3_10_OR"><OPort NNm="FB3_10_OR"/><IPort NNm="FB3_PT18"/><IPort NNm="FB3_PT17"/></Or></Mc><Mc Nm="FB3_11"><RMux Nm="FB3_11_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_11_MC_CLK"/></ClkMux><FbMux Nm="FB3_11_N"><IPort NNm="FB3_11_Q"/></FbMux><DFlop Nm="FB3_11_FF"><FlopPort NNm="FB3_11_OR" Port="D"/><FlopPort NNm="FB3_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_11_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB3_11_OR"><OPort NNm="FB3_11_OR"/><IPort NNm="FB3_PT16"/><IPort NNm="FB3_PT15"/></Or></Mc><Mc Nm="FB3_12"><RMux Nm="FB3_12_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_12_MC_CLK"/></ClkMux><FbMux Nm="FB3_12_N"><IPort NNm="FB3_12_Q"/></FbMux><FbMux Nm="FB3_12_P"><IPort NNm="FB3_12_I"/></FbMux><InBuf Nm="FB3_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="evcnt_res"/><OPort NNm="FB3_12_I"/></InBuf><DFlop Nm="FB3_12_FF"><FlopPort NNm="FB3_12_OR" Port="D"/><FlopPort NNm="FB3_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_12_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB3_12_OR"><OPort NNm="FB3_12_OR"/><IPort NNm="FB3_PT27"/><IPort NNm="FB3_PT32"/><IPort NNm="FB3_PT29"/><IPort NNm="FB3_PT30"/></Or></Mc><Mc Nm="FB3_13"><FbMux Nm="FB3_13_N"><IPort NNm="FB3_13_OR"/></FbMux><FbMux Nm="FB3_13_P"><IPort NNm="FB3_13_I"/></FbMux><InBuf Nm="FB3_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_done&lt;2&gt;"/><OPort NNm="FB3_13_I"/></InBuf><Or Nm="FB3_13_OR"><OPort NNm="FB3_13_OR"/><IPort NNm="FB3_PT20"/><IPort NNm="FB3_PT21"/><IPort NNm="FB3_PT23"/><IPort NNm="FB3_PT24"/><IPort NNm="FB3_PT26"/><IPort NNm="FB3_PT19"/><IPort NNm="FB3_PT22"/></Or></Mc><Mc Nm="FB3_14"><RMux Nm="FB3_14_RST"><IPort NNm="FB1_3_I"/></RMux><ClkMux Nm="FB3_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_14_MC_CLK"/></ClkMux><FbMux Nm="FB3_14_N"><IPort NNm="FB3_14_Q"/></FbMux><DFlop Nm="FB3_14_FF"><FlopPort NNm="FB3_14_OR" Port="D"/><FlopPort NNm="FB3_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_14_Q" Port="Q"/><FlopPort NNm="FB1_3_I" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB3_14_OR"><OPort NNm="FB3_14_OR"/><IPort NNm="FB3_PT14"/><IPort NNm="FB3_PT1"/><IPort NNm="FB3_PT2"/><IPort NNm="FB3_PT3"/><IPort NNm="FB3_PT4"/><IPort NNm="FB3_PT6"/><IPort NNm="FB3_PT7"/><IPort NNm="FB3_PT8"/><IPort NNm="FB3_PT9"/><IPort NNm="FB3_PT10"/><IPort NNm="FB3_PT11"/><IPort NNm="FB3_PT12"/><IPort NNm="FB3_PT13"/></Or></Mc><Mc Nm="FB3_15"><RMux Nm="FB3_15_RST"><IPort NNm="FB3_PT5"/></RMux><ClkMux Nm="FB3_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_15_MC_CLK"/></ClkMux><XorMux Nm="FB3_15_AND"><IPort NNm="FB3_PT52"/></XorMux><FbMux Nm="FB3_15_N"><IPort NNm="FB3_15_Q"/></FbMux><FbMux Nm="FB3_15_P"><IPort NNm="FB3_15_I"/></FbMux><InBuf Nm="FB3_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_done&lt;3&gt;"/><OPort NNm="FB3_15_I"/></InBuf><DFlop Nm="FB3_15_FF"><FlopPort NNm="FB3_PT52" Port="D"/><FlopPort NNm="FB3_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_15_Q" Port="Q"/><FlopPort NNm="FB3_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB3_16"><RMux Nm="FB3_16_RST"><IPort NNm="FB1_3_I"/></RMux><ClkMux Nm="FB3_16_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB3_16_MC_CLK"/></ClkMux><FbMux Nm="FB3_16_N"><IPort NNm="FB3_16_Q"/></FbMux><DFlop Nm="FB3_16_FF"><FlopPort NNm="FB3_16_OR" Port="D"/><FlopPort NNm="FB3_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB3_16_Q" Port="Q"/><FlopPort NNm="FB1_3_I" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB3_PT55" Port="CE"/></DFlop><Or Nm="FB3_16_OR"><OPort NNm="FB3_16_OR"/><IPort NNm="FB3_PT0"/></Or></Mc></Lb><Lb Nm="FB4"><LbT Nm="FB4_PT0" PtT="XBR_CT_X"><OPort NNm="FB4_PT0"/><IPort NNm="FB5_4_I"/></LbT><LbT Nm="FB4_PT1" PtT="XBR_CT_X"><OPort NNm="FB4_PT1"/><IPort NNm="FB6_1_I"/></LbT><LbT Nm="FB4_PT2" PtT="XBR_CT_X"><OPort NNm="FB4_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB22_12_I"/></LbT><LbT Nm="FB4_PT3" PtT="XBR_CT_X"><OPort NNm="FB4_PT3"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_4_I"/></LbT><LbT Nm="FB4_PT4" PtT="XBR_CT"><OPort NNm="FB4_PT4"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_14_Q"/></LbT><LbT Nm="FB4_PT5" PtT="XBR_CT"><OPort NNm="FB4_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB4_PT6" PtT="XBR_CT"><OPort NNm="FB4_PT6"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB4_PT7" PtT="XBR_CT"><OPort NNm="FB4_PT7"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_13_Q"/></LbT><LbT Nm="FB4_PT8" PtT="XBR_A"><OPort NNm="FB4_PT8"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_9_Q"/></LbT><LbT Nm="FB4_PT9" PtT="XBR_B"><OPort NNm="FB4_PT9"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_1_Q"/></LbT><LbT Nm="FB4_PT10" PtT="XBR_C"><OPort NNm="FB4_PT10"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB4_PT11" PtT="XBR_A"><OPort NNm="FB4_PT11"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_4_Q"/></LbT><LbT Nm="FB4_PT12" PtT="XBR_B"><OPort NNm="FB4_PT12"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_14_Q"/></LbT><LbT Nm="FB4_PT13" PtT="XBR_C"><OPort NNm="FB4_PT13"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_5_Q"/></LbT><LbT Nm="FB4_PT14" PtT="XBR_A"><OPort NNm="FB4_PT14"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_8_Q"/></LbT><LbT Nm="FB4_PT15" PtT="XBR_B"><OPort NNm="FB4_PT15"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_16_I"/></LbT><LbT Nm="FB4_PT16" PtT="XBR_C"><OPort NNm="FB4_PT16"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_7_Q"/></LbT><LbT Nm="FB4_PT17" PtT="XBR_A"><OPort NNm="FB4_PT17"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_5_Q"/></LbT><LbT Nm="FB4_PT18" PtT="XBR_B"><OPort NNm="FB4_PT18"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB15_16_Q"/></LbT><LbT Nm="FB4_PT19" PtT="XBR_C"><OPort NNm="FB4_PT19"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB15_16_Q"/></LbT><LbT Nm="FB4_PT20" PtT="XBR_A"><OPort NNm="FB4_PT20"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_14_Q"/></LbT><LbT Nm="FB4_PT21" PtT="XBR_B"><OPort NNm="FB4_PT21"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_12_Q"/></LbT><LbT Nm="FB4_PT22" PtT="XBR_C"><OPort NNm="FB4_PT22"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB4_PT23" PtT="XBR_A"><OPort NNm="FB4_PT23"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_10_Q"/></LbT><LbT Nm="FB4_PT24" PtT="XBR_B"><OPort NNm="FB4_PT24"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB22_3_I"/></LbT><LbT Nm="FB4_PT25" PtT="XBR_C"><OPort NNm="FB4_PT25"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB16_12_Q"/></LbT><LbT Nm="FB4_PT26" PtT="XBR_A"><OPort NNm="FB4_PT26"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_11_Q"/></LbT><LbT Nm="FB4_PT27" PtT="XBR_B"><OPort NNm="FB4_PT27"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_7_Q"/></LbT><LbT Nm="FB4_PT28" PtT="XBR_C"><OPort NNm="FB4_PT28"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB4_PT29" PtT="XBR_A"><OPort NNm="FB4_PT29"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_14_Q"/></LbT><LbT Nm="FB4_PT30" PtT="XBR_B"><OPort NNm="FB4_PT30"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB12_10_Q"/></LbT><LbT Nm="FB4_PT31" PtT="XBR_C"><OPort NNm="FB4_PT31"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB4_PT32" PtT="XBR_A"><OPort NNm="FB4_PT32"/><IPort NNm="FB4_3_I"/></LbT><LbT Nm="FB4_PT33" PtT="XBR_B"><OPort NNm="FB4_PT33"/><IPort NNm="FB4_5_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB4_PT34" PtT="XBR_C"><OPort NNm="FB4_PT34"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB4_PT35" PtT="XBR_A"><OPort NNm="FB4_PT35"/><IPort NNm="FB21_12_I"/><IPort NNm="FB4_10_Q"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB4_PT40" PtT="XBR_C"><OPort NNm="FB4_PT40"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB4_PT43" PtT="XBR_C"><OPort NNm="FB4_PT43"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB4_PT46" PtT="XBR_C"><OPort NNm="FB4_PT46"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB4_PT49" PtT="XBR_C"><OPort NNm="FB4_PT49"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB4_PT52" PtT="XBR_C"><OPort NNm="FB4_PT52"/><IPort NNm="FB5_PT40"/></LbT><Mc Nm="FB4_1"><RMux Nm="FB4_1_PST"><IPort NNm="FB4_PT6"/></RMux><ClkMux Nm="FB4_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_1_MC_CLK"/></ClkMux><OeMux Nm="FB4_1_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB4_1_N"><IPort NNm="FB4_1_Q"/></FbMux><FbMux Nm="FB4_1_P"><IPort NNm="FB4_1_I"/></FbMux><InBuf Nm="FB4_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;0&gt;"/><OPort NNm="FB4_1_I"/></InBuf><OutBuf Nm="FB4_1_O" IOS="LVCMOS33"><IPort NNm="FB4_1_Q"/><OPort NNm="db&lt;0&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB4_1_FF"><FlopPort NNm="FB4_1_I" Port="D"/><FlopPort NNm="FB4_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB4_PT6" Port="PST"/><FlopPort NNm="FB4_PT10" Port="CE"/></DFlop></Mc><Mc Nm="FB4_2"/><Mc Nm="FB4_3"><OeMux Nm="FB4_3_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB4_3_P"><IPort NNm="FB4_3_I"/></FbMux><InBuf Nm="FB4_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;8&gt;"/><OPort NNm="FB4_3_I"/></InBuf><OutBuf Nm="FB4_3_O" IOS="LVCMOS33"><IPort NNm="FB4_3_OR"/><OPort NNm="db&lt;8&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><Or Nm="FB4_3_OR"><OPort NNm="FB4_3_OR"/><IPort NNm="FB4_PT27"/><IPort NNm="FB4_PT29"/><IPort NNm="FB4_PT26"/><IPort NNm="FB4_PT24"/><IPort NNm="FB4_PT30"/><IPort NNm="FB4_PT25"/></Or></Mc><Mc Nm="FB4_4"><XorMux Nm="FB4_4_AND"><IPort NNm="FB4_PT19"/></XorMux><OeMux Nm="FB4_4_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB4_4_P"><IPort NNm="FB4_4_I"/></FbMux><InBuf Nm="FB4_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;15&gt;"/><OPort NNm="FB4_4_I"/></InBuf><OutBuf Nm="FB4_4_O" IOS="LVCMOS33"><IPort NNm="FB4_PT19"/><OPort NNm="db&lt;15&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf></Mc><Mc Nm="FB4_5"><RMux Nm="FB4_5_RST"><IPort NNm="FB4_PT5"/></RMux><ClkMux Nm="FB4_5_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_5_MC_CLK"/></ClkMux><OeMux Nm="FB4_5_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB4_5_N"><IPort NNm="FB4_5_Q"/></FbMux><FbMux Nm="FB4_5_P"><IPort NNm="FB4_5_I"/></FbMux><InBuf Nm="FB4_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;7&gt;"/><OPort NNm="FB4_5_I"/></InBuf><OutBuf Nm="FB4_5_O" IOS="LVCMOS33"><IPort NNm="FB4_5_Q"/><OPort NNm="db&lt;7&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB4_5_FF"><FlopPort NNm="FB4_5_I" Port="D"/><FlopPort NNm="FB4_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_5_Q" Port="Q"/><FlopPort NNm="FB4_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB4_PT22" Port="CE"/></DFlop></Mc><Mc Nm="FB4_6"/><Mc Nm="FB4_7"><RMux Nm="FB4_7_RST"><IPort NNm="FB4_PT5"/></RMux><ClkMux Nm="FB4_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_7_MC_CLK"/></ClkMux><FbMux Nm="FB4_7_N"><IPort NNm="FB4_7_Q"/></FbMux><DFlop Nm="FB4_7_FF"><FlopPort NNm="FB4_7_OR" Port="D"/><FlopPort NNm="FB4_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_7_Q" Port="Q"/><FlopPort NNm="FB4_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB4_PT28" Port="CE"/></DFlop><Or Nm="FB4_7_OR"><OPort NNm="FB4_7_OR"/><IPort NNm="FB4_PT32"/></Or></Mc><Mc Nm="FB4_8"><XorMux Nm="FB4_8_AND"><IPort NNm="FB4_PT31"/></XorMux><FbMux Nm="FB4_8_N"><IPort NNm="FB4_PT31"/></FbMux></Mc><Mc Nm="FB4_9"><XorMux Nm="FB4_9_AND"><IPort NNm="FB4_PT34"/></XorMux><FbMux Nm="FB4_9_N"><IPort NNm="FB4_PT34"/></FbMux></Mc><Mc Nm="FB4_10"><RMux Nm="FB4_10_RST"><IPort NNm="FB4_PT5"/></RMux><ClkMux Nm="FB4_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_10_MC_CLK"/></ClkMux><FbMux Nm="FB4_10_N"><IPort NNm="FB4_10_Q"/></FbMux><DFlop Nm="FB4_10_FF"><FlopPort NNm="FB4_10_OR" Port="D"/><FlopPort NNm="FB4_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_10_Q" Port="Q"/><FlopPort NNm="FB4_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB4_10_OR"><OPort NNm="FB4_10_OR"/><IPort NNm="FB4_PT33"/><IPort NNm="FB4_PT35"/></Or></Mc><Mc Nm="FB4_11"><RMux Nm="FB4_11_RST"><IPort NNm="FB4_PT5"/></RMux><ClkMux Nm="FB4_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_11_MC_CLK"/></ClkMux><FbMux Nm="FB4_11_N"><IPort NNm="FB4_11_Q"/></FbMux><DFlop Nm="FB4_11_FF"><FlopPort NNm="FB4_11_OR" Port="D"/><FlopPort NNm="FB4_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_11_Q" Port="Q"/><FlopPort NNm="FB4_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB4_PT22" Port="CE"/></DFlop><Or Nm="FB4_11_OR"><OPort NNm="FB4_11_OR"/><IPort NNm="FB4_PT32"/></Or></Mc><Mc Nm="FB4_12"><RMux Nm="FB4_12_RST"><IPort NNm="FB4_PT5"/></RMux><ClkMux Nm="FB4_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_12_MC_CLK"/></ClkMux><FbMux Nm="FB4_12_N"><IPort NNm="FB4_12_Q"/></FbMux><InBuf Nm="FB4_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_init&lt;1&gt;"/></InBuf><OutBuf Nm="FB4_12_O" IOS="LVCMOS33"><IPort NNm="FB4_12_Q"/><OPort NNm="fpga_init&lt;1&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB4_12_FF"><FlopPort NNm="FB4_12_OR" Port="D"/><FlopPort NNm="FB4_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_12_Q" Port="Q"/><FlopPort NNm="FB4_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB4_PT43" Port="CE"/></DFlop><Or Nm="FB4_12_OR"><OPort NNm="FB4_12_OR"/><IPort NNm="FB4_PT0"/></Or></Mc><Mc Nm="FB4_13"><RMux Nm="FB4_13_RST"><IPort NNm="FB4_PT5"/></RMux><ClkMux Nm="FB4_13_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_13_MC_CLK"/></ClkMux><FbMux Nm="FB4_13_N"><IPort NNm="FB4_13_Q"/></FbMux><InBuf Nm="FB4_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="i2c_ce_1wire"/></InBuf><OutBuf Nm="FB4_13_O" IOS="LVCMOS33"><IPort NNm="FB4_13_Q"/><OPort NNm="i2c_ce_1wire"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB4_13_FF"><FlopPort NNm="FB4_13_OR" Port="D"/><FlopPort NNm="FB4_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_13_Q" Port="Q"/><FlopPort NNm="FB4_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB4_PT46" Port="CE"/></DFlop><Or Nm="FB4_13_OR"><OPort NNm="FB4_13_OR"/><IPort NNm="FB4_PT0"/></Or></Mc><Mc Nm="FB4_14"><RMux Nm="FB4_14_RST"><IPort NNm="FB4_PT5"/></RMux><ClkMux Nm="FB4_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_14_MC_CLK"/></ClkMux><FbMux Nm="FB4_14_N"><IPort NNm="FB4_14_Q"/></FbMux><InBuf Nm="FB4_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_init&lt;2&gt;"/></InBuf><OutBuf Nm="FB4_14_O" IOS="LVCMOS33"><IPort NNm="FB4_14_Q"/><OPort NNm="fpga_init&lt;2&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB4_14_FF"><FlopPort NNm="FB4_14_OR" Port="D"/><FlopPort NNm="FB4_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_14_Q" Port="Q"/><FlopPort NNm="FB4_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB4_PT43" Port="CE"/></DFlop><Or Nm="FB4_14_OR"><OPort NNm="FB4_14_OR"/><IPort NNm="FB4_PT1"/></Or></Mc><Mc Nm="FB4_15"><RMux Nm="FB4_15_PST"><IPort NNm="FB4_PT6"/></RMux><ClkMux Nm="FB4_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB4_15_MC_CLK"/></ClkMux><FbMux Nm="FB4_15_N"><IPort NNm="FB4_15_Q"/></FbMux><InBuf Nm="FB4_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="gol_off"/></InBuf><OutBuf Nm="FB4_15_O" IOS="LVCMOS33"><IPort NNm="FB4_15_Q"/><OPort NNm="gol_off"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB4_15_FF"><FlopPort NNm="FB4_15_OR" Port="D"/><FlopPort NNm="FB4_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB4_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB4_PT6" Port="PST"/><FlopPort NNm="FB4_PT46" Port="CE"/></DFlop><Or Nm="FB4_15_OR"><OPort NNm="FB4_15_OR"/><IPort NNm="FB4_PT1"/></Or></Mc><Mc Nm="FB4_16"><FbMux Nm="FB4_16_P"><IPort NNm="FB4_16_I"/></FbMux><InBuf Nm="FB4_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sff&lt;2&gt;"/><OPort NNm="FB4_16_I"/></InBuf></Mc></Lb><Lb Nm="FB5"><LbT Nm="FB5_PT0" PtT="XBR_CT_X"><OPort NNm="FB5_PT0"/><IPort NNm="FB8_1_I"/></LbT><LbT Nm="FB5_PT1" PtT="XBR_CT_X"><OPort NNm="FB5_PT1"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB22_13_I"/></LbT><LbT Nm="FB5_PT2" PtT="XBR_CT_X"><OPort NNm="FB5_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_2_I"/></LbT><LbT Nm="FB5_PT3" PtT="XBR_CT_X"><OPort NNm="FB5_PT3"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_13_Q"/></LbT><LbT Nm="FB5_PT4" PtT="XBR_CT"><OPort NNm="FB5_PT4"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_12_Q"/></LbT><LbT Nm="FB5_PT5" PtT="XBR_CT"><OPort NNm="FB5_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB5_PT6" PtT="XBR_CT"><OPort NNm="FB5_PT6"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_8_Q"/></LbT><LbT Nm="FB5_PT7" PtT="XBR_CT"><OPort NNm="FB5_PT7"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB8_5_Q"/></LbT><LbT Nm="FB5_PT8" PtT="XBR_A"><OPort NNm="FB5_PT8"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_13_Q"/></LbT><LbT Nm="FB5_PT9" PtT="XBR_B"><OPort NNm="FB5_PT9"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB5_5_Q"/></LbT><LbT Nm="FB5_PT10" PtT="XBR_C"><OPort NNm="FB5_PT10"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_6_Q"/></LbT><LbT Nm="FB5_PT11" PtT="XBR_A"><OPort NNm="FB5_PT11"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_9_Q"/></LbT><LbT Nm="FB5_PT12" PtT="XBR_B"><OPort NNm="FB5_PT12"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB23_14_Q"/></LbT><LbT Nm="FB5_PT13" PtT="XBR_C"><OPort NNm="FB5_PT13"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB5_12_Q"/></LbT><LbT Nm="FB5_PT14" PtT="XBR_A"><OPort NNm="FB5_PT14"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB5_PT15" PtT="XBR_B"><OPort NNm="FB5_PT15"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB11_7_Q"/></LbT><LbT Nm="FB5_PT16" PtT="XBR_C"><OPort NNm="FB5_PT16"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB14_15_Q"/></LbT><LbT Nm="FB5_PT17" PtT="XBR_A"><OPort NNm="FB5_PT17"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB20_5_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB5_PT18" PtT="XBR_B"><OPort NNm="FB5_PT18"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB22_4_I"/></LbT><LbT Nm="FB5_PT19" PtT="XBR_C"><OPort NNm="FB5_PT19"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB23_12_Q"/></LbT><LbT Nm="FB5_PT20" PtT="XBR_A"><OPort NNm="FB5_PT20"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB17_14_I"/></LbT><LbT Nm="FB5_PT21" PtT="XBR_B"><OPort NNm="FB5_PT21"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB5_5_Q"/></LbT><LbT Nm="FB5_PT22" PtT="XBR_C"><OPort NNm="FB5_PT22"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB5_PT23" PtT="XBR_A"><OPort NNm="FB5_PT23"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB11_10_Q"/></LbT><LbT Nm="FB5_PT24" PtT="XBR_B"><OPort NNm="FB5_PT24"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB20_4_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB5_PT34" PtT="XBR_C"><OPort NNm="FB5_PT34"/><IPort NNm="FB7_8_Q"/></LbT><LbT Nm="FB5_PT37" PtT="XBR_C"><OPort NNm="FB5_PT37"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/></LbT><LbT Nm="FB5_PT40" PtT="XBR_C"><OPort NNm="FB5_PT40"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/></LbT><LbT Nm="FB5_PT43" PtT="XBR_C"><OPort NNm="FB5_PT43"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB5_PT49" PtT="XBR_C"><OPort NNm="FB5_PT49"/><IPort NNm="FB4_PT34"/></LbT><Mc Nm="FB5_1"/><Mc Nm="FB5_2"/><Mc Nm="FB5_3"/><Mc Nm="FB5_4"><OeMux Nm="FB5_4_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB5_4_P"><IPort NNm="FB5_4_I"/></FbMux><InBuf Nm="FB5_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;1&gt;"/><OPort NNm="FB5_4_I"/></InBuf><OutBuf Nm="FB5_4_O" IOS="LVCMOS33"><IPort NNm="FB5_4_OR"/><OPort NNm="db&lt;1&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><Or Nm="FB5_4_OR"><OPort NNm="FB5_4_OR"/><IPort NNm="FB5_PT9"/><IPort NNm="FB5_PT10"/><IPort NNm="FB5_PT8"/><IPort NNm="FB5_PT6"/><IPort NNm="FB5_PT1"/><IPort NNm="FB5_PT3"/><IPort NNm="FB5_PT7"/><IPort NNm="FB5_PT11"/><IPort NNm="FB5_PT4"/><IPort NNm="FB5_PT2"/></Or></Mc><Mc Nm="FB5_5"><RMux Nm="FB5_5_RST"><IPort NNm="FB5_PT5"/></RMux><ClkMux Nm="FB5_5_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB5_5_MC_CLK"/></ClkMux><OeMux Nm="FB5_5_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB5_5_N"><IPort NNm="FB5_5_Q"/></FbMux><FbMux Nm="FB5_5_P"><IPort NNm="FB5_5_I"/></FbMux><InBuf Nm="FB5_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;9&gt;"/><OPort NNm="FB5_5_I"/></InBuf><OutBuf Nm="FB5_5_O" IOS="LVCMOS33"><IPort NNm="FB5_5_Q"/><OPort NNm="db&lt;9&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB5_5_FF"><FlopPort NNm="FB5_5_I" Port="D"/><FlopPort NNm="FB5_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB5_5_Q" Port="Q"/><FlopPort NNm="FB5_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB5_PT22" Port="CE"/></DFlop></Mc><Mc Nm="FB5_6"/><Mc Nm="FB5_7"/><Mc Nm="FB5_8"/><Mc Nm="FB5_9"><ClkMux Nm="FB5_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB5_9_MC_CLK"/></ClkMux><XorMux Nm="FB5_9_AND"><IPort NNm="FB5_PT34"/></XorMux><FbMux Nm="FB5_9_N"><IPort NNm="FB5_9_Q"/></FbMux><DFlop Nm="FB5_9_FF"><FlopPort NNm="FB5_PT34" Port="D"/><FlopPort NNm="FB5_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB5_9_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB5_10"><XorMux Nm="FB5_10_AND"><IPort NNm="FB5_PT37"/></XorMux><FbMux Nm="FB5_10_N"><IPort NNm="FB5_PT37"/></FbMux></Mc><Mc Nm="FB5_11"><XorMux Nm="FB5_11_AND"><IPort NNm="FB5_PT40"/></XorMux><FbMux Nm="FB5_11_N"><IPort NNm="FB5_PT40"/></FbMux></Mc><Mc Nm="FB5_12"><RMux Nm="FB5_12_RST"><IPort NNm="FB5_PT5"/></RMux><ClkMux Nm="FB5_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB5_12_MC_CLK"/></ClkMux><OeMux Nm="FB5_12_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB5_12_N"><IPort NNm="FB5_12_Q"/></FbMux><FbMux Nm="FB5_12_P"><IPort NNm="FB5_12_I"/></FbMux><InBuf Nm="FB5_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;10&gt;"/><OPort NNm="FB5_12_I"/></InBuf><OutBuf Nm="FB5_12_O" IOS="LVCMOS33"><IPort NNm="FB5_12_Q"/><OPort NNm="db&lt;10&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB5_12_FF"><FlopPort NNm="FB5_12_I" Port="D"/><FlopPort NNm="FB5_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB5_12_Q" Port="Q"/><FlopPort NNm="FB5_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB5_PT43" Port="CE"/></DFlop></Mc><Mc Nm="FB5_13"/><Mc Nm="FB5_14"><RMux Nm="FB5_14_RST"><IPort NNm="FB5_PT5"/></RMux><ClkMux Nm="FB5_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB5_14_MC_CLK"/></ClkMux><FbMux Nm="FB5_14_N"><IPort NNm="FB5_14_Q"/></FbMux><InBuf Nm="FB5_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_init&lt;3&gt;"/></InBuf><OutBuf Nm="FB5_14_O" IOS="LVCMOS33"><IPort NNm="FB5_14_Q"/><OPort NNm="fpga_init&lt;3&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB5_14_FF"><FlopPort NNm="FB5_14_OR" Port="D"/><FlopPort NNm="FB5_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB5_14_Q" Port="Q"/><FlopPort NNm="FB5_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB5_PT43" Port="CE"/></DFlop><Or Nm="FB5_14_OR"><OPort NNm="FB5_14_OR"/><IPort NNm="FB5_PT0"/></Or></Mc><Mc Nm="FB5_15"><FbMux Nm="FB5_15_P"><IPort NNm="FB5_15_I"/></FbMux><InBuf Nm="FB5_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fl_switch&lt;0&gt;"/><OPort NNm="FB5_15_I"/></InBuf></Mc><Mc Nm="FB5_16"><FbMux Nm="FB5_16_P"><IPort NNm="FB5_16_I"/></FbMux><InBuf Nm="FB5_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fl_switch&lt;1&gt;"/><OPort NNm="FB5_16_I"/></InBuf></Mc></Lb><Lb Nm="FB6"><LbT Nm="FB6_PT0" PtT="XBR_CT_X"><OPort NNm="FB6_PT0"/><IPort NNm="FB6_16_I"/></LbT><LbT Nm="FB6_PT1" PtT="XBR_CT_X"><OPort NNm="FB6_PT1"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB22_14_I"/></LbT><LbT Nm="FB6_PT2" PtT="XBR_CT_X"><OPort NNm="FB6_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_15_Q"/></LbT><LbT Nm="FB6_PT3" PtT="XBR_CT_X"><OPort NNm="FB6_PT3"/><IPort NNm="FB7_14_I"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/></LbT><LbT Nm="FB6_PT4" PtT="XBR_CT"><OPort NNm="FB6_PT4"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB4_14_Q"/></LbT><LbT Nm="FB6_PT5" PtT="XBR_CT"><OPort NNm="FB6_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB6_PT6" PtT="XBR_CT"><OPort NNm="FB6_PT6"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB6_PT7" PtT="XBR_CT"><OPort NNm="FB6_PT7"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_7_Q"/></LbT><LbT Nm="FB6_PT8" PtT="XBR_A"><OPort NNm="FB6_PT8"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB6_PT9" PtT="XBR_B"><OPort NNm="FB6_PT9"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_6_Q"/></LbT><LbT Nm="FB6_PT10" PtT="XBR_C"><OPort NNm="FB6_PT10"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB6_PT11" PtT="XBR_A"><OPort NNm="FB6_PT11"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB6_PT12" PtT="XBR_B"><OPort NNm="FB6_PT12"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_7_Q"/></LbT><LbT Nm="FB6_PT13" PtT="XBR_C"><OPort NNm="FB6_PT13"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_10_Q"/></LbT><LbT Nm="FB6_PT14" PtT="XBR_A"><OPort NNm="FB6_PT14"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB23_2_I"/></LbT><LbT Nm="FB6_PT15" PtT="XBR_B"><OPort NNm="FB6_PT15"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB3_13_I"/></LbT><LbT Nm="FB6_PT16" PtT="XBR_C"><OPort NNm="FB6_PT16"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB6_PT17" PtT="XBR_A"><OPort NNm="FB6_PT17"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB6_3_Q"/></LbT><LbT Nm="FB6_PT18" PtT="XBR_B"><OPort NNm="FB6_PT18"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_11_Q"/></LbT><LbT Nm="FB6_PT19" PtT="XBR_C"><OPort NNm="FB6_PT19"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_10_Q"/></LbT><LbT Nm="FB6_PT20" PtT="XBR_A"><OPort NNm="FB6_PT20"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_9_Q"/></LbT><LbT Nm="FB6_PT21" PtT="XBR_B"><OPort NNm="FB6_PT21"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_16_Q"/></LbT><LbT Nm="FB6_PT22" PtT="XBR_C"><OPort NNm="FB6_PT22"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_4_Q"/></LbT><LbT Nm="FB6_PT23" PtT="XBR_A"><OPort NNm="FB6_PT23"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB6_PT24" PtT="XBR_B"><OPort NNm="FB6_PT24"/><IPort NNm="FB16_12_Q"/><IPort NNm="FB3_12_I"/></LbT><LbT Nm="FB6_PT25" PtT="XBR_C"><OPort NNm="FB6_PT25"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB4_4_I"/></LbT><Mc Nm="FB6_1"><RMux Nm="FB6_1_PST"><IPort NNm="FB6_PT6"/></RMux><ClkMux Nm="FB6_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB6_1_MC_CLK"/></ClkMux><OeMux Nm="FB6_1_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB6_1_N"><IPort NNm="FB6_1_Q"/></FbMux><FbMux Nm="FB6_1_P"><IPort NNm="FB6_1_I"/></FbMux><InBuf Nm="FB6_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;2&gt;"/><OPort NNm="FB6_1_I"/></InBuf><OutBuf Nm="FB6_1_O" IOS="LVCMOS33"><IPort NNm="FB6_1_Q"/><OPort NNm="db&lt;2&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB6_1_FF"><FlopPort NNm="FB6_1_I" Port="D"/><FlopPort NNm="FB6_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB6_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB6_PT6" Port="PST"/><FlopPort NNm="FB6_PT10" Port="CE"/></DFlop></Mc><Mc Nm="FB6_2"/><Mc Nm="FB6_3"><RMux Nm="FB6_3_RST"><IPort NNm="FB6_PT5"/></RMux><ClkMux Nm="FB6_3_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB6_3_MC_CLK"/></ClkMux><FbMux Nm="FB6_3_N"><IPort NNm="FB6_3_Q"/></FbMux><InBuf Nm="FB6_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_init&lt;4&gt;"/></InBuf><OutBuf Nm="FB6_3_O" IOS="LVCMOS33"><IPort NNm="FB6_3_Q"/><OPort NNm="fpga_init&lt;4&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB6_3_FF"><FlopPort NNm="FB6_3_OR" Port="D"/><FlopPort NNm="FB6_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB6_3_Q" Port="Q"/><FlopPort NNm="FB6_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB6_PT16" Port="CE"/></DFlop><Or Nm="FB6_3_OR"><OPort NNm="FB6_3_OR"/><IPort NNm="FB6_PT0"/></Or></Mc><Mc Nm="FB6_4"/><Mc Nm="FB6_5"/><Mc Nm="FB6_6"/><Mc Nm="FB6_7"/><Mc Nm="FB6_8"/><Mc Nm="FB6_9"/><Mc Nm="FB6_10"/><Mc Nm="FB6_11"/><Mc Nm="FB6_12"/><Mc Nm="FB6_13"/><Mc Nm="FB6_14"/><Mc Nm="FB6_15"><ClkMux Nm="FB6_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB6_15_MC_CLK"/></ClkMux><FbMux Nm="FB6_15_N"><IPort NNm="FB6_15_Q"/></FbMux><DFlop Nm="FB6_15_FF"><FlopPort NNm="FB6_15_OR" Port="D"/><FlopPort NNm="FB6_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB6_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB6_15_OR"><OPort NNm="FB6_15_OR"/><IPort NNm="FB6_PT5"/><IPort NNm="FB6_PT24"/><IPort NNm="FB6_PT25"/></Or></Mc><Mc Nm="FB6_16"><OeMux Nm="FB6_16_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB6_16_P"><IPort NNm="FB6_16_I"/></FbMux><InBuf Nm="FB6_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;4&gt;"/><OPort NNm="FB6_16_I"/></InBuf><OutBuf Nm="FB6_16_O" IOS="LVCMOS33"><IPort NNm="FB6_16_OR"/><OPort NNm="db&lt;4&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><Or Nm="FB6_16_OR"><OPort NNm="FB6_16_OR"/><IPort NNm="FB6_PT19"/><IPort NNm="FB6_PT20"/><IPort NNm="FB6_PT23"/><IPort NNm="FB6_PT18"/><IPort NNm="FB6_PT14"/><IPort NNm="FB6_PT22"/><IPort NNm="FB6_PT21"/><IPort NNm="FB6_PT17"/><IPort NNm="FB6_PT15"/></Or></Mc></Lb><Lb Nm="FB7"><LbT Nm="FB7_PT0" PtT="XBR_CT_X"><OPort NNm="FB7_PT0"/><IPort NNm="FB1_3_I"/></LbT><LbT Nm="FB7_PT1" PtT="XBR_CT_X"><OPort NNm="FB7_PT1"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB8_3_I"/></LbT><LbT Nm="FB7_PT2" PtT="XBR_CT_X"><OPort NNm="FB7_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB4_4_I"/><IPort NNm="FB8_3_Q"/></LbT><LbT Nm="FB7_PT3" PtT="XBR_CT_X"><OPort NNm="FB7_PT3"/><IPort NNm="FB10_12_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB3_16_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB7_PT4" PtT="XBR_CT"><OPort NNm="FB7_PT4"/><IPort NNm="FB10_12_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB3_16_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB7_PT5" PtT="XBR_CT"><OPort NNm="FB7_PT5"/><IPort NNm="FB11_16_Q"/></LbT><LbT Nm="FB7_PT6" PtT="XBR_CT"><OPort NNm="FB7_PT6"/><IPort NNm="FB10_13_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB3_16_Q"/><IPort NNm="FB2_8_Q"/></LbT><LbT Nm="FB7_PT7" PtT="XBR_CT"><OPort NNm="FB7_PT7"/><IPort NNm="FB10_13_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB3_16_Q"/><IPort NNm="FB2_8_Q"/></LbT><LbT Nm="FB7_PT8" PtT="XBR_A"><OPort NNm="FB7_PT8"/><IPort NNm="FB10_14_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB3_16_Q"/><IPort NNm="FB2_7_Q"/></LbT><LbT Nm="FB7_PT9" PtT="XBR_B"><OPort NNm="FB7_PT9"/><IPort NNm="FB10_14_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB3_16_Q"/><IPort NNm="FB2_7_Q"/></LbT><LbT Nm="FB7_PT10" PtT="XBR_C"><OPort NNm="FB7_PT10"/><IPort NNm="FB7_14_I"/><IPort NNm="FB3_13_OR"/></LbT><LbT Nm="FB7_PT13" PtT="XBR_C"><OPort NNm="FB7_PT13"/><IPort NNm="FB7_16_I"/><IPort NNm="FB3_13_OR"/></LbT><LbT Nm="FB7_PT16" PtT="XBR_C"><OPort NNm="FB7_PT16"/><IPort NNm="FB3_13_I"/><IPort NNm="FB3_13_OR"/></LbT><LbT Nm="FB7_PT19" PtT="XBR_C"><OPort NNm="FB7_PT19"/><IPort NNm="FB3_15_I"/><IPort NNm="FB3_13_OR"/></LbT><LbT Nm="FB7_PT22" PtT="XBR_C"><OPort NNm="FB7_PT22"/><IPort NNm="FB21_4_I"/><IPort NNm="FB3_13_OR"/></LbT><LbT Nm="FB7_PT28" PtT="XBR_C"><OPort NNm="FB7_PT28"/><IPort NNm="FB6_15_Q"/></LbT><LbT Nm="FB7_PT31" PtT="XBR_C"><OPort NNm="FB7_PT31"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB10_7_Q"/></LbT><LbT Nm="FB7_PT34" PtT="XBR_C"><OPort NNm="FB7_PT34"/><IPort NNm="FB7_6_Q"/></LbT><LbT Nm="FB7_PT37" PtT="XBR_C"><OPort NNm="FB7_PT37"/><IPort NNm="FB5_9_Q"/></LbT><LbT Nm="FB7_PT40" PtT="XBR_C"><OPort NNm="FB7_PT40"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB7_11_Q"/></LbT><LbT Nm="FB7_PT43" PtT="XBR_C"><OPort NNm="FB7_PT43"/><IPort NNm="FB3_12_I"/><IPort NNm="FB8_16_Q"/></LbT><LbT Nm="FB7_PT46" PtT="XBR_C"><OPort NNm="FB7_PT46"/><IPort NNm="FB7_6_Q"/><IPort NNm="FB7_9_Q"/></LbT><LbT Nm="FB7_PT49" PtT="XBR_C"><OPort NNm="FB7_PT49"/><IPort NNm="FB21_13_I"/><IPort NNm="FB3_16_Q"/></LbT><Mc Nm="FB7_1"><ClkMux Nm="FB7_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_1_MC_CLK"/></ClkMux><XorMux Nm="FB7_1_AND"><IPort NNm="FB7_PT10"/></XorMux><InBuf Nm="FB7_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cclk&lt;0&gt;"/></InBuf><OutBuf Nm="FB7_1_O" IOS="LVCMOS33"><IPort NNm="FB7_1_Q"/><OPort NNm="cclk&lt;0&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB7_1_FF"><FlopPort NNm="FB7_PT10" Port="D"/><FlopPort NNm="FB7_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_2"><ClkMux Nm="FB7_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_2_MC_CLK"/></ClkMux><XorMux Nm="FB7_2_AND"><IPort NNm="FB7_PT13"/></XorMux><InBuf Nm="FB7_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cclk&lt;1&gt;"/></InBuf><OutBuf Nm="FB7_2_O" IOS="LVCMOS33"><IPort NNm="FB7_2_Q"/><OPort NNm="cclk&lt;1&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB7_2_FF"><FlopPort NNm="FB7_PT13" Port="D"/><FlopPort NNm="FB7_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_2_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_3"><ClkMux Nm="FB7_3_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_3_MC_CLK"/></ClkMux><XorMux Nm="FB7_3_AND"><IPort NNm="FB7_PT16"/></XorMux><InBuf Nm="FB7_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cclk&lt;2&gt;"/></InBuf><OutBuf Nm="FB7_3_O" IOS="LVCMOS33"><IPort NNm="FB7_3_Q"/><OPort NNm="cclk&lt;2&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB7_3_FF"><FlopPort NNm="FB7_PT16" Port="D"/><FlopPort NNm="FB7_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_3_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_4"><ClkMux Nm="FB7_4_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_4_MC_CLK"/></ClkMux><XorMux Nm="FB7_4_AND"><IPort NNm="FB7_PT19"/></XorMux><InBuf Nm="FB7_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cclk&lt;3&gt;"/></InBuf><OutBuf Nm="FB7_4_O" IOS="LVCMOS33"><IPort NNm="FB7_4_Q"/><OPort NNm="cclk&lt;3&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB7_4_FF"><FlopPort NNm="FB7_PT19" Port="D"/><FlopPort NNm="FB7_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_4_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_5"><ClkMux Nm="FB7_5_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_5_MC_CLK"/></ClkMux><XorMux Nm="FB7_5_AND"><IPort NNm="FB7_PT22"/></XorMux><InBuf Nm="FB7_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cclk&lt;4&gt;"/></InBuf><OutBuf Nm="FB7_5_O" IOS="LVCMOS33"><IPort NNm="FB7_5_Q"/><OPort NNm="cclk&lt;4&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB7_5_FF"><FlopPort NNm="FB7_PT22" Port="D"/><FlopPort NNm="FB7_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_5_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_6"><ClkMux Nm="FB7_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_6_MC_CLK"/></ClkMux><FbMux Nm="FB7_6_N"><IPort NNm="FB7_6_Q"/></FbMux><DFlop Nm="FB7_6_FF"><FlopPort NNm="FB7_6_OR" Port="D"/><FlopPort NNm="FB7_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_6_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB7_6_OR"><OPort NNm="FB7_6_OR"/><IPort NNm="FB7_PT0"/><IPort NNm="FB7_PT1"/></Or></Mc><Mc Nm="FB7_7"><ClkMux Nm="FB7_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_7_MC_CLK"/></ClkMux><XorMux Nm="FB7_7_AND"><IPort NNm="FB7_PT28"/></XorMux><FbMux Nm="FB7_7_N"><IPort NNm="FB7_7_Q"/></FbMux><DFlop Nm="FB7_7_FF"><FlopPort NNm="FB7_PT28" Port="D"/><FlopPort NNm="FB7_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_7_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_8"><ClkMux Nm="FB7_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_8_MC_CLK"/></ClkMux><XorMux Nm="FB7_8_AND"><IPort NNm="FB7_PT31"/></XorMux><FbMux Nm="FB7_8_N"><IPort NNm="FB7_8_Q"/></FbMux><DFlop Nm="FB7_8_FF"><FlopPort NNm="FB7_PT31" Port="D"/><FlopPort NNm="FB7_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_8_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_9"><ClkMux Nm="FB7_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_9_MC_CLK"/></ClkMux><XorMux Nm="FB7_9_AND"><IPort NNm="FB7_PT34"/></XorMux><FbMux Nm="FB7_9_N"><IPort NNm="FB7_9_Q"/></FbMux><DFlop Nm="FB7_9_FF"><FlopPort NNm="FB7_PT34" Port="D"/><FlopPort NNm="FB7_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_9_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_10"><ClkMux Nm="FB7_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_10_MC_CLK"/></ClkMux><XorMux Nm="FB7_10_AND"><IPort NNm="FB7_PT37"/></XorMux><FbMux Nm="FB7_10_N"><IPort NNm="FB7_10_Q"/></FbMux><DFlop Nm="FB7_10_FF"><FlopPort NNm="FB7_PT37" Port="D"/><FlopPort NNm="FB7_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_10_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_11"><RMux Nm="FB7_11_RST"><IPort NNm="FB7_PT5"/></RMux><ClkMux Nm="FB7_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB7_11_MC_CLK"/></ClkMux><XorMux Nm="FB7_11_AND"><IPort NNm="FB7_PT40"/></XorMux><FbMux Nm="FB7_11_N"><IPort NNm="FB7_11_Q"/></FbMux><DFlop Nm="FB7_11_FF"><FlopPort NNm="FB7_PT40" Port="D"/><FlopPort NNm="FB7_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB7_11_Q" Port="Q"/><FlopPort NNm="FB7_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB7_12"><XorMux Nm="FB7_12_AND"><IPort NNm="FB7_PT43"/></XorMux><FbMux Nm="FB7_12_N"><IPort NNm="FB7_PT43"/></FbMux><InBuf Nm="FB7_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="clk"/><OPort NNm="FB7_12_I"/></InBuf></Mc><Mc Nm="FB7_13"><XorMux Nm="FB7_13_AND"><IPort NNm="FB7_PT46"/></XorMux><FbMux Nm="FB7_13_N"><IPort NNm="FB7_PT46"/></FbMux></Mc><Mc Nm="FB7_14"><XorMux Nm="FB7_14_AND"><IPort NNm="FB7_14_OR"/></XorMux><FbMux Nm="FB7_14_N"><IPort NNm="FB7_14_OR"/></FbMux><FbMux Nm="FB7_14_P"><IPort NNm="FB7_14_I"/></FbMux><InBuf Nm="FB7_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_done&lt;0&gt;"/><OPort NNm="FB7_14_I"/></InBuf><Or Nm="FB7_14_OR"><OPort NNm="FB7_14_OR"/><IPort NNm="FB7_PT7"/><IPort NNm="FB7_PT6"/><IPort NNm="FB7_PT4"/><IPort NNm="FB7_PT3"/><IPort NNm="FB7_PT9"/><IPort NNm="FB7_PT8"/><IPort NNm="FB7_PT49"/></Or></Mc><Mc Nm="FB7_15"><FbMux Nm="FB7_15_N"><IPort NNm="FB7_15_OR"/></FbMux><InBuf Nm="FB7_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="clk_slow"/><OPort NNm="FB7_15_I"/></InBuf><Or Nm="FB7_15_OR"><OPort NNm="FB7_15_OR"/><IPort NNm="FB7_PT43"/><IPort NNm="FB7_PT2"/></Or></Mc><Mc Nm="FB7_16"><FbMux Nm="FB7_16_N"><IPort NNm="FB7_16_OR"/></FbMux><FbMux Nm="FB7_16_P"><IPort NNm="FB7_16_I"/></FbMux><InBuf Nm="FB7_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_done&lt;1&gt;"/><OPort NNm="FB7_16_I"/></InBuf><Or Nm="FB7_16_OR"><OPort NNm="FB7_16_OR"/><IPort NNm="FB7_PT0"/><IPort NNm="FB7_PT1"/></Or></Mc></Lb><Lb Nm="FB8"><LbT Nm="FB8_PT0" PtT="XBR_CT_X"><OPort NNm="FB8_PT0"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB22_15_I"/></LbT><LbT Nm="FB8_PT1" PtT="XBR_CT_X"><OPort NNm="FB8_PT1"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB21_12_I"/></LbT><LbT Nm="FB8_PT2" PtT="XBR_CT_X"><OPort NNm="FB8_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB7_16_I"/></LbT><LbT Nm="FB8_PT3" PtT="XBR_CT_X"><OPort NNm="FB8_PT3"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB5_14_Q"/></LbT><LbT Nm="FB8_PT4" PtT="XBR_CT"><OPort NNm="FB8_PT4"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_6_Q"/></LbT><LbT Nm="FB8_PT5" PtT="XBR_CT"><OPort NNm="FB8_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB8_PT6" PtT="XBR_CT"><OPort NNm="FB8_PT6"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB8_PT7" PtT="XBR_CT"><OPort NNm="FB8_PT7"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_15_Q"/></LbT><LbT Nm="FB8_PT8" PtT="XBR_A"><OPort NNm="FB8_PT8"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_11_Q"/></LbT><LbT Nm="FB8_PT9" PtT="XBR_B"><OPort NNm="FB8_PT9"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_8_Q"/></LbT><LbT Nm="FB8_PT10" PtT="XBR_C"><OPort NNm="FB8_PT10"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_11_Q"/></LbT><LbT Nm="FB8_PT11" PtT="XBR_A"><OPort NNm="FB8_PT11"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_16_I"/></LbT><LbT Nm="FB8_PT12" PtT="XBR_B"><OPort NNm="FB8_PT12"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB21_4_I"/></LbT><LbT Nm="FB8_PT13" PtT="XBR_C"><OPort NNm="FB8_PT13"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB8_PT14" PtT="XBR_A"><OPort NNm="FB8_PT14"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_8_Q"/></LbT><LbT Nm="FB8_PT15" PtT="XBR_B"><OPort NNm="FB8_PT15"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB8_2_Q"/></LbT><LbT Nm="FB8_PT16" PtT="XBR_C"><OPort NNm="FB8_PT16"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB8_PT17" PtT="XBR_A"><OPort NNm="FB8_PT17"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_9_Q"/></LbT><LbT Nm="FB8_PT18" PtT="XBR_B"><OPort NNm="FB8_PT18"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_11_Q"/></LbT><LbT Nm="FB8_PT19" PtT="XBR_C"><OPort NNm="FB8_PT19"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB8_PT20" PtT="XBR_A"><OPort NNm="FB8_PT20"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_1_Q"/></LbT><LbT Nm="FB8_PT21" PtT="XBR_B"><OPort NNm="FB8_PT21"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB8_14_Q"/></LbT><LbT Nm="FB8_PT22" PtT="XBR_C"><OPort NNm="FB8_PT22"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB5_PT37"/></LbT><LbT Nm="FB8_PT23" PtT="XBR_A"><OPort NNm="FB8_PT23"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB8_4_Q"/></LbT><LbT Nm="FB8_PT24" PtT="XBR_B"><OPort NNm="FB8_PT24"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_10_Q"/></LbT><LbT Nm="FB8_PT25" PtT="XBR_C"><OPort NNm="FB8_PT25"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB11_14_Q"/></LbT><LbT Nm="FB8_PT26" PtT="XBR_A"><OPort NNm="FB8_PT26"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB21_1_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB8_PT27" PtT="XBR_B"><OPort NNm="FB8_PT27"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB8_3_Q"/></LbT><LbT Nm="FB8_PT28" PtT="XBR_C"><OPort NNm="FB8_PT28"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_9_Q"/></LbT><LbT Nm="FB8_PT29" PtT="XBR_A"><OPort NNm="FB8_PT29"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB21_3_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB8_PT30" PtT="XBR_B"><OPort NNm="FB8_PT30"/><IPort NNm="FB5_4_I"/></LbT><LbT Nm="FB8_PT31" PtT="XBR_C"><OPort NNm="FB8_PT31"/><IPort NNm="FB9_2_I"/></LbT><LbT Nm="FB8_PT32" PtT="XBR_A"><OPort NNm="FB8_PT32"/><IPort NNm="FB8_2_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB8_PT33" PtT="XBR_B"><OPort NNm="FB8_PT33"/><IPort NNm="FB8_14_Q"/><IPort NNm="FB22_2_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB8_PT55" PtT="XBR_C"><OPort NNm="FB8_PT55"/><IPort NNm="FB4_PT34"/></LbT><Mc Nm="FB8_1"><OeMux Nm="FB8_1_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB8_1_P"><IPort NNm="FB8_1_I"/></FbMux><InBuf Nm="FB8_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;3&gt;"/><OPort NNm="FB8_1_I"/></InBuf><OutBuf Nm="FB8_1_O" IOS="LVCMOS33"><IPort NNm="FB8_1_OR"/><OPort NNm="db&lt;3&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><Or Nm="FB8_1_OR"><OPort NNm="FB8_1_OR"/><IPort NNm="FB8_PT8"/><IPort NNm="FB8_PT9"/><IPort NNm="FB8_PT7"/><IPort NNm="FB8_PT4"/><IPort NNm="FB8_PT0"/><IPort NNm="FB8_PT1"/><IPort NNm="FB8_PT10"/><IPort NNm="FB8_PT3"/><IPort NNm="FB8_PT2"/></Or></Mc><Mc Nm="FB8_2"><RMux Nm="FB8_2_RST"><IPort NNm="FB8_PT5"/></RMux><ClkMux Nm="FB8_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB8_2_MC_CLK"/></ClkMux><OeMux Nm="FB8_2_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB8_2_N"><IPort NNm="FB8_2_Q"/></FbMux><FbMux Nm="FB8_2_P"><IPort NNm="FB8_2_I"/></FbMux><InBuf Nm="FB8_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;6&gt;"/><OPort NNm="FB8_2_I"/></InBuf><OutBuf Nm="FB8_2_O" IOS="LVCMOS33"><IPort NNm="FB8_2_Q"/><OPort NNm="db&lt;6&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB8_2_FF"><FlopPort NNm="FB8_2_I" Port="D"/><FlopPort NNm="FB8_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB8_2_Q" Port="Q"/><FlopPort NNm="FB8_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB8_PT13" Port="CE"/></DFlop></Mc><Mc Nm="FB8_3"><RMux Nm="FB8_3_RST"><IPort NNm="FB8_PT5"/></RMux><ClkMux Nm="FB8_3_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB8_3_MC_CLK"/></ClkMux><OeMux Nm="FB8_3_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB8_3_N"><IPort NNm="FB8_3_Q"/></FbMux><FbMux Nm="FB8_3_P"><IPort NNm="FB8_3_I"/></FbMux><InBuf Nm="FB8_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;14&gt;"/><OPort NNm="FB8_3_I"/></InBuf><OutBuf Nm="FB8_3_O" IOS="LVCMOS33"><IPort NNm="FB8_3_Q"/><OPort NNm="db&lt;14&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB8_3_FF"><FlopPort NNm="FB8_3_I" Port="D"/><FlopPort NNm="FB8_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB8_3_Q" Port="Q"/><FlopPort NNm="FB8_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB8_PT16" Port="CE"/></DFlop></Mc><Mc Nm="FB8_4"><RMux Nm="FB8_4_PST"><IPort NNm="FB8_PT6"/></RMux><ClkMux Nm="FB8_4_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB8_4_MC_CLK"/></ClkMux><OeMux Nm="FB8_4_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB8_4_N"><IPort NNm="FB8_4_Q"/></FbMux><FbMux Nm="FB8_4_P"><IPort NNm="FB8_4_I"/></FbMux><InBuf Nm="FB8_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;12&gt;"/><OPort NNm="FB8_4_I"/></InBuf><OutBuf Nm="FB8_4_O" IOS="LVCMOS33"><IPort NNm="FB8_4_Q"/><OPort NNm="db&lt;12&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB8_4_FF"><FlopPort NNm="FB8_4_I" Port="D"/><FlopPort NNm="FB8_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB8_4_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB8_PT6" Port="PST"/><FlopPort NNm="FB8_PT16" Port="CE"/></DFlop></Mc><Mc Nm="FB8_5"><RMux Nm="FB8_5_PST"><IPort NNm="FB8_PT6"/></RMux><ClkMux Nm="FB8_5_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB8_5_MC_CLK"/></ClkMux><FbMux Nm="FB8_5_N"><IPort NNm="FB8_5_Q"/></FbMux><DFlop Nm="FB8_5_FF"><FlopPort NNm="FB8_5_OR" Port="D"/><FlopPort NNm="FB8_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB8_5_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB8_PT6" Port="PST"/><FlopPort NNm="FB8_PT22" Port="CE"/></DFlop><Or Nm="FB8_5_OR"><OPort NNm="FB8_5_OR"/><IPort NNm="FB8_PT30"/></Or></Mc><Mc Nm="FB8_6"/><Mc Nm="FB8_7"/><Mc Nm="FB8_8"/><Mc Nm="FB8_9"/><Mc Nm="FB8_10"/><Mc Nm="FB8_11"/><Mc Nm="FB8_12"/><Mc Nm="FB8_13"><InBuf Nm="FB8_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="mspare_1"/></InBuf><OutBuf Nm="FB8_13_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="mspare_1"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB8_14"><RMux Nm="FB8_14_RST"><IPort NNm="FB8_PT5"/></RMux><ClkMux Nm="FB8_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB8_14_MC_CLK"/></ClkMux><FbMux Nm="FB8_14_N"><IPort NNm="FB8_14_Q"/></FbMux><DFlop Nm="FB8_14_FF"><FlopPort NNm="FB8_14_OR" Port="D"/><FlopPort NNm="FB8_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB8_14_Q" Port="Q"/><FlopPort NNm="FB8_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB8_14_OR"><OPort NNm="FB8_14_OR"/><IPort NNm="FB8_PT32"/><IPort NNm="FB8_PT33"/></Or></Mc><Mc Nm="FB8_15"><FbMux Nm="FB8_15_P"><IPort NNm="FB8_15_I"/></FbMux><InBuf Nm="FB8_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fl_switch&lt;2&gt;"/><OPort NNm="FB8_15_I"/></InBuf></Mc><Mc Nm="FB8_16"><RMux Nm="FB8_16_RST"><IPort NNm="FB8_PT5"/></RMux><ClkMux Nm="FB8_16_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB8_16_MC_CLK"/></ClkMux><FbMux Nm="FB8_16_N"><IPort NNm="FB8_16_Q"/></FbMux><DFlop Nm="FB8_16_FF"><FlopPort NNm="FB8_16_OR" Port="D"/><FlopPort NNm="FB8_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB8_16_Q" Port="Q"/><FlopPort NNm="FB8_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB8_PT16" Port="CE"/></DFlop><Or Nm="FB8_16_OR"><OPort NNm="FB8_16_OR"/><IPort NNm="FB8_PT31"/></Or></Mc></Lb><Lb Nm="FB9"><LbT Nm="FB9_PT0" PtT="XBR_CT_X"><OPort NNm="FB9_PT0"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_15_I"/></LbT><LbT Nm="FB9_PT1" PtT="XBR_CT_X"><OPort NNm="FB9_PT1"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB22_2_I"/></LbT><LbT Nm="FB9_PT2" PtT="XBR_CT_X"><OPort NNm="FB9_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB3_15_I"/></LbT><LbT Nm="FB9_PT3" PtT="XBR_CT_X"><OPort NNm="FB9_PT3"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB9_PT4" PtT="XBR_CT"><OPort NNm="FB9_PT4"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_10_Q"/></LbT><LbT Nm="FB9_PT5" PtT="XBR_CT"><OPort NNm="FB9_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB9_PT6" PtT="XBR_CT"><OPort NNm="FB9_PT6"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB9_PT7" PtT="XBR_CT"><OPort NNm="FB9_PT7"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_2_Q"/></LbT><LbT Nm="FB9_PT8" PtT="XBR_A"><OPort NNm="FB9_PT8"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_10_Q"/></LbT><LbT Nm="FB9_PT9" PtT="XBR_B"><OPort NNm="FB9_PT9"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB13_2_Q"/></LbT><LbT Nm="FB9_PT10" PtT="XBR_C"><OPort NNm="FB9_PT10"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB9_PT11" PtT="XBR_A"><OPort NNm="FB9_PT11"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB8_16_Q"/></LbT><LbT Nm="FB9_PT12" PtT="XBR_B"><OPort NNm="FB9_PT12"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB9_2_Q"/></LbT><LbT Nm="FB9_PT13" PtT="XBR_C"><OPort NNm="FB9_PT13"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><LbT Nm="FB9_PT14" PtT="XBR_A"><OPort NNm="FB9_PT14"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB21_2_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB9_PT15" PtT="XBR_B"><OPort NNm="FB9_PT15"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB13_2_Q"/></LbT><LbT Nm="FB9_PT16" PtT="XBR_C"><OPort NNm="FB9_PT16"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_16_Q"/></LbT><LbT Nm="FB9_PT17" PtT="XBR_A"><OPort NNm="FB9_PT17"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_16_Q"/></LbT><LbT Nm="FB9_PT18" PtT="XBR_B"><OPort NNm="FB9_PT18"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_11_Q"/></LbT><LbT Nm="FB9_PT19" PtT="XBR_C"><OPort NNm="FB9_PT19"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_11_Q"/></LbT><LbT Nm="FB9_PT20" PtT="XBR_A"><OPort NNm="FB9_PT20"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_10_Q"/></LbT><LbT Nm="FB9_PT21" PtT="XBR_B"><OPort NNm="FB9_PT21"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_10_Q"/></LbT><LbT Nm="FB9_PT22" PtT="XBR_C"><OPort NNm="FB9_PT22"/><IPort NNm="FB15_4_Q"/><IPort NNm="FB7_PT43"/></LbT><LbT Nm="FB9_PT23" PtT="XBR_A"><OPort NNm="FB9_PT23"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_9_Q"/></LbT><LbT Nm="FB9_PT24" PtT="XBR_B"><OPort NNm="FB9_PT24"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_9_Q"/></LbT><LbT Nm="FB9_PT25" PtT="XBR_C"><OPort NNm="FB9_PT25"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB9_8_Q"/></LbT><LbT Nm="FB9_PT43" PtT="XBR_C"><OPort NNm="FB9_PT43"/><IPort NNm="FB15_1_Q"/><IPort NNm="FB7_PT43"/></LbT><LbT Nm="FB9_PT46" PtT="XBR_C"><OPort NNm="FB9_PT46"/><IPort NNm="FB17_15_Q"/><IPort NNm="FB7_PT43"/></LbT><LbT Nm="FB9_PT49" PtT="XBR_C"><OPort NNm="FB9_PT49"/><IPort NNm="FB17_11_Q"/><IPort NNm="FB7_PT43"/></LbT><LbT Nm="FB9_PT52" PtT="XBR_C"><OPort NNm="FB9_PT52"/><IPort NNm="FB17_10_Q"/><IPort NNm="FB7_PT43"/></LbT><Mc Nm="FB9_1"><RMux Nm="FB9_1_PST"><IPort NNm="FB9_PT6"/></RMux><ClkMux Nm="FB9_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB9_1_MC_CLK"/></ClkMux><OeMux Nm="FB9_1_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB9_1_N"><IPort NNm="FB9_1_Q"/></FbMux><FbMux Nm="FB9_1_P"><IPort NNm="FB9_1_I"/></FbMux><InBuf Nm="FB9_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;5&gt;"/><OPort NNm="FB9_1_I"/></InBuf><OutBuf Nm="FB9_1_O" IOS="LVCMOS33"><IPort NNm="FB9_1_Q"/><OPort NNm="db&lt;5&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB9_1_FF"><FlopPort NNm="FB9_1_I" Port="D"/><FlopPort NNm="FB9_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB9_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB9_PT6" Port="PST"/><FlopPort NNm="FB9_PT10" Port="CE"/></DFlop></Mc><Mc Nm="FB9_2"><RMux Nm="FB9_2_RST"><IPort NNm="FB9_PT5"/></RMux><ClkMux Nm="FB9_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB9_2_MC_CLK"/></ClkMux><OeMux Nm="FB9_2_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB9_2_N"><IPort NNm="FB9_2_Q"/></FbMux><FbMux Nm="FB9_2_P"><IPort NNm="FB9_2_I"/></FbMux><InBuf Nm="FB9_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;13&gt;"/><OPort NNm="FB9_2_I"/></InBuf><OutBuf Nm="FB9_2_O" IOS="LVCMOS33"><IPort NNm="FB9_2_Q"/><OPort NNm="db&lt;13&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB9_2_FF"><FlopPort NNm="FB9_2_I" Port="D"/><FlopPort NNm="FB9_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB9_2_Q" Port="Q"/><FlopPort NNm="FB9_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB9_PT10" Port="CE"/></DFlop></Mc><Mc Nm="FB9_3"><InBuf Nm="FB9_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_f_p&lt;15&gt;"/></InBuf><OutBuf Nm="FB9_3_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="add_f_p&lt;15&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB9_4"><InBuf Nm="FB9_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_f_p&lt;9&gt;"/></InBuf><OutBuf Nm="FB9_4_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="add_f_p&lt;9&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB9_5"><XorMux Nm="FB9_5_AND"><IPort NNm="FB9_PT22"/></XorMux><InBuf Nm="FB9_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="prgm_fpga_p&lt;0&gt;"/></InBuf><OutBuf Nm="FB9_5_O" IOS="LVCMOS33"><IPort NNm="FB9_PT22"/><OPort NNm="prgm_fpga_p&lt;0&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB9_6"/><Mc Nm="FB9_7"/><Mc Nm="FB9_8"><RMux Nm="FB9_8_RST"><IPort NNm="FB9_PT5"/></RMux><ClkMux Nm="FB9_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB9_8_MC_CLK"/></ClkMux><FbMux Nm="FB9_8_N"><IPort NNm="FB9_8_Q"/></FbMux><DFlop Nm="FB9_8_FF"><FlopPort NNm="FB9_8_OR" Port="D"/><FlopPort NNm="FB9_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB9_8_Q" Port="Q"/><FlopPort NNm="FB9_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB9_8_OR"><OPort NNm="FB9_8_OR"/><IPort NNm="FB9_PT24"/><IPort NNm="FB9_PT25"/></Or></Mc><Mc Nm="FB9_9"><RMux Nm="FB9_9_RST"><IPort NNm="FB9_PT5"/></RMux><ClkMux Nm="FB9_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB9_9_MC_CLK"/></ClkMux><FbMux Nm="FB9_9_N"><IPort NNm="FB9_9_Q"/></FbMux><DFlop Nm="FB9_9_FF"><FlopPort NNm="FB9_9_OR" Port="D"/><FlopPort NNm="FB9_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB9_9_Q" Port="Q"/><FlopPort NNm="FB9_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB9_9_OR"><OPort NNm="FB9_9_OR"/><IPort NNm="FB9_PT21"/><IPort NNm="FB9_PT23"/></Or></Mc><Mc Nm="FB9_10"><RMux Nm="FB9_10_RST"><IPort NNm="FB9_PT5"/></RMux><ClkMux Nm="FB9_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB9_10_MC_CLK"/></ClkMux><FbMux Nm="FB9_10_N"><IPort NNm="FB9_10_Q"/></FbMux><DFlop Nm="FB9_10_FF"><FlopPort NNm="FB9_10_OR" Port="D"/><FlopPort NNm="FB9_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB9_10_Q" Port="Q"/><FlopPort NNm="FB9_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB9_10_OR"><OPort NNm="FB9_10_OR"/><IPort NNm="FB9_PT19"/><IPort NNm="FB9_PT20"/></Or></Mc><Mc Nm="FB9_11"><RMux Nm="FB9_11_RST"><IPort NNm="FB9_PT5"/></RMux><ClkMux Nm="FB9_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB9_11_MC_CLK"/></ClkMux><FbMux Nm="FB9_11_N"><IPort NNm="FB9_11_Q"/></FbMux><DFlop Nm="FB9_11_FF"><FlopPort NNm="FB9_11_OR" Port="D"/><FlopPort NNm="FB9_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB9_11_Q" Port="Q"/><FlopPort NNm="FB9_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB9_11_OR"><OPort NNm="FB9_11_OR"/><IPort NNm="FB9_PT17"/><IPort NNm="FB9_PT18"/></Or></Mc><Mc Nm="FB9_12"><XorMux Nm="FB9_12_AND"><IPort NNm="FB9_PT43"/></XorMux><InBuf Nm="FB9_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="prgm_fpga_p&lt;1&gt;"/></InBuf><OutBuf Nm="FB9_12_O" IOS="LVCMOS33"><IPort NNm="FB9_PT43"/><OPort NNm="prgm_fpga_p&lt;1&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB9_13"><XorMux Nm="FB9_13_AND"><IPort NNm="FB9_PT46"/></XorMux><InBuf Nm="FB9_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="prgm_fpga_p&lt;2&gt;"/></InBuf><OutBuf Nm="FB9_13_O" IOS="LVCMOS33"><IPort NNm="FB9_PT46"/><OPort NNm="prgm_fpga_p&lt;2&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB9_14"><XorMux Nm="FB9_14_AND"><IPort NNm="FB9_PT49"/></XorMux><InBuf Nm="FB9_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="prgm_fpga_p&lt;3&gt;"/></InBuf><OutBuf Nm="FB9_14_O" IOS="LVCMOS33"><IPort NNm="FB9_PT49"/><OPort NNm="prgm_fpga_p&lt;3&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB9_15"><XorMux Nm="FB9_15_AND"><IPort NNm="FB9_PT52"/></XorMux><InBuf Nm="FB9_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="prgm_fpga_p&lt;4&gt;"/></InBuf><OutBuf Nm="FB9_15_O" IOS="LVCMOS33"><IPort NNm="FB9_PT52"/><OPort NNm="prgm_fpga_p&lt;4&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB9_16"><RMux Nm="FB9_16_RST"><IPort NNm="FB9_PT5"/></RMux><ClkMux Nm="FB9_16_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB9_16_MC_CLK"/></ClkMux><FbMux Nm="FB9_16_N"><IPort NNm="FB9_16_Q"/></FbMux><DFlop Nm="FB9_16_FF"><FlopPort NNm="FB9_16_OR" Port="D"/><FlopPort NNm="FB9_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB9_16_Q" Port="Q"/><FlopPort NNm="FB9_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB9_16_OR"><OPort NNm="FB9_16_OR"/><IPort NNm="FB9_PT15"/><IPort NNm="FB9_PT16"/></Or></Mc></Lb><Lb Nm="FB10"><LbT Nm="FB10_PT0" PtT="XBR_CT_X"><OPort NNm="FB10_PT0"/><IPort NNm="FB10_11_Q"/></LbT><LbT Nm="FB10_PT1" PtT="XBR_CT_X"><OPort NNm="FB10_PT1"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB11_8_Q"/></LbT><LbT Nm="FB10_PT2" PtT="XBR_CT_X"><OPort NNm="FB10_PT2"/><IPort NNm="FB11_8_Q"/><IPort NNm="FB7_14_OR"/></LbT><LbT Nm="FB10_PT3" PtT="XBR_CT_X"><OPort NNm="FB10_PT3"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB10_16_Q"/></LbT><LbT Nm="FB10_PT4" PtT="XBR_CT"><OPort NNm="FB10_PT4"/><IPort NNm="FB10_16_Q"/><IPort NNm="FB7_14_OR"/></LbT><LbT Nm="FB10_PT5" PtT="XBR_CT"><OPort NNm="FB10_PT5"/><IPort NNm="FB1_1_I"/><IPort NNm="FB19_15_I"/></LbT><LbT Nm="FB10_PT6" PtT="XBR_CT"><OPort NNm="FB10_PT6"/><IPort NNm="FB19_12_I"/></LbT><LbT Nm="FB10_PT7" PtT="XBR_CT"><OPort NNm="FB10_PT7"/><IPort NNm="FB10_16_Q"/><IPort NNm="FB10_14_Q"/></LbT><LbT Nm="FB10_PT10" PtT="XBR_C"><OPort NNm="FB10_PT10"/><IPort NNm="FB19_14_I"/></LbT><LbT Nm="FB10_PT11" PtT="XBR_A"><OPort NNm="FB10_PT11"/><IPort NNm="FB1_1_I"/><IPort NNm="FB19_15_I"/></LbT><LbT Nm="FB10_PT13" PtT="XBR_C"><OPort NNm="FB10_PT13"/><IPort NNm="FB19_13_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB21_15_I"/><IPort NNm="FB10_15_I"/><IPort NNm="FB23_3_I"/><IPort NNm="FB19_4_I"/><IPort NNm="FB14_14_I"/><IPort NNm="FB10_16_I"/><IPort NNm="FB19_5_I"/><IPort NNm="FB14_16_I"/><IPort NNm="FB11_6_Q"/><IPort NNm="FB10_2_Q"/></LbT><LbT Nm="FB10_PT14" PtT="XBR_A"><OPort NNm="FB10_PT14"/><IPort NNm="FB1_1_I"/></LbT><LbT Nm="FB10_PT19" PtT="XBR_C"><OPort NNm="FB10_PT19"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB24_2_I"/></LbT><LbT Nm="FB10_PT22" PtT="XBR_C"><OPort NNm="FB10_PT22"/><IPort NNm="FB10_11_Q"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB21_5_I"/><IPort NNm="FB19_1_Q"/></LbT><LbT Nm="FB10_PT25" PtT="XBR_C"><OPort NNm="FB10_PT25"/><IPort NNm="FB10_9_Q"/></LbT><LbT Nm="FB10_PT28" PtT="XBR_C"><OPort NNm="FB10_PT28"/><IPort NNm="FB10_6_Q"/></LbT><LbT Nm="FB10_PT31" PtT="XBR_C"><OPort NNm="FB10_PT31"/><IPort NNm="FB1_1_I"/><IPort NNm="FB19_15_I"/></LbT><LbT Nm="FB10_PT34" PtT="XBR_C"><OPort NNm="FB10_PT34"/><IPort NNm="FB19_1_Q"/></LbT><LbT Nm="FB10_PT37" PtT="XBR_C"><OPort NNm="FB10_PT37"/><IPort NNm="FB19_13_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB21_15_I"/><IPort NNm="FB10_15_I"/><IPort NNm="FB23_3_I"/><IPort NNm="FB19_4_I"/><IPort NNm="FB14_14_I"/><IPort NNm="FB10_16_I"/><IPort NNm="FB19_5_I"/><IPort NNm="FB14_16_I"/><IPort NNm="FB11_6_Q"/></LbT><LbT Nm="FB10_PT40" PtT="XBR_C"><OPort NNm="FB10_PT40"/><IPort NNm="FB19_13_I"/><IPort NNm="FB10_11_Q"/><IPort NNm="FB21_13_I"/><IPort NNm="FB21_15_I"/><IPort NNm="FB10_15_I"/><IPort NNm="FB23_3_I"/><IPort NNm="FB19_4_I"/><IPort NNm="FB14_14_I"/><IPort NNm="FB10_16_I"/><IPort NNm="FB19_5_I"/><IPort NNm="FB14_16_I"/><IPort NNm="FB11_6_Q"/></LbT><LbT Nm="FB10_PT50" PtT="XBR_A"><OPort NNm="FB10_PT50"/><IPort NNm="FB1_1_I"/></LbT><LbT Nm="FB10_PT53" PtT="XBR_A"><OPort NNm="FB10_PT53"/><IPort NNm="FB1_1_I"/></LbT><LbT Nm="FB10_PT55" PtT="XBR_C"><OPort NNm="FB10_PT55"/><IPort NNm="FB11_8_Q"/></LbT><Mc Nm="FB10_1"><XorMux Nm="FB10_1_AND"><IPort NNm="FB10_PT10"/></XorMux><InBuf Nm="FB10_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="etr_vf"/></InBuf><OutBuf Nm="FB10_1_O" IOS="LVCMOS33"><IPort NNm="FB10_PT10"/><OPort NNm="etr_vf"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB10_2"><ClkMux Nm="FB10_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_2_MC_CLK"/></ClkMux><XorMux Nm="FB10_2_AND"><IPort NNm="FB10_PT13"/></XorMux><FbMux Nm="FB10_2_N"><IPort NNm="FB10_2_Q"/></FbMux><InBuf Nm="FB10_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="etr_x"/></InBuf><OutBuf Nm="FB10_2_O" IOS="LVCMOS33"><IPort NNm="FB10_2_Q"/><OPort NNm="etr_x"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB10_2_FF"><FlopPort NNm="FB10_PT13" Port="D"/><FlopPort NNm="FB10_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_2_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB10_3"><ClkMux Nm="FB10_3_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_3_MC_CLK"/></ClkMux><FbMux Nm="FB10_3_N"><IPort NNm="FB10_3_Q"/></FbMux><DFlop Nm="FB10_3_FF"><FlopPort NNm="FB10_3_OR" Port="D"/><FlopPort NNm="FB10_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_3_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB10_3_OR"><OPort NNm="FB10_3_OR"/><IPort NNm="FB10_PT1"/><IPort NNm="FB10_PT2"/></Or></Mc><Mc Nm="FB10_4"><XorMux Nm="FB10_4_AND"><IPort NNm="FB10_PT19"/></XorMux><InBuf Nm="FB10_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="ldpreg"/></InBuf><OutBuf Nm="FB10_4_O" IOS="LVCMOS33"><IPort NNm="FB10_PT19"/><OPort NNm="ldpreg"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB10_5"><XorMux Nm="FB10_5_AND"><IPort NNm="FB10_PT22"/></XorMux><InBuf Nm="FB10_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="g245_p"/></InBuf><OutBuf Nm="FB10_5_O" IOS="LVCMOS33"><IPort NNm="FB10_PT22"/><OPort NNm="g245_p"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB10_6"><RMux Nm="FB10_6_RST"><IPort NNm="FB10_PT5"/></RMux><ClkMux Nm="FB10_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_6_MC_CLK"/></ClkMux><XorMux Nm="FB10_6_AND"><IPort NNm="FB10_PT25"/></XorMux><FbMux Nm="FB10_6_N"><IPort NNm="FB10_6_Q"/></FbMux><DFlop Nm="FB10_6_FF"><FlopPort NNm="FB10_PT25" Port="D"/><FlopPort NNm="FB10_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_6_Q" Port="Q"/><FlopPort NNm="FB10_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB10_7"><RMux Nm="FB10_7_RST"><IPort NNm="FB10_PT5"/></RMux><ClkMux Nm="FB10_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_7_MC_CLK"/></ClkMux><XorMux Nm="FB10_7_AND"><IPort NNm="FB10_PT28"/></XorMux><FbMux Nm="FB10_7_N"><IPort NNm="FB10_7_Q"/></FbMux><DFlop Nm="FB10_7_FF"><FlopPort NNm="FB10_PT28" Port="D"/><FlopPort NNm="FB10_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_7_Q" Port="Q"/><FlopPort NNm="FB10_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB10_8"><ClkMux Nm="FB10_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_8_MC_CLK"/></ClkMux><XorMux Nm="FB10_8_AND"><IPort NNm="FB10_PT31"/></XorMux><FbMux Nm="FB10_8_N"><IPort NNm="FB10_8_Q"/></FbMux><DFlop Nm="FB10_8_FF"><FlopPort NNm="FB10_PT31" Port="D"/><FlopPort NNm="FB10_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_8_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB10_9"><RMux Nm="FB10_9_RST"><IPort NNm="FB10_PT5"/></RMux><ClkMux Nm="FB10_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_9_MC_CLK"/></ClkMux><XorMux Nm="FB10_9_AND"><IPort NNm="FB10_PT34"/></XorMux><FbMux Nm="FB10_9_N"><IPort NNm="FB10_9_Q"/></FbMux><DFlop Nm="FB10_9_FF"><FlopPort NNm="FB10_PT34" Port="D"/><FlopPort NNm="FB10_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_9_Q" Port="Q"/><FlopPort NNm="FB10_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB10_10"><RMux Nm="FB10_10_RST"><IPort NNm="FB10_PT5"/></RMux><ClkMux Nm="FB10_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_10_MC_CLK"/></ClkMux><FbMux Nm="FB10_10_N"><IPort NNm="FB10_10_Q"/></FbMux><DFlop Nm="FB10_10_FF"><FlopPort NNm="FB10_10_OR" Port="D"/><FlopPort NNm="FB10_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_10_Q" Port="Q"/><FlopPort NNm="FB10_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB10_PT37" Port="CE"/></DFlop><Or Nm="FB10_10_OR"><OPort NNm="FB10_10_OR"/><IPort NNm="FB10_PT0"/></Or></Mc><Mc Nm="FB10_11"><RMux Nm="FB10_11_RST"><IPort NNm="FB10_PT5"/></RMux><ClkMux Nm="FB10_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_11_MC_CLK"/></ClkMux><XorMux Nm="FB10_11_AND"><IPort NNm="FB10_PT40"/></XorMux><FbMux Nm="FB10_11_N"><IPort NNm="FB10_11_Q"/></FbMux><DFlop Nm="FB10_11_FF"><FlopPort NNm="FB10_PT40" Port="D"/><FlopPort NNm="FB10_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_11_Q" Port="Q"/><FlopPort NNm="FB10_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB10_12"><FbMux Nm="FB10_12_P"><IPort NNm="FB10_12_I"/></FbMux><InBuf Nm="FB10_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;0&gt;"/><OPort NNm="FB10_12_I"/></InBuf></Mc><Mc Nm="FB10_13"><FbMux Nm="FB10_13_P"><IPort NNm="FB10_13_I"/></FbMux><InBuf Nm="FB10_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;1&gt;"/><OPort NNm="FB10_13_I"/></InBuf></Mc><Mc Nm="FB10_14"><RMux Nm="FB10_14_PST"><IPort NNm="FB10_PT6"/></RMux><ClkMux Nm="FB10_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_14_MC_CLK"/></ClkMux><FbMux Nm="FB10_14_N"><IPort NNm="FB10_14_Q"/></FbMux><FbMux Nm="FB10_14_P"><IPort NNm="FB10_14_I"/></FbMux><InBuf Nm="FB10_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;2&gt;"/><OPort NNm="FB10_14_I"/></InBuf><DFlop Nm="FB10_14_FF"><FlopPort NNm="FB10_14_OR" Port="D"/><FlopPort NNm="FB10_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_14_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB10_PT6" Port="PST"/></DFlop><Or Nm="FB10_14_OR"><OPort NNm="FB10_14_OR"/><IPort NNm="FB10_PT4"/><IPort NNm="FB10_PT7"/></Or></Mc><Mc Nm="FB10_15"><ClkMux Nm="FB10_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_15_MC_CLK"/></ClkMux><FbMux Nm="FB10_15_N"><IPort NNm="FB10_15_Q"/></FbMux><FbMux Nm="FB10_15_P"><IPort NNm="FB10_15_I"/></FbMux><InBuf Nm="FB10_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_mod&lt;0&gt;"/><OPort NNm="FB10_15_I"/></InBuf><DFlop Nm="FB10_15_FF"><FlopPort NNm="FB10_15_OR" Port="D"/><FlopPort NNm="FB10_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB10_15_OR"><OPort NNm="FB10_15_OR"/><IPort NNm="FB10_PT4"/><IPort NNm="FB10_PT3"/></Or></Mc><Mc Nm="FB10_16"><ClkMux Nm="FB10_16_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB10_16_MC_CLK"/></ClkMux><XorMux Nm="FB10_16_AND"><IPort NNm="FB10_PT55"/></XorMux><FbMux Nm="FB10_16_N"><IPort NNm="FB10_16_Q"/></FbMux><FbMux Nm="FB10_16_P"><IPort NNm="FB10_16_I"/></FbMux><InBuf Nm="FB10_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_mod&lt;1&gt;"/><OPort NNm="FB10_16_I"/></InBuf><DFlop Nm="FB10_16_FF"><FlopPort NNm="FB10_PT55" Port="D"/><FlopPort NNm="FB10_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB10_16_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc></Lb><Lb Nm="FB11"><LbT Nm="FB11_PT0" PtT="XBR_CT_X"><OPort NNm="FB11_PT0"/><IPort NNm="FB5_5_I"/></LbT><LbT Nm="FB11_PT1" PtT="XBR_CT_X"><OPort NNm="FB11_PT1"/><IPort NNm="FB5_12_I"/></LbT><LbT Nm="FB11_PT2" PtT="XBR_CT_X"><OPort NNm="FB11_PT2"/><IPort NNm="FB24_2_I"/></LbT><LbT Nm="FB11_PT3" PtT="XBR_CT_X"><OPort NNm="FB11_PT3"/><IPort NNm="FB8_4_I"/></LbT><LbT Nm="FB11_PT5" PtT="XBR_CT"><OPort NNm="FB11_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB11_PT10" PtT="XBR_C"><OPort NNm="FB11_PT10"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_8_Q"/><IPort NNm="FB2_7_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB11_PT11" PtT="XBR_A"><OPort NNm="FB11_PT11"/><IPort NNm="FB11_15_Q"/></LbT><LbT Nm="FB11_PT13" PtT="XBR_C"><OPort NNm="FB11_PT13"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB11_2_Q"/></LbT><LbT Nm="FB11_PT16" PtT="XBR_C"><OPort NNm="FB11_PT16"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_8_Q"/><IPort NNm="FB2_7_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB11_PT19" PtT="XBR_C"><OPort NNm="FB11_PT19"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_8_Q"/><IPort NNm="FB2_7_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB11_PT22" PtT="XBR_C"><OPort NNm="FB11_PT22"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_8_Q"/><IPort NNm="FB2_7_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB11_PT23" PtT="XBR_A"><OPort NNm="FB11_PT23"/><IPort NNm="FB1_1_I"/></LbT><LbT Nm="FB11_PT25" PtT="XBR_C"><OPort NNm="FB11_PT25"/><IPort NNm="FB10_8_Q"/></LbT><LbT Nm="FB11_PT28" PtT="XBR_C"><OPort NNm="FB11_PT28"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB11_PT29" PtT="XBR_A"><OPort NNm="FB11_PT29"/><IPort NNm="FB1_1_I"/></LbT><LbT Nm="FB11_PT31" PtT="XBR_C"><OPort NNm="FB11_PT31"/><IPort NNm="FB11_11_Q"/></LbT><LbT Nm="FB11_PT34" PtT="XBR_C"><OPort NNm="FB11_PT34"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB11_PT37" PtT="XBR_C"><OPort NNm="FB11_PT37"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB11_PT38" PtT="XBR_A"><OPort NNm="FB11_PT38"/><IPort NNm="FB1_1_I"/></LbT><LbT Nm="FB11_PT40" PtT="XBR_C"><OPort NNm="FB11_PT40"/><IPort NNm="FB21_14_I"/></LbT><LbT Nm="FB11_PT43" PtT="XBR_C"><OPort NNm="FB11_PT43"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_8_Q"/><IPort NNm="FB2_7_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB11_PT44" PtT="XBR_A"><OPort NNm="FB11_PT44"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB11_PT46" PtT="XBR_C"><OPort NNm="FB11_PT46"/><IPort NNm="FB14_4_Q"/></LbT><LbT Nm="FB11_PT49" PtT="XBR_C"><OPort NNm="FB11_PT49"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB11_PT50" PtT="XBR_A"><OPort NNm="FB11_PT50"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB11_PT52" PtT="XBR_C"><OPort NNm="FB11_PT52"/><IPort NNm="FB14_5_Q"/></LbT><LbT Nm="FB11_PT53" PtT="XBR_A"><OPort NNm="FB11_PT53"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB11_PT55" PtT="XBR_C"><OPort NNm="FB11_PT55"/><IPort NNm="FB14_13_Q"/></LbT><Mc Nm="FB11_1"><XorMux Nm="FB11_1_AND"><IPort NNm="FB11_PT10"/></XorMux><InBuf Nm="FB11_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="irq&lt;1&gt;"/></InBuf><OutBuf Nm="FB11_1_O" IOS="LVCMOS33"><IPort NNm="FB11_PT10"/><OPort NNm="irq&lt;1&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB11_2"><ClkMux Nm="FB11_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_2_MC_CLK"/></ClkMux><XorMux Nm="FB11_2_AND"><IPort NNm="FB11_PT13"/></XorMux><FbMux Nm="FB11_2_N"><IPort NNm="FB11_2_Q"/></FbMux><DFlop Nm="FB11_2_FF"><FlopPort NNm="FB11_PT13" Port="D"/><FlopPort NNm="FB11_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_2_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB11_3"><XorMux Nm="FB11_3_AND"><IPort NNm="FB11_PT16"/></XorMux><InBuf Nm="FB11_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="irq&lt;2&gt;"/></InBuf><OutBuf Nm="FB11_3_O" IOS="LVCMOS33"><IPort NNm="FB11_PT16"/><OPort NNm="irq&lt;2&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB11_4"><XorMux Nm="FB11_4_AND"><IPort NNm="FB11_PT19"/></XorMux><InBuf Nm="FB11_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="irq&lt;3&gt;"/></InBuf><OutBuf Nm="FB11_4_O" IOS="LVCMOS33"><IPort NNm="FB11_PT19"/><OPort NNm="irq&lt;3&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB11_5"><XorMux Nm="FB11_5_AND"><IPort NNm="FB11_PT22"/></XorMux><InBuf Nm="FB11_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="irq&lt;4&gt;"/></InBuf><OutBuf Nm="FB11_5_O" IOS="LVCMOS33"><IPort NNm="FB11_PT22"/><OPort NNm="irq&lt;4&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB11_6"><ClkMux Nm="FB11_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_6_MC_CLK"/></ClkMux><XorMux Nm="FB11_6_AND"><IPort NNm="FB11_PT25"/></XorMux><FbMux Nm="FB11_6_N"><IPort NNm="FB11_6_Q"/></FbMux><DFlop Nm="FB11_6_FF"><FlopPort NNm="FB11_PT25" Port="D"/><FlopPort NNm="FB11_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_6_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB11_7"><RMux Nm="FB11_7_RST"><IPort NNm="FB11_PT5"/></RMux><ClkMux Nm="FB11_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_7_MC_CLK"/></ClkMux><FbMux Nm="FB11_7_N"><IPort NNm="FB11_7_Q"/></FbMux><DFlop Nm="FB11_7_FF"><FlopPort NNm="FB11_7_OR" Port="D"/><FlopPort NNm="FB11_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_7_Q" Port="Q"/><FlopPort NNm="FB11_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB11_PT28" Port="CE"/></DFlop><Or Nm="FB11_7_OR"><OPort NNm="FB11_7_OR"/><IPort NNm="FB11_PT1"/></Or></Mc><Mc Nm="FB11_8"><ClkMux Nm="FB11_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_8_MC_CLK"/></ClkMux><XorMux Nm="FB11_8_AND"><IPort NNm="FB11_PT31"/></XorMux><FbMux Nm="FB11_8_N"><IPort NNm="FB11_8_Q"/></FbMux><DFlop Nm="FB11_8_FF"><FlopPort NNm="FB11_PT31" Port="D"/><FlopPort NNm="FB11_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_8_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB11_9"><RMux Nm="FB11_9_RST"><IPort NNm="FB11_PT5"/></RMux><ClkMux Nm="FB11_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_9_MC_CLK"/></ClkMux><FbMux Nm="FB11_9_N"><IPort NNm="FB11_9_Q"/></FbMux><DFlop Nm="FB11_9_FF"><FlopPort NNm="FB11_9_OR" Port="D"/><FlopPort NNm="FB11_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_9_Q" Port="Q"/><FlopPort NNm="FB11_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB11_PT28" Port="CE"/></DFlop><Or Nm="FB11_9_OR"><OPort NNm="FB11_9_OR"/><IPort NNm="FB11_PT2"/></Or></Mc><Mc Nm="FB11_10"><RMux Nm="FB11_10_RST"><IPort NNm="FB11_PT5"/></RMux><ClkMux Nm="FB11_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_10_MC_CLK"/></ClkMux><FbMux Nm="FB11_10_N"><IPort NNm="FB11_10_Q"/></FbMux><DFlop Nm="FB11_10_FF"><FlopPort NNm="FB11_10_OR" Port="D"/><FlopPort NNm="FB11_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_10_Q" Port="Q"/><FlopPort NNm="FB11_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB11_PT28" Port="CE"/></DFlop><Or Nm="FB11_10_OR"><OPort NNm="FB11_10_OR"/><IPort NNm="FB11_PT0"/></Or></Mc><Mc Nm="FB11_11"><ClkMux Nm="FB11_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_11_MC_CLK"/></ClkMux><XorMux Nm="FB11_11_AND"><IPort NNm="FB11_PT40"/></XorMux><FbMux Nm="FB11_11_N"><IPort NNm="FB11_11_Q"/></FbMux><DFlop Nm="FB11_11_FF"><FlopPort NNm="FB11_PT40" Port="D"/><FlopPort NNm="FB11_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_11_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB11_12"><XorMux Nm="FB11_12_AND"><IPort NNm="FB11_PT43"/></XorMux><InBuf Nm="FB11_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="irq&lt;5&gt;"/></InBuf><OutBuf Nm="FB11_12_O" IOS="LVCMOS33"><IPort NNm="FB11_PT43"/><OPort NNm="irq&lt;5&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB11_13"><ClkMux Nm="FB11_13_MC_CLK" Rate="1"><IPort NNm="FB7_15_I"/><OPort NNm="FB11_13_MC_CLK"/></ClkMux><XorMux Nm="FB11_13_AND"><IPort NNm="FB11_PT46"/></XorMux><FbMux Nm="FB11_13_N"><IPort NNm="FB11_13_Q"/></FbMux><DFlop Nm="FB11_13_FF"><FlopPort NNm="FB11_PT46" Port="D"/><FlopPort NNm="FB11_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_13_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB11_14"><RMux Nm="FB11_14_RST"><IPort NNm="FB11_PT5"/></RMux><ClkMux Nm="FB11_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB11_14_MC_CLK"/></ClkMux><FbMux Nm="FB11_14_N"><IPort NNm="FB11_14_Q"/></FbMux><DFlop Nm="FB11_14_FF"><FlopPort NNm="FB11_14_OR" Port="D"/><FlopPort NNm="FB11_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_14_Q" Port="Q"/><FlopPort NNm="FB11_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB11_PT28" Port="CE"/></DFlop><Or Nm="FB11_14_OR"><OPort NNm="FB11_14_OR"/><IPort NNm="FB11_PT3"/></Or></Mc><Mc Nm="FB11_15"><ClkMux Nm="FB11_15_MC_CLK" Rate="1"><IPort NNm="FB7_15_I"/><OPort NNm="FB11_15_MC_CLK"/></ClkMux><XorMux Nm="FB11_15_AND"><IPort NNm="FB11_PT52"/></XorMux><FbMux Nm="FB11_15_N"><IPort NNm="FB11_15_Q"/></FbMux><DFlop Nm="FB11_15_FF"><FlopPort NNm="FB11_PT52" Port="D"/><FlopPort NNm="FB11_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB11_16"><ClkMux Nm="FB11_16_MC_CLK" Rate="1"><IPort NNm="FB7_15_I"/><OPort NNm="FB11_16_MC_CLK"/></ClkMux><XorMux Nm="FB11_16_AND"><IPort NNm="FB11_PT55"/></XorMux><FbMux Nm="FB11_16_N"><IPort NNm="FB11_16_Q"/></FbMux><DFlop Nm="FB11_16_FF"><FlopPort NNm="FB11_PT55" Port="D"/><FlopPort NNm="FB11_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB11_16_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc></Lb><Lb Nm="FB12"><LbT Nm="FB12_PT0" PtT="XBR_CT_X"><OPort NNm="FB12_PT0"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB21_1_I"/><IPort NNm="FB4_1_Q"/></LbT><LbT Nm="FB12_PT1" PtT="XBR_CT_X"><OPort NNm="FB12_PT1"/><IPort NNm="FB21_3_I"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT2" PtT="XBR_CT_X"><OPort NNm="FB12_PT2"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_5_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT3" PtT="XBR_CT_X"><OPort NNm="FB12_PT3"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_13_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT4" PtT="XBR_CT"><OPort NNm="FB12_PT4"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB21_2_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT5" PtT="XBR_CT"><OPort NNm="FB12_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB12_PT6" PtT="XBR_CT"><OPort NNm="FB12_PT6"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_4_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT7" PtT="XBR_CT"><OPort NNm="FB12_PT7"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB21_3_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT8" PtT="XBR_A"><OPort NNm="FB12_PT8"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB12_PT9" PtT="XBR_B"><OPort NNm="FB12_PT9"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB21_2_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT10" PtT="XBR_C"><OPort NNm="FB12_PT10"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB21_1_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT11" PtT="XBR_A"><OPort NNm="FB12_PT11"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_13_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT12" PtT="XBR_B"><OPort NNm="FB12_PT12"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_5_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT13" PtT="XBR_C"><OPort NNm="FB12_PT13"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_4_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT14" PtT="XBR_A"><OPort NNm="FB12_PT14"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT15" PtT="XBR_B"><OPort NNm="FB12_PT15"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT16" PtT="XBR_C"><OPort NNm="FB12_PT16"/><IPort NNm="FB1_9_Q"/><IPort NNm="FB8_2_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT17" PtT="XBR_A"><OPort NNm="FB12_PT17"/><IPort NNm="FB1_9_Q"/><IPort NNm="FB12_13_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT18" PtT="XBR_B"><OPort NNm="FB12_PT18"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT19" PtT="XBR_C"><OPort NNm="FB12_PT19"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT20" PtT="XBR_A"><OPort NNm="FB12_PT20"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB8_2_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT21" PtT="XBR_B"><OPort NNm="FB12_PT21"/><IPort NNm="FB1_7_Q"/><IPort NNm="FB12_13_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT22" PtT="XBR_C"><OPort NNm="FB12_PT22"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT23" PtT="XBR_A"><OPort NNm="FB12_PT23"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT24" PtT="XBR_B"><OPort NNm="FB12_PT24"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB8_2_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT25" PtT="XBR_C"><OPort NNm="FB12_PT25"/><IPort NNm="FB1_6_Q"/><IPort NNm="FB12_13_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT26" PtT="XBR_A"><OPort NNm="FB12_PT26"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT27" PtT="XBR_B"><OPort NNm="FB12_PT27"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT28" PtT="XBR_C"><OPort NNm="FB12_PT28"/><IPort NNm="FB1_11_Q"/><IPort NNm="FB8_2_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT29" PtT="XBR_A"><OPort NNm="FB12_PT29"/><IPort NNm="FB1_11_Q"/><IPort NNm="FB12_13_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT30" PtT="XBR_B"><OPort NNm="FB12_PT30"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT31" PtT="XBR_C"><OPort NNm="FB12_PT31"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT32" PtT="XBR_A"><OPort NNm="FB12_PT32"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB8_2_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT33" PtT="XBR_B"><OPort NNm="FB12_PT33"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB12_13_Q"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB12_PT34" PtT="XBR_C"><OPort NNm="FB12_PT34"/><IPort NNm="FB1_8_Q"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB8_2_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT35" PtT="XBR_A"><OPort NNm="FB12_PT35"/><IPort NNm="FB1_8_Q"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_2_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT36" PtT="XBR_B"><OPort NNm="FB12_PT36"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT37" PtT="XBR_C"><OPort NNm="FB12_PT37"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB20_1_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT38" PtT="XBR_A"><OPort NNm="FB12_PT38"/><IPort NNm="FB1_8_Q"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB12_13_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT39" PtT="XBR_B"><OPort NNm="FB12_PT39"/><IPort NNm="FB1_8_Q"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB12_13_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT40" PtT="XBR_C"><OPort NNm="FB12_PT40"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT41" PtT="XBR_A"><OPort NNm="FB12_PT41"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT42" PtT="XBR_B"><OPort NNm="FB12_PT42"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB12_PT43" PtT="XBR_C"><OPort NNm="FB12_PT43"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB12_PT44" PtT="XBR_A"><OPort NNm="FB12_PT44"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB12_13_Q"/></LbT><LbT Nm="FB12_PT45" PtT="XBR_B"><OPort NNm="FB12_PT45"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB12_PT46" PtT="XBR_C"><OPort NNm="FB12_PT46"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/></LbT><LbT Nm="FB12_PT47" PtT="XBR_A"><OPort NNm="FB12_PT47"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB12_8_Q"/></LbT><LbT Nm="FB12_PT48" PtT="XBR_B"><OPort NNm="FB12_PT48"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB13_15_Q"/></LbT><LbT Nm="FB12_PT49" PtT="XBR_C"><OPort NNm="FB12_PT49"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB12_10_Q"/></LbT><LbT Nm="FB12_PT50" PtT="XBR_A"><OPort NNm="FB12_PT50"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB12_10_Q"/></LbT><LbT Nm="FB12_PT51" PtT="XBR_B"><OPort NNm="FB12_PT51"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB12_9_Q"/></LbT><LbT Nm="FB12_PT52" PtT="XBR_C"><OPort NNm="FB12_PT52"/><IPort NNm="FB12_9_Q"/><IPort NNm="FB1_5_OR"/></LbT><LbT Nm="FB12_PT53" PtT="XBR_A"><OPort NNm="FB12_PT53"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB1_5_OR"/></LbT><LbT Nm="FB12_PT54" PtT="XBR_B"><OPort NNm="FB12_PT54"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB3_12_Q"/><IPort NNm="FB14_11_Q"/><IPort NNm="FB15_14_Q"/><IPort NNm="FB15_11_Q"/></LbT><LbT Nm="FB12_PT55" PtT="XBR_C"><OPort NNm="FB12_PT55"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/></LbT><Mc Nm="FB12_1"><ClkMux Nm="FB12_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB12_1_MC_CLK"/></ClkMux><InBuf Nm="FB12_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fl_tdo"/></InBuf><OutBuf Nm="FB12_1_O" IOS="LVCMOS33"><IPort NNm="FB12_1_Q"/><OPort NNm="fl_tdo"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB12_1_FF"><FlopPort NNm="FB12_1_OR" Port="D"/><FlopPort NNm="FB12_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB12_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB12_1_OR"><OPort NNm="FB12_1_OR"/><IPort NNm="FB12_PT10"/><IPort NNm="FB12_PT11"/><IPort NNm="FB12_PT7"/><IPort NNm="FB12_PT12"/><IPort NNm="FB12_PT9"/><IPort NNm="FB12_PT13"/><IPort NNm="FB12_PT0"/><IPort NNm="FB12_PT1"/><IPort NNm="FB12_PT4"/><IPort NNm="FB12_PT3"/><IPort NNm="FB12_PT2"/><IPort NNm="FB12_PT6"/></Or></Mc><Mc Nm="FB12_2"><InBuf Nm="FB12_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tck_p&lt;0&gt;"/></InBuf><OutBuf Nm="FB12_2_O" IOS="LVCMOS33"><IPort NNm="FB12_2_OR"/><OPort NNm="flash_tck_p&lt;0&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB12_2_OR"><OPort NNm="FB12_2_OR"/><IPort NNm="FB12_PT16"/><IPort NNm="FB12_PT17"/><IPort NNm="FB12_PT15"/><IPort NNm="FB12_PT14"/></Or></Mc><Mc Nm="FB12_3"><InBuf Nm="FB12_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tck_p&lt;1&gt;"/></InBuf><OutBuf Nm="FB12_3_O" IOS="LVCMOS33"><IPort NNm="FB12_3_OR"/><OPort NNm="flash_tck_p&lt;1&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB12_3_OR"><OPort NNm="FB12_3_OR"/><IPort NNm="FB12_PT37"/><IPort NNm="FB12_PT35"/><IPort NNm="FB12_PT39"/><IPort NNm="FB12_PT34"/><IPort NNm="FB12_PT38"/><IPort NNm="FB12_PT36"/></Or></Mc><Mc Nm="FB12_4"><InBuf Nm="FB12_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tck_p&lt;2&gt;"/></InBuf><OutBuf Nm="FB12_4_O" IOS="LVCMOS33"><IPort NNm="FB12_4_OR"/><OPort NNm="flash_tck_p&lt;2&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB12_4_OR"><OPort NNm="FB12_4_OR"/><IPort NNm="FB12_PT20"/><IPort NNm="FB12_PT21"/><IPort NNm="FB12_PT19"/><IPort NNm="FB12_PT18"/></Or></Mc><Mc Nm="FB12_5"><InBuf Nm="FB12_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tck_p&lt;3&gt;"/></InBuf><OutBuf Nm="FB12_5_O" IOS="LVCMOS33"><IPort NNm="FB12_5_OR"/><OPort NNm="flash_tck_p&lt;3&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB12_5_OR"><OPort NNm="FB12_5_OR"/><IPort NNm="FB12_PT24"/><IPort NNm="FB12_PT25"/><IPort NNm="FB12_PT23"/><IPort NNm="FB12_PT22"/></Or></Mc><Mc Nm="FB12_6"/><Mc Nm="FB12_7"/><Mc Nm="FB12_8"><RMux Nm="FB12_8_RST"><IPort NNm="FB12_PT5"/></RMux><ClkMux Nm="FB12_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB12_8_MC_CLK"/></ClkMux><FbMux Nm="FB12_8_N"><IPort NNm="FB12_8_Q"/></FbMux><DFlop Nm="FB12_8_FF"><FlopPort NNm="FB12_8_OR" Port="D"/><FlopPort NNm="FB12_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB12_8_Q" Port="Q"/><FlopPort NNm="FB12_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB12_8_OR"><OPort NNm="FB12_8_OR"/><IPort NNm="FB12_PT55"/><IPort NNm="FB12_PT54"/></Or></Mc><Mc Nm="FB12_9"><RMux Nm="FB12_9_RST"><IPort NNm="FB12_PT5"/></RMux><ClkMux Nm="FB12_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB12_9_MC_CLK"/></ClkMux><FbMux Nm="FB12_9_N"><IPort NNm="FB12_9_Q"/></FbMux><DFlop Nm="FB12_9_FF"><FlopPort NNm="FB12_9_OR" Port="D"/><FlopPort NNm="FB12_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB12_9_Q" Port="Q"/><FlopPort NNm="FB12_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB12_9_OR"><OPort NNm="FB12_9_OR"/><IPort NNm="FB12_PT45"/><IPort NNm="FB12_PT51"/><IPort NNm="FB12_PT52"/><IPort NNm="FB12_PT53"/></Or></Mc><Mc Nm="FB12_10"><RMux Nm="FB12_10_RST"><IPort NNm="FB12_PT5"/></RMux><ClkMux Nm="FB12_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB12_10_MC_CLK"/></ClkMux><FbMux Nm="FB12_10_N"><IPort NNm="FB12_10_Q"/></FbMux><DFlop Nm="FB12_10_FF"><FlopPort NNm="FB12_10_OR" Port="D"/><FlopPort NNm="FB12_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB12_10_Q" Port="Q"/><FlopPort NNm="FB12_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB12_10_OR"><OPort NNm="FB12_10_OR"/><IPort NNm="FB12_PT45"/><IPort NNm="FB12_PT49"/><IPort NNm="FB12_PT50"/><IPort NNm="FB12_PT48"/></Or></Mc><Mc Nm="FB12_11"><RMux Nm="FB12_11_RST"><IPort NNm="FB12_PT5"/></RMux><ClkMux Nm="FB12_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB12_11_MC_CLK"/></ClkMux><FbMux Nm="FB12_11_N"><IPort NNm="FB12_11_Q"/></FbMux><DFlop Nm="FB12_11_FF"><FlopPort NNm="FB12_11_OR" Port="D"/><FlopPort NNm="FB12_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB12_11_Q" Port="Q"/><FlopPort NNm="FB12_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB12_11_OR"><OPort NNm="FB12_11_OR"/><IPort NNm="FB12_PT47"/><IPort NNm="FB12_PT45"/><IPort NNm="FB12_PT46"/></Or></Mc><Mc Nm="FB12_12"><InBuf Nm="FB12_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tck_p&lt;4&gt;"/></InBuf><OutBuf Nm="FB12_12_O" IOS="LVCMOS33"><IPort NNm="FB12_12_OR"/><OPort NNm="flash_tck_p&lt;4&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB12_12_OR"><OPort NNm="FB12_12_OR"/><IPort NNm="FB12_PT28"/><IPort NNm="FB12_PT29"/><IPort NNm="FB12_PT27"/><IPort NNm="FB12_PT26"/></Or></Mc><Mc Nm="FB12_13"><RMux Nm="FB12_13_RST"><IPort NNm="FB12_PT5"/></RMux><ClkMux Nm="FB12_13_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB12_13_MC_CLK"/></ClkMux><FbMux Nm="FB12_13_N"><IPort NNm="FB12_13_Q"/></FbMux><DFlop Nm="FB12_13_FF"><FlopPort NNm="FB12_13_OR" Port="D"/><FlopPort NNm="FB12_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB12_13_Q" Port="Q"/><FlopPort NNm="FB12_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB12_13_OR"><OPort NNm="FB12_13_OR"/><IPort NNm="FB12_PT43"/><IPort NNm="FB12_PT44"/></Or></Mc><Mc Nm="FB12_14"><FbMux Nm="FB12_14_N"><IPort NNm="FB12_14_OR"/></FbMux><Or Nm="FB12_14_OR"><OPort NNm="FB12_14_OR"/><IPort NNm="FB12_PT41"/><IPort NNm="FB12_PT42"/></Or></Mc><Mc Nm="FB12_15"><FbMux Nm="FB12_15_N"><IPort NNm="FB12_15_OR"/></FbMux><Or Nm="FB12_15_OR"><OPort NNm="FB12_15_OR"/><IPort NNm="FB12_PT41"/><IPort NNm="FB12_PT40"/></Or></Mc><Mc Nm="FB12_16"><InBuf Nm="FB12_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tck_p&lt;5&gt;"/></InBuf><OutBuf Nm="FB12_16_O" IOS="LVCMOS33"><IPort NNm="FB12_16_OR"/><OPort NNm="flash_tck_p&lt;5&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB12_16_OR"><OPort NNm="FB12_16_OR"/><IPort NNm="FB12_PT32"/><IPort NNm="FB12_PT33"/><IPort NNm="FB12_PT31"/><IPort NNm="FB12_PT30"/></Or></Mc></Lb><Lb Nm="FB13"><LbT Nm="FB13_PT0" PtT="XBR_CT_X"><OPort NNm="FB13_PT0"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB12_10_Q"/></LbT><LbT Nm="FB13_PT1" PtT="XBR_CT_X"><OPort NNm="FB13_PT1"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT2" PtT="XBR_CT_X"><OPort NNm="FB13_PT2"/><IPort NNm="FB4_5_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT3" PtT="XBR_CT_X"><OPort NNm="FB13_PT3"/><IPort NNm="FB13_14_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT4" PtT="XBR_CT"><OPort NNm="FB13_PT4"/><IPort NNm="FB8_2_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT5" PtT="XBR_CT"><OPort NNm="FB13_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB13_PT6" PtT="XBR_CT"><OPort NNm="FB13_PT6"/><IPort NNm="FB13_14_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT7" PtT="XBR_CT"><OPort NNm="FB13_PT7"/><IPort NNm="FB13_11_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT8" PtT="XBR_A"><OPort NNm="FB13_PT8"/><IPort NNm="FB9_1_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT9" PtT="XBR_B"><OPort NNm="FB13_PT9"/><IPort NNm="FB13_11_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT10" PtT="XBR_C"><OPort NNm="FB13_PT10"/><IPort NNm="FB13_10_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT11" PtT="XBR_A"><OPort NNm="FB13_PT11"/><IPort NNm="FB6_16_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT12" PtT="XBR_B"><OPort NNm="FB13_PT12"/><IPort NNm="FB13_10_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT13" PtT="XBR_C"><OPort NNm="FB13_PT13"/><IPort NNm="FB13_9_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT14" PtT="XBR_A"><OPort NNm="FB13_PT14"/><IPort NNm="FB8_1_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT15" PtT="XBR_B"><OPort NNm="FB13_PT15"/><IPort NNm="FB13_9_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT16" PtT="XBR_C"><OPort NNm="FB13_PT16"/><IPort NNm="FB7_12_I"/></LbT><LbT Nm="FB13_PT17" PtT="XBR_A"><OPort NNm="FB13_PT17"/><IPort NNm="FB13_8_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT18" PtT="XBR_B"><OPort NNm="FB13_PT18"/><IPort NNm="FB6_1_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT19" PtT="XBR_C"><OPort NNm="FB13_PT19"/><IPort NNm="FB13_8_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT20" PtT="XBR_A"><OPort NNm="FB13_PT20"/><IPort NNm="FB13_7_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT21" PtT="XBR_B"><OPort NNm="FB13_PT21"/><IPort NNm="FB5_4_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT22" PtT="XBR_C"><OPort NNm="FB13_PT22"/><IPort NNm="FB13_7_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT23" PtT="XBR_A"><OPort NNm="FB13_PT23"/><IPort NNm="FB13_6_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT24" PtT="XBR_B"><OPort NNm="FB13_PT24"/><IPort NNm="FB4_1_I"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT25" PtT="XBR_C"><OPort NNm="FB13_PT25"/><IPort NNm="FB13_6_Q"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT26" PtT="XBR_A"><OPort NNm="FB13_PT26"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_5_Q"/><IPort NNm="FB4_PT31"/></LbT><LbT Nm="FB13_PT27" PtT="XBR_B"><OPort NNm="FB13_PT27"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB13_1_Q"/></LbT><LbT Nm="FB13_PT28" PtT="XBR_C"><OPort NNm="FB13_PT28"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB13_2_Q"/></LbT><LbT Nm="FB13_PT29" PtT="XBR_A"><OPort NNm="FB13_PT29"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB13_12_Q"/></LbT><LbT Nm="FB13_PT30" PtT="XBR_B"><OPort NNm="FB13_PT30"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB13_1_Q"/></LbT><LbT Nm="FB13_PT31" PtT="XBR_C"><OPort NNm="FB13_PT31"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB13_12_Q"/></LbT><LbT Nm="FB13_PT32" PtT="XBR_A"><OPort NNm="FB13_PT32"/><IPort NNm="FB12_11_Q"/><IPort NNm="FB13_15_Q"/><IPort NNm="FB12_9_Q"/></LbT><LbT Nm="FB13_PT33" PtT="XBR_B"><OPort NNm="FB13_PT33"/><IPort NNm="FB6_16_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB13_PT34" PtT="XBR_C"><OPort NNm="FB13_PT34"/><IPort NNm="FB13_4_Q"/><IPort NNm="FB21_16_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB13_PT46" PtT="XBR_C"><OPort NNm="FB13_PT46"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><LbT Nm="FB13_PT55" PtT="XBR_C"><OPort NNm="FB13_PT55"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><Mc Nm="FB13_1"><RMux Nm="FB13_1_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_1_MC_CLK"/></ClkMux><FbMux Nm="FB13_1_N"><IPort NNm="FB13_1_Q"/></FbMux><DFlop Nm="FB13_1_FF"><FlopPort NNm="FB13_1_OR" Port="D"/><FlopPort NNm="FB13_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_1_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_1_OR"><OPort NNm="FB13_1_OR"/><IPort NNm="FB13_PT29"/><IPort NNm="FB13_PT30"/></Or></Mc><Mc Nm="FB13_2"><RMux Nm="FB13_2_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_2_MC_CLK"/></ClkMux><FbMux Nm="FB13_2_N"><IPort NNm="FB13_2_Q"/></FbMux><DFlop Nm="FB13_2_FF"><FlopPort NNm="FB13_2_OR" Port="D"/><FlopPort NNm="FB13_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_2_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_2_OR"><OPort NNm="FB13_2_OR"/><IPort NNm="FB13_PT27"/><IPort NNm="FB13_PT28"/></Or></Mc><Mc Nm="FB13_3"><XorMux Nm="FB13_3_AND"><IPort NNm="FB13_PT16"/></XorMux><InBuf Nm="FB13_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="tp4"/></InBuf><OutBuf Nm="FB13_3_O" IOS="LVCMOS33"><IPort NNm="FB13_PT16"/><OPort NNm="tp4"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB13_4"><RMux Nm="FB13_4_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_4_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_4_MC_CLK"/></ClkMux><FbMux Nm="FB13_4_N"><IPort NNm="FB13_4_Q"/></FbMux><FbMux Nm="FB13_4_P"><IPort NNm="FB13_4_I"/></FbMux><InBuf Nm="FB13_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;7&gt;"/><OPort NNm="FB13_4_I"/></InBuf><DFlop Nm="FB13_4_FF"><FlopPort NNm="FB13_4_OR" Port="D"/><FlopPort NNm="FB13_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_4_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_4_OR"><OPort NNm="FB13_4_OR"/><IPort NNm="FB13_PT33"/><IPort NNm="FB13_PT34"/></Or></Mc><Mc Nm="FB13_5"><RMux Nm="FB13_5_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_5_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_5_MC_CLK"/></ClkMux><FbMux Nm="FB13_5_N"><IPort NNm="FB13_5_Q"/></FbMux><DFlop Nm="FB13_5_FF"><FlopPort NNm="FB13_5_OR" Port="D"/><FlopPort NNm="FB13_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_5_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_5_OR"><OPort NNm="FB13_5_OR"/><IPort NNm="FB13_PT24"/><IPort NNm="FB13_PT25"/><IPort NNm="FB13_PT26"/></Or></Mc><Mc Nm="FB13_6"><RMux Nm="FB13_6_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_6_MC_CLK"/></ClkMux><FbMux Nm="FB13_6_N"><IPort NNm="FB13_6_Q"/></FbMux><DFlop Nm="FB13_6_FF"><FlopPort NNm="FB13_6_OR" Port="D"/><FlopPort NNm="FB13_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_6_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_6_OR"><OPort NNm="FB13_6_OR"/><IPort NNm="FB13_PT21"/><IPort NNm="FB13_PT23"/><IPort NNm="FB13_PT22"/></Or></Mc><Mc Nm="FB13_7"><RMux Nm="FB13_7_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_7_MC_CLK"/></ClkMux><FbMux Nm="FB13_7_N"><IPort NNm="FB13_7_Q"/></FbMux><DFlop Nm="FB13_7_FF"><FlopPort NNm="FB13_7_OR" Port="D"/><FlopPort NNm="FB13_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_7_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_7_OR"><OPort NNm="FB13_7_OR"/><IPort NNm="FB13_PT18"/><IPort NNm="FB13_PT20"/><IPort NNm="FB13_PT19"/></Or></Mc><Mc Nm="FB13_8"><RMux Nm="FB13_8_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_8_MC_CLK"/></ClkMux><FbMux Nm="FB13_8_N"><IPort NNm="FB13_8_Q"/></FbMux><DFlop Nm="FB13_8_FF"><FlopPort NNm="FB13_8_OR" Port="D"/><FlopPort NNm="FB13_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_8_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_8_OR"><OPort NNm="FB13_8_OR"/><IPort NNm="FB13_PT14"/><IPort NNm="FB13_PT17"/><IPort NNm="FB13_PT15"/></Or></Mc><Mc Nm="FB13_9"><RMux Nm="FB13_9_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_9_MC_CLK"/></ClkMux><FbMux Nm="FB13_9_N"><IPort NNm="FB13_9_Q"/></FbMux><DFlop Nm="FB13_9_FF"><FlopPort NNm="FB13_9_OR" Port="D"/><FlopPort NNm="FB13_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_9_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_9_OR"><OPort NNm="FB13_9_OR"/><IPort NNm="FB13_PT11"/><IPort NNm="FB13_PT13"/><IPort NNm="FB13_PT12"/></Or></Mc><Mc Nm="FB13_10"><RMux Nm="FB13_10_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_10_MC_CLK"/></ClkMux><FbMux Nm="FB13_10_N"><IPort NNm="FB13_10_Q"/></FbMux><DFlop Nm="FB13_10_FF"><FlopPort NNm="FB13_10_OR" Port="D"/><FlopPort NNm="FB13_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_10_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_10_OR"><OPort NNm="FB13_10_OR"/><IPort NNm="FB13_PT8"/><IPort NNm="FB13_PT10"/><IPort NNm="FB13_PT9"/></Or></Mc><Mc Nm="FB13_11"><RMux Nm="FB13_11_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_11_MC_CLK"/></ClkMux><FbMux Nm="FB13_11_N"><IPort NNm="FB13_11_Q"/></FbMux><DFlop Nm="FB13_11_FF"><FlopPort NNm="FB13_11_OR" Port="D"/><FlopPort NNm="FB13_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_11_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_11_OR"><OPort NNm="FB13_11_OR"/><IPort NNm="FB13_PT4"/><IPort NNm="FB13_PT7"/><IPort NNm="FB13_PT6"/></Or></Mc><Mc Nm="FB13_12"><RMux Nm="FB13_12_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_12_MC_CLK"/></ClkMux><FbMux Nm="FB13_12_N"><IPort NNm="FB13_12_Q"/></FbMux><FbMux Nm="FB13_12_P"><IPort NNm="FB13_12_I"/></FbMux><InBuf Nm="FB13_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_p&lt;6&gt;"/><OPort NNm="FB13_12_I"/></InBuf><DFlop Nm="FB13_12_FF"><FlopPort NNm="FB13_12_OR" Port="D"/><FlopPort NNm="FB13_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_12_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_12_OR"><OPort NNm="FB13_12_OR"/><IPort NNm="FB13_PT32"/><IPort NNm="FB13_PT31"/></Or></Mc><Mc Nm="FB13_13"><XorMux Nm="FB13_13_AND"><IPort NNm="FB13_PT46"/></XorMux><InBuf Nm="FB13_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cscr_p&lt;0&gt;"/></InBuf><OutBuf Nm="FB13_13_O" IOS="LVCMOS33"><IPort NNm="FB13_PT46"/><OPort NNm="cscr_p&lt;0&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB13_14"><RMux Nm="FB13_14_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_14_MC_CLK"/></ClkMux><FbMux Nm="FB13_14_N"><IPort NNm="FB13_14_Q"/></FbMux><DFlop Nm="FB13_14_FF"><FlopPort NNm="FB13_14_OR" Port="D"/><FlopPort NNm="FB13_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_14_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_14_OR"><OPort NNm="FB13_14_OR"/><IPort NNm="FB13_PT2"/><IPort NNm="FB13_PT3"/></Or></Mc><Mc Nm="FB13_15"><RMux Nm="FB13_15_RST"><IPort NNm="FB13_PT5"/></RMux><ClkMux Nm="FB13_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB13_15_MC_CLK"/></ClkMux><FbMux Nm="FB13_15_N"><IPort NNm="FB13_15_Q"/></FbMux><DFlop Nm="FB13_15_FF"><FlopPort NNm="FB13_15_OR" Port="D"/><FlopPort NNm="FB13_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB13_15_Q" Port="Q"/><FlopPort NNm="FB13_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB13_15_OR"><OPort NNm="FB13_15_OR"/><IPort NNm="FB13_PT1"/><IPort NNm="FB13_PT0"/></Or></Mc><Mc Nm="FB13_16"><XorMux Nm="FB13_16_AND"><IPort NNm="FB13_PT55"/></XorMux><InBuf Nm="FB13_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cscr_p&lt;1&gt;"/></InBuf><OutBuf Nm="FB13_16_O" IOS="LVCMOS33"><IPort NNm="FB13_PT55"/><OPort NNm="cscr_p&lt;1&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc></Lb><Lb Nm="FB14"><LbT Nm="FB14_PT0" PtT="XBR_CT_X"><OPort NNm="FB14_PT0"/><IPort NNm="FB16_12_Q"/><IPort NNm="FB3_12_I"/></LbT><LbT Nm="FB14_PT1" PtT="XBR_CT_X"><OPort NNm="FB14_PT1"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB8_4_I"/></LbT><LbT Nm="FB14_PT2" PtT="XBR_CT_X"><OPort NNm="FB14_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB4_4_I"/></LbT><LbT Nm="FB14_PT3" PtT="XBR_CT_X"><OPort NNm="FB14_PT3"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB9_2_I"/></LbT><LbT Nm="FB14_PT4" PtT="XBR_CT"><OPort NNm="FB14_PT4"/><IPort NNm="FB5_12_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB14_PT5" PtT="XBR_CT"><OPort NNm="FB14_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB14_PT6" PtT="XBR_CT"><OPort NNm="FB14_PT6"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB14_PT7" PtT="XBR_CT"><OPort NNm="FB14_PT7"/><IPort NNm="FB14_15_Q"/><IPort NNm="FB17_14_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB14_PT8" PtT="XBR_A"><OPort NNm="FB14_PT8"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB14_12_Q"/><IPort NNm="FB19_16_I"/></LbT><LbT Nm="FB14_PT9" PtT="XBR_B"><OPort NNm="FB14_PT9"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB14_12_Q"/></LbT><LbT Nm="FB14_PT10" PtT="XBR_C"><OPort NNm="FB14_PT10"/><IPort NNm="FB14_12_Q"/><IPort NNm="FB7_10_Q"/></LbT><LbT Nm="FB14_PT11" PtT="XBR_A"><OPort NNm="FB14_PT11"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB14_11_Q"/></LbT><LbT Nm="FB14_PT12" PtT="XBR_B"><OPort NNm="FB14_PT12"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB14_11_Q"/><IPort NNm="FB11_7_Q"/></LbT><LbT Nm="FB14_PT13" PtT="XBR_C"><OPort NNm="FB14_PT13"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB14_11_Q"/><IPort NNm="FB11_7_Q"/></LbT><LbT Nm="FB14_PT14" PtT="XBR_A"><OPort NNm="FB14_PT14"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB3_12_Q"/></LbT><LbT Nm="FB14_PT16" PtT="XBR_C"><OPort NNm="FB14_PT16"/><IPort NNm="FB7_6_Q"/><IPort NNm="FB7_9_Q"/></LbT><LbT Nm="FB14_PT19" PtT="XBR_C"><OPort NNm="FB14_PT19"/><IPort NNm="FB14_12_Q"/></LbT><LbT Nm="FB14_PT22" PtT="XBR_C"><OPort NNm="FB14_PT22"/><IPort NNm="FB11_2_Q"/></LbT><LbT Nm="FB14_PT41" PtT="XBR_A"><OPort NNm="FB14_PT41"/><IPort NNm="FB11_13_Q"/></LbT><LbT Nm="FB14_PT44" PtT="XBR_A"><OPort NNm="FB14_PT44"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB14_PT46" PtT="XBR_C"><OPort NNm="FB14_PT46"/><IPort NNm="FB7_11_Q"/></LbT><Mc Nm="FB14_1"><InBuf Nm="FB14_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="mrs"/></InBuf><OutBuf Nm="FB14_1_O" IOS="LVCMOS33"><IPort NNm="FB14_1_OR"/><OPort NNm="mrs"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB14_1_OR"><OPort NNm="FB14_1_OR"/><IPort NNm="FB14_PT5"/><IPort NNm="FB14_PT3"/></Or></Mc><Mc Nm="FB14_2"><InBuf Nm="FB14_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="prs"/></InBuf><OutBuf Nm="FB14_2_O" IOS="LVCMOS33"><IPort NNm="FB14_2_OR"/><OPort NNm="prs"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB14_2_OR"><OPort NNm="FB14_2_OR"/><IPort NNm="FB14_PT5"/><IPort NNm="FB14_PT0"/><IPort NNm="FB14_PT2"/><IPort NNm="FB14_PT1"/></Or></Mc><Mc Nm="FB14_3"><XorMux Nm="FB14_3_AND"><IPort NNm="FB14_PT16"/></XorMux><InBuf Nm="FB14_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="tp3"/></InBuf><OutBuf Nm="FB14_3_O" IOS="LVCMOS33"><IPort NNm="FB14_PT16"/><OPort NNm="tp3"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB14_4"><RMux Nm="FB14_4_PST"><IPort NNm="FB14_PT6"/></RMux><ClkMux Nm="FB14_4_MC_CLK" Rate="1"><IPort NNm="FB7_15_I"/><OPort NNm="FB14_4_MC_CLK"/></ClkMux><XorMux Nm="FB14_4_AND"><IPort NNm="FB14_PT19"/></XorMux><FbMux Nm="FB14_4_N"><IPort NNm="FB14_4_Q"/></FbMux><InBuf Nm="FB14_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="dtack_led"/></InBuf><OutBuf Nm="FB14_4_O" IOS="LVCMOS33"><IPort NNm="FB14_4_Q"/><OPort NNm="dtack_led"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB14_4_FF"><FlopPort NNm="FB14_PT19" Port="D"/><FlopPort NNm="FB14_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB14_4_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB14_PT6" Port="PST"/></DFlop></Mc><Mc Nm="FB14_5"><RMux Nm="FB14_5_PST"><IPort NNm="FB14_PT6"/></RMux><ClkMux Nm="FB14_5_MC_CLK" Rate="1"><IPort NNm="FB7_15_I"/><OPort NNm="FB14_5_MC_CLK"/></ClkMux><XorMux Nm="FB14_5_AND"><IPort NNm="FB14_PT22"/></XorMux><FbMux Nm="FB14_5_N"><IPort NNm="FB14_5_Q"/></FbMux><InBuf Nm="FB14_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="intrpt_led"/></InBuf><OutBuf Nm="FB14_5_O" IOS="LVCMOS33"><IPort NNm="FB14_5_Q"/><OPort NNm="intrpt_led"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB14_5_FF"><FlopPort NNm="FB14_PT22" Port="D"/><FlopPort NNm="FB14_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB14_5_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB14_PT6" Port="PST"/></DFlop></Mc><Mc Nm="FB14_6"/><Mc Nm="FB14_7"/><Mc Nm="FB14_8"/><Mc Nm="FB14_9"/><Mc Nm="FB14_10"/><Mc Nm="FB14_11"><RMux Nm="FB14_11_RST"><IPort NNm="FB14_PT5"/></RMux><ClkMux Nm="FB14_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB14_11_MC_CLK"/></ClkMux><FbMux Nm="FB14_11_N"><IPort NNm="FB14_11_Q"/></FbMux><DFlop Nm="FB14_11_FF"><FlopPort NNm="FB14_11_OR" Port="D"/><FlopPort NNm="FB14_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB14_11_Q" Port="Q"/><FlopPort NNm="FB14_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB14_11_OR"><OPort NNm="FB14_11_OR"/><IPort NNm="FB14_PT11"/><IPort NNm="FB14_PT12"/><IPort NNm="FB14_PT14"/><IPort NNm="FB14_PT13"/></Or></Mc><Mc Nm="FB14_12"><ClkMux Nm="FB14_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB14_12_MC_CLK"/></ClkMux><FbMux Nm="FB14_12_N"><IPort NNm="FB14_12_Q"/></FbMux><DFlop Nm="FB14_12_FF"><FlopPort NNm="FB14_12_OR" Port="D"/><FlopPort NNm="FB14_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB14_12_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB14_12_OR"><OPort NNm="FB14_12_OR"/><IPort NNm="FB14_PT9"/><IPort NNm="FB14_PT10"/><IPort NNm="FB14_PT8"/></Or></Mc><Mc Nm="FB14_13"><ClkMux Nm="FB14_13_MC_CLK" Rate="1"><IPort NNm="FB7_15_I"/><OPort NNm="FB14_13_MC_CLK"/></ClkMux><XorMux Nm="FB14_13_AND"><IPort NNm="FB14_PT46"/></XorMux><FbMux Nm="FB14_13_N"><IPort NNm="FB14_13_Q"/></FbMux><InBuf Nm="FB14_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="spare_led"/></InBuf><OutBuf Nm="FB14_13_O" IOS="LVCMOS33"><IPort NNm="FB14_13_Q"/><OPort NNm="spare_led"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB14_13_FF"><FlopPort NNm="FB14_PT46" Port="D"/><FlopPort NNm="FB14_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB14_13_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB14_14"><FbMux Nm="FB14_14_P"><IPort NNm="FB14_14_I"/></FbMux><InBuf Nm="FB14_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_mod&lt;2&gt;"/><OPort NNm="FB14_14_I"/></InBuf></Mc><Mc Nm="FB14_15"><RMux Nm="FB14_15_RST"><IPort NNm="FB14_PT5"/></RMux><ClkMux Nm="FB14_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB14_15_MC_CLK"/></ClkMux><FbMux Nm="FB14_15_N"><IPort NNm="FB14_15_Q"/></FbMux><DFlop Nm="FB14_15_FF"><FlopPort NNm="FB14_15_OR" Port="D"/><FlopPort NNm="FB14_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB14_15_Q" Port="Q"/><FlopPort NNm="FB14_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB14_15_OR"><OPort NNm="FB14_15_OR"/><IPort NNm="FB14_PT4"/><IPort NNm="FB14_PT7"/></Or></Mc><Mc Nm="FB14_16"><FbMux Nm="FB14_16_P"><IPort NNm="FB14_16_I"/></FbMux><InBuf Nm="FB14_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_mod&lt;3&gt;"/><OPort NNm="FB14_16_I"/></InBuf></Mc></Lb><Lb Nm="FB15"><LbT Nm="FB15_PT0" PtT="XBR_CT_X"><OPort NNm="FB15_PT0"/><IPort NNm="FB4_4_I"/></LbT><LbT Nm="FB15_PT1" PtT="XBR_CT_X"><OPort NNm="FB15_PT1"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB15_14_Q"/></LbT><LbT Nm="FB15_PT2" PtT="XBR_CT_X"><OPort NNm="FB15_PT2"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB15_14_Q"/><IPort NNm="FB11_9_Q"/></LbT><LbT Nm="FB15_PT3" PtT="XBR_CT_X"><OPort NNm="FB15_PT3"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB15_14_Q"/><IPort NNm="FB11_9_Q"/></LbT><LbT Nm="FB15_PT4" PtT="XBR_CT"><OPort NNm="FB15_PT4"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB3_12_Q"/><IPort NNm="FB14_11_Q"/></LbT><LbT Nm="FB15_PT5" PtT="XBR_CT"><OPort NNm="FB15_PT5"/><IPort NNm="FB7_15_OR"/></LbT><LbT Nm="FB15_PT6" PtT="XBR_CT"><OPort NNm="FB15_PT6"/><IPort NNm="FB7_15_OR"/></LbT><LbT Nm="FB15_PT7" PtT="XBR_CT"><OPort NNm="FB15_PT7"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB15_11_Q"/></LbT><LbT Nm="FB15_PT8" PtT="XBR_A"><OPort NNm="FB15_PT8"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB15_11_Q"/><IPort NNm="FB11_14_Q"/></LbT><LbT Nm="FB15_PT9" PtT="XBR_B"><OPort NNm="FB15_PT9"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB15_11_Q"/><IPort NNm="FB11_14_Q"/></LbT><LbT Nm="FB15_PT10" PtT="XBR_C"><OPort NNm="FB15_PT10"/><IPort NNm="FB3_15_Q"/><IPort NNm="FB12_8_Q"/><IPort NNm="FB1_15_Q"/><IPort NNm="FB1_3_Q"/><IPort NNm="FB3_12_Q"/><IPort NNm="FB14_11_Q"/><IPort NNm="FB15_14_Q"/></LbT><LbT Nm="FB15_PT11" PtT="XBR_A"><OPort NNm="FB15_PT11"/><IPort NNm="FB15_10_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT12" PtT="XBR_B"><OPort NNm="FB15_PT12"/><IPort NNm="FB15_10_Q"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB15_9_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT13" PtT="XBR_C"><OPort NNm="FB15_PT13"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><LbT Nm="FB15_PT14" PtT="XBR_A"><OPort NNm="FB15_PT14"/><IPort NNm="FB15_10_Q"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT15" PtT="XBR_B"><OPort NNm="FB15_PT15"/><IPort NNm="FB15_9_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT16" PtT="XBR_C"><OPort NNm="FB15_PT16"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><LbT Nm="FB15_PT17" PtT="XBR_A"><OPort NNm="FB15_PT17"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT18" PtT="XBR_B"><OPort NNm="FB15_PT18"/><IPort NNm="FB15_10_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT19" PtT="XBR_C"><OPort NNm="FB15_PT19"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB15_9_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT20" PtT="XBR_A"><OPort NNm="FB15_PT20"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT21" PtT="XBR_B"><OPort NNm="FB15_PT21"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT22" PtT="XBR_C"><OPort NNm="FB15_PT22"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><LbT Nm="FB15_PT23" PtT="XBR_A"><OPort NNm="FB15_PT23"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB15_9_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT24" PtT="XBR_B"><OPort NNm="FB15_PT24"/><IPort NNm="FB15_10_Q"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB15_9_Q"/></LbT><LbT Nm="FB15_PT25" PtT="XBR_C"><OPort NNm="FB15_PT25"/><IPort NNm="FB15_6_Q"/></LbT><LbT Nm="FB15_PT26" PtT="XBR_A"><OPort NNm="FB15_PT26"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT27" PtT="XBR_B"><OPort NNm="FB15_PT27"/><IPort NNm="FB15_10_Q"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT28" PtT="XBR_C"><OPort NNm="FB15_PT28"/><IPort NNm="FB9_1_I"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT29" PtT="XBR_A"><OPort NNm="FB15_PT29"/><IPort NNm="FB15_4_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT30" PtT="XBR_B"><OPort NNm="FB15_PT30"/><IPort NNm="FB8_2_I"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT31" PtT="XBR_C"><OPort NNm="FB15_PT31"/><IPort NNm="FB15_1_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB15_PT38" PtT="XBR_A"><OPort NNm="FB15_PT38"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB15_PT43" PtT="XBR_C"><OPort NNm="FB15_PT43"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><LbT Nm="FB15_PT46" PtT="XBR_C"><OPort NNm="FB15_PT46"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/></LbT><LbT Nm="FB15_PT47" PtT="XBR_A"><OPort NNm="FB15_PT47"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB15_PT52" PtT="XBR_C"><OPort NNm="FB15_PT52"/><IPort NNm="FB6_15_Q"/><IPort NNm="FB7_7_Q"/></LbT><LbT Nm="FB15_PT53" PtT="XBR_A"><OPort NNm="FB15_PT53"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB15_PT55" PtT="XBR_C"><OPort NNm="FB15_PT55"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB3_14_Q"/></LbT><Mc Nm="FB15_1"><RMux Nm="FB15_1_PST"><IPort NNm="FB15_PT6"/></RMux><ClkMux Nm="FB15_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_1_MC_CLK"/></ClkMux><FbMux Nm="FB15_1_N"><IPort NNm="FB15_1_Q"/></FbMux><DFlop Nm="FB15_1_FF"><FlopPort NNm="FB15_1_OR" Port="D"/><FlopPort NNm="FB15_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB15_PT6" Port="PST"/></DFlop><Or Nm="FB15_1_OR"><OPort NNm="FB15_1_OR"/><IPort NNm="FB15_PT30"/><IPort NNm="FB15_PT31"/><IPort NNm="FB15_PT12"/></Or></Mc><Mc Nm="FB15_2"><XorMux Nm="FB15_2_AND"><IPort NNm="FB15_PT13"/></XorMux><InBuf Nm="FB15_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cscr_p&lt;2&gt;"/></InBuf><OutBuf Nm="FB15_2_O" IOS="LVCMOS33"><IPort NNm="FB15_PT13"/><OPort NNm="cscr_p&lt;2&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB15_3"><XorMux Nm="FB15_3_AND"><IPort NNm="FB15_PT16"/></XorMux><InBuf Nm="FB15_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cscr_p&lt;3&gt;"/></InBuf><OutBuf Nm="FB15_3_O" IOS="LVCMOS33"><IPort NNm="FB15_PT16"/><OPort NNm="cscr_p&lt;3&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB15_4"><RMux Nm="FB15_4_PST"><IPort NNm="FB15_PT6"/></RMux><ClkMux Nm="FB15_4_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_4_MC_CLK"/></ClkMux><FbMux Nm="FB15_4_N"><IPort NNm="FB15_4_Q"/></FbMux><DFlop Nm="FB15_4_FF"><FlopPort NNm="FB15_4_OR" Port="D"/><FlopPort NNm="FB15_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_4_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB15_PT6" Port="PST"/></DFlop><Or Nm="FB15_4_OR"><OPort NNm="FB15_4_OR"/><IPort NNm="FB15_PT28"/><IPort NNm="FB15_PT29"/><IPort NNm="FB15_PT12"/></Or></Mc><Mc Nm="FB15_5"><XorMux Nm="FB15_5_AND"><IPort NNm="FB15_PT22"/></XorMux><InBuf Nm="FB15_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cscr_p&lt;4&gt;"/></InBuf><OutBuf Nm="FB15_5_O" IOS="LVCMOS33"><IPort NNm="FB15_PT22"/><OPort NNm="cscr_p&lt;4&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB15_6"><RMux Nm="FB15_6_RST"><IPort NNm="FB15_PT5"/></RMux><ClkMux Nm="FB15_6_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_6_MC_CLK"/></ClkMux><XorMux Nm="FB15_6_AND"><IPort NNm="FB15_6_OR"/></XorMux><FbMux Nm="FB15_6_N"><IPort NNm="FB15_6_Q"/></FbMux><DFlop Nm="FB15_6_FF"><FlopPort NNm="FB15_6_OR" Port="D"/><FlopPort NNm="FB15_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_6_Q" Port="Q"/><FlopPort NNm="FB15_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB15_6_OR"><OPort NNm="FB15_6_OR"/><IPort NNm="FB15_PT26"/><IPort NNm="FB15_PT27"/><IPort NNm="FB15_PT24"/><IPort NNm="FB15_PT25"/></Or></Mc><Mc Nm="FB15_7"><RMux Nm="FB15_7_RST"><IPort NNm="FB15_PT5"/></RMux><ClkMux Nm="FB15_7_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_7_MC_CLK"/></ClkMux><FbMux Nm="FB15_7_N"><IPort NNm="FB15_7_Q"/></FbMux><DFlop Nm="FB15_7_FF"><FlopPort NNm="FB15_7_OR" Port="D"/><FlopPort NNm="FB15_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_7_Q" Port="Q"/><FlopPort NNm="FB15_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB15_7_OR"><OPort NNm="FB15_7_OR"/><IPort NNm="FB15_PT20"/><IPort NNm="FB15_PT18"/><IPort NNm="FB15_PT21"/><IPort NNm="FB15_PT23"/></Or></Mc><Mc Nm="FB15_8"><RMux Nm="FB15_8_RST"><IPort NNm="FB15_PT5"/></RMux><ClkMux Nm="FB15_8_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_8_MC_CLK"/></ClkMux><FbMux Nm="FB15_8_N"><IPort NNm="FB15_8_Q"/></FbMux><DFlop Nm="FB15_8_FF"><FlopPort NNm="FB15_8_OR" Port="D"/><FlopPort NNm="FB15_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_8_Q" Port="Q"/><FlopPort NNm="FB15_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB15_8_OR"><OPort NNm="FB15_8_OR"/><IPort NNm="FB15_PT17"/><IPort NNm="FB15_PT18"/><IPort NNm="FB15_PT19"/></Or></Mc><Mc Nm="FB15_9"><RMux Nm="FB15_9_RST"><IPort NNm="FB15_PT5"/></RMux><ClkMux Nm="FB15_9_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_9_MC_CLK"/></ClkMux><FbMux Nm="FB15_9_N"><IPort NNm="FB15_9_Q"/></FbMux><DFlop Nm="FB15_9_FF"><FlopPort NNm="FB15_9_OR" Port="D"/><FlopPort NNm="FB15_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_9_Q" Port="Q"/><FlopPort NNm="FB15_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB15_9_OR"><OPort NNm="FB15_9_OR"/><IPort NNm="FB15_PT15"/><IPort NNm="FB15_PT14"/></Or></Mc><Mc Nm="FB15_10"><RMux Nm="FB15_10_RST"><IPort NNm="FB15_PT5"/></RMux><ClkMux Nm="FB15_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_10_MC_CLK"/></ClkMux><FbMux Nm="FB15_10_N"><IPort NNm="FB15_10_Q"/></FbMux><DFlop Nm="FB15_10_FF"><FlopPort NNm="FB15_10_OR" Port="D"/><FlopPort NNm="FB15_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_10_Q" Port="Q"/><FlopPort NNm="FB15_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB15_10_OR"><OPort NNm="FB15_10_OR"/><IPort NNm="FB15_PT11"/><IPort NNm="FB15_PT12"/></Or></Mc><Mc Nm="FB15_11"><ClkMux Nm="FB15_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_11_MC_CLK"/></ClkMux><FbMux Nm="FB15_11_N"><IPort NNm="FB15_11_Q"/></FbMux><DFlop Nm="FB15_11_FF"><FlopPort NNm="FB15_11_OR" Port="D"/><FlopPort NNm="FB15_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_11_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB15_11_OR"><OPort NNm="FB15_11_OR"/><IPort NNm="FB15_PT7"/><IPort NNm="FB15_PT8"/><IPort NNm="FB15_PT9"/><IPort NNm="FB15_PT10"/></Or></Mc><Mc Nm="FB15_12"><XorMux Nm="FB15_12_AND"><IPort NNm="FB15_PT43"/></XorMux><InBuf Nm="FB15_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cscr_p&lt;5&gt;"/></InBuf><OutBuf Nm="FB15_12_O" IOS="LVCMOS33"><IPort NNm="FB15_PT43"/><OPort NNm="cscr_p&lt;5&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB15_13"><XorMux Nm="FB15_13_AND"><IPort NNm="FB15_PT46"/></XorMux><InBuf Nm="FB15_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="cscr_p&lt;6&gt;"/></InBuf><OutBuf Nm="FB15_13_O" IOS="LVCMOS33"><IPort NNm="FB15_PT46"/><OPort NNm="cscr_p&lt;6&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB15_14"><ClkMux Nm="FB15_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_14_MC_CLK"/></ClkMux><FbMux Nm="FB15_14_N"><IPort NNm="FB15_14_Q"/></FbMux><DFlop Nm="FB15_14_FF"><FlopPort NNm="FB15_14_OR" Port="D"/><FlopPort NNm="FB15_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_14_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB15_14_OR"><OPort NNm="FB15_14_OR"/><IPort NNm="FB15_PT1"/><IPort NNm="FB15_PT2"/><IPort NNm="FB15_PT3"/><IPort NNm="FB15_PT4"/></Or></Mc><Mc Nm="FB15_15"><XorMux Nm="FB15_15_AND"><IPort NNm="FB15_PT52"/></XorMux><InBuf Nm="FB15_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="vspare_0"/></InBuf><OutBuf Nm="FB15_15_O" IOS="LVCMOS33"><IPort NNm="FB15_PT52"/><OPort NNm="vspare_0"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB15_16"><ClkMux Nm="FB15_16_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB15_16_MC_CLK"/></ClkMux><FbMux Nm="FB15_16_N"><IPort NNm="FB15_16_Q"/></FbMux><DFlop Nm="FB15_16_FF"><FlopPort NNm="FB15_16_OR" Port="D"/><FlopPort NNm="FB15_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB15_16_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB15_PT55" Port="CE"/></DFlop><Or Nm="FB15_16_OR"><OPort NNm="FB15_16_OR"/><IPort NNm="FB15_PT0"/></Or></Mc></Lb><Lb Nm="FB16"><LbT Nm="FB16_PT0" PtT="XBR_CT_X"><OPort NNm="FB16_PT0"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB4_11_Q"/><IPort NNm="FB13_5_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB16_PT1" PtT="XBR_CT_X"><OPort NNm="FB16_PT1"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB4_11_Q"/><IPort NNm="FB13_5_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB16_PT2" PtT="XBR_CT_X"><OPort NNm="FB16_PT2"/><IPort NNm="FB20_2_Q"/><IPort NNm="FB12_15_OR"/></LbT><LbT Nm="FB16_PT3" PtT="XBR_CT_X"><OPort NNm="FB16_PT3"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB8_15_I"/><IPort NNm="FB5_16_I"/><IPort NNm="FB5_15_I"/><IPort NNm="FB4_7_Q"/><IPort NNm="FB4_5_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB16_PT4" PtT="XBR_CT"><OPort NNm="FB16_PT4"/><IPort NNm="FB8_5_Q"/><IPort NNm="FB4_7_Q"/><IPort NNm="FB4_5_Q"/><IPort NNm="FB4_1_Q"/><IPort NNm="FB6_1_Q"/></LbT><LbT Nm="FB16_PT5" PtT="XBR_CT"><OPort NNm="FB16_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB16_PT6" PtT="XBR_CT"><OPort NNm="FB16_PT6"/><IPort NNm="FB20_3_Q"/><IPort NNm="FB12_15_OR"/></LbT><LbT Nm="FB16_PT7" PtT="XBR_CT"><OPort NNm="FB16_PT7"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB19_16_I"/><IPort NNm="FB7_10_Q"/></LbT><LbT Nm="FB16_PT8" PtT="XBR_A"><OPort NNm="FB16_PT8"/><IPort NNm="FB10_15_Q"/><IPort NNm="FB1_10_Q"/><IPort NNm="FB7_10_Q"/></LbT><LbT Nm="FB16_PT9" PtT="XBR_B"><OPort NNm="FB16_PT9"/><IPort NNm="FB4_3_I"/></LbT><LbT Nm="FB16_PT16" PtT="XBR_C"><OPort NNm="FB16_PT16"/><IPort NNm="FB1_1_I"/><IPort NNm="FB19_15_I"/></LbT><LbT Nm="FB16_PT19" PtT="XBR_C"><OPort NNm="FB16_PT19"/><IPort NNm="FB21_14_I"/><IPort NNm="FB10_14_Q"/></LbT><LbT Nm="FB16_PT43" PtT="XBR_C"><OPort NNm="FB16_PT43"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/></LbT><Mc Nm="FB16_1"><InBuf Nm="FB16_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tdi_p"/></InBuf><OutBuf Nm="FB16_1_O" IOS="LVCMOS33"><IPort NNm="FB16_1_OR"/><OPort NNm="flash_tdi_p"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB16_1_OR"><OPort NNm="FB16_1_OR"/><IPort NNm="FB16_PT2"/><IPort NNm="FB16_PT1"/><IPort NNm="FB16_PT0"/></Or></Mc><Mc Nm="FB16_2"><InBuf Nm="FB16_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tms_p"/></InBuf><OutBuf Nm="FB16_2_O" IOS="LVCMOS33"><IPort NNm="FB16_2_OR"/><OPort NNm="flash_tms_p"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB16_2_OR"><OPort NNm="FB16_2_OR"/><IPort NNm="FB16_PT6"/><IPort NNm="FB16_PT4"/><IPort NNm="FB16_PT3"/></Or></Mc><Mc Nm="FB16_3"><XorMux Nm="FB16_3_AND"><IPort NNm="FB16_PT16"/></XorMux><InBuf Nm="FB16_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_hold"/></InBuf><OutBuf Nm="FB16_3_O" IOS="LVCMOS33"><IPort NNm="FB16_PT16"/><OPort NNm="add_hold"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB16_4"><XorMux Nm="FB16_4_AND"><IPort NNm="FB16_PT19"/></XorMux><InBuf Nm="FB16_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="iackout"/></InBuf><OutBuf Nm="FB16_4_O" IOS="LVCMOS33"><IPort NNm="FB16_PT19"/><OPort NNm="iackout"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB16_5"/><Mc Nm="FB16_6"/><Mc Nm="FB16_7"/><Mc Nm="FB16_8"/><Mc Nm="FB16_9"/><Mc Nm="FB16_10"/><Mc Nm="FB16_11"/><Mc Nm="FB16_12"><RMux Nm="FB16_12_RST"><IPort NNm="FB16_PT5"/></RMux><ClkMux Nm="FB16_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB16_12_MC_CLK"/></ClkMux><FbMux Nm="FB16_12_N"><IPort NNm="FB16_12_Q"/></FbMux><DFlop Nm="FB16_12_FF"><FlopPort NNm="FB16_12_OR" Port="D"/><FlopPort NNm="FB16_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB16_12_Q" Port="Q"/><FlopPort NNm="FB16_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB16_PT43" Port="CE"/></DFlop><Or Nm="FB16_12_OR"><OPort NNm="FB16_12_OR"/><IPort NNm="FB16_PT9"/></Or></Mc><Mc Nm="FB16_13"/><Mc Nm="FB16_14"><InBuf Nm="FB16_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="vspare_1"/></InBuf><OutBuf Nm="FB16_14_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="vspare_1"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB16_15"/><Mc Nm="FB16_16"><InBuf Nm="FB16_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="dtack_p"/></InBuf><OutBuf Nm="FB16_16_O" IOS="LVCMOS33"><IPort NNm="FB16_16_OR"/><OPort NNm="dtack_p"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB16_16_OR"><OPort NNm="FB16_16_OR"/><IPort NNm="FB16_PT8"/><IPort NNm="FB16_PT7"/></Or></Mc></Lb><Lb Nm="FB17"><LbT Nm="FB17_PT0" PtT="XBR_CT_X"><OPort NNm="FB17_PT0"/><IPort NNm="FB24_2_I"/><IPort NNm="FB5_PT40"/></LbT><LbT Nm="FB17_PT1" PtT="XBR_CT_X"><OPort NNm="FB17_PT1"/><IPort NNm="FB7_PT46"/></LbT><LbT Nm="FB17_PT2" PtT="XBR_CT_X"><OPort NNm="FB17_PT2"/><IPort NNm="FB4_5_I"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB17_PT3" PtT="XBR_CT_X"><OPort NNm="FB17_PT3"/><IPort NNm="FB15_10_Q"/><IPort NNm="FB15_8_Q"/><IPort NNm="FB15_7_Q"/><IPort NNm="FB15_6_Q"/><IPort NNm="FB15_9_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB17_PT4" PtT="XBR_CT"><OPort NNm="FB17_PT4"/><IPort NNm="FB17_15_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB17_PT5" PtT="XBR_CT"><OPort NNm="FB17_PT5"/><IPort NNm="FB4_3_I"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB17_PT6" PtT="XBR_CT"><OPort NNm="FB17_PT6"/><IPort NNm="FB7_15_OR"/></LbT><LbT Nm="FB17_PT7" PtT="XBR_CT"><OPort NNm="FB17_PT7"/><IPort NNm="FB17_11_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB17_PT8" PtT="XBR_A"><OPort NNm="FB17_PT8"/><IPort NNm="FB5_5_I"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB17_PT9" PtT="XBR_B"><OPort NNm="FB17_PT9"/><IPort NNm="FB17_10_Q"/><IPort NNm="FB4_PT34"/></LbT><LbT Nm="FB17_PT13" PtT="XBR_C"><OPort NNm="FB17_PT13"/><IPort NNm="FB7_6_Q"/><IPort NNm="FB7_9_Q"/></LbT><LbT Nm="FB17_PT16" PtT="XBR_C"><OPort NNm="FB17_PT16"/><IPort NNm="FB7_6_Q"/><IPort NNm="FB7_9_Q"/></LbT><LbT Nm="FB17_PT46" PtT="XBR_C"><OPort NNm="FB17_PT46"/><IPort NNm="FB17_16_I"/></LbT><Mc Nm="FB17_1"><InBuf Nm="FB17_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="gol_reset"/></InBuf><OutBuf Nm="FB17_1_O" IOS="LVCMOS33"><IPort NNm="FB17_1_OR"/><OPort NNm="gol_reset"/><CntlPort NNm="PT_VCC"/></OutBuf><Or Nm="FB17_1_OR"><OPort NNm="FB17_1_OR"/><IPort NNm="FB17_PT1"/><IPort NNm="FB17_PT0"/></Or></Mc><Mc Nm="FB17_2"><XorMux Nm="FB17_2_AND"><IPort NNm="FB17_PT13"/></XorMux><InBuf Nm="FB17_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="i2c_reset"/></InBuf><OutBuf Nm="FB17_2_O" IOS="LVCMOS33"><IPort NNm="FB17_PT13"/><OPort NNm="i2c_reset"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB17_3"><XorMux Nm="FB17_3_AND"><IPort NNm="FB17_PT13"/></XorMux><InBuf Nm="FB17_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="reset_p"/></InBuf><OutBuf Nm="FB17_3_O" IOS="LVCMOS33"><IPort NNm="FB17_PT13"/><OPort NNm="reset_p"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB17_4"/><Mc Nm="FB17_5"/><Mc Nm="FB17_6"/><Mc Nm="FB17_7"/><Mc Nm="FB17_8"/><Mc Nm="FB17_9"/><Mc Nm="FB17_10"><RMux Nm="FB17_10_PST"><IPort NNm="FB17_PT6"/></RMux><ClkMux Nm="FB17_10_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB17_10_MC_CLK"/></ClkMux><FbMux Nm="FB17_10_N"><IPort NNm="FB17_10_Q"/></FbMux><DFlop Nm="FB17_10_FF"><FlopPort NNm="FB17_10_OR" Port="D"/><FlopPort NNm="FB17_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB17_10_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB17_PT6" Port="PST"/></DFlop><Or Nm="FB17_10_OR"><OPort NNm="FB17_10_OR"/><IPort NNm="FB17_PT8"/><IPort NNm="FB17_PT9"/><IPort NNm="FB17_PT3"/></Or></Mc><Mc Nm="FB17_11"><RMux Nm="FB17_11_PST"><IPort NNm="FB17_PT6"/></RMux><ClkMux Nm="FB17_11_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB17_11_MC_CLK"/></ClkMux><FbMux Nm="FB17_11_N"><IPort NNm="FB17_11_Q"/></FbMux><DFlop Nm="FB17_11_FF"><FlopPort NNm="FB17_11_OR" Port="D"/><FlopPort NNm="FB17_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB17_11_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB17_PT6" Port="PST"/></DFlop><Or Nm="FB17_11_OR"><OPort NNm="FB17_11_OR"/><IPort NNm="FB17_PT5"/><IPort NNm="FB17_PT7"/><IPort NNm="FB17_PT3"/></Or></Mc><Mc Nm="FB17_12"/><Mc Nm="FB17_13"><XorMux Nm="FB17_13_AND"><IPort NNm="FB17_PT46"/></XorMux><InBuf Nm="FB17_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="enw_vf"/></InBuf><OutBuf Nm="FB17_13_O" IOS="LVCMOS33"><IPort NNm="FB17_PT46"/><OPort NNm="enw_vf"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB17_14"><FbMux Nm="FB17_14_P"><IPort NNm="FB17_14_I"/></FbMux><InBuf Nm="FB17_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sel_tim_p"/><OPort NNm="FB17_14_I"/></InBuf></Mc><Mc Nm="FB17_15"><RMux Nm="FB17_15_PST"><IPort NNm="FB17_PT6"/></RMux><ClkMux Nm="FB17_15_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB17_15_MC_CLK"/></ClkMux><FbMux Nm="FB17_15_N"><IPort NNm="FB17_15_Q"/></FbMux><DFlop Nm="FB17_15_FF"><FlopPort NNm="FB17_15_OR" Port="D"/><FlopPort NNm="FB17_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB17_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB17_PT6" Port="PST"/></DFlop><Or Nm="FB17_15_OR"><OPort NNm="FB17_15_OR"/><IPort NNm="FB17_PT2"/><IPort NNm="FB17_PT4"/><IPort NNm="FB17_PT3"/></Or></Mc><Mc Nm="FB17_16"><FbMux Nm="FB17_16_P"><IPort NNm="FB17_16_I"/></FbMux><InBuf Nm="FB17_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="i2c_int_p"/><OPort NNm="FB17_16_I"/></InBuf></Mc></Lb><Lb Nm="FB18"><LbT Nm="FB18_PT13" PtT="XBR_C"><OPort NNm="FB18_PT13"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_8_Q"/><IPort NNm="FB2_7_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB18_PT16" PtT="XBR_C"><OPort NNm="FB18_PT16"/><IPort NNm="FB3_14_Q"/><IPort NNm="FB2_8_Q"/><IPort NNm="FB2_7_Q"/><IPort NNm="FB9_1_Q"/></LbT><LbT Nm="FB18_PT22" PtT="XBR_C"><OPort NNm="FB18_PT22"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/><IPort NNm="FB2_PT13"/></LbT><LbT Nm="FB18_PT46" PtT="XBR_C"><OPort NNm="FB18_PT46"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/></LbT><Mc Nm="FB18_1"/><Mc Nm="FB18_2"><XorMux Nm="FB18_2_AND"><IPort NNm="FB18_PT13"/></XorMux><InBuf Nm="FB18_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="irq&lt;6&gt;"/></InBuf><OutBuf Nm="FB18_2_O" IOS="LVCMOS33"><IPort NNm="FB18_PT13"/><OPort NNm="irq&lt;6&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB18_3"><XorMux Nm="FB18_3_AND"><IPort NNm="FB18_PT16"/></XorMux><InBuf Nm="FB18_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="irq&lt;7&gt;"/></InBuf><OutBuf Nm="FB18_3_O" IOS="LVCMOS33"><IPort NNm="FB18_PT16"/><OPort NNm="irq&lt;7&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB18_4"><InBuf Nm="FB18_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="mspare_0"/></InBuf><OutBuf Nm="FB18_4_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="mspare_0"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB18_5"><XorMux Nm="FB18_5_AND"><IPort NNm="FB18_PT22"/></XorMux><InBuf Nm="FB18_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="i2c_wr"/></InBuf><OutBuf Nm="FB18_5_O" IOS="LVCMOS33"><IPort NNm="FB18_PT22"/><OPort NNm="i2c_wr"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB18_6"/><Mc Nm="FB18_7"/><Mc Nm="FB18_8"/><Mc Nm="FB18_9"/><Mc Nm="FB18_10"/><Mc Nm="FB18_11"/><Mc Nm="FB18_12"><InBuf Nm="FB18_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="mspare_2"/></InBuf><OutBuf Nm="FB18_12_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="mspare_2"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB18_13"><XorMux Nm="FB18_13_AND"><IPort NNm="FB18_PT46"/></XorMux><InBuf Nm="FB18_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="enw_x"/></InBuf><OutBuf Nm="FB18_13_O" IOS="LVCMOS33"><IPort NNm="FB18_PT46"/><OPort NNm="enw_x"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB18_14"/><Mc Nm="FB18_15"><InBuf Nm="FB18_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="mspare_3"/></InBuf><OutBuf Nm="FB18_15_O" IOS="LVCMOS33"><IPort NNm="PT_GND"/><OPort NNm="mspare_3"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB18_16"/></Lb><Lb Nm="FB19"><LbT Nm="FB19_PT6" PtT="XBR_CT"><OPort NNm="FB19_PT6"/><IPort NNm="FB1_1_I"/><IPort NNm="FB19_15_I"/></LbT><LbT Nm="FB19_PT10" PtT="XBR_C"><OPort NNm="FB19_PT10"/><IPort NNm="FB19_13_I"/><IPort NNm="FB21_13_I"/><IPort NNm="FB21_15_I"/><IPort NNm="FB10_15_I"/><IPort NNm="FB23_3_I"/><IPort NNm="FB19_4_I"/><IPort NNm="FB14_14_I"/><IPort NNm="FB10_16_I"/><IPort NNm="FB19_5_I"/><IPort NNm="FB14_16_I"/><IPort NNm="FB11_6_Q"/><IPort NNm="FB19_1_Q"/></LbT><Mc Nm="FB19_1"><RMux Nm="FB19_1_PST"><IPort NNm="FB19_PT6"/></RMux><ClkMux Nm="FB19_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB19_1_MC_CLK"/></ClkMux><XorMux Nm="FB19_1_AND"><IPort NNm="FB19_PT10"/></XorMux><FbMux Nm="FB19_1_N"><IPort NNm="FB19_1_Q"/></FbMux><InBuf Nm="FB19_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="tp2"/></InBuf><OutBuf Nm="FB19_1_O" IOS="LVCMOS33"><IPort NNm="FB19_1_Q"/><OPort NNm="tp2"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB19_1_FF"><FlopPort NNm="FB19_PT10" Port="D"/><FlopPort NNm="FB19_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB19_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="FB19_PT6" Port="PST"/></DFlop></Mc><Mc Nm="FB19_2"/><Mc Nm="FB19_3"/><Mc Nm="FB19_4"><FbMux Nm="FB19_4_P"><IPort NNm="FB19_4_I"/></FbMux><InBuf Nm="FB19_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_mod&lt;4&gt;"/><OPort NNm="FB19_4_I"/></InBuf></Mc><Mc Nm="FB19_5"><FbMux Nm="FB19_5_P"><IPort NNm="FB19_5_I"/></FbMux><InBuf Nm="FB19_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="add_mod&lt;5&gt;"/><OPort NNm="FB19_5_I"/></InBuf></Mc><Mc Nm="FB19_6"/><Mc Nm="FB19_7"/><Mc Nm="FB19_8"/><Mc Nm="FB19_9"/><Mc Nm="FB19_10"/><Mc Nm="FB19_11"/><Mc Nm="FB19_12"><FbMux Nm="FB19_12_P"><IPort NNm="FB19_12_I"/></FbMux><InBuf Nm="FB19_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="as"/><OPort NNm="FB19_12_I"/></InBuf></Mc><Mc Nm="FB19_13"><FbMux Nm="FB19_13_P"><IPort NNm="FB19_13_I"/></FbMux><InBuf Nm="FB19_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="brd_sel_16"/><OPort NNm="FB19_13_I"/></InBuf></Mc><Mc Nm="FB19_14"><FbMux Nm="FB19_14_P"><IPort NNm="FB19_14_I"/></FbMux><InBuf Nm="FB19_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="brd_sel_24"/><OPort NNm="FB19_14_I"/></InBuf></Mc><Mc Nm="FB19_15"><FbMux Nm="FB19_15_P"><IPort NNm="FB19_15_I"/></FbMux><InBuf Nm="FB19_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="ds1"/><OPort NNm="FB19_15_I"/></InBuf></Mc><Mc Nm="FB19_16"><FbMux Nm="FB19_16_P"><IPort NNm="FB19_16_I"/></FbMux><InBuf Nm="FB19_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="dtack_mem"/><OPort NNm="FB19_16_I"/></InBuf></Mc></Lb><Lb Nm="FB20"><LbT Nm="FB20_PT5" PtT="XBR_CT"><OPort NNm="FB20_PT5"/><IPort NNm="FB7_PT46"/></LbT><Mc Nm="FB20_1"><RMux Nm="FB20_1_RST"><IPort NNm="FB20_PT5"/></RMux><ClkMux Nm="FB20_1_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB20_1_MC_CLK"/></ClkMux><FbMux Nm="FB20_1_N"><IPort NNm="FB20_1_Q"/></FbMux><InBuf Nm="FB20_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fl_tck"/><OPort NNm="FB20_1_I"/></InBuf><DFlop Nm="FB20_1_FF"><FlopPort NNm="FB20_1_I" Port="D"/><FlopPort NNm="FB20_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB20_1_Q" Port="Q"/><FlopPort NNm="FB20_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB20_2"><RMux Nm="FB20_2_RST"><IPort NNm="FB20_PT5"/></RMux><ClkMux Nm="FB20_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB20_2_MC_CLK"/></ClkMux><FbMux Nm="FB20_2_N"><IPort NNm="FB20_2_Q"/></FbMux><InBuf Nm="FB20_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fl_tdi"/><OPort NNm="FB20_2_I"/></InBuf><DFlop Nm="FB20_2_FF"><FlopPort NNm="FB20_2_I" Port="D"/><FlopPort NNm="FB20_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB20_2_Q" Port="Q"/><FlopPort NNm="FB20_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB20_3"><RMux Nm="FB20_3_RST"><IPort NNm="FB20_PT5"/></RMux><ClkMux Nm="FB20_3_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB20_3_MC_CLK"/></ClkMux><FbMux Nm="FB20_3_N"><IPort NNm="FB20_3_Q"/></FbMux><InBuf Nm="FB20_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fl_tms"/><OPort NNm="FB20_3_I"/></InBuf><DFlop Nm="FB20_3_FF"><FlopPort NNm="FB20_3_I" Port="D"/><FlopPort NNm="FB20_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB20_3_Q" Port="Q"/><FlopPort NNm="FB20_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB20_4"><FbMux Nm="FB20_4_P"><IPort NNm="FB20_4_I"/></FbMux><InBuf Nm="FB20_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tdo_p&lt;0&gt;"/><OPort NNm="FB20_4_I"/></InBuf></Mc><Mc Nm="FB20_5"><FbMux Nm="FB20_5_P"><IPort NNm="FB20_5_I"/></FbMux><InBuf Nm="FB20_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tdo_p&lt;1&gt;"/><OPort NNm="FB20_5_I"/></InBuf></Mc><Mc Nm="FB20_6"/><Mc Nm="FB20_7"/><Mc Nm="FB20_8"/><Mc Nm="FB20_9"/><Mc Nm="FB20_10"/><Mc Nm="FB20_11"/><Mc Nm="FB20_12"/><Mc Nm="FB20_13"><FbMux Nm="FB20_13_P"><IPort NNm="FB20_13_I"/></FbMux><InBuf Nm="FB20_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tdo_p&lt;2&gt;"/><OPort NNm="FB20_13_I"/></InBuf></Mc><Mc Nm="FB20_14"/><Mc Nm="FB20_15"/><Mc Nm="FB20_16"/></Lb><Lb Nm="FB21"><Mc Nm="FB21_1"><FbMux Nm="FB21_1_P"><IPort NNm="FB21_1_I"/></FbMux><InBuf Nm="FB21_1_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tdo_p&lt;3&gt;"/><OPort NNm="FB21_1_I"/></InBuf></Mc><Mc Nm="FB21_2"><FbMux Nm="FB21_2_P"><IPort NNm="FB21_2_I"/></FbMux><InBuf Nm="FB21_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tdo_p&lt;4&gt;"/><OPort NNm="FB21_2_I"/></InBuf></Mc><Mc Nm="FB21_3"><FbMux Nm="FB21_3_P"><IPort NNm="FB21_3_I"/></FbMux><InBuf Nm="FB21_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="flash_tdo_p&lt;5&gt;"/><OPort NNm="FB21_3_I"/></InBuf></Mc><Mc Nm="FB21_4"><FbMux Nm="FB21_4_P"><IPort NNm="FB21_4_I"/></FbMux><InBuf Nm="FB21_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="fpga_done&lt;4&gt;"/><OPort NNm="FB21_4_I"/></InBuf></Mc><Mc Nm="FB21_5"><FbMux Nm="FB21_5_P"><IPort NNm="FB21_5_I"/></FbMux><InBuf Nm="FB21_5_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="g245_mem"/><OPort NNm="FB21_5_I"/></InBuf></Mc><Mc Nm="FB21_6"/><Mc Nm="FB21_7"/><Mc Nm="FB21_8"/><Mc Nm="FB21_9"/><Mc Nm="FB21_10"/><Mc Nm="FB21_11"/><Mc Nm="FB21_12"><FbMux Nm="FB21_12_P"><IPort NNm="FB21_12_I"/></FbMux><InBuf Nm="FB21_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="gol_ready"/><OPort NNm="FB21_12_I"/></InBuf></Mc><Mc Nm="FB21_13"><FbMux Nm="FB21_13_P"><IPort NNm="FB21_13_I"/></FbMux><InBuf Nm="FB21_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="iack"/><OPort NNm="FB21_13_I"/></InBuf></Mc><Mc Nm="FB21_14"><FbMux Nm="FB21_14_P"><IPort NNm="FB21_14_I"/></FbMux><InBuf Nm="FB21_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="iackin"/><OPort NNm="FB21_14_I"/></InBuf></Mc><Mc Nm="FB21_15"><FbMux Nm="FB21_15_P"><IPort NNm="FB21_15_I"/></FbMux><InBuf Nm="FB21_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="lword"/><OPort NNm="FB21_15_I"/></InBuf></Mc><Mc Nm="FB21_16"><FbMux Nm="FB21_16_P"><IPort NNm="FB21_16_I"/></FbMux><InBuf Nm="FB21_16_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="qpll_error"/><OPort NNm="FB21_16_I"/></InBuf></Mc></Lb><Lb Nm="FB22"><Mc Nm="FB22_1"/><Mc Nm="FB22_2"><FbMux Nm="FB22_2_P"><IPort NNm="FB22_2_I"/></FbMux><InBuf Nm="FB22_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="qpll_locked"/><OPort NNm="FB22_2_I"/></InBuf></Mc><Mc Nm="FB22_3"><FbMux Nm="FB22_3_P"><IPort NNm="FB22_3_I"/></FbMux><InBuf Nm="FB22_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sff&lt;3&gt;"/><OPort NNm="FB22_3_I"/></InBuf></Mc><Mc Nm="FB22_4"><FbMux Nm="FB22_4_P"><IPort NNm="FB22_4_I"/></FbMux><InBuf Nm="FB22_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sff&lt;4&gt;"/><OPort NNm="FB22_4_I"/></InBuf></Mc><Mc Nm="FB22_5"/><Mc Nm="FB22_6"/><Mc Nm="FB22_7"/><Mc Nm="FB22_8"/><Mc Nm="FB22_9"/><Mc Nm="FB22_10"/><Mc Nm="FB22_11"/><Mc Nm="FB22_12"><FbMux Nm="FB22_12_P"><IPort NNm="FB22_12_I"/></FbMux><InBuf Nm="FB22_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="spaf&lt;0&gt;"/><OPort NNm="FB22_12_I"/></InBuf></Mc><Mc Nm="FB22_13"><FbMux Nm="FB22_13_P"><IPort NNm="FB22_13_I"/></FbMux><InBuf Nm="FB22_13_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="spaf&lt;1&gt;"/><OPort NNm="FB22_13_I"/></InBuf></Mc><Mc Nm="FB22_14"><FbMux Nm="FB22_14_P"><IPort NNm="FB22_14_I"/></FbMux><InBuf Nm="FB22_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="spaf&lt;2&gt;"/><OPort NNm="FB22_14_I"/></InBuf></Mc><Mc Nm="FB22_15"><FbMux Nm="FB22_15_P"><IPort NNm="FB22_15_I"/></FbMux><InBuf Nm="FB22_15_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="spaf&lt;3&gt;"/><OPort NNm="FB22_15_I"/></InBuf></Mc><Mc Nm="FB22_16"/></Lb><Lb Nm="FB23"><LbT Nm="FB23_PT0" PtT="XBR_CT_X"><OPort NNm="FB23_PT0"/><IPort NNm="FB5_5_I"/></LbT><LbT Nm="FB23_PT1" PtT="XBR_CT_X"><OPort NNm="FB23_PT1"/><IPort NNm="FB5_12_I"/></LbT><LbT Nm="FB23_PT5" PtT="XBR_CT"><OPort NNm="FB23_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB23_PT19" PtT="XBR_C"><OPort NNm="FB23_PT19"/><IPort NNm="FB2_PT13"/><IPort NNm="FB19_1_Q"/></LbT><LbT Nm="FB23_PT43" PtT="XBR_C"><OPort NNm="FB23_PT43"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/></LbT><LbT Nm="FB23_PT49" PtT="XBR_C"><OPort NNm="FB23_PT49"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB19_13_I"/><IPort NNm="FB2_15_I"/><IPort NNm="FB13_4_I"/><IPort NNm="FB13_12_I"/><IPort NNm="FB10_10_Q"/><IPort NNm="FB7_8_Q"/></LbT><Mc Nm="FB23_1"/><Mc Nm="FB23_2"><FbMux Nm="FB23_2_P"><IPort NNm="FB23_2_I"/></FbMux><InBuf Nm="FB23_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="spaf&lt;4&gt;"/><OPort NNm="FB23_2_I"/></InBuf></Mc><Mc Nm="FB23_3"><FbMux Nm="FB23_3_P"><IPort NNm="FB23_3_I"/></FbMux><InBuf Nm="FB23_3_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="write"/><OPort NNm="FB23_3_I"/></InBuf></Mc><Mc Nm="FB23_4"><XorMux Nm="FB23_4_AND"><IPort NNm="FB23_PT19"/></XorMux><InBuf Nm="FB23_4_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="i2c_rd"/></InBuf><OutBuf Nm="FB23_4_O" IOS="LVCMOS33"><IPort NNm="FB23_PT19"/><OPort NNm="i2c_rd"/><CntlPort NNm="PT_VCC"/></OutBuf></Mc><Mc Nm="FB23_5"/><Mc Nm="FB23_6"/><Mc Nm="FB23_7"/><Mc Nm="FB23_8"/><Mc Nm="FB23_9"/><Mc Nm="FB23_10"/><Mc Nm="FB23_11"/><Mc Nm="FB23_12"><RMux Nm="FB23_12_RST"><IPort NNm="FB23_PT5"/></RMux><ClkMux Nm="FB23_12_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB23_12_MC_CLK"/></ClkMux><FbMux Nm="FB23_12_N"><IPort NNm="FB23_12_Q"/></FbMux><InBuf Nm="FB23_12_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sel_tim_clk&lt;0&gt;"/></InBuf><OutBuf Nm="FB23_12_O" IOS="LVCMOS33"><IPort NNm="FB23_12_Q"/><OPort NNm="sel_tim_clk&lt;0&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB23_12_FF"><FlopPort NNm="FB23_12_OR" Port="D"/><FlopPort NNm="FB23_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB23_12_Q" Port="Q"/><FlopPort NNm="FB23_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB23_PT43" Port="CE"/></DFlop><Or Nm="FB23_12_OR"><OPort NNm="FB23_12_OR"/><IPort NNm="FB23_PT0"/></Or></Mc><Mc Nm="FB23_13"/><Mc Nm="FB23_14"><RMux Nm="FB23_14_RST"><IPort NNm="FB23_PT5"/></RMux><ClkMux Nm="FB23_14_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB23_14_MC_CLK"/></ClkMux><FbMux Nm="FB23_14_N"><IPort NNm="FB23_14_Q"/></FbMux><InBuf Nm="FB23_14_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="sel_tim_clk&lt;1&gt;"/></InBuf><OutBuf Nm="FB23_14_O" IOS="LVCMOS33"><IPort NNm="FB23_14_Q"/><OPort NNm="sel_tim_clk&lt;1&gt;"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB23_14_FF"><FlopPort NNm="FB23_14_OR" Port="D"/><FlopPort NNm="FB23_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB23_14_Q" Port="Q"/><FlopPort NNm="FB23_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB23_PT43" Port="CE"/></DFlop><Or Nm="FB23_14_OR"><OPort NNm="FB23_14_OR"/><IPort NNm="FB23_PT1"/></Or></Mc><Mc Nm="FB23_15"/><Mc Nm="FB23_16"/></Lb><Lb Nm="FB24"><LbT Nm="FB24_PT0" PtT="XBR_CT_X"><OPort NNm="FB24_PT0"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB24_2_Q"/></LbT><LbT Nm="FB24_PT1" PtT="XBR_CT_X"><OPort NNm="FB24_PT1"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB2_11_Q"/></LbT><LbT Nm="FB24_PT2" PtT="XBR_CT_X"><OPort NNm="FB24_PT2"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB11_9_Q"/></LbT><LbT Nm="FB24_PT3" PtT="XBR_CT_X"><OPort NNm="FB24_PT3"/><IPort NNm="FB10_13_I"/><IPort NNm="FB10_12_I"/><IPort NNm="FB2_4_I"/><IPort NNm="FB2_5_I"/><IPort NNm="FB2_13_I"/><IPort NNm="FB10_14_I"/><IPort NNm="FB10_3_Q"/><IPort NNm="FB20_13_I"/><IPort NNm="FB12_14_OR"/></LbT><LbT Nm="FB24_PT5" PtT="XBR_CT"><OPort NNm="FB24_PT5"/><IPort NNm="FB7_16_OR"/></LbT><LbT Nm="FB24_PT13" PtT="XBR_C"><OPort NNm="FB24_PT13"/><IPort NNm="FB4_PT34"/></LbT><Mc Nm="FB24_1"/><Mc Nm="FB24_2"><RMux Nm="FB24_2_RST"><IPort NNm="FB24_PT5"/></RMux><ClkMux Nm="FB24_2_MC_CLK" Rate="1"><IPort NNm="FB7_12_I"/><OPort NNm="FB24_2_MC_CLK"/></ClkMux><OeMux Nm="FB24_2_OE"><IPort NNm="FB2_5_OR"/></OeMux><FbMux Nm="FB24_2_N"><IPort NNm="FB24_2_Q"/></FbMux><FbMux Nm="FB24_2_P"><IPort NNm="FB24_2_I"/></FbMux><InBuf Nm="FB24_2_I" IOS="LVCMOS33" DataGate="N"><IPort NNm="db&lt;11&gt;"/><OPort NNm="FB24_2_I"/></InBuf><OutBuf Nm="FB24_2_O" IOS="LVCMOS33"><IPort NNm="FB24_2_Q"/><OPort NNm="db&lt;11&gt;"/><CntlPort NNm="FB2_5_OR"/></OutBuf><DFlop Nm="FB24_2_FF"><FlopPort NNm="FB24_2_I" Port="D"/><FlopPort NNm="FB24_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB24_2_Q" Port="Q"/><FlopPort NNm="FB24_PT5" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/><FlopPort NNm="FB24_PT13" Port="CE"/></DFlop></Mc><Mc Nm="FB24_3"/><Mc Nm="FB24_4"/><Mc Nm="FB24_5"/><Mc Nm="FB24_6"/><Mc Nm="FB24_7"/><Mc Nm="FB24_8"/><Mc Nm="FB24_9"/><Mc Nm="FB24_10"/><Mc Nm="FB24_11"/><Mc Nm="FB24_12"/><Mc Nm="FB24_13"/><Mc Nm="FB24_14"/><Mc Nm="FB24_15"/><Mc Nm="FB24_16"/></Lb></Document>
