library ieee;
use ieee.std_logic_1164.all;

entity ffr is
	port (
	d, clk, ce, cr: in std_logic;
	q: out std_logic);
end ffr;

architecture arch of ffr is
begin

process (clk, cr)
begin
	if cr='1' then
		q <= '0';
	elsif clk'event and clk='1' then
		if ce='1' then
			q <= d;
		end if;
	end if;
end process;
end arch;

