" XPLAOPT Version 9.99.99.99
" Created on Fri Dec 04 17:41:18 2009
" 348 Mcells, 638 PLApts, 8 Levels, 1059 Fanins
" XPLAOPT -run s -it b -i rosvme.blx -dev XC2C384-7PQ208 -reg -xor a -mode 1 
"         -th 56 -fi 40 -bfi 40 -pre keep -unused ground -terminate keeper -no_output_files 
MODULE rosvme

	add_f_p<10>  pin 197 ;  " 1 pt.
 	add_f_p<11>  pin 196 ;  " 1 pt.
 	add_f_p<12>  pin 198 ;  " 1 pt.
 	add_f_p<13>  pin 195 ;  " 1 pt.
 	add_f_p<14>  pin 194 ;  " 1 pt.
 	add_f_p<15>  pin 39 ;  " 1 pt.
 	add_f_p<9>  pin 38 ;  " 1 pt.
 	add_hold  pin 147 ;  " 1 pt.
 	add_mod<0>  pin 70 ; 
 	add_mod<1>  pin 71 ; 
 	add_mod<2>  pin 151 ; 
 	add_mod<3>  pin 150 ; 
 	add_mod<4>  pin 107 ; 
 	add_mod<5>  pin 108 ; 
 	add_p<0>  pin 66 ; 
 	add_p<1>  pin 67 ; 
 	add_p<2>  pin 69 ; 
 	add_p<3>  pin 8 ; 
 	add_p<4>  pin 7 ; 
 	add_p<5>  pin 6 ; 
 	add_p<6>  pin 162 ; 
 	add_p<7>  pin 161 ; 
 	add_p<8>  pin 9 ; 
 	as  pin 109 ; 
 	brd_sel_16  pin 110 ; 
 	brd_sel_24  pin 111 ; 
 	cclk<0>  pin 51 ;  " 1 pt.
 	cclk<1>  pin 50 ;  " 1 pt.
 	cclk<2>  pin 49 ;  " 1 pt.
 	cclk<3>  pin 48 ;  " 1 pt.
 	cclk<4>  pin 47 ;  " 1 pt.
 	clk  pin 46 ; 
 	clk_slow  pin 44 ; 
 	cscr_p<0>  pin 163 ;  " 1 pt.
 	cscr_p<1>  pin 164 ;  " 1 pt.
 	cscr_p<2>  pin 165 ;  " 1 pt.
 	cscr_p<3>  pin 166 ;  " 1 pt.
 	cscr_p<4>  pin 167 ;  " 1 pt.
 	cscr_p<5>  pin 168 ;  " 1 pt.
 	cscr_p<6>  pin 169 ;  " 1 pt.
 	cspare_8  pin 203 ;  " 1 pt.
 	cspare_9  pin 5 ;  " 1 pt.
 	db<0>  pin 12 ;  " 10 pt.
 	db<10>  pin 187 ;  " 6 pt.
 	db<11>  pin 84 ;  " 4 pt.
 	db<12>  pin 57 ;  " 4 pt.
 	db<13>  pin 40 ;  " 3 pt.
 	db<14>  pin 56 ;  " 3 pt.
 	db<15>  pin 15 ;  " 1 pt.
 	db<1>  pin 189 ;  " 10 pt.
 	db<2>  pin 22 ;  " 10 pt.
 	db<3>  pin 54 ;  " 9 pt.
 	db<4>  pin 25 ;  " 9 pt.
 	db<5>  pin 41 ;  " 8 pt.
 	db<6>  pin 55 ;  " 8 pt.
 	db<7>  pin 16 ;  " 7 pt.
 	db<8>  pin 14 ;  " 6 pt.
 	db<9>  pin 188 ;  " 6 pt.
 	ds0  pin 2 ; 
 	ds1  pin 112 ; 
 	dtack_led  pin 154 ;  " 1 pt.
 	dtack_mem  pin 113 ; 
 	dtack_p  pin 143 ;  " 1 pt.
 	enw_vf  pin 179 ;  " 1 pt.
 	enw_x  pin 136 ;  " 1 pt.
 	etr_vf  pin 62 ;  " 1 pt.
 	etr_x  pin 63 ;  " 1 pt.
 	evcnt_res  pin 193 ; 
 	fl_switch<0>  pin 184 ; 
 	fl_switch<1>  pin 183 ; 
 	fl_switch<2>  pin 61 ; 
 	fl_tck  pin 102 ; 
 	fl_tdi  pin 101 ; 
 	fl_tdo  pin 72 ;  " 6 pt.
 	fl_tms  pin 100 ; 
 	flash_tck_p<0>  pin 73 ;  " 2 pt.
 	flash_tck_p<1>  pin 74 ;  " 2 pt.
 	flash_tck_p<2>  pin 75 ;  " 2 pt.
 	flash_tck_p<3>  pin 76 ;  " 3 pt.
 	flash_tck_p<4>  pin 77 ;  " 2 pt.
 	flash_tck_p<5>  pin 78 ;  " 3 pt.
 	flash_tdi_p  pin 149 ;  " 2 pt.
 	flash_tdo_p<0>  pin 99 ; 
 	flash_tdo_p<1>  pin 97 ; 
 	flash_tdo_p<2>  pin 95 ; 
 	flash_tdo_p<3>  pin 114 ; 
 	flash_tdo_p<4>  pin 115 ; 
 	flash_tdo_p<5>  pin 116 ; 
 	flash_tms_p  pin 148 ;  " 2 pt.
 	fpga_done<0>  pin 45 ; 
 	fpga_done<1>  pin 43 ; 
 	fpga_done<2>  pin 192 ; 
 	fpga_done<3>  pin 191 ; 
 	fpga_done<4>  pin 117 ; 
 	fpga_init<0>  pin 202 ;  " 1 pt.
 	fpga_init<1>  pin 17 ;  " 1 pt.
 	fpga_init<2>  pin 19 ;  " 1 pt.
 	fpga_init<3>  pin 185 ;  " 1 pt.
 	fpga_init<4>  pin 23 ;  " 1 pt.
 	g245_mem  pin 118 ; 
 	g245_p  pin 65 ;  " 1 pt.
 	gol_off  pin 20 ;  " 1 pt.
 	gol_ready  pin 119 ; 
 	gol_reset  pin 173 ;  " 2 pt.
 	i2c_ce_1wire  pin 18 ;  " 1 pt.
 	i2c_ce_gol  pin 201 ;  " 2 pt.
 	i2c_ce_p  pin 4 ;  " 1 pt.
 	i2c_int_p  pin 182 ; 
 	i2c_rd  pin 127 ;  " 1 pt.
 	i2c_reset  pin 174 ;  " 1 pt.
 	i2c_wr  pin 138 ;  " 1 pt.
 	iack  pin 120 ; 
 	iackin  pin 121 ; 
 	iackout  pin 146 ;  " 1 pt.
 	intrpt_led  pin 153 ;  " 1 pt.
 	irq<1>  pin 31 ;  " 1 pt.
 	irq<2>  pin 30 ;  " 1 pt.
 	irq<3>  pin 29 ;  " 1 pt.
 	irq<4>  pin 28 ;  " 1 pt.
 	irq<5>  pin 27 ;  " 1 pt.
 	irq<6>  pin 142 ;  " 1 pt.
 	irq<7>  pin 140 ;  " 1 pt.
 	ldpreg  pin 64 ;  " 1 pt.
 	lword  pin 122 ; 
 	mem_done  pin 208 ; 
 	mrs  pin 159 ;  " 2 pt.
 	mspare_0  pin 139 ;  " 1 pt.
 	mspare_1  pin 60 ;  " 1 pt.
 	mspare_2  pin 137 ;  " 1 pt.
 	mspare_3  pin 134 ;  " 1 pt.
 	on_244  pin 10 ;  " 0 pt.
 	prgm_fpga_p<0>  pin 37 ;  " 1 pt.
 	prgm_fpga_p<1>  pin 36 ;  " 1 pt.
 	prgm_fpga_p<2>  pin 35 ;  " 1 pt.
 	prgm_fpga_p<3>  pin 34 ;  " 1 pt.
 	prgm_fpga_p<4>  pin 32 ;  " 1 pt.
 	prs  pin 158 ;  " 3 pt.
 	qpll_error  pin 123 ; 
 	qpll_locked  pin 91 ; 
 	qpll_reset  pin 3 ;  " 2 pt.
 	reset_p  pin 175 ;  " 1 pt.
 	ros_waiting  pin 205 ; 
 	sel_tim_clk<0>  pin 128 ;  " 1 pt.
 	sel_tim_clk<1>  pin 131 ;  " 1 pt.
 	sel_tim_p  pin 180 ; 
 	sff<0>  pin 200 ; 
 	sff<1>  pin 199 ; 
 	sff<2>  pin 21 ; 
 	sff<3>  pin 90 ; 
 	sff<4>  pin 89 ; 
 	spaf<0>  pin 88 ; 
 	spaf<1>  pin 87 ; 
 	spaf<2>  pin 86 ; 
 	spaf<3>  pin 85 ; 
 	spaf<4>  pin 125 ; 
 	spare_led  pin 152 ;  " 1 pt.
 	sysreset  pin 206 ; 
 	tp2  pin 103 ;  " 1 pt.
 	tp3  pin 155 ;  " 1 pt.
 	tp4  pin 160 ;  " 1 pt.
 	vspare_0  pin 170 ;  " 1 pt.
 	vspare_1  pin 144 ;  " 1 pt.
 	write  pin 126 ; 
 

	N_PZ_1000  node istype 'collapse';  " 1 pt.
 	N_PZ_1001  node istype 'collapse';  " 2 pt.
 	N_PZ_1002  node istype 'collapse';  " 2 pt.
 	N_PZ_1003  node istype 'collapse';  " 1 pt.
 	N_PZ_1004  node istype 'collapse';  " 1 pt.
 	N_PZ_1005  node istype 'collapse';  " 1 pt.
 	N_PZ_1006  node istype 'collapse';  " 1 pt.
 	N_PZ_1007  node istype 'collapse';  " 1 pt.
 	N_PZ_1008  node istype 'collapse';  " 1 pt.
 	N_PZ_1009  node istype 'collapse';  " 1 pt.
 	N_PZ_1010  node istype 'collapse';  " 2 pt.
 	N_PZ_1011  node istype 'collapse';  " 2 pt.
 	N_PZ_1012  node istype 'collapse';  " 2 pt.
 	N_PZ_1013  node istype 'collapse';  " 2 pt.
 	N_PZ_1014  node istype 'collapse';  " 2 pt.
 	N_PZ_1015  node istype 'collapse';  " 2 pt.
 	N_PZ_1016  node istype 'collapse';  " 2 pt.
 	N_PZ_1017  node istype 'collapse';  " 2 pt.
 	N_PZ_1018  node istype 'collapse';  " 2 pt.
 	N_PZ_1019  node istype 'collapse';  " 2 pt.
 	N_PZ_1020  node istype 'collapse';  " 2 pt.
 	N_PZ_1021  node istype 'collapse';  " 1 pt.
 	N_PZ_1022  node istype 'collapse';  " 1 pt.
 	N_PZ_1023  node istype 'collapse';  " 1 pt.
 	N_PZ_1024  node istype 'collapse';  " 1 pt.
 	N_PZ_1025  node istype 'collapse';  " 1 pt.
 	N_PZ_1026  node istype 'collapse';  " 1 pt.
 	N_PZ_1027  node istype 'collapse';  " 1 pt.
 	N_PZ_1028  node istype 'collapse';  " 1 pt.
 	N_PZ_1029  node istype 'collapse';  " 1 pt.
 	N_PZ_1030  node istype 'collapse';  " 1 pt.
 	N_PZ_1031  node istype 'collapse';  " 1 pt.
 	N_PZ_1032  node istype 'collapse';  " 1 pt.
 	N_PZ_1033  node istype 'collapse';  " 1 pt.
 	N_PZ_1034  node istype 'collapse';  " 1 pt.
 	N_PZ_1035  node istype 'collapse';  " 2 pt.
 	N_PZ_1036  node istype 'collapse';  " 2 pt.
 	N_PZ_1037  node istype 'collapse';  " 2 pt.
 	N_PZ_1038  node istype 'collapse';  " 2 pt.
 	N_PZ_1039  node istype 'collapse';  " 2 pt.
 	N_PZ_1040  node istype 'collapse';  " 1 pt.
 	N_PZ_1041  node istype 'collapse';  " 1 pt.
 	N_PZ_1042  node istype 'collapse';  " 1 pt.
 	N_PZ_1043  node istype 'collapse';  " 1 pt.
 	N_PZ_1044  node istype 'collapse';  " 1 pt.
 	N_PZ_1045  node istype 'collapse';  " 1 pt.
 	N_PZ_1046  node istype 'collapse';  " 1 pt.
 	N_PZ_1047  node istype 'collapse';  " 1 pt.
 	N_PZ_1048  node istype 'collapse';  " 1 pt.
 	N_PZ_1049  node istype 'collapse';  " 1 pt.
 	N_PZ_1050  node istype 'collapse';  " 1 pt.
 	N_PZ_1051  node istype 'collapse';  " 1 pt.
 	N_PZ_1052  node istype 'collapse';  " 1 pt.
 	N_PZ_1053  node istype 'collapse';  " 1 pt.
 	N_PZ_814  node istype 'collapse';  " 2 pt.
 	N_PZ_823  node istype 'collapse';  " 2 pt.
 	N_PZ_831  node istype 'collapse';  " 4 pt.
 	N_PZ_840  node istype 'collapse';  " 2 pt.
 	N_PZ_845  node istype 'collapse';  " 3 pt.
 	N_PZ_854  node istype 'collapse';  " 3 pt.
 	N_PZ_925  node istype 'collapse';  " 2 pt.
 	N_PZ_930  node istype 'collapse';  " 1 pt.
 	N_PZ_938  node istype 'collapse';  " 2 pt.
 	N_PZ_939  node istype 'collapse';  " 2 pt.
 	N_PZ_940  node istype 'collapse';  " 2 pt.
 	N_PZ_941  node istype 'collapse';  " 2 pt.
 	N_PZ_942  node istype 'collapse';  " 1 pt.
 	N_PZ_943  node istype 'collapse';  " 2 pt.
 	N_PZ_944  node istype 'collapse';  " 2 pt.
 	N_PZ_945  node istype 'collapse';  " 2 pt.
 	N_PZ_946  node istype 'collapse';  " 2 pt.
 	N_PZ_947  node istype 'collapse';  " 1 pt.
 	N_PZ_948  node istype 'collapse';  " 2 pt.
 	N_PZ_949  node istype 'collapse';  " 2 pt.
 	N_PZ_950  node istype 'collapse';  " 2 pt.
 	N_PZ_951  node istype 'collapse';  " 1 pt.
 	N_PZ_952  node istype 'collapse';  " 1 pt.
 	N_PZ_953  node istype 'collapse';  " 2 pt.
 	N_PZ_954  node istype 'collapse';  " 2 pt.
 	N_PZ_955  node istype 'collapse';  " 1 pt.
 	N_PZ_956  node istype 'collapse';  " 2 pt.
 	N_PZ_957  node istype 'collapse';  " 1 pt.
 	N_PZ_958  node istype 'collapse';  " 2 pt.
 	N_PZ_959  node istype 'collapse';  " 1 pt.
 	N_PZ_960  node istype 'collapse';  " 1 pt.
 	N_PZ_961  node istype 'collapse';  " 1 pt.
 	N_PZ_962  node istype 'collapse';  " 1 pt.
 	N_PZ_963  node istype 'collapse';  " 1 pt.
 	N_PZ_964  node istype 'collapse';  " 2 pt.
 	N_PZ_965  node istype 'collapse';  " 1 pt.
 	N_PZ_966  node istype 'collapse';  " 2 pt.
 	N_PZ_967  node istype 'collapse';  " 2 pt.
 	N_PZ_968  node istype 'collapse';  " 2 pt.
 	N_PZ_969  node istype 'collapse';  " 2 pt.
 	N_PZ_970  node istype 'collapse';  " 2 pt.
 	N_PZ_971  node istype 'collapse';  " 2 pt.
 	N_PZ_972  node istype 'collapse';  " 2 pt.
 	N_PZ_973  node istype 'collapse';  " 1 pt.
 	N_PZ_974  node istype 'collapse';  " 1 pt.
 	N_PZ_975  node istype 'collapse';  " 1 pt.
 	N_PZ_976  node istype 'collapse';  " 1 pt.
 	N_PZ_977  node istype 'collapse';  " 1 pt.
 	N_PZ_978  node istype 'collapse';  " 2 pt.
 	N_PZ_979  node istype 'collapse';  " 2 pt.
 	N_PZ_980  node istype 'collapse';  " 2 pt.
 	N_PZ_981  node istype 'collapse';  " 1 pt.
 	N_PZ_982  node istype 'collapse';  " 1 pt.
 	N_PZ_983  node istype 'collapse';  " 2 pt.
 	N_PZ_984  node istype 'collapse';  " 2 pt.
 	N_PZ_985  node istype 'collapse';  " 2 pt.
 	N_PZ_986  node istype 'collapse';  " 2 pt.
 	N_PZ_987  node istype 'collapse';  " 2 pt.
 	N_PZ_988  node istype 'collapse';  " 2 pt.
 	N_PZ_989  node istype 'collapse';  " 1 pt.
 	N_PZ_990  node istype 'collapse';  " 1 pt.
 	N_PZ_991  node istype 'collapse';  " 1 pt.
 	N_PZ_992  node istype 'collapse';  " 1 pt.
 	N_PZ_993  node istype 'collapse';  " 2 pt.
 	N_PZ_994  node istype 'collapse';  " 2 pt.
 	N_PZ_995  node istype 'collapse';  " 1 pt.
 	N_PZ_996  node istype 'collapse';  " 1 pt.
 	N_PZ_997  node istype 'collapse';  " 2 pt.
 	N_PZ_998  node istype 'collapse';  " 1 pt.
 	N_PZ_999  node istype 'collapse';  " 1 pt.
 	U1/dssync  node ;  " 1 pt.
 	U1/q1  node ;  " 1 pt.
 	U1/q2  node ;  " 1 pt.
 	U1/q4  node ;  " 1 pt.
 	U1/q44  node ;  " 1 pt.
 	U1/q444  node ;  " 1 pt.
 	U1/q6  node ;  " 1 pt.
 	U1/q7  node ;  " 1 pt.
 	U1/q8  node ;  " 1 pt.
 	U1/q9  node ;  " 1 pt.
 	U3/r3  node ;  " 1 pt.
 	U3/r4  node ;  " 1 pt.
 	U3/r5  node ;  " 1 pt.
 	U3/r6  node ;  " 1 pt.
 	U3/r7  node ;  " 1 pt.
 	U3/r8  node ;  " 2 pt.
 	U5/_n0041  node ;  " 2 pt.
 	U5/_n007019  node ;  " 6 pt.
 	U5/bits_to_send<0>  node ;  " 4 pt.
 	U5/bits_to_send<1>  node ;  " 4 pt.
 	U5/bits_to_send<2>  node ;  " 4 pt.
 	U5/bits_to_send<3>  node ;  " 4 pt.
 	U5/cclk_counter<0>  node ;  " 1 pt.
 	U5/cclk_counter<1>  node ;  " 1 pt.
 	U5/cclk_counter<2>  node ;  " 1 pt.
 	U5/cclk_counter<3>  node ;  " 1 pt.
 	U5/cclk_counter<4>  node ;  " 1 pt.
 	U5/cclk_freq<0>  node ;  " 1 pt.
 	U5/cclk_freq<1>  node ;  " 1 pt.
 	U5/cclk_freq<2>  node ;  " 1 pt.
 	U5/cuenta_prgm_0_0  node ;  " 3 pt.
 	U5/cuenta_prgm_0_1  node ;  " 3 pt.
 	U5/cuenta_prgm_0_2  node ;  " 4 pt.
 	U5/cuenta_prgm_0_3  node ;  " 3 pt.
 	U5/cuenta_prgm_0_4  node ;  " 2 pt.
 	U5/ena_evres  node ;  " 1 pt.
 	U5/ena_rst_prgm  node ;  " 1 pt.
 	U5/flash_enable<0>  node ;  " 2 pt.
 	U5/flash_enable<1>  node ;  " 2 pt.
 	U5/flash_enable<2>  node ;  " 2 pt.
 	U5/flash_enable<3>  node ;  " 2 pt.
 	U5/flash_enable<4>  node ;  " 2 pt.
 	U5/flash_tck  node ;  " 2 pt.
 	U5/flash_tck_reg  node ;  " 1 pt.
 	U5/flash_tdi_reg  node ;  " 1 pt.
 	U5/flash_tms  node ;  " 1 pt.
 	U5/flash_tms_reg  node ;  " 1 pt.
 	U5/gol_notready_reg  node ;  " 3 pt.
 	U5/int_ena_mdone  node ;  " 3 pt.
 	U5/int_ena_rosw  node ;  " 3 pt.
 	U5/int_ena_sff  node ;  " 3 pt.
 	U5/int_ena_spaf  node ;  " 3 pt.
 	U5/int_vect<0>  node ;  " 1 pt.
 	U5/int_vect<1>  node ;  " 1 pt.
 	U5/int_vect<2>  node ;  " 1 pt.
 	U5/int_vect<3>  node ;  " 1 pt.
 	U5/int_vect<4>  node ;  " 1 pt.
 	U5/int_vect<5>  node ;  " 1 pt.
 	U5/int_vect<6>  node ;  " 1 pt.
 	U5/int_vect<7>  node ;  " 1 pt.
 	U5/jtag_end  node ;  " 3 pt.
 	U5/jtag_num_bits<0>  node ;  " 1 pt.
 	U5/jtag_num_bits<1>  node ;  " 1 pt.
 	U5/jtag_num_bits<2>  node ;  " 1 pt.
 	U5/jtag_num_bits<3>  node ;  " 1 pt.
 	U5/jtag_shift  node ;  " 3 pt.
 	U5/jtag_start  node ;  " 2 pt.
 	U5/local_reset  node ;  " 2 pt.
 	U5/mem_d0  node ;  " 1 pt.
 	U5/mem_done_reg  node ;  " 2 pt.
 	U5/not_sel_tim_reg  node ;  " 3 pt.
 	U5/qpll_error_reg  node ;  " 3 pt.
 	U5/qpll_hasunlock_reg  node ;  " 3 pt.
 	U5/reset_1  node ;  " 2 pt.
 	U5/reset_2  node ;  " 1 pt.
 	U5/ros_w0  node ;  " 1 pt.
 	U5/ros_waiting_reg  node ;  " 2 pt.
 	U5/s_reset_1  node ;  " 2 pt.
 	U5/s_reset_2  node ;  " 1 pt.
 	U5/state_FFD1  node ;  " 3 pt.
 	U5/state_FFD2  node ;  " 3 pt.
 	U5/state_FFD3  node ;  " 2 pt.
 	U5/tdi_bits<0>  node ;  " 3 pt.
 	U5/tdi_bits<1>  node ;  " 3 pt.
 	U5/tdi_bits<2>  node ;  " 3 pt.
 	U5/tdi_bits<3>  node ;  " 3 pt.
 	U5/tdi_bits<4>  node ;  " 3 pt.
 	U5/tdi_bits<5>  node ;  " 3 pt.
 	U5/tdi_bits<6>  node ;  " 3 pt.
 	U5/tdi_bits<7>  node ;  " 2 pt.
 	U5/tdo_bits<0>  node ;  " 2 pt.
 	U5/tdo_bits<1>  node ;  " 2 pt.
 	U5/tdo_bits<2>  node ;  " 2 pt.
 	U5/tdo_bits<3>  node ;  " 2 pt.
 	U5/tdo_bits<4>  node ;  " 2 pt.
 	U5/tdo_bits<5>  node ;  " 2 pt.
 	U5/tdo_bits<6>  node ;  " 2 pt.
 	U5/tdo_bits<7>  node ;  " 2 pt.
 	U5/tdo_reg  node ;  " 4 pt.
 	ULED1/q1  node ;  " 1 pt.
 	ULED1/q3  node ;  " 1 pt.
 	ULED2/q1  node ;  " 1 pt.
 	ULED2/q3  node ;  " 1 pt.
 	ULED3/q1  node ;  " 1 pt.
 	ULED3/q3  node ;  " 1 pt.
 	_n0009  node ;  " 2 pt.
 	ack_int  node ;  " 2 pt.
 	dtack_int  node ;  " 2 pt.
 	ena_evres_prgm  node ;  " 1 pt.
 	fl_tck_r  node ;  " 1 pt.
 	fl_tdi_r  node ;  " 1 pt.
 	fl_tms_r  node ;  " 1 pt.
 	fl_vme<0>  node ;  " 1 pt.
 	fl_vme<1>  node ;  " 1 pt.
 	fl_vme<2>  node ;  " 1 pt.
 	flash_ena_5_rosmem  node ;  " 2 pt.
 	int_lev<0>  node ;  " 1 pt.
 	int_lev<1>  node ;  " 1 pt.
 	int_lev<2>  node ;  " 1 pt.
 	int_rst  node ;  " 13 pt.
 	prgm_fpga<0>  node ;  " 3 pt.
 	prgm_fpga<1>  node ;  " 3 pt.
 	prgm_fpga<2>  node ;  " 3 pt.
 	prgm_fpga<3>  node ;  " 3 pt.
 	prgm_fpga<4>  node ;  " 3 pt.
 

xpla property 'USER_SLEW_RATE fpga_init<0> db<0> fpga_init<1> db<1> fpga_init<2> db<2> fpga_init<3> 
	db<3> fpga_init<4> db<4> gol_off i2c_ce_1wire i2c_ce_gol sel_tim_clk<0> db<9> sel_tim_clk<1> 
	db<10> db<8> db<5> db<6> db<7> db<11> db<13> db<12> db<14> db<15> enw_x cscr_p<0> cscr_p<1> cscr_p<2> 
	cscr_p<4> irq<7> i2c_reset intrpt_led dtack_led spare_led tp2 fl_tdo flash_tck_p<2> flash_tck_p<4> 
	i2c_ce_p dtack_p flash_tck_p<1> flash_tdi_p flash_tms_p mrs cclk<0> cclk<1> cclk<2> cclk<3> 
	cclk<4> cscr_p<3> cscr_p<5> cscr_p<6> flash_tck_p<0> flash_tck_p<3> flash_tck_p<5> g245_p 
	gol_reset iackout irq<1> irq<2> irq<3> irq<4> irq<5> irq<6> ldpreg qpll_reset prgm_fpga_p<4> 
	prgm_fpga_p<3> prgm_fpga_p<2> prgm_fpga_p<1> prgm_fpga_p<0> add_hold enw_vf etr_vf i2c_rd 
	i2c_wr prs etr_x tp3 reset_p tp4 vspare_0 vspare_1 cspare_9 cspare_8 add_f_p<9> add_f_p<15> add_f_p<14> 
	add_f_p<13> add_f_p<12> add_f_p<11> add_f_p<10> mspare_3 mspare_2 mspare_1 mspare_0 on_244 
	'; 
xpla property 'GLOBAL_CLK clk '; 
xpla property 'GLOBAL_RESET sysreset '; 
xpla property 'POWER_UP_HIGH gol_off intrpt_led dtack_led tp2 etr_x int_lev<0> U5/cclk_freq<2> 
	fl_vme<0> fl_vme<1> fl_vme<2> U3/r8 prgm_fpga<0> prgm_fpga<1> prgm_fpga<2> prgm_fpga<3> prgm_fpga<4> 
	'; 
xpla property 'terminate_unused'; 
xpla property 'timespec  clk enw_x 1.000000'; 
xpla property 'timespec  clk i2c_wr 1.000000'; 
xpla property 'timespec  evcnt_res U5/cuenta_prgm_0_0.AR 2.000000'; 
xpla property 'timespec  evcnt_res U5/cuenta_prgm_0_1.AR 2.000000'; 
xpla property 'timespec  evcnt_res U5/cuenta_prgm_0_2.AR 2.000000'; 
xpla property 'timespec  evcnt_res U5/cuenta_prgm_0_3.AR 2.000000'; 
xpla property 'timespec  evcnt_res U5/cuenta_prgm_0_4.AR 2.000000'; 
xpla property 'timespec  evcnt_res prgm_fpga<0>.AP 2.000000'; 
xpla property 'timespec  evcnt_res prgm_fpga<1>.AP 2.000000'; 
xpla property 'timespec  evcnt_res prgm_fpga<2>.AP 2.000000'; 
xpla property 'timespec  evcnt_res prgm_fpga<3>.AP 2.000000'; 
xpla property 'timespec  evcnt_res prgm_fpga<4>.AP 2.000000'; 
xpla property 'timespec  evcnt_res U5/s_reset_1.D 3.000000'; 
xpla property 'IOSTD sff<4> 0 -1';
xpla property 'IOSTD sff<3> 0 -1';
xpla property 'IOSTD sff<2> 0 -1';
xpla property 'IOSTD sff<1> 0 -1';
xpla property 'IOSTD sff<0> 0 -1';
xpla property 'IOSTD spaf<4> 0 -1';
xpla property 'IOSTD spaf<3> 0 -1';
xpla property 'IOSTD spaf<2> 0 -1';
xpla property 'IOSTD spaf<1> 0 -1';
xpla property 'IOSTD spaf<0> 0 -1';
xpla property 'IOSTD fpga_init<0> 0 -1';
xpla property 'IOSTD db<0> 0 -1';
xpla property 'IOSTD clk 0 -1';
xpla property 'IOSTD fpga_init<1> 0 -1';
xpla property 'IOSTD db<1> 0 -1';
xpla property 'IOSTD fpga_init<2> 0 -1';
xpla property 'IOSTD db<2> 0 -1';
xpla property 'IOSTD fpga_init<3> 0 -1';
xpla property 'IOSTD db<3> 0 -1';
xpla property 'IOSTD fpga_init<4> 0 -1';
xpla property 'IOSTD db<4> 0 -1';
xpla property 'IOSTD gol_off 0 -1';
xpla property 'IOSTD i2c_ce_1wire 0 -1';
xpla property 'IOSTD i2c_ce_gol 0 -1';
xpla property 'IOSTD sel_tim_clk<0> 0 -1';
xpla property 'IOSTD db<9> 0 -1';
xpla property 'IOSTD sel_tim_clk<1> 0 -1';
xpla property 'IOSTD db<10> 0 -1';
xpla property 'IOSTD db<8> 0 -1';
xpla property 'IOSTD iack 0 -1';
xpla property 'IOSTD ds0 0 -1';
xpla property 'IOSTD db<5> 0 -1';
xpla property 'IOSTD db<6> 0 -1';
xpla property 'IOSTD db<7> 0 -1';
xpla property 'IOSTD db<11> 0 -1';
xpla property 'IOSTD db<13> 0 -1';
xpla property 'IOSTD db<12> 0 -1';
xpla property 'IOSTD db<14> 0 -1';
xpla property 'IOSTD db<15> 0 -1';
xpla property 'IOSTD as 0 -1';
xpla property 'IOSTD mem_done 0 -1';
xpla property 'IOSTD ros_waiting 0 -1';
xpla property 'IOSTD sysreset 0 -1';
xpla property 'IOSTD lword 0 -1';
xpla property 'IOSTD add_mod<0> 0 -1';
xpla property 'IOSTD write 0 -1';
xpla property 'IOSTD add_p<1> 0 -1';
xpla property 'IOSTD add_p<0> 0 -1';
xpla property 'IOSTD add_p<5> 0 -1';
xpla property 'IOSTD add_p<4> 0 -1';
xpla property 'IOSTD add_p<3> 0 -1';
xpla property 'IOSTD add_p<2> 0 -1';
xpla property 'IOSTD enw_x 0 -1';
xpla property 'IOSTD cscr_p<0> 0 -1';
xpla property 'IOSTD brd_sel_16 0 -1';
xpla property 'IOSTD add_p<8> 0 -1';
xpla property 'IOSTD add_p<7> 0 -1';
xpla property 'IOSTD add_p<6> 0 -1';
xpla property 'IOSTD cscr_p<1> 0 -1';
xpla property 'IOSTD cscr_p<2> 0 -1';
xpla property 'IOSTD cscr_p<4> 0 -1';
xpla property 'IOSTD irq<7> 0 -1';
xpla property 'IOSTD fl_tck 0 -1';
xpla property 'IOSTD i2c_reset 0 -1';
xpla property 'IOSTD intrpt_led 0 -1';
xpla property 'IOSTD clk_slow 0 -1';
xpla property 'IOSTD dtack_led 0 -1';
xpla property 'IOSTD spare_led 0 -1';
xpla property 'IOSTD tp2 0 -1';
xpla property 'IOSTD iackin 0 -1';
xpla property 'IOSTD fl_tdi 0 -1';
xpla property 'IOSTD fl_tms 0 -1';
xpla property 'IOSTD add_mod<4> 0 -1';
xpla property 'IOSTD add_mod<2> 0 -1';
xpla property 'IOSTD add_mod<1> 0 -1';
xpla property 'IOSTD sel_tim_p 0 -1';
xpla property 'IOSTD flash_tdo_p<4> 0 -1';
xpla property 'IOSTD fl_tdo 0 -1';
xpla property 'IOSTD flash_tck_p<2> 0 -1';
xpla property 'IOSTD flash_tck_p<4> 0 -1';
xpla property 'IOSTD ds1 0 -1';
xpla property 'IOSTD flash_tdo_p<0> 0 -1';
xpla property 'IOSTD flash_tdo_p<1> 0 -1';
xpla property 'IOSTD flash_tdo_p<2> 0 -1';
xpla property 'IOSTD flash_tdo_p<3> 0 -1';
xpla property 'IOSTD flash_tdo_p<5> 0 -1';
xpla property 'IOSTD fl_switch<2> 0 -1';
xpla property 'IOSTD fl_switch<1> 0 -1';
xpla property 'IOSTD fl_switch<0> 0 -1';
xpla property 'IOSTD add_mod<5> 0 -1';
xpla property 'IOSTD add_mod<3> 0 -1';
xpla property 'IOSTD qpll_locked 0 -1';
xpla property 'IOSTD fpga_done<3> 0 -1';
xpla property 'IOSTD fpga_done<2> 0 -1';
xpla property 'IOSTD gol_ready 0 -1';
xpla property 'IOSTD fpga_done<1> 0 -1';
xpla property 'IOSTD fpga_done<0> 0 -1';
xpla property 'IOSTD fpga_done<4> 0 -1';
xpla property 'IOSTD evcnt_res 0 -1';
xpla property 'IOSTD qpll_error 0 -1';
xpla property 'IOSTD i2c_ce_p 0 -1';
xpla property 'IOSTD dtack_mem 0 -1';
xpla property 'IOSTD g245_mem 0 -1';
xpla property 'IOSTD dtack_p 0 -1';
xpla property 'IOSTD flash_tck_p<1> 0 -1';
xpla property 'IOSTD flash_tdi_p 0 -1';
xpla property 'IOSTD flash_tms_p 0 -1';
xpla property 'IOSTD mrs 0 -1';
xpla property 'IOSTD cclk<0> 0 -1';
xpla property 'IOSTD cclk<1> 0 -1';
xpla property 'IOSTD cclk<2> 0 -1';
xpla property 'IOSTD cclk<3> 0 -1';
xpla property 'IOSTD cclk<4> 0 -1';
xpla property 'IOSTD cscr_p<3> 0 -1';
xpla property 'IOSTD cscr_p<5> 0 -1';
xpla property 'IOSTD cscr_p<6> 0 -1';
xpla property 'IOSTD flash_tck_p<0> 0 -1';
xpla property 'IOSTD flash_tck_p<3> 0 -1';
xpla property 'IOSTD flash_tck_p<5> 0 -1';
xpla property 'IOSTD g245_p 0 -1';
xpla property 'IOSTD gol_reset 0 -1';
xpla property 'IOSTD iackout 0 -1';
xpla property 'IOSTD irq<1> 0 -1';
xpla property 'IOSTD irq<2> 0 -1';
xpla property 'IOSTD irq<3> 0 -1';
xpla property 'IOSTD irq<4> 0 -1';
xpla property 'IOSTD irq<5> 0 -1';
xpla property 'IOSTD irq<6> 0 -1';
xpla property 'IOSTD ldpreg 0 -1';
xpla property 'IOSTD qpll_reset 0 -1';
xpla property 'IOSTD prgm_fpga_p<4> 0 -1';
xpla property 'IOSTD prgm_fpga_p<3> 0 -1';
xpla property 'IOSTD prgm_fpga_p<2> 0 -1';
xpla property 'IOSTD prgm_fpga_p<1> 0 -1';
xpla property 'IOSTD prgm_fpga_p<0> 0 -1';
xpla property 'IOSTD add_hold 0 -1';
xpla property 'IOSTD enw_vf 0 -1';
xpla property 'IOSTD i2c_int_p 0 -1';
xpla property 'IOSTD etr_vf 0 -1';
xpla property 'IOSTD brd_sel_24 0 -1';
xpla property 'IOSTD i2c_rd 0 -1';
xpla property 'IOSTD i2c_wr 0 -1';
xpla property 'IOSTD prs 0 -1';
xpla property 'IOSTD etr_x 0 -1';
xpla property 'IOSTD tp3 0 -1';
xpla property 'IOSTD reset_p 0 -1';
xpla property 'IOSTD tp4 0 -1';
xpla property 'IOSTD vspare_0 0 -1';
xpla property 'IOSTD vspare_1 0 -1';
xpla property 'IOSTD cspare_9 0 -1';
xpla property 'IOSTD cspare_8 0 -1';
xpla property 'IOSTD add_f_p<9> 0 -1';
xpla property 'IOSTD add_f_p<15> 0 -1';
xpla property 'IOSTD add_f_p<14> 0 -1';
xpla property 'IOSTD add_f_p<13> 0 -1';
xpla property 'IOSTD add_f_p<12> 0 -1';
xpla property 'IOSTD add_f_p<11> 0 -1';
xpla property 'IOSTD add_f_p<10> 0 -1';
xpla property 'IOSTD mspare_3 0 -1';
xpla property 'IOSTD mspare_2 0 -1';
xpla property 'IOSTD mspare_1 0 -1';
xpla property 'IOSTD mspare_0 0 -1';
xpla property 'IOSTD on_244 0 -1';
EQUATIONS 

 N_PZ_1000 = N_PZ_957 & N_PZ_962;		"--- [PT=1, FI=2, LVL=6] ---
 N_PZ_1001 = db<15>.PIN & N_PZ_1049
      # evcnt_res & U5/ena_evres.Q;		"--- [PT=2, FI=4, LVL=6] ---
 N_PZ_1002 = fl_vme<0>.Q & N_PZ_987
      # N_PZ_948;		"--- [PT=2, FI=3, LVL=3] ---
 N_PZ_1003 = fl_vme<0>.Q & !N_PZ_948;		"--- [PT=1, FI=2, LVL=2] ---
 N_PZ_1004 = N_PZ_952 & !N_PZ_993;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_1005 = N_PZ_944 & !N_PZ_956;		"--- [PT=1, FI=2, LVL=6] ---
 N_PZ_1006 = !N_PZ_980 & N_PZ_1005;		"--- [PT=1, FI=2, LVL=7] ---
 N_PZ_1007 = !dtack_int.Q & U5/int_ena_sff.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1008 = N_PZ_840 & N_PZ_957;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_1009 = !dtack_int.Q & U5/int_ena_spaf.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1010 = !U5/state_FFD1.Q
      # !U5/state_FFD3.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_1011 = fl_switch<2> & !fl_switch<1> & fl_switch<0>
      # !fl_vme<1>.Q;		"--- [PT=2, FI=4, LVL=1] ---
 N_PZ_1012 = fl_switch<0> & N_PZ_1048
      # !fl_vme<2>.Q;		"--- [PT=2, FI=3, LVL=2] ---
 N_PZ_1013 = flash_ena_5_rosmem.Q
      # !dtack_mem;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_1014 = db<1>.PIN
      # !db<0>.PIN;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_1015 = !db<5>.PIN
      # db<4>.PIN;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_1016 = db<5>.PIN
      # !db<4>.PIN;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_1017 = N_PZ_956
      # !U5/cuenta_prgm_0_2.Q;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_1018 = N_PZ_994
      # !add_p<4>;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_1019 = N_PZ_1015
      # N_PZ_988;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_1020 = N_PZ_1016
      # N_PZ_988;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_1021 = int_lev<0>.Q & int_rst.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1022 = lword & add_mod<3>;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1023 = !brd_sel_16 & !add_mod<4>;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1024 = !add_mod<1> & add_mod<5>;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1025 = iack & N_PZ_1023;		"--- [PT=1, FI=2, LVL=2] ---
 N_PZ_1026 = N_PZ_1024 & N_PZ_1025;		"--- [PT=1, FI=2, LVL=3] ---
 N_PZ_1027 = N_PZ_1022 & N_PZ_1026;		"--- [PT=1, FI=2, LVL=4] ---
 N_PZ_1028 = add_mod<0> & N_PZ_1027;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_1029 = !add_mod<2> & N_PZ_1028;		"--- [PT=1, FI=2, LVL=6] ---
 N_PZ_1030 = U1/dssync.Q & N_PZ_1029;		"--- [PT=1, FI=2, LVL=7] ---
 N_PZ_1031 = !flash_ena_5_rosmem.Q & N_PZ_949;		"--- [PT=1, FI=2, LVL=6] ---
 N_PZ_1032 = !U5/flash_enable<4>.Q & N_PZ_1031;		"--- [PT=1, FI=2, LVL=7] ---
 N_PZ_1033 = !brd_sel_16 & !add_p<8>;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1034 = !U5/state_FFD3.Q & N_PZ_974;		"--- [PT=1, FI=2, LVL=2] ---
 N_PZ_1035 = U5/state_FFD1.Q
      # U5/jtag_start.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_1036 = U1/q444.Q
      # dtack_int.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_1037 = !U5/cclk_freq<2>.Q & U5/cclk_counter<4>.Q
      # U5/cclk_freq<2>.Q & U5/cclk_counter<0>.Q
    ;		"--- [PT=2, FI=3, LVL=1] ---
 N_PZ_1038 = N_PZ_964
      # N_PZ_956;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_1039 = N_PZ_1036
      # !N_PZ_1013;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_1040 = !iack & N_PZ_954;		"--- [PT=1, FI=2, LVL=2] ---
 N_PZ_1041 = U3/r4.Q & N_PZ_1040;		"--- [PT=1, FI=2, LVL=3] ---
 N_PZ_1042 = N_PZ_925 & N_PZ_1041;		"--- [PT=1, FI=2, LVL=4] ---
 N_PZ_1043 = !N_PZ_948 & N_PZ_958;		"--- [PT=1, FI=2, LVL=4] ---
 N_PZ_1044 = U1/q2.Q & !U1/q4.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1045 = !N_PZ_946 & N_PZ_947;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_1046 = !fl_switch<1> & N_PZ_1003;		"--- [PT=1, FI=2, LVL=3] ---
 N_PZ_1047 = fl_vme<0>.Q & fl_tck_r.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1048 = !fl_switch<2> & fl_switch<1>;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1049 = N_PZ_952 & !N_PZ_993;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_1050 = !U5/bits_to_send<0>.Q & !U5/bits_to_send<1>.Q
    ;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1051 = !int_lev<0>.Q & int_rst.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_1052 = !N_PZ_941 & !N_PZ_946;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_1053 = U5/cclk_counter<0>.Q & U5/cclk_counter<1>.Q
    ;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_814 = N_PZ_978
      # add_p<4>;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_823 = !add_p<0>
      # !add_p<1>;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_831 = add_p<2>
      # !add_p<3>
      # add_p<4>
      # add_p<5>;		"--- [PT=4, FI=4, LVL=1] ---
 N_PZ_840 = U5/flash_tck.Q
      # U5/flash_tck_reg.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_845 = !U5/cclk_freq<1>.Q & U5/cclk_freq<0>.Q & !U5/cclk_freq<2>.Q & 
    U5/cclk_counter<3>.Q
      # U5/cclk_freq<1>.Q & !U5/cclk_freq<0>.Q & !U5/cclk_freq<2>.Q & 
    U5/cclk_counter<2>.Q
      # U5/cclk_freq<0>.Q & U5/cclk_freq<2>.Q & U5/cclk_counter<4>.Q
    ;		"--- [PT=3, FI=6, LVL=1] ---
 N_PZ_854 = U5/cclk_freq<1>.Q & U5/cclk_freq<0>.Q & !U5/cclk_freq<2>.Q & 
    U5/cclk_counter<1>.Q
      # !U5/cclk_freq<1>.Q & !U5/cclk_freq<0>.Q & N_PZ_1037
      # U5/cclk_freq<1>.Q & U5/cclk_freq<2>.Q & U5/cclk_counter<4>.Q
    ;		"--- [PT=3, FI=6, LVL=2] ---
 N_PZ_925 = !add_p<2> & !int_lev<2>.Q & N_PZ_986
      # add_p<2> & int_lev<2>.Q & N_PZ_986;		"--- [PT=2, FI=3, LVL=2] ---
 N_PZ_930 = !U5/reset_1.Q & !U5/reset_2.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_938 = !N_PZ_1044
      # N_PZ_997;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_939 = N_PZ_814
      # !add_p<2>;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_940 = fl_vme<0>.Q & !N_PZ_987
      # !fl_vme<0>.Q;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_941 = N_PZ_939
      # N_PZ_938;		"--- [PT=2, FI=2, LVL=4] ---
 N_PZ_942 = !add_p<2> & !N_PZ_814;		"--- [PT=1, FI=2, LVL=3] ---
 N_PZ_943 = add_p<0>
      # !add_p<1>;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_944 = N_PZ_993
      # N_PZ_941;		"--- [PT=2, FI=2, LVL=5] ---
 N_PZ_945 = N_PZ_941
      # N_PZ_823;		"--- [PT=2, FI=2, LVL=5] ---
 N_PZ_946 = !add_p<0>
      # add_p<1>;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_947 = !ack_int.Q & !N_PZ_939;		"--- [PT=1, FI=2, LVL=4] ---
 N_PZ_948 = !fl_vme<2>.Q
      # !fl_vme<1>.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_949 = N_PZ_943
      # N_PZ_941;		"--- [PT=2, FI=2, LVL=5] ---
 N_PZ_950 = N_PZ_946
      # N_PZ_831;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_951 = !ack_int.Q & N_PZ_942;		"--- [PT=1, FI=2, LVL=4] ---
 N_PZ_952 = !N_PZ_938 & N_PZ_942;		"--- [PT=1, FI=2, LVL=4] ---
 N_PZ_953 = N_PZ_950
      # N_PZ_938;		"--- [PT=2, FI=2, LVL=4] ---
 N_PZ_954 = !add_p<0> & !int_lev<0>.Q
      # add_p<0> & int_lev<0>.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_955 = !N_PZ_823 & N_PZ_952;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_956 = !U5/cuenta_prgm_0_1.Q
      # !U5/cuenta_prgm_0_0.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_957 = N_PZ_940 & !N_PZ_948;		"--- [PT=1, FI=2, LVL=4] ---
 N_PZ_958 = !N_PZ_987
      # !fl_vme<0>.Q;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_959 = !N_PZ_823 & N_PZ_951;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_960 = !int_rst.Q & N_PZ_955;		"--- [PT=1, FI=2, LVL=6] ---
 N_PZ_961 = U5/state_FFD2.Q & !U5/state_FFD1.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_962 = !N_PZ_943 & N_PZ_947;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_963 = !N_PZ_823 & N_PZ_947;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_964 = !U5/cuenta_prgm_0_3.Q
      # !U5/cuenta_prgm_0_2.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_965 = !U5/cclk_counter<4>.Q & N_PZ_961;		"--- [PT=1, FI=2, LVL=2] ---
 N_PZ_966 = !ena_evres_prgm.Q
      # !evcnt_res;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_967 = !add_p<8>
      # brd_sel_16;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_968 = !fl_switch<2> & !fl_switch<1> & fl_switch<0> & !N_PZ_948
      # !fl_vme<1>.Q & !fl_vme<2>.Q;		"--- [PT=2, FI=6, LVL=2] ---
 N_PZ_969 = !fl_switch<2> & !fl_switch<0> & N_PZ_1046
      # !fl_vme<0>.Q & !fl_vme<1>.Q & !fl_vme<2>.Q
    ;		"--- [PT=2, FI=6, LVL=4] ---
 N_PZ_970 = fl_switch<0>
      # !fl_switch<2>;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_971 = N_PZ_854
      # N_PZ_845;		"--- [PT=2, FI=2, LVL=3] ---
 N_PZ_972 = !fl_switch<0> & N_PZ_1003 & N_PZ_1048
      # !fl_vme<0>.Q & fl_vme<1>.Q & !fl_vme<2>.Q
    ;		"--- [PT=2, FI=6, LVL=3] ---
 N_PZ_973 = !N_PZ_943 & N_PZ_951;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_974 = !U5/state_FFD2.Q & !U5/state_FFD1.Q
    ;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_975 = N_PZ_951 & !N_PZ_993;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_976 = N_PZ_947 & !N_PZ_993;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_977 = !ack_int.Q & !N_PZ_950;		"--- [PT=1, FI=2, LVL=3] ---
 N_PZ_978 = add_p<3>
      # add_p<5>;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_979 = !fl_vme<0>.Q & !fl_vme<1>.Q & fl_vme<2>.Q
      # !N_PZ_970 & N_PZ_1046;		"--- [PT=2, FI=5, LVL=4] ---
 N_PZ_980 = N_PZ_964
      # !U5/cuenta_prgm_0_4.Q;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_981 = !ack_int.Q & !N_PZ_831;		"--- [PT=1, FI=2, LVL=2] ---
 N_PZ_982 = N_PZ_981 & !N_PZ_993;		"--- [PT=1, FI=2, LVL=3] ---
 N_PZ_983 = db<1>.PIN
      # db<0>.PIN;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_984 = db<3>.PIN
      # db<2>.PIN;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_985 = !add_p<6>
      # !add_p<7>;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_986 = !add_p<1> & !int_lev<1>.Q
      # add_p<1> & int_lev<1>.Q;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_987 = N_PZ_970
      # !fl_switch<1>;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_988 = N_PZ_984
      # N_PZ_983;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_989 = !U5/jtag_start.Q & U5/jtag_shift.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_990 = !U5/jtag_shift.Q & N_PZ_945;		"--- [PT=1, FI=2, LVL=6] ---
 N_PZ_991 = !U5/jtag_start.Q & !U5/jtag_shift.Q
    ;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_992 = ds0 & ds1;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_993 = add_p<0>
      # add_p<1>;		"--- [PT=2, FI=2, LVL=1] ---
 N_PZ_994 = N_PZ_978
      # add_p<2>;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_995 = U5/state_FFD3.Q & !U5/state_FFD2.Q;		"--- [PT=1, FI=2, LVL=1] ---
 N_PZ_996 = U5/jtag_shift.Q & N_PZ_945;		"--- [PT=1, FI=2, LVL=6] ---
 N_PZ_997 = N_PZ_985
      # N_PZ_967;		"--- [PT=2, FI=2, LVL=2] ---
 N_PZ_998 = N_PZ_957 & N_PZ_965;		"--- [PT=1, FI=2, LVL=5] ---
 N_PZ_999 = !U5/state_FFD3.Q & N_PZ_965;		"--- [PT=1, FI=2, LVL=3] ---
 U1/dssync.AR = ds0;		"--- [PT=1, FI=1, LVL=1] ---
 U1/dssync.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/dssync.D = U1/q8.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q1.AR = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 U1/q1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q1.T = !write & !U1/q1.Q & N_PZ_1030;		"--- [PT=1, FI=3, LVL=8] ---
 U1/q2.AR = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 U1/q2.CE = !write & N_PZ_1030;		"--- [PT=1, FI=2, LVL=8] ---
 U1/q2.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q2.D = U1/q1.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q4.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U1/q4.D = !U1/q2.Q & !U1/q7.Q;		"--- [PT=1, FI=2, LVL=1] ---
 U1/q44.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q44.D = U1/q4.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q444.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q444.D = U1/q44.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q6.AR = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 U1/q6.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q6.D = !tp2.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q7.AR = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 U1/q7.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q7.D = U1/q9.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q8.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q8.D = !ds0 & !ds1;		"--- [PT=1, FI=2, LVL=1] ---
 U1/q9.AR = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 U1/q9.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U1/q9.D = U1/q6.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r3.AR = sysreset;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r3.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r3.D = ds0;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r4.AR = sysreset;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r4.CE = U3/r3.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r4.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r4.D = int_rst.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r5.AR = ds0;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r5.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r5.D = !iackin;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r6.AR = ds0;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r6.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r6.D = U3/r5.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r7.AR = ds0;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r7.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r7.D = U3/r6.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r8.AP = as;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r8.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U3/r8.D = U3/r7.Q & N_PZ_1042
      # U3/r8.Q & !U3/r7.Q;		"--- [PT=2, FI=3, LVL=5] ---
 U5/_n0041 = db<15>.PIN & !add_p<4> & U5/ena_rst_prgm.Q & !N_PZ_993 & !
    N_PZ_994 & !N_PZ_997 & N_PZ_1044
      # evcnt_res & ena_evres_prgm.Q;		"--- [PT=2, FI=9, LVL=3] ---
 U5/_n007019 = flash_tdo_p<3> & U5/flash_enable<3>.Q & N_PZ_998
      # flash_tdo_p<2> & U5/flash_enable<2>.Q & N_PZ_998
      # flash_tdo_p<1> & U5/flash_enable<1>.Q & N_PZ_998
      # flash_tdo_p<0> & U5/flash_enable<0>.Q & N_PZ_998
      # flash_tdo_p<4> & U5/flash_enable<4>.Q & N_PZ_998
      # flash_tdo_p<5> & flash_ena_5_rosmem.Q & N_PZ_998
    ;		"--- [PT=6, FI=13, LVL=6] ---
 U5/bits_to_send<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/bits_to_send<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/bits_to_send<0>.T = U5/jtag_num_bits<0>.Q & !U5/bits_to_send<0>.Q & 
    N_PZ_1034
      # !U5/jtag_num_bits<0>.Q & U5/bits_to_send<0>.Q & N_PZ_974
      # U5/bits_to_send<0>.Q & N_PZ_995
      # N_PZ_999;		"--- [PT=4, FI=6, LVL=4] ---
 U5/bits_to_send<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/bits_to_send<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/bits_to_send<1>.T = U5/jtag_num_bits<1>.Q & !U5/bits_to_send<1>.Q & 
    N_PZ_1034
      # !U5/jtag_num_bits<1>.Q & U5/bits_to_send<1>.Q & N_PZ_974
      # !U5/bits_to_send<0>.Q & N_PZ_999
      # U5/bits_to_send<1>.Q & N_PZ_995;		"--- [PT=4, FI=7, LVL=4] ---
 U5/bits_to_send<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/bits_to_send<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/bits_to_send<2>.T = U5/jtag_num_bits<2>.Q & !U5/bits_to_send<2>.Q & 
    N_PZ_1034
      # !U5/jtag_num_bits<2>.Q & U5/bits_to_send<2>.Q & N_PZ_974
      # N_PZ_999 & N_PZ_1050
      # U5/bits_to_send<2>.Q & N_PZ_995;		"--- [PT=4, FI=7, LVL=4] ---
 U5/bits_to_send<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/bits_to_send<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/bits_to_send<3>.T = !U5/bits_to_send<2>.Q & N_PZ_999 & N_PZ_1050
      # U5/jtag_num_bits<3>.Q & !U5/bits_to_send<3>.Q & N_PZ_1034
      # !U5/jtag_num_bits<3>.Q & U5/bits_to_send<3>.Q & N_PZ_974
      # U5/bits_to_send<3>.Q & N_PZ_995;		"--- [PT=4, FI=8, LVL=4] ---
 U5/cclk_counter<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_counter<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_counter<0>.T = 1;
 U5/cclk_counter<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_counter<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_counter<1>.T = U5/cclk_counter<0>.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_counter<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_counter<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_counter<2>.T = N_PZ_1053;		"--- [PT=1, FI=1, LVL=2] ---
 U5/cclk_counter<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_counter<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_counter<3>.T = U5/cclk_counter<2>.Q & N_PZ_1053
    ;		"--- [PT=1, FI=2, LVL=2] ---
 U5/cclk_counter<4>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_counter<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_counter<4>.T = U5/cclk_counter<2>.Q & U5/cclk_counter<3>.Q & 
    N_PZ_1053;		"--- [PT=1, FI=3, LVL=2] ---
 U5/cclk_freq<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_freq<0>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 U5/cclk_freq<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_freq<0>.D = db<10>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_freq<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_freq<1>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 U5/cclk_freq<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_freq<1>.D = db<11>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_freq<2>.AP = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cclk_freq<2>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 U5/cclk_freq<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cclk_freq<2>.D = db<12>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/cuenta_prgm_0_0.AR = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cuenta_prgm_0_0.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/cuenta_prgm_0_0.D = U5/cuenta_prgm_0_0.Q & N_PZ_980
      # U5/cuenta_prgm_0_0.Q & !U5/cuenta_prgm_0_1.Q
      # !N_PZ_944;		"--- [PT=3, FI=4, LVL=6] ---
 U5/cuenta_prgm_0_1.AR = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cuenta_prgm_0_1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/cuenta_prgm_0_1.D = !N_PZ_956 & N_PZ_980
      # !U5/cuenta_prgm_0_0.Q & !U5/cuenta_prgm_0_1.Q
      # !N_PZ_944;		"--- [PT=3, FI=5, LVL=6] ---
 U5/cuenta_prgm_0_2.AR = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cuenta_prgm_0_2.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/cuenta_prgm_0_2.D = !U5/cuenta_prgm_0_4.Q & !N_PZ_1017
      # !U5/cuenta_prgm_0_3.Q & !N_PZ_1017
      # !U5/cuenta_prgm_0_2.Q & N_PZ_956
      # !N_PZ_944;		"--- [PT=4, FI=6, LVL=6] ---
 U5/cuenta_prgm_0_3.AR = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cuenta_prgm_0_3.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/cuenta_prgm_0_3.D = !U5/cuenta_prgm_0_4.Q & !N_PZ_1038
      # !U5/cuenta_prgm_0_3.Q & N_PZ_1017
      # !N_PZ_944;		"--- [PT=3, FI=5, LVL=6] ---
 U5/cuenta_prgm_0_4.AR = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 U5/cuenta_prgm_0_4.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/cuenta_prgm_0_4.D = !U5/cuenta_prgm_0_4.Q & N_PZ_1038
      # !N_PZ_944;		"--- [PT=2, FI=3, LVL=6] ---
 U5/ena_evres.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/ena_evres.CE = N_PZ_1004;		"--- [PT=1, FI=1, LVL=6] ---
 U5/ena_evres.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/ena_evres.D = db<8>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/ena_rst_prgm.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/ena_rst_prgm.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 U5/ena_rst_prgm.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/ena_rst_prgm.D = db<14>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_enable<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_enable<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_enable<0>.D = U5/flash_enable<0>.Q & N_PZ_1032
      # db<0>.PIN & !N_PZ_949;		"--- [PT=2, FI=4, LVL=8] ---
 U5/flash_enable<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_enable<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_enable<1>.D = U5/flash_enable<1>.Q & N_PZ_1032
      # db<1>.PIN & !N_PZ_949;		"--- [PT=2, FI=4, LVL=8] ---
 U5/flash_enable<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_enable<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_enable<2>.D = U5/flash_enable<2>.Q & N_PZ_1032
      # db<2>.PIN & !N_PZ_949;		"--- [PT=2, FI=4, LVL=8] ---
 U5/flash_enable<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_enable<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_enable<3>.D = U5/flash_enable<3>.Q & N_PZ_1032
      # db<3>.PIN & !N_PZ_949;		"--- [PT=2, FI=4, LVL=8] ---
 U5/flash_enable<4>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_enable<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_enable<4>.T = !U5/flash_enable<4>.Q & !N_PZ_949 & !N_PZ_1020
    
      # U5/flash_enable<4>.Q & !N_PZ_949 & N_PZ_1020
    ;		"--- [PT=2, FI=3, LVL=6] ---
 U5/flash_tck.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_tck.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tck.D = U5/state_FFD2.Q & U5/flash_tck.Q & !N_PZ_1010
      # !U5/state_FFD3.Q & N_PZ_961;		"--- [PT=2, FI=5, LVL=2] ---
 U5/flash_tck_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_tck_reg.CE = !N_PZ_949;		"--- [PT=1, FI=1, LVL=6] ---
 U5/flash_tck_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tck_reg.D = db<6>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tdi_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_tdi_reg.CE = !N_PZ_949;		"--- [PT=1, FI=1, LVL=6] ---
 U5/flash_tdi_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tdi_reg.D = db<8>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tms.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_tms.CE = !N_PZ_945;		"--- [PT=1, FI=1, LVL=6] ---
 U5/flash_tms.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tms.D = db<8>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tms_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/flash_tms_reg.CE = !N_PZ_949;		"--- [PT=1, FI=1, LVL=6] ---
 U5/flash_tms_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/flash_tms_reg.D = db<7>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/gol_notready_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/gol_notready_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/gol_notready_reg.T = db<7>.PIN & !U5/gol_notready_reg.Q & !N_PZ_953
    
      # !db<7>.PIN & U5/gol_notready_reg.Q & !N_PZ_953
      # !gol_ready & !U5/gol_notready_reg.Q & N_PZ_953
    ;		"--- [PT=3, FI=4, LVL=5] ---
 U5/int_ena_mdone.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_ena_mdone.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_ena_mdone.T = db<2>.PIN & !U5/int_ena_mdone.Q & N_PZ_960
      # !db<2>.PIN & U5/int_ena_mdone.Q & N_PZ_955
      # U5/int_ena_mdone.Q & int_rst.Q;		"--- [PT=3, FI=5, LVL=7] ---
 U5/int_ena_rosw.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_ena_rosw.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_ena_rosw.T = db<3>.PIN & !U5/int_ena_rosw.Q & N_PZ_960
      # !db<3>.PIN & U5/int_ena_rosw.Q & N_PZ_955
      # U5/int_ena_rosw.Q & int_rst.Q;		"--- [PT=3, FI=5, LVL=7] ---
 U5/int_ena_sff.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_ena_sff.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_ena_sff.T = db<1>.PIN & !U5/int_ena_sff.Q & N_PZ_960
      # !db<1>.PIN & U5/int_ena_sff.Q & N_PZ_955
      # U5/int_ena_sff.Q & int_rst.Q;		"--- [PT=3, FI=5, LVL=7] ---
 U5/int_ena_spaf.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_ena_spaf.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_ena_spaf.T = db<0>.PIN & !U5/int_ena_spaf.Q & N_PZ_960
      # !db<0>.PIN & U5/int_ena_spaf.Q & N_PZ_955
      # U5/int_ena_spaf.Q & int_rst.Q;		"--- [PT=3, FI=5, LVL=7] ---
 U5/int_vect<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<0>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<0>.D = db<8>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<1>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<1>.D = db<9>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<2>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<2>.D = db<10>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<3>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<3>.D = db<11>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<4>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<4>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<4>.D = db<12>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<5>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<5>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<5>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<5>.D = db<13>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<6>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<6>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<6>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<6>.D = db<14>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<7>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/int_vect<7>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 U5/int_vect<7>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/int_vect<7>.D = db<15>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_end.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/jtag_end.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/jtag_end.D = !U5/jtag_end.Q & N_PZ_1010
      # U5/jtag_start.Q & N_PZ_974
      # N_PZ_995;		"--- [PT=3, FI=5, LVL=2] ---
 U5/jtag_num_bits<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/jtag_num_bits<0>.CE = !N_PZ_945;		"--- [PT=1, FI=1, LVL=6] ---
 U5/jtag_num_bits<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_num_bits<0>.D = db<9>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_num_bits<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/jtag_num_bits<1>.CE = !N_PZ_945;		"--- [PT=1, FI=1, LVL=6] ---
 U5/jtag_num_bits<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_num_bits<1>.D = db<10>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_num_bits<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/jtag_num_bits<2>.CE = !N_PZ_945;		"--- [PT=1, FI=1, LVL=6] ---
 U5/jtag_num_bits<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_num_bits<2>.D = db<11>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_num_bits<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/jtag_num_bits<3>.CE = !N_PZ_945;		"--- [PT=1, FI=1, LVL=6] ---
 U5/jtag_num_bits<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_num_bits<3>.D = db<12>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_shift.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/jtag_shift.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/jtag_shift.D = !U5/state_FFD3.Q & !U5/jtag_shift.Q
      # U5/state_FFD2.Q & U5/state_FFD1.Q
      # N_PZ_995;		"--- [PT=3, FI=5, LVL=2] ---
 U5/jtag_start.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/jtag_start.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/jtag_start.D = U5/jtag_start.Q & !U5/jtag_end.Q
      # !N_PZ_945;		"--- [PT=2, FI=3, LVL=6] ---
 U5/local_reset = db<14>.PIN & !add_p<4> & !N_PZ_993 & !N_PZ_994 & !N_PZ_997
     & N_PZ_1044
      # sysreset;		"--- [PT=2, FI=7, LVL=3] ---
 U5/mem_d0.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/mem_d0.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/mem_d0.D = mem_done;		"--- [PT=1, FI=1, LVL=1] ---
 U5/mem_done_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/mem_done_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/mem_done_reg.D = mem_done & U5/mem_done_reg.Q & !int_rst.Q & U5/mem_d0.Q
    
      # mem_done & !U5/mem_d0.Q;		"--- [PT=2, FI=4, LVL=1] ---
 U5/not_sel_tim_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/not_sel_tim_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/not_sel_tim_reg.T = db<10>.PIN & !U5/not_sel_tim_reg.Q & !N_PZ_953
    
      # !db<10>.PIN & U5/not_sel_tim_reg.Q & !N_PZ_953
      # !sel_tim_p & !U5/not_sel_tim_reg.Q & N_PZ_953
    ;		"--- [PT=3, FI=4, LVL=5] ---
 U5/qpll_error_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/qpll_error_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/qpll_error_reg.T = db<4>.PIN & !U5/qpll_error_reg.Q & !N_PZ_953
      # !db<4>.PIN & U5/qpll_error_reg.Q & !N_PZ_953
      # qpll_error & !U5/qpll_error_reg.Q & N_PZ_953
    ;		"--- [PT=3, FI=4, LVL=5] ---
 U5/qpll_hasunlock_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/qpll_hasunlock_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/qpll_hasunlock_reg.T = db<6>.PIN & !U5/qpll_hasunlock_reg.Q & !N_PZ_953
    
      # !db<6>.PIN & U5/qpll_hasunlock_reg.Q & !N_PZ_953
      # !qpll_locked & !U5/qpll_hasunlock_reg.Q & N_PZ_953
    ;		"--- [PT=3, FI=4, LVL=5] ---
 U5/reset_1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/reset_1.D = db<14>.PIN & N_PZ_1004
      # sysreset;		"--- [PT=2, FI=3, LVL=6] ---
 U5/reset_2.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/reset_2.D = U5/reset_1.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U5/ros_w0.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/ros_w0.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/ros_w0.D = ros_waiting;		"--- [PT=1, FI=1, LVL=1] ---
 U5/ros_waiting_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/ros_waiting_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/ros_waiting_reg.D = ros_waiting & U5/ros_waiting_reg.Q & !int_rst.Q & 
    U5/ros_w0.Q
      # ros_waiting & !U5/ros_w0.Q;		"--- [PT=2, FI=4, LVL=1] ---
 U5/s_reset_1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/s_reset_1.D = N_PZ_1001
      # U5/local_reset;		"--- [PT=2, FI=2, LVL=7] ---
 U5/s_reset_2.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/s_reset_2.D = U5/s_reset_1.Q;		"--- [PT=1, FI=1, LVL=1] ---
 U5/state_FFD1.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/state_FFD1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/state_FFD1.D = !U5/state_FFD3.Q & !U5/state_FFD2.Q & N_PZ_1035
      # !U5/state_FFD3.Q & U5/state_FFD1.Q & !U5/cclk_counter<4>.Q
      # U5/state_FFD3.Q & N_PZ_961;		"--- [PT=3, FI=6, LVL=2] ---
 U5/state_FFD2.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/state_FFD2.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/state_FFD2.D = !U5/state_FFD2.Q & U5/cclk_counter<4>.Q
      # !N_PZ_1010
      # N_PZ_974;		"--- [PT=3, FI=4, LVL=2] ---
 U5/state_FFD3.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/state_FFD3.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/state_FFD3.D = U5/state_FFD3.Q & !U5/bits_to_send<2>.Q & !
    U5/bits_to_send<3>.Q & N_PZ_961 & N_PZ_1050
      # N_PZ_999;		"--- [PT=2, FI=6, LVL=4] ---
 U5/tdi_bits<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<0>.D = U5/tdi_bits<1>.Q & N_PZ_996
      # U5/tdi_bits<0>.Q & N_PZ_990
      # db<0>.PIN & !N_PZ_945;		"--- [PT=3, FI=6, LVL=7] ---
 U5/tdi_bits<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<1>.D = U5/tdi_bits<2>.Q & N_PZ_996
      # U5/tdi_bits<1>.Q & N_PZ_990
      # db<1>.PIN & !N_PZ_945;		"--- [PT=3, FI=6, LVL=7] ---
 U5/tdi_bits<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<2>.D = U5/tdi_bits<3>.Q & N_PZ_996
      # U5/tdi_bits<2>.Q & N_PZ_990
      # db<2>.PIN & !N_PZ_945;		"--- [PT=3, FI=6, LVL=7] ---
 U5/tdi_bits<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<3>.D = U5/tdi_bits<4>.Q & N_PZ_996
      # U5/tdi_bits<3>.Q & N_PZ_990
      # db<3>.PIN & !N_PZ_945;		"--- [PT=3, FI=6, LVL=7] ---
 U5/tdi_bits<4>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<4>.D = U5/tdi_bits<5>.Q & N_PZ_996
      # U5/tdi_bits<4>.Q & N_PZ_990
      # db<4>.PIN & !N_PZ_945;		"--- [PT=3, FI=6, LVL=7] ---
 U5/tdi_bits<5>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<5>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<5>.D = U5/tdi_bits<6>.Q & N_PZ_996
      # U5/tdi_bits<5>.Q & N_PZ_990
      # db<5>.PIN & !N_PZ_945;		"--- [PT=3, FI=6, LVL=7] ---
 U5/tdi_bits<6>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<6>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<6>.D = U5/tdi_bits<7>.Q & N_PZ_996
      # U5/tdi_bits<6>.Q & N_PZ_990
      # db<6>.PIN & !N_PZ_945;		"--- [PT=3, FI=6, LVL=7] ---
 U5/tdi_bits<7>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdi_bits<7>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdi_bits<7>.D = U5/tdi_bits<7>.Q & N_PZ_990
      # db<7>.PIN & !N_PZ_945;		"--- [PT=2, FI=4, LVL=7] ---
 U5/tdo_bits<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<0>.D = U5/tdo_bits<0>.Q & N_PZ_991
      # U5/tdo_bits<1>.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_bits<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<1>.D = U5/tdo_bits<1>.Q & N_PZ_991
      # U5/tdo_bits<2>.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_bits<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<2>.D = U5/tdo_bits<2>.Q & N_PZ_991
      # U5/tdo_bits<3>.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_bits<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<3>.D = U5/tdo_bits<3>.Q & N_PZ_991
      # U5/tdo_bits<4>.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_bits<4>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<4>.D = U5/tdo_bits<4>.Q & N_PZ_991
      # U5/tdo_bits<5>.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_bits<5>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<5>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<5>.D = U5/tdo_bits<5>.Q & N_PZ_991
      # U5/tdo_bits<6>.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_bits<6>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<6>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<6>.D = U5/tdo_bits<6>.Q & N_PZ_991
      # U5/tdo_bits<7>.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_bits<7>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_bits<7>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 U5/tdo_bits<7>.D = U5/tdo_bits<7>.Q & N_PZ_991
      # U5/tdo_reg.Q & N_PZ_989;		"--- [PT=2, FI=4, LVL=2] ---
 U5/tdo_reg.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 U5/tdo_reg.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! U5/tdo_reg.D = !U5/_n007019 & N_PZ_999
      # U5/state_FFD3.Q & !U5/tdo_reg.Q
      # !U5/_n007019 & !U5/tdo_reg.Q
      # N_PZ_995;		"--- [PT=4, FI=5, LVL=7] ---
 ULED1/q1.AR = ULED1/q3.Q;		"--- [PT=1, FI=1, LVL=1] ---
 ULED1/q1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 ULED1/q1.T = int_rst.Q & !ULED1/q1.Q;		"--- [PT=1, FI=2, LVL=1] ---
 ULED1/q3.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 ULED1/q3.CLK = clk_slow;		"--- [PT=1, FI=1, LVL=1] ---
 ULED1/q3.D = !intrpt_led.Q;		"--- [PT=1, FI=1, LVL=1] ---
 ULED2/q1.AR = ULED2/q3.Q;		"--- [PT=1, FI=1, LVL=1] ---
 ULED2/q1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 ULED2/q1.T = !ULED2/q1.Q & N_PZ_1039;		"--- [PT=1, FI=2, LVL=3] ---
 ULED2/q3.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 ULED2/q3.CLK = clk_slow;		"--- [PT=1, FI=1, LVL=1] ---
 ULED2/q3.D = !dtack_led.Q;		"--- [PT=1, FI=1, LVL=1] ---
 ULED3/q1.AR = ULED3/q3.Q;		"--- [PT=1, FI=1, LVL=1] ---
 ULED3/q1.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 ULED3/q1.T = !ULED3/q1.Q & N_PZ_1044;		"--- [PT=1, FI=2, LVL=2] ---
 ULED3/q3.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 ULED3/q3.CLK = clk_slow;		"--- [PT=1, FI=1, LVL=1] ---
 ULED3/q3.D = spare_led.Q;		"--- [PT=1, FI=1, LVL=1] ---
 _n0009 = !tp2.Q & !N_PZ_997 & N_PZ_1018
      # ack_int.Q;		"--- [PT=2, FI=4, LVL=4] ---
 ack_int.AR = ds0;		"--- [PT=1, FI=1, LVL=1] ---
 ack_int.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 ack_int.D = U3/r6.Q & N_PZ_1042
      # ack_int.Q & !U3/r6.Q;		"--- [PT=2, FI=3, LVL=5] ---
 add_f_p<10> = 1;
 add_f_p<11> = 1;
 add_f_p<12> = 1;
 add_f_p<13> = 1;
 add_f_p<14> = 1;
 add_f_p<15> = 1;
 add_f_p<9> = 1;
! add_hold = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 cclk<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 cclk<0>.D = fpga_done<0> & N_PZ_971;		"--- [PT=1, FI=2, LVL=4] ---
 cclk<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 cclk<1>.D = fpga_done<1> & N_PZ_971;		"--- [PT=1, FI=2, LVL=4] ---
 cclk<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 cclk<2>.D = fpga_done<2> & N_PZ_971;		"--- [PT=1, FI=2, LVL=4] ---
 cclk<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 cclk<3>.D = fpga_done<3> & N_PZ_971;		"--- [PT=1, FI=2, LVL=4] ---
 cclk<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 cclk<4>.D = fpga_done<4> & N_PZ_971;		"--- [PT=1, FI=2, LVL=4] ---
 cscr_p<0> = !add_p<7> & !add_p<6> & N_PZ_1033;		"--- [PT=1, FI=3, LVL=2] ---
 cscr_p<1> = !add_p<7> & add_p<6> & N_PZ_1033;		"--- [PT=1, FI=3, LVL=2] ---
 cscr_p<2> = add_p<7> & !add_p<6> & N_PZ_1033;		"--- [PT=1, FI=3, LVL=2] ---
 cscr_p<3> = !N_PZ_985 & N_PZ_1033;		"--- [PT=1, FI=2, LVL=2] ---
 cscr_p<4> = !add_p<7> & !add_p<6> & !N_PZ_967;		"--- [PT=1, FI=3, LVL=2] ---
 cscr_p<5> = !add_p<7> & add_p<6> & !N_PZ_967;		"--- [PT=1, FI=3, LVL=2] ---
 cscr_p<6> = add_p<7> & !add_p<6> & !N_PZ_967;		"--- [PT=1, FI=3, LVL=2] ---
 cspare_8 = 1;
 cspare_9 = 1;
 db<0> = fl_vme<0>.Q & N_PZ_1045
      # U5/tdo_bits<0>.Q & N_PZ_982
      # i2c_ce_gol.Q & N_PZ_977
      # fpga_init<0>.Q & N_PZ_976
      # ros_waiting & N_PZ_975
      # spaf<0> & N_PZ_973
      # U5/tdi_bits<0>.Q & N_PZ_963
      # U5/flash_enable<0>.Q & N_PZ_962
      # U5/int_ena_spaf.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<0>.Q;		"--- [PT=10, FI=20, LVL=6] ---
 db<0>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<10> = flash_tdo_p<1> & N_PZ_1000
      # U5/not_sel_tim_reg.Q & N_PZ_977
      # U5/cclk_freq<0>.Q & N_PZ_976
      # sel_tim_clk<1>.Q & N_PZ_975
      # U5/jtag_num_bits<1>.Q & N_PZ_963
      # U5/int_vect<2>.Q & N_PZ_959;		"--- [PT=6, FI=12, LVL=7] ---
 db<10>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<11> = flash_tdo_p<2> & N_PZ_1000
      # U5/cclk_freq<1>.Q & N_PZ_976
      # U5/jtag_num_bits<2>.Q & N_PZ_963
      # U5/int_vect<3>.Q & N_PZ_959;		"--- [PT=4, FI=8, LVL=7] ---
 db<11>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<12> = flash_tdo_p<3> & N_PZ_1000
      # U5/cclk_freq<2>.Q & N_PZ_976
      # U5/jtag_num_bits<3>.Q & N_PZ_963
      # U5/int_vect<4>.Q & N_PZ_959;		"--- [PT=4, FI=8, LVL=7] ---
 db<12>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<13> = flash_tdo_p<4> & N_PZ_1000
      # ena_evres_prgm.Q & N_PZ_976
      # U5/int_vect<5>.Q & N_PZ_959;		"--- [PT=3, FI=6, LVL=7] ---
 db<13>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<14> = flash_tdo_p<5> & N_PZ_1000
      # U5/ena_rst_prgm.Q & N_PZ_976
      # U5/int_vect<6>.Q & N_PZ_959;		"--- [PT=3, FI=6, LVL=7] ---
 db<14>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<15> = U5/int_vect<7>.Q & N_PZ_959;		"--- [PT=1, FI=2, LVL=6] ---
 db<15>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<1> = fl_vme<1>.Q & N_PZ_1045
      # U5/tdo_bits<1>.Q & N_PZ_982
      # i2c_ce_1wire.Q & N_PZ_977
      # fpga_init<1>.Q & N_PZ_976
      # mem_done & N_PZ_975
      # spaf<1> & N_PZ_973
      # U5/tdi_bits<1>.Q & N_PZ_963
      # U5/flash_enable<1>.Q & N_PZ_962
      # U5/int_ena_sff.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<1>.Q;		"--- [PT=10, FI=20, LVL=6] ---
 db<1>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<2> = fl_vme<2>.Q & N_PZ_1045
      # U5/tdo_bits<2>.Q & N_PZ_982
      # gol_off.Q & N_PZ_977
      # fpga_init<2>.Q & N_PZ_976
      # !fpga_done<0> & N_PZ_975
      # spaf<2> & N_PZ_973
      # U5/tdi_bits<2>.Q & N_PZ_963
      # U5/flash_enable<2>.Q & N_PZ_962
      # U5/int_ena_mdone.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<2>.Q;		"--- [PT=10, FI=20, LVL=6] ---
 db<2>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<3> = U5/tdo_bits<3>.Q & N_PZ_982
      # gol_ready & N_PZ_977
      # fpga_init<3>.Q & N_PZ_976
      # !fpga_done<1> & N_PZ_975
      # spaf<3> & N_PZ_973
      # U5/tdi_bits<3>.Q & N_PZ_963
      # U5/flash_enable<3>.Q & N_PZ_962
      # U5/int_ena_rosw.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<3>.Q;		"--- [PT=9, FI=18, LVL=6] ---
 db<3>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<4> = U5/tdo_bits<4>.Q & N_PZ_982
      # U5/qpll_error_reg.Q & N_PZ_977
      # fpga_init<4>.Q & N_PZ_976
      # !fpga_done<2> & N_PZ_975
      # spaf<4> & N_PZ_973
      # U5/tdi_bits<4>.Q & N_PZ_963
      # U5/flash_enable<4>.Q & N_PZ_962
      # int_rst.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<4>.Q;		"--- [PT=9, FI=18, LVL=6] ---
 db<4>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<5> = U5/tdo_bits<5>.Q & N_PZ_982
      # qpll_locked & N_PZ_977
      # !fpga_done<3> & N_PZ_975
      # sff<0> & N_PZ_973
      # U5/tdi_bits<5>.Q & N_PZ_963
      # flash_ena_5_rosmem.Q & N_PZ_962
      # int_lev<0>.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<5>.Q;		"--- [PT=8, FI=16, LVL=6] ---
 db<5>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<6> = U5/tdo_bits<6>.Q & N_PZ_982
      # U5/qpll_hasunlock_reg.Q & N_PZ_977
      # !fpga_done<4> & N_PZ_975
      # sff<1> & N_PZ_973
      # U5/tdi_bits<6>.Q & N_PZ_963
      # U5/flash_tck_reg.Q & N_PZ_962
      # int_lev<1>.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<6>.Q;		"--- [PT=8, FI=16, LVL=6] ---
 db<6>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<7> = U5/tdo_bits<7>.Q & N_PZ_982
      # U5/gol_notready_reg.Q & N_PZ_977
      # sff<2> & N_PZ_973
      # U5/tdi_bits<7>.Q & N_PZ_963
      # U5/flash_tms_reg.Q & N_PZ_962
      # int_lev<2>.Q & N_PZ_959
      # ack_int.Q & U5/int_vect<7>.Q;		"--- [PT=7, FI=14, LVL=6] ---
 db<7>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<8> = U5/jtag_end.Q & N_PZ_982
      # U5/ena_evres.Q & N_PZ_975
      # sff<3> & N_PZ_973
      # U5/flash_tms.Q & N_PZ_963
      # U5/flash_tdi_reg.Q & N_PZ_962
      # U5/int_vect<0>.Q & N_PZ_959;		"--- [PT=6, FI=12, LVL=6] ---
 db<8>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 db<9> = flash_tdo_p<0> & N_PZ_1000
      # !sel_tim_p & N_PZ_977
      # sel_tim_clk<0>.Q & N_PZ_975
      # sff<4> & N_PZ_973
      # U5/jtag_num_bits<0>.Q & N_PZ_963
      # U5/int_vect<1>.Q & N_PZ_959;		"--- [PT=6, FI=12, LVL=7] ---
 db<9>.OE = _n0009;		"--- [PT=1, FI=1, LVL=5] ---
 dtack_int.AR = ds0;		"--- [PT=1, FI=1, LVL=1] ---
 dtack_int.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 dtack_int.D = U3/r7.Q & N_PZ_1042
      # dtack_int.Q & !U3/r7.Q;		"--- [PT=2, FI=3, LVL=5] ---
 dtack_led.AP = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 dtack_led.CLK = clk_slow;		"--- [PT=1, FI=1, LVL=1] ---
 dtack_led.D = !ULED2/q1.Q;		"--- [PT=1, FI=1, LVL=1] ---
! dtack_p = !N_PZ_1039;		"--- [PT=1, FI=1, LVL=3] ---
 ena_evres_prgm.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 ena_evres_prgm.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 ena_evres_prgm.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 ena_evres_prgm.D = db<13>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 enw_vf = i2c_int_p;		"--- [PT=1, FI=1, LVL=1] ---
 enw_x = N_PZ_1044;		"--- [PT=1, FI=1, LVL=2] ---
 etr_vf = brd_sel_24;		"--- [PT=1, FI=1, LVL=1] ---
 etr_x.AP = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 etr_x.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 etr_x.T = write & etr_x.Q & N_PZ_1030;		"--- [PT=1, FI=3, LVL=8] ---
 fl_tck_r.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 fl_tck_r.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fl_tck_r.D = fl_tck;		"--- [PT=1, FI=1, LVL=1] ---
 fl_tdi_r.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 fl_tdi_r.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fl_tdi_r.D = fl_tdi;		"--- [PT=1, FI=1, LVL=1] ---
 fl_tdo.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 fl_tdo.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! fl_tdo.D = !flash_tdo_p<3> & fl_vme<0>.Q & fl_vme<1>.Q & N_PZ_1012
      # !flash_tdo_p<5> & fl_vme<0>.Q & fl_vme<2>.Q & N_PZ_1011
      # !flash_tdo_p<1> & fl_vme<0>.Q & N_PZ_968
      # !flash_tdo_p<4> & N_PZ_979
      # !flash_tdo_p<2> & N_PZ_972
      # !flash_tdo_p<0> & N_PZ_969;		"--- [PT=6, FI=15, LVL=5] ---
 fl_tms_r.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 fl_tms_r.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fl_tms_r.D = fl_tms;		"--- [PT=1, FI=1, LVL=1] ---
 fl_vme<0>.AP = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fl_vme<0>.CE = N_PZ_1052;		"--- [PT=1, FI=1, LVL=6] ---
 fl_vme<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fl_vme<0>.D = db<0>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 fl_vme<1>.AP = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fl_vme<1>.CE = N_PZ_1052;		"--- [PT=1, FI=1, LVL=6] ---
 fl_vme<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fl_vme<1>.D = db<1>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 fl_vme<2>.AP = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fl_vme<2>.CE = N_PZ_1052;		"--- [PT=1, FI=1, LVL=6] ---
 fl_vme<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fl_vme<2>.D = db<2>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 flash_ena_5_rosmem.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 flash_ena_5_rosmem.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 flash_ena_5_rosmem.T = !flash_ena_5_rosmem.Q & !N_PZ_949 & !N_PZ_1019
    
      # flash_ena_5_rosmem.Q & !N_PZ_949 & N_PZ_1019
    ;		"--- [PT=2, FI=3, LVL=6] ---
 flash_tck_p<0> = U5/flash_enable<0>.Q & N_PZ_1008
      # fl_tck_r.Q & N_PZ_969;		"--- [PT=2, FI=4, LVL=6] ---
 flash_tck_p<1> = U5/flash_enable<1>.Q & N_PZ_840 & N_PZ_1043
      # N_PZ_968 & N_PZ_1047;		"--- [PT=2, FI=5, LVL=5] ---
 flash_tck_p<2> = U5/flash_enable<2>.Q & N_PZ_1008
      # fl_tck_r.Q & N_PZ_972;		"--- [PT=2, FI=4, LVL=6] ---
 flash_tck_p<3> = fl_switch<0> & fl_tck_r.Q & N_PZ_1003 & N_PZ_1048
      # fl_vme<1>.Q & !fl_vme<2>.Q & N_PZ_1047
      # U5/flash_enable<3>.Q & N_PZ_1008;		"--- [PT=3, FI=9, LVL=6] ---
 flash_tck_p<4> = U5/flash_enable<4>.Q & N_PZ_1008
      # fl_tck_r.Q & N_PZ_979;		"--- [PT=2, FI=4, LVL=6] ---
 flash_tck_p<5> = fl_switch<2> & fl_switch<0> & fl_tck_r.Q & N_PZ_1046
    
      # !fl_vme<1>.Q & fl_vme<2>.Q & N_PZ_1047
      # flash_ena_5_rosmem.Q & N_PZ_1008;		"--- [PT=3, FI=9, LVL=6] ---
! flash_tdi_p = !U5/flash_tdi_reg.Q & !U5/tdi_bits<0>.Q & N_PZ_1043
      # !fl_tdi_r.Q & N_PZ_1002;		"--- [PT=2, FI=5, LVL=5] ---
! flash_tms_p = !U5/flash_tms.Q & !U5/flash_tms_reg.Q & N_PZ_1043
      # !fl_tms_r.Q & N_PZ_1002;		"--- [PT=2, FI=5, LVL=5] ---
 fpga_init<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fpga_init<0>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 fpga_init<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<0>.D = db<0>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fpga_init<1>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 fpga_init<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<1>.D = db<1>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fpga_init<2>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 fpga_init<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<2>.D = db<2>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<3>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fpga_init<3>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 fpga_init<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<3>.D = db<3>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<4>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 fpga_init<4>.CE = !N_PZ_944;		"--- [PT=1, FI=1, LVL=6] ---
 fpga_init<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 fpga_init<4>.D = db<4>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 g245_p = tp2.Q & g245_mem & !ack_int.Q & !flash_ena_5_rosmem.Q & !U1/q1.Q
    ;		"--- [PT=1, FI=5, LVL=1] ---
 gol_off.AP = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 gol_off.CE = !N_PZ_953;		"--- [PT=1, FI=1, LVL=5] ---
 gol_off.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 gol_off.D = db<2>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
! gol_reset = db<11>.PIN & !N_PZ_953
      # !N_PZ_930;		"--- [PT=2, FI=3, LVL=5] ---
 i2c_ce_1wire.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 i2c_ce_1wire.CE = !N_PZ_953;		"--- [PT=1, FI=1, LVL=5] ---
 i2c_ce_1wire.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 i2c_ce_1wire.D = db<1>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 i2c_ce_gol.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 i2c_ce_gol.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 i2c_ce_gol.T = !i2c_ce_gol.Q & !N_PZ_953 & !N_PZ_1014
      # i2c_ce_gol.Q & !N_PZ_953 & N_PZ_1014;		"--- [PT=2, FI=3, LVL=5] ---
! i2c_ce_p = !N_PZ_997 & !N_PZ_1018;		"--- [PT=1, FI=2, LVL=4] ---
! i2c_rd = !tp2.Q & !i2c_ce_p;		"--- [PT=1, FI=2, LVL=5] ---
 i2c_reset = N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
! i2c_wr = !i2c_ce_p & N_PZ_1044;		"--- [PT=1, FI=2, LVL=5] ---
 iackout = iackin & U3/r8.Q;		"--- [PT=1, FI=2, LVL=1] ---
 int_lev<0>.AP = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 int_lev<0>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 int_lev<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 int_lev<0>.D = db<5>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 int_lev<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 int_lev<1>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 int_lev<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 int_lev<1>.D = db<6>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 int_lev<2>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 int_lev<2>.CE = N_PZ_960;		"--- [PT=1, FI=1, LVL=7] ---
 int_lev<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 int_lev<2>.D = db<7>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 int_rst.AR = sysreset;		"--- [PT=1, FI=1, LVL=1] ---
 int_rst.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 int_rst.D = !dtack_int.Q & U5/int_ena_rosw.Q & U5/ros_waiting_reg.Q
      # !dtack_int.Q & U5/int_ena_mdone.Q & U5/mem_done_reg.Q
      # spaf<0> & N_PZ_1009
      # spaf<1> & N_PZ_1009
      # spaf<2> & N_PZ_1009
      # spaf<3> & N_PZ_1009
      # spaf<4> & N_PZ_1009
      # sff<0> & N_PZ_1007
      # sff<1> & N_PZ_1007
      # sff<2> & N_PZ_1007
      # sff<3> & N_PZ_1007
      # sff<4> & N_PZ_1007
      # !dtack_int.Q & int_rst.Q;		"--- [PT=13, FI=18, LVL=2] ---
 intrpt_led.AP = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 intrpt_led.CLK = clk_slow;		"--- [PT=1, FI=1, LVL=1] ---
 intrpt_led.D = !ULED1/q1.Q;		"--- [PT=1, FI=1, LVL=1] ---
 irq<1> = !int_lev<1>.Q & !int_lev<2>.Q & N_PZ_1021
    ;		"--- [PT=1, FI=3, LVL=2] ---
 irq<2> = int_lev<1>.Q & !int_lev<2>.Q & N_PZ_1051
    ;		"--- [PT=1, FI=3, LVL=2] ---
 irq<3> = int_lev<1>.Q & !int_lev<2>.Q & N_PZ_1021
    ;		"--- [PT=1, FI=3, LVL=2] ---
 irq<4> = !int_lev<1>.Q & int_lev<2>.Q & N_PZ_1051
    ;		"--- [PT=1, FI=3, LVL=2] ---
 irq<5> = !int_lev<1>.Q & int_lev<2>.Q & N_PZ_1021
    ;		"--- [PT=1, FI=3, LVL=2] ---
 irq<6> = int_lev<1>.Q & int_lev<2>.Q & N_PZ_1051
    ;		"--- [PT=1, FI=3, LVL=2] ---
 irq<7> = int_lev<1>.Q & int_lev<2>.Q & N_PZ_1021
    ;		"--- [PT=1, FI=3, LVL=2] ---
 ldpreg = db<11>.PIN & N_PZ_1004;		"--- [PT=1, FI=2, LVL=6] ---
 mrs = db<13>.PIN & N_PZ_1049
      # U5/local_reset;		"--- [PT=2, FI=3, LVL=6] ---
 mspare_0 = 1;
 mspare_1 = 1;
 mspare_2 = 1;
 mspare_3 = 1;
 on_244 = 0;
 prgm_fpga<0>.AP = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 prgm_fpga<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! prgm_fpga<0>.D = !db<5>.PIN & !N_PZ_944
      # !prgm_fpga<0>.Q & N_PZ_944
      # N_PZ_1006;		"--- [PT=3, FI=4, LVL=8] ---
 prgm_fpga<1>.AP = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 prgm_fpga<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! prgm_fpga<1>.D = !db<6>.PIN & !N_PZ_944
      # !prgm_fpga<1>.Q & N_PZ_944
      # N_PZ_1006;		"--- [PT=3, FI=4, LVL=8] ---
 prgm_fpga<2>.AP = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 prgm_fpga<2>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! prgm_fpga<2>.D = !db<7>.PIN & !N_PZ_944
      # !prgm_fpga<2>.Q & N_PZ_944
      # N_PZ_1006;		"--- [PT=3, FI=4, LVL=8] ---
 prgm_fpga<3>.AP = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 prgm_fpga<3>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! prgm_fpga<3>.D = !db<8>.PIN & !N_PZ_944
      # !prgm_fpga<3>.Q & N_PZ_944
      # N_PZ_1006;		"--- [PT=3, FI=4, LVL=8] ---
 prgm_fpga<4>.AP = U5/_n0041;		"--- [PT=1, FI=1, LVL=4] ---
 prgm_fpga<4>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
! prgm_fpga<4>.D = !db<9>.PIN & !N_PZ_944
      # !prgm_fpga<4>.Q & N_PZ_944
      # N_PZ_1006;		"--- [PT=3, FI=4, LVL=8] ---
 prgm_fpga_p<0> = !prgm_fpga<0>.Q & N_PZ_966;		"--- [PT=1, FI=2, LVL=2] ---
 prgm_fpga_p<1> = !prgm_fpga<1>.Q & N_PZ_966;		"--- [PT=1, FI=2, LVL=2] ---
 prgm_fpga_p<2> = !prgm_fpga<2>.Q & N_PZ_966;		"--- [PT=1, FI=2, LVL=2] ---
 prgm_fpga_p<3> = !prgm_fpga<3>.Q & N_PZ_966;		"--- [PT=1, FI=2, LVL=2] ---
 prgm_fpga_p<4> = !prgm_fpga<4>.Q & N_PZ_966;		"--- [PT=1, FI=2, LVL=2] ---
 prs = db<12>.PIN & N_PZ_1049
      # N_PZ_1001
      # U5/local_reset;		"--- [PT=3, FI=4, LVL=7] ---
! qpll_reset = db<8>.PIN & !N_PZ_953
      # !N_PZ_930;		"--- [PT=2, FI=3, LVL=5] ---
! reset_p = N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 sel_tim_clk<0>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 sel_tim_clk<0>.CE = N_PZ_1004;		"--- [PT=1, FI=1, LVL=6] ---
 sel_tim_clk<0>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 sel_tim_clk<0>.D = db<9>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 sel_tim_clk<1>.AR = U5/local_reset;		"--- [PT=1, FI=1, LVL=4] ---
 sel_tim_clk<1>.CE = N_PZ_1004;		"--- [PT=1, FI=1, LVL=6] ---
 sel_tim_clk<1>.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 sel_tim_clk<1>.D = db<10>.PIN;		"--- [PT=1, FI=1, LVL=1] ---
 spare_led.AR = !N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 spare_led.CLK = clk_slow;		"--- [PT=1, FI=1, LVL=1] ---
 spare_led.D = ULED3/q1.Q;		"--- [PT=1, FI=1, LVL=1] ---
 tp2.AP = N_PZ_992;		"--- [PT=1, FI=1, LVL=2] ---
 tp2.CLK = clk;		"--- [PT=1, FI=1, LVL=1] ---
 tp2.T = write & tp2.Q & N_PZ_1030;		"--- [PT=1, FI=3, LVL=8] ---
! tp3 = N_PZ_930;		"--- [PT=1, FI=1, LVL=2] ---
 tp4 = clk;		"--- [PT=1, FI=1, LVL=1] ---
! vspare_0 = !U5/s_reset_1.Q & !U5/s_reset_2.Q;		"--- [PT=1, FI=2, LVL=1] ---
 vspare_1 = 1;
END
