### Equations

add_f_p(10) <= NOT ('0');
add_f_p(11) <= NOT ('0');
add_f_p(12) <= NOT ('0');
add_f_p(13) <= NOT ('0');
add_f_p(14) <= NOT ('0');
add_f_p(15) <= NOT ('0');
add_f_p(9) <= NOT ('0');
add_hold <= NOT ((ds0 AND ds1));
FDCPE_cclk0: FDCPE port map (cclk(0),cclk_D(0),clk,'0','0','1'); cclk_D(0) <= (fpga_done(0) AND N_PZ_971);
N_PZ_971 <= ((U5/cclk_freq(1) AND U5/cclk_freq(2) AND U5/cclk_counter(4)) OR (U5/cclk_freq(0) AND U5/cclk_freq(2) AND U5/cclk_counter(4)) OR (U5/cclk_freq(1) AND U5/cclk_freq(0) AND
NOT U5/cclk_freq(2) AND U5/cclk_counter(1))
OR (U5/cclk_freq(1) AND NOT U5/cclk_freq(0) AND
NOT U5/cclk_freq(2) AND U5/cclk_counter(2))
OR (NOT U5/cclk_freq(1) AND U5/cclk_freq(0) AND
NOT U5/cclk_freq(2) AND U5/cclk_counter(3))
OR (NOT U5/cclk_freq(1) AND NOT U5/cclk_freq(0) AND
U5/cclk_freq(2) AND U5/cclk_counter(0))
OR (NOT U5/cclk_freq(1) AND NOT U5/cclk_freq(0) AND
NOT U5/cclk_freq(2) AND U5/cclk_counter(4)));
db(11) <= ((U5/cclk_freq(1) AND NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(2))
OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(3))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(2)));FDCPE_U5/cclk_freq1: FDCPE port map (U5/cclk_freq(1),db(11).PIN,clk,U5/local_reset,'0',N_PZ_944);
N_PZ_944 <= (NOT add_p(1) AND NOT add_p(0) AND N_PZ_941);
N_PZ_941 <= (NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4);
FDCPE_U1/q2: FDCPE port map (U1/q2,U1/q1,clk,U1/q2_CLR,'0',U1/q2_CE); U1/q2_CLR <= (ds0 AND ds1); U1/q2_CE <= (NOT brd_sel_16 AND iack AND lword AND add_mod(0) AND NOT write AND NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND add_mod(5) AND
add_mod(3) AND U1/dssync);
FTCPE_U1/q1: FTCPE port map (U1/q1,U1/q1_T,clk,U1/q1_CLR,'0','1'); U1/q1_T <= (NOT brd_sel_16 AND NOT U1/q1 AND iack AND lword AND add_mod(0) AND NOT write AND NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND add_mod(5) AND add_mod(3) AND U1/dssync);
U1/q1_CLR <= (ds0 AND ds1);
FDCPE_U1/dssync: FDCPE port map (U1/dssync,U1/q8,clk,ds0,'0','1');
FDCPE_U1/q8: FDCPE port map (U1/q8,U1/q8_D,clk,'0','0','1'); U1/q8_D <= (NOT ds0 AND NOT ds1);
FDCPE_U1/q4: FDCPE port map (U1/q4,U1/q4_D,clk,'0','0','1'); U1/q4_D <= NOT ((NOT U1/q2 AND NOT U1/q7));
FDCPE_U1/q7: FDCPE port map (U1/q7,U1/q9,clk,U1/q7_CLR,'0','1'); U1/q7_CLR <= (ds0 AND ds1);
FDCPE_U1/q9: FDCPE port map (U1/q9,U1/q6,clk,U1/q9_CLR,'0','1'); U1/q9_CLR <= (ds0 AND ds1);
FDCPE_U1/q6: FDCPE port map (U1/q6,NOT tp2,clk,U1/q6_CLR,'0','1'); U1/q6_CLR <= (ds0 AND ds1);
FTCPE_tp2: FTCPE port map (tp2,tp2_T,clk,'0',tp2_PRE,'1'); tp2_T <= (NOT brd_sel_16 AND iack AND lword AND add_mod(0) AND write AND NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND add_mod(5) AND add_mod(3) AND U1/dssync AND tp2); tp2_PRE <= (ds0 AND ds1);
U5/local_reset <= ((sysreset) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4 AND db(14).PIN));
_n0009_MC.GLB <= ((ack_int) OR (add_p(5) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND NOT tp2) OR (NOT add_p(4) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND NOT tp2)
OR (add_p(3) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND NOT tp2)
OR (add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND NOT tp2));
FDCPE_ack_int: FDCPE port map (ack_int,ack_int_D,clk,ds0,'0','1'); ack_int_D <= ((ack_int AND NOT U3/r6) OR (U3/r6 AND N_PZ_1042));
FDCPE_U3/r6: FDCPE port map (U3/r6,U3/r5,clk,ds0,'0','1');
FDCPE_U3/r5: FDCPE port map (U3/r5,NOT iackin,clk,ds0,'0','1');
N_PZ_1042 <= (NOT iack AND U3/r4) XOR ((add_p(1) AND NOT iack AND U3/r4 AND NOT int_lev(1)) OR (NOT add_p(1) AND NOT iack AND U3/r4 AND int_lev(1)) OR (add_p(0) AND NOT iack AND U3/r4 AND NOT int_lev(0)) OR (NOT add_p(0) AND NOT iack AND U3/r4 AND int_lev(0))
OR (add_p(2) AND NOT iack AND U3/r4 AND NOT int_lev(2))
OR (NOT add_p(2) AND NOT iack AND U3/r4 AND int_lev(2)));
FDCPE_U3/r4: FDCPE port map (U3/r4,int_rst,clk,sysreset,'0',U3/r3);
FDCPE_int_rst: FDCPE port map (int_rst,int_rst_D,clk,sysreset,'0','1'); int_rst_D <= ((int_rst AND NOT dtack_int) OR (sff(4) AND NOT dtack_int AND U5/int_ena_sff) OR (NOT dtack_int AND U5/int_ena_sff AND sff(3)) OR (NOT dtack_int AND U5/int_ena_sff AND sff(2))
OR (NOT dtack_int AND U5/int_ena_sff AND sff(1))
OR (NOT dtack_int AND U5/int_ena_sff AND sff(0))
OR (NOT dtack_int AND spaf(4) AND U5/int_ena_spaf)
OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(3))
OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(2))
OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(1))
OR (NOT dtack_int AND U5/int_ena_spaf AND spaf(0))
OR (NOT dtack_int AND U5/int_ena_mdone AND U5/mem_done_reg)
OR (NOT dtack_int AND U5/int_ena_rosw AND U5/ros_waiting_reg));
FDCPE_dtack_int: FDCPE port map (dtack_int,dtack_int_D,clk,ds0,'0','1'); dtack_int_D <= ((N_PZ_1042 AND U3/r7) OR (dtack_int AND NOT U3/r7));
FDCPE_U3/r7: FDCPE port map (U3/r7,U3/r6,clk,ds0,'0','1');
FTCPE_U5/int_ena_sff: FTCPE port map (U5/int_ena_sff,U5/int_ena_sff_T,clk,U5/local_reset,'0','1'); U5/int_ena_sff_T <= ((int_rst AND U5/int_ena_sff) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_sff AND NOT db(1).PIN)
OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_sff AND
db(1).PIN));
FTCPE_U5/int_ena_spaf: FTCPE port map (U5/int_ena_spaf,U5/int_ena_spaf_T,clk,U5/local_reset,'0','1'); U5/int_ena_spaf_T <= ((int_rst AND U5/int_ena_spaf) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_spaf AND NOT db(0).PIN)
OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_spaf AND
db(0).PIN));
FTCPE_U5/int_ena_mdone: FTCPE port map (U5/int_ena_mdone,U5/int_ena_mdone_T,clk,U5/local_reset,'0','1'); U5/int_ena_mdone_T <= ((int_rst AND U5/int_ena_mdone) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_mdone AND NOT db(2).PIN)
OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_mdone AND
db(2).PIN));
FDCPE_U5/mem_done_reg: FDCPE port map (U5/mem_done_reg,U5/mem_done_reg_D,clk,U5/local_reset,'0','1'); U5/mem_done_reg_D <= ((mem_done AND NOT U5/mem_d0) OR (NOT int_rst AND U5/mem_done_reg AND mem_done AND U5/mem_d0));
FDCPE_U5/mem_d0: FDCPE port map (U5/mem_d0,mem_done,clk,U5/local_reset,'0','1');
FTCPE_U5/int_ena_rosw: FTCPE port map (U5/int_ena_rosw,U5/int_ena_rosw_T,clk,U5/local_reset,'0','1'); U5/int_ena_rosw_T <= ((int_rst AND U5/int_ena_rosw) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND U5/int_ena_rosw AND NOT db(3).PIN)
OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst AND NOT U5/int_ena_rosw AND
db(3).PIN));
FDCPE_U5/ros_waiting_reg: FDCPE port map (U5/ros_waiting_reg,U5/ros_waiting_reg_D,clk,U5/local_reset,'0','1'); U5/ros_waiting_reg_D <= ((ros_waiting AND NOT U5/ros_w0) OR (NOT int_rst AND U5/ros_waiting_reg AND ros_waiting AND U5/ros_w0));
FDCPE_U5/ros_w0: FDCPE port map (U5/ros_w0,ros_waiting,clk,U5/local_reset,'0','1');
FDCPE_U3/r3: FDCPE port map (U3/r3,ds0,clk,sysreset,'0','1');
db(5) <= ((ack_int AND U5/int_vect(5)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(5)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_lev(0))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND flash_ena_5_rosmem)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(0))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND qpll_locked)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(5))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(3)));FDCPE_int_lev0: FDCPE port map (int_lev(0),db(5).PIN,clk,'0',U5/local_reset,int_lev_CE(0));
int_lev_CE(0) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_int_lev1: FDCPE port map (int_lev(1),db(6).PIN,clk,U5/local_reset,'0',int_lev_CE(1)); int_lev_CE(1) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_int_lev2: FDCPE port map (int_lev(2),db(7).PIN,clk,U5/local_reset,'0',int_lev_CE(2)); int_lev_CE(2) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
db(10) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(1)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(2))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/not_sel_tim_reg)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/cclk_freq(0))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sel_tim_clk(1))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(1)));FDCPE_U5/cclk_freq0: FDCPE port map (U5/cclk_freq(0),db(10).PIN,clk,U5/local_reset,'0',N_PZ_944);
db(12) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(3)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(4))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/cclk_freq(2))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(3)));FDCPE_U5/cclk_freq2: FDCPE port map (U5/cclk_freq(2),db(12).PIN,clk,'0',U5/local_reset,N_PZ_944);
FTCPE_U5/cclk_counter0: FTCPE port map (U5/cclk_counter(0),'0',clk,U5/local_reset,'0','1');
FTCPE_U5/cclk_counter4: FTCPE port map (U5/cclk_counter(4),U5/cclk_counter_T(4),clk,U5/local_reset,'0','1'); U5/cclk_counter_T(4) <= (U5/cclk_counter(0) AND U5/cclk_counter(1) AND U5/cclk_counter(2) AND U5/cclk_counter(3));
FTCPE_U5/cclk_counter1: FTCPE port map (U5/cclk_counter(1),U5/cclk_counter(0),clk,U5/local_reset,'0','1');
FTCPE_U5/cclk_counter2: FTCPE port map (U5/cclk_counter(2),U5/cclk_counter_T(2),clk,U5/local_reset,'0','1'); U5/cclk_counter_T(2) <= (U5/cclk_counter(0) AND U5/cclk_counter(1));
FTCPE_U5/cclk_counter3: FTCPE port map (U5/cclk_counter(3),U5/cclk_counter_T(3),clk,U5/local_reset,'0','1'); U5/cclk_counter_T(3) <= (U5/cclk_counter(0) AND U5/cclk_counter(1) AND U5/cclk_counter(2));
FDCPE_cclk1: FDCPE port map (cclk(1),cclk_D(1),clk,'0','0','1'); cclk_D(1) <= (N_PZ_971 AND fpga_done(1));
FDCPE_cclk2: FDCPE port map (cclk(2),cclk_D(2),clk,'0','0','1'); cclk_D(2) <= (N_PZ_971 AND fpga_done(2));
FDCPE_cclk3: FDCPE port map (cclk(3),cclk_D(3),clk,'0','0','1'); cclk_D(3) <= (N_PZ_971 AND fpga_done(3));
FDCPE_cclk4: FDCPE port map (cclk(4),cclk_D(4),clk,'0','0','1'); cclk_D(4) <= (N_PZ_971 AND fpga_done(4));
cscr_p(0) <= (NOT brd_sel_16 AND NOT add_p(8) AND NOT add_p(7) AND NOT add_p(6));
cscr_p(1) <= (NOT brd_sel_16 AND NOT add_p(8) AND NOT add_p(7) AND add_p(6));
cscr_p(2) <= (NOT brd_sel_16 AND NOT add_p(8) AND add_p(7) AND NOT add_p(6));
cscr_p(3) <= (NOT brd_sel_16 AND NOT add_p(8) AND add_p(7) AND add_p(6));
cscr_p(4) <= (NOT brd_sel_16 AND add_p(8) AND NOT add_p(7) AND NOT add_p(6));
cscr_p(5) <= (NOT brd_sel_16 AND add_p(8) AND NOT add_p(7) AND add_p(6));
cscr_p(6) <= (NOT brd_sel_16 AND add_p(8) AND add_p(7) AND NOT add_p(6));
cspare_8 <= NOT ('0');
cspare_9 <= NOT ('0');
db_I(15) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(7));
FDCPE_U5/int_vect7: FDCPE port map (U5/int_vect(7),db(15).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(7)); U5/int_vect_CE(7) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
db_I(1) <= ((ack_int AND U5/int_vect(1)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(1)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_sff)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(1))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(1))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND i2c_ce_1wire)
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fl_vme(1))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(1))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(1))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND mem_done));
FDCPE_i2c_ce_1wire: FDCPE port map (i2c_ce_1wire,db(1).PIN,clk,U5/local_reset,'0',N_PZ_953);
N_PZ_953 <= (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4);
FDCPE_fpga_init1: FDCPE port map (fpga_init(1),db(1).PIN,clk,U5/local_reset,'0',N_PZ_944);
FDCPE_U5/flash_enable1: FDCPE port map (U5/flash_enable(1),U5/flash_enable_D(1),clk,U5/local_reset,'0','1'); U5/flash_enable_D(1) <= ((U5/flash_enable(1) AND N_PZ_1032) OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(1).PIN));
N_PZ_1032 <= (NOT flash_ena_5_rosmem AND NOT U5/flash_enable(4)) XOR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND NOT flash_ena_5_rosmem AND NOT U5/flash_enable(4));
FDCPE_flash_ena_5_rosmem: FDCPE port map (flash_ena_5_rosmem,flash_ena_5_rosmem_D,clk,U5/local_reset,'0','1'); flash_ena_5_rosmem_D <= ((NOT add_p(1) AND flash_ena_5_rosmem) OR (add_p(0) AND flash_ena_5_rosmem) OR (NOT N_PZ_941 AND flash_ena_5_rosmem)
OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND NOT db(1).PIN AND
NOT db(0).PIN AND NOT db(2).PIN AND NOT db(3).PIN AND NOT db(4).PIN AND db(5).PIN));
FDCPE_U5/flash_enable4: FDCPE port map (U5/flash_enable(4),U5/flash_enable_D(4),clk,U5/local_reset,'0','1'); U5/flash_enable_D(4) <= ((NOT add_p(1) AND U5/flash_enable(4)) OR (add_p(0) AND U5/flash_enable(4)) OR (NOT N_PZ_941 AND U5/flash_enable(4))
OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND NOT db(1).PIN AND
NOT db(0).PIN AND NOT db(2).PIN AND NOT db(3).PIN AND db(4).PIN AND NOT db(5).PIN));
FDCPE_fl_vme1: FDCPE port map (fl_vme(1),db(1).PIN,clk,'0',U5/local_reset,fl_vme_CE(1)); fl_vme_CE(1) <= (NOT add_p(1) AND add_p(0) AND N_PZ_941);
db(9) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/jtag_num_bits(0)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(1))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(4))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT sel_tim_p)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sel_tim_clk(0))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(0)));FDCPE_U5/int_vect1: FDCPE port map (U5/int_vect(1),db(9).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(1));
U5/int_vect_CE(1) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_U5/tdi_bits1: FDCPE port map (U5/tdi_bits(1),U5/tdi_bits_D(1),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(1) <= ((db(1).PIN AND N_PZ_945) OR (U5/tdi_bits(1) AND NOT N_PZ_945 AND NOT U5/jtag_shift) OR (NOT N_PZ_945 AND U5/tdi_bits(2) AND U5/jtag_shift));
N_PZ_945 <= (add_p(1) AND add_p(0) AND N_PZ_941);
FDCPE_U5/tdi_bits2: FDCPE port map (U5/tdi_bits(2),U5/tdi_bits_D(2),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(2) <= ((db(2).PIN AND N_PZ_945) OR (NOT N_PZ_945 AND U5/tdi_bits(2) AND NOT U5/jtag_shift) OR (NOT N_PZ_945 AND U5/tdi_bits(3) AND U5/jtag_shift));
FDCPE_U5/tdi_bits3: FDCPE port map (U5/tdi_bits(3),U5/tdi_bits_D(3),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(3) <= ((db(3).PIN AND N_PZ_945) OR (NOT N_PZ_945 AND U5/tdi_bits(3) AND NOT U5/jtag_shift) OR (NOT N_PZ_945 AND U5/tdi_bits(4) AND U5/jtag_shift));
FDCPE_U5/tdi_bits4: FDCPE port map (U5/tdi_bits(4),U5/tdi_bits_D(4),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(4) <= ((db(4).PIN AND N_PZ_945) OR (NOT N_PZ_945 AND U5/tdi_bits(4) AND NOT U5/jtag_shift) OR (NOT N_PZ_945 AND U5/tdi_bits(5) AND U5/jtag_shift));
FDCPE_U5/tdi_bits5: FDCPE port map (U5/tdi_bits(5),U5/tdi_bits_D(5),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(5) <= ((db(5).PIN AND N_PZ_945) OR (NOT N_PZ_945 AND U5/tdi_bits(5) AND NOT U5/jtag_shift) OR (NOT N_PZ_945 AND U5/tdi_bits(6) AND U5/jtag_shift));
FDCPE_U5/tdi_bits6: FDCPE port map (U5/tdi_bits(6),U5/tdi_bits_D(6),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(6) <= ((db(6).PIN AND N_PZ_945) OR (NOT N_PZ_945 AND U5/tdi_bits(6) AND NOT U5/jtag_shift) OR (NOT N_PZ_945 AND U5/tdi_bits(7) AND U5/jtag_shift));
FDCPE_U5/tdi_bits7: FDCPE port map (U5/tdi_bits(7),U5/tdi_bits_D(7),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(7) <= ((db(7).PIN AND N_PZ_945) OR (NOT N_PZ_945 AND U5/tdi_bits(7) AND NOT U5/jtag_shift));
FDCPE_U5/jtag_shift: FDCPE port map (U5/jtag_shift,U5/jtag_shift_D,clk,U5/local_reset,'0','1'); U5/jtag_shift_D <= NOT (((NOT U5/jtag_shift AND NOT U5/state_FFD3) OR (U5/state_FFD3 AND NOT U5/state_FFD2) OR (U5/state_FFD2 AND U5/state_FFD1)));
FDCPE_U5/state_FFD3: FDCPE port map (U5/state_FFD3,U5/state_FFD3_D,clk,U5/local_reset,'0','1'); U5/state_FFD3_D <= ((NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND U5/state_FFD2 AND NOT U5/state_FFD1) OR (U5/state_FFD3 AND U5/state_FFD2 AND NOT U5/state_FFD1 AND
NOT U5/bits_to_send(0) AND NOT U5/bits_to_send(1) AND NOT U5/bits_to_send(2) AND
NOT U5/bits_to_send(3)));
FDCPE_U5/state_FFD2: FDCPE port map (U5/state_FFD2,U5/state_FFD2_D,clk,U5/local_reset,'0','1'); U5/state_FFD2_D <= NOT (((U5/cclk_counter(4) AND NOT U5/state_FFD2) OR (U5/state_FFD3 AND U5/state_FFD1) OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1)));
FDCPE_U5/state_FFD1: FDCPE port map (U5/state_FFD1,U5/state_FFD1_D,clk,U5/local_reset,'0','1'); U5/state_FFD1_D <= ((NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND U5/state_FFD1) OR (U5/state_FFD3 AND U5/state_FFD2 AND NOT U5/state_FFD1) OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/state_FFD1)
OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/jtag_start));
FDCPE_U5/jtag_start: FDCPE port map (U5/jtag_start,U5/jtag_start_D,clk,U5/local_reset,'0','1'); U5/jtag_start_D <= ((N_PZ_945) OR (U5/jtag_start AND NOT U5/jtag_end));
FDCPE_U5/jtag_end: FDCPE port map (U5/jtag_end,U5/jtag_end_D,clk,U5/local_reset,'0','1'); U5/jtag_end_D <= NOT (((U5/state_FFD3 AND NOT U5/state_FFD2) OR (NOT U5/state_FFD3 AND NOT U5/jtag_end) OR (NOT U5/state_FFD1 AND NOT U5/jtag_end) OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND U5/jtag_start)));
FTCPE_U5/bits_to_send0: FTCPE port map (U5/bits_to_send(0),U5/bits_to_send_T(0),clk,U5/local_reset,'0','1'); U5/bits_to_send_T(0) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/bits_to_send(0)) OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
U5/state_FFD2 AND NOT U5/state_FFD1)
OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
U5/bits_to_send(0) AND NOT U5/jtag_num_bits(0))
OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
NOT U5/bits_to_send(0) AND U5/jtag_num_bits(0)));
FDCPE_U5/jtag_num_bits0: FDCPE port map (U5/jtag_num_bits(0),db(9).PIN,clk,U5/local_reset,'0',N_PZ_945);
FTCPE_U5/bits_to_send1: FTCPE port map (U5/bits_to_send(1),U5/bits_to_send_T(1),clk,U5/local_reset,'0','1'); U5/bits_to_send_T(1) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/bits_to_send(1)) OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND U5/bits_to_send(1) AND NOT U5/jtag_num_bits(1))
OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/bits_to_send(0))
OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
NOT U5/bits_to_send(1) AND U5/jtag_num_bits(1)));
FDCPE_U5/jtag_num_bits1: FDCPE port map (U5/jtag_num_bits(1),db(10).PIN,clk,U5/local_reset,'0',N_PZ_945);
FTCPE_U5/bits_to_send2: FTCPE port map (U5/bits_to_send(2),U5/bits_to_send_T(2),clk,U5/local_reset,'0','1'); U5/bits_to_send_T(2) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/bits_to_send(2)) OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND U5/bits_to_send(2) AND NOT U5/jtag_num_bits(2))
OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
NOT U5/bits_to_send(2) AND U5/jtag_num_bits(2))
OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/bits_to_send(0) AND
NOT U5/bits_to_send(1)));
FDCPE_U5/jtag_num_bits2: FDCPE port map (U5/jtag_num_bits(2),db(11).PIN,clk,U5/local_reset,'0',N_PZ_945);
FTCPE_U5/bits_to_send3: FTCPE port map (U5/bits_to_send(3),U5/bits_to_send_T(3),clk,U5/local_reset,'0','1'); U5/bits_to_send_T(3) <= ((U5/state_FFD3 AND NOT U5/state_FFD2 AND U5/bits_to_send(3)) OR (NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND U5/bits_to_send(3) AND NOT U5/jtag_num_bits(3))
OR (NOT U5/state_FFD3 AND NOT U5/state_FFD2 AND NOT U5/state_FFD1 AND
NOT U5/bits_to_send(3) AND U5/jtag_num_bits(3))
OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/bits_to_send(0) AND
NOT U5/bits_to_send(1) AND NOT U5/bits_to_send(2)));
FDCPE_U5/jtag_num_bits3: FDCPE port map (U5/jtag_num_bits(3),db(12).PIN,clk,U5/local_reset,'0',N_PZ_945);
FDCPE_U5/tdo_bits1: FDCPE port map (U5/tdo_bits(1),U5/tdo_bits_D(1),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(1) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(2)) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(1)));
FDCPE_U5/tdo_bits2: FDCPE port map (U5/tdo_bits(2),U5/tdo_bits_D(2),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(2) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(3)) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(2)));
FDCPE_U5/tdo_bits3: FDCPE port map (U5/tdo_bits(3),U5/tdo_bits_D(3),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(3) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(4)) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(3)));
FDCPE_U5/tdo_bits4: FDCPE port map (U5/tdo_bits(4),U5/tdo_bits_D(4),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(4) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(5)) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(4)));
FDCPE_U5/tdo_bits5: FDCPE port map (U5/tdo_bits(5),U5/tdo_bits_D(5),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(5) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(6)) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(5)));
FDCPE_U5/tdo_bits6: FDCPE port map (U5/tdo_bits(6),U5/tdo_bits_D(6),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(6) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(7)) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(6)));
FDCPE_U5/tdo_bits7: FDCPE port map (U5/tdo_bits(7),U5/tdo_bits_D(7),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(7) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_reg) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(7)));
FDCPE_U5/tdo_reg: FDCPE port map (U5/tdo_reg,U5/tdo_reg_D,clk,U5/local_reset,'0','1'); U5/tdo_reg_D <= NOT (((U5/state_FFD3 AND NOT U5/state_FFD2) OR (U5/state_FFD3 AND NOT U5/tdo_reg) OR (NOT U5/tdo_reg AND NOT U5/_n007019) OR (NOT U5/cclk_counter(4) AND NOT U5/state_FFD3 AND
U5/state_FFD2 AND NOT U5/state_FFD1 AND NOT U5/_n007019)));
U5/_n007019 <= ((NOT U5/cclk_counter(4) AND U5/flash_enable(1) AND U5/state_FFD2 AND NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(1)) OR (NOT U5/cclk_counter(4) AND flash_ena_5_rosmem AND U5/state_FFD2 AND NOT U5/state_FFD1 AND flash_tdo_p(5) AND N_PZ_957)
OR (NOT U5/cclk_counter(4) AND U5/flash_enable(4) AND
U5/state_FFD2 AND NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(4))
OR (NOT U5/cclk_counter(4) AND U5/state_FFD2 AND
NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(0) AND U5/flash_enable(0))
OR (NOT U5/cclk_counter(4) AND U5/state_FFD2 AND
NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(2) AND U5/flash_enable(2))
OR (NOT U5/cclk_counter(4) AND U5/state_FFD2 AND
NOT U5/state_FFD1 AND N_PZ_957 AND flash_tdo_p(3) AND U5/flash_enable(3)));
N_PZ_957 <= ((fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2)) OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2)));
db(0) <= ((ack_int AND U5/int_vect(0)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(0)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_spaf)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(0))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(0))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND i2c_ce_gol)
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fl_vme(0))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(0))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(0))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND ros_waiting));FDCPE_fl_vme0: FDCPE port map (fl_vme(0),db(0).PIN,clk,'0',U5/local_reset,fl_vme_CE(0));
fl_vme_CE(0) <= (NOT add_p(1) AND add_p(0) AND N_PZ_941);
db(2) <= ((ack_int AND U5/int_vect(2)) OR (NOT fpga_done(0) AND NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(2))
OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_mdone)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(2))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(2))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND gol_off)
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fl_vme(2))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(2))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(2)));FDCPE_fl_vme2: FDCPE port map (fl_vme(2),db(2).PIN,clk,'0',U5/local_reset,fl_vme_CE(2));
fl_vme_CE(2) <= (NOT add_p(1) AND add_p(0) AND N_PZ_941);
FDCPE_U5/flash_enable0: FDCPE port map (U5/flash_enable(0),U5/flash_enable_D(0),clk,U5/local_reset,'0','1'); U5/flash_enable_D(0) <= ((N_PZ_1032 AND U5/flash_enable(0)) OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(0).PIN));
FDCPE_U5/flash_enable2: FDCPE port map (U5/flash_enable(2),U5/flash_enable_D(2),clk,U5/local_reset,'0','1'); U5/flash_enable_D(2) <= ((N_PZ_1032 AND U5/flash_enable(2)) OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(2).PIN));
FDCPE_U5/flash_enable3: FDCPE port map (U5/flash_enable(3),U5/flash_enable_D(3),clk,U5/local_reset,'0','1'); U5/flash_enable_D(3) <= ((N_PZ_1032 AND U5/flash_enable(3)) OR (add_p(1) AND NOT add_p(0) AND N_PZ_941 AND db(3).PIN));
db_I(3) <= ((ack_int AND U5/int_vect(3)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(3)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_ena_rosw)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(3))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(3))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND gol_ready)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(3))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(3))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(1)));
FDCPE_fpga_init3: FDCPE port map (fpga_init(3),db(3).PIN,clk,U5/local_reset,'0',N_PZ_944);
FDCPE_U5/int_vect3: FDCPE port map (U5/int_vect(3),db(11).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(3)); U5/int_vect_CE(3) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
db_I(4) <= ((ack_int AND U5/int_vect(4)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(4)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_rst)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_enable(4))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND spaf(4))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/qpll_error_reg)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(4))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND fpga_init(4))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(2)));
FDCPE_fpga_init4: FDCPE port map (fpga_init(4),db(4).PIN,clk,U5/local_reset,'0',N_PZ_944);
FDCPE_U5/int_vect4: FDCPE port map (U5/int_vect(4),db(12).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(4)); U5/int_vect_CE(4) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_U5/qpll_error_reg: FDCPE port map (U5/qpll_error_reg,U5/qpll_error_reg_D,clk,U5/local_reset,'0','1'); U5/qpll_error_reg_D <= NOT (((N_PZ_953 AND NOT db(4).PIN) OR (NOT N_PZ_953 AND NOT U5/qpll_error_reg AND NOT qpll_error)));
db_I(8) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tms) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(0))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tdi_reg)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(3))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/jtag_end)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/ena_evres));
FDCPE_U5/ena_evres: FDCPE port map (U5/ena_evres,db(8).PIN,clk,U5/local_reset,'0',U5/ena_evres_CE); U5/ena_evres_CE <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4);
FDCPE_U5/flash_tdi_reg: FDCPE port map (U5/flash_tdi_reg,db(8).PIN,clk,U5/local_reset,'0',U5/flash_tdi_reg_CE); U5/flash_tdi_reg_CE <= (add_p(1) AND NOT add_p(0) AND N_PZ_941);
FDCPE_U5/flash_tms: FDCPE port map (U5/flash_tms,db(8).PIN,clk,U5/local_reset,'0',N_PZ_945);
FDCPE_U5/int_vect0: FDCPE port map (U5/int_vect(0),db(8).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(0)); U5/int_vect_CE(0) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_dtack_led: FDCPE port map (dtack_led,NOT ULED2/q1,clk_slow,'0',NOT N_PZ_930,'1');
FTCPE_ULED2/q1: FTCPE port map (ULED2/q1,ULED2/q1_T,clk,ULED2/q3,'0','1'); ULED2/q1_T <= ((dtack_int AND NOT ULED2/q1) OR (NOT ULED2/q1 AND U1/q444) OR (NOT flash_ena_5_rosmem AND NOT ULED2/q1 AND dtack_mem));
FDCPE_U1/q444: FDCPE port map (U1/q444,U1/q44,clk,'0','0','1');
FDCPE_U1/q44: FDCPE port map (U1/q44,U1/q4,clk,'0','0','1');
FDCPE_ULED2/q3: FDCPE port map (ULED2/q3,NOT dtack_led,clk_slow,NOT N_PZ_930,'0','1');
N_PZ_930 <= (NOT U5/reset_1 AND NOT U5/reset_2);
FDCPE_U5/reset_1: FDCPE port map (U5/reset_1,U5/reset_1_D,clk,'0','0','1'); U5/reset_1_D <= ((sysreset) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND db(14).PIN));
FDCPE_U5/reset_2: FDCPE port map (U5/reset_2,U5/reset_1,clk,'0','0','1');
dtack_p <= NOT (((NOT dtack_int AND flash_ena_5_rosmem AND NOT U1/q444) OR (NOT dtack_int AND NOT dtack_mem AND NOT U1/q444)));
enw_vf <= i2c_int_p;
enw_x <= (U1/q2 AND NOT U1/q4);
etr_vf <= brd_sel_24;
FTCPE_etr_x: FTCPE port map (etr_x,etr_x_T,clk,'0',etr_x_PRE,'1'); etr_x_T <= (NOT brd_sel_16 AND iack AND lword AND add_mod(0) AND write AND NOT add_mod(4) AND NOT add_mod(2) AND NOT add_mod(1) AND add_mod(5) AND add_mod(3) AND U1/dssync AND etr_x);
etr_x_PRE <= (ds0 AND ds1);
FDCPE_fl_tdo: FDCPE port map (fl_tdo,fl_tdo_D,clk,NOT N_PZ_930,'0','1'); fl_tdo_D <= NOT (((fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND NOT flash_tdo_p(3)) OR (fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND NOT flash_tdo_p(2))
OR (NOT fl_vme(1) AND NOT flash_tdo_p(5) AND fl_vme(0) AND
fl_vme(2))
OR (NOT fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND
NOT flash_tdo_p(1))
OR (NOT fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND
NOT flash_tdo_p(4))
OR (NOT fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND
NOT flash_tdo_p(0))
OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND
fl_switch(0) AND fl_vme(0) AND NOT flash_tdo_p(3))
OR (NOT flash_tdo_p(5) AND fl_switch(2) AND NOT fl_switch(1) AND
fl_switch(0) AND fl_vme(0) AND fl_vme(2))
OR (fl_vme(1) AND fl_switch(2) AND NOT fl_switch(1) AND
NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(4))
OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND
NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(2))
OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(1))
OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND NOT flash_tdo_p(0))));
flash_tck_p(0) <= ((N_PZ_957 AND U5/flash_enable(0) AND U5/flash_tck_reg) OR (N_PZ_957 AND U5/flash_enable(0) AND U5/flash_tck) OR (NOT fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r) OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));
FDCPE_fl_tck_r: FDCPE port map (fl_tck_r,fl_tck,clk,NOT N_PZ_930,'0','1');
db(6) <= ((ack_int AND U5/int_vect(6)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(6)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_lev(1))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tck_reg)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(1))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/qpll_hasunlock_reg)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(6))
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND NOT fpga_done(4)));FDCPE_U5/flash_tck_reg: FDCPE port map (U5/flash_tck_reg,db(6).PIN,clk,U5/local_reset,'0',U5/flash_tck_reg_CE);
U5/flash_tck_reg_CE <= (add_p(1) AND NOT add_p(0) AND N_PZ_941);
FDCPE_U5/flash_tck: FDCPE port map (U5/flash_tck,U5/flash_tck_D,clk,U5/local_reset,'0','1'); U5/flash_tck_D <= ((NOT U5/state_FFD3 AND U5/state_FFD2 AND NOT U5/state_FFD1) OR (U5/state_FFD3 AND U5/state_FFD2 AND U5/state_FFD1 AND U5/flash_tck));
flash_tck_p(1) <= ((NOT fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r) OR (U5/flash_enable(1) AND fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND U5/flash_tck_reg) OR (U5/flash_enable(1) AND fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND U5/flash_tck)
OR (U5/flash_enable(1) AND fl_vme(1) AND fl_switch(2) AND
fl_switch(1) AND NOT fl_switch(0) AND fl_vme(2) AND U5/flash_tck_reg)
OR (U5/flash_enable(1) AND fl_vme(1) AND fl_switch(2) AND
fl_switch(1) AND NOT fl_switch(0) AND fl_vme(2) AND U5/flash_tck)
OR (fl_vme(1) AND NOT fl_switch(2) AND NOT fl_switch(1) AND
fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));
flash_tck_p(2) <= ((N_PZ_957 AND U5/flash_enable(2) AND U5/flash_tck_reg) OR (N_PZ_957 AND U5/flash_enable(2) AND U5/flash_tck) OR (fl_vme(1) AND NOT fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r) OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND
NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));
flash_tck_p(3) <= ((N_PZ_957 AND U5/flash_enable(3) AND U5/flash_tck_reg) OR (N_PZ_957 AND U5/flash_enable(3) AND U5/flash_tck) OR (fl_vme(1) AND fl_vme(0) AND NOT fl_vme(2) AND fl_tck_r) OR (fl_vme(1) AND NOT fl_switch(2) AND fl_switch(1) AND fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));
flash_tck_p(4) <= ((U5/flash_enable(4) AND N_PZ_957 AND U5/flash_tck_reg) OR (U5/flash_enable(4) AND N_PZ_957 AND U5/flash_tck) OR (NOT fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND fl_tck_r) OR (fl_vme(1) AND fl_switch(2) AND NOT fl_switch(1) AND
NOT fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));
flash_tck_p(5) <= ((flash_ena_5_rosmem AND N_PZ_957 AND U5/flash_tck_reg) OR (flash_ena_5_rosmem AND N_PZ_957 AND U5/flash_tck) OR (NOT fl_vme(1) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r) OR (fl_vme(1) AND fl_switch(2) AND NOT fl_switch(1) AND fl_switch(0) AND fl_vme(0) AND fl_vme(2) AND fl_tck_r));
flash_tdi_p <= NOT (((NOT fl_tdi_r AND NOT N_PZ_1002) OR (fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND NOT U5/flash_tdi_reg AND NOT U5/tdi_bits(0)) OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND NOT fl_switch(0) AND fl_vme(2) AND NOT U5/flash_tdi_reg AND NOT U5/tdi_bits(0))));
FDCPE_U5/tdi_bits0: FDCPE port map (U5/tdi_bits(0),U5/tdi_bits_D(0),clk,U5/local_reset,'0','1'); U5/tdi_bits_D(0) <= ((db(0).PIN AND N_PZ_945) OR (U5/tdi_bits(1) AND NOT N_PZ_945 AND U5/jtag_shift) OR (NOT N_PZ_945 AND NOT U5/jtag_shift AND U5/tdi_bits(0)));
FDCPE_fl_tdi_r: FDCPE port map (fl_tdi_r,fl_tdi,clk,NOT N_PZ_930,'0','1');
N_PZ_1002 <= ((fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2)) OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND NOT fl_switch(0) AND fl_vme(2)));
flash_tms_p <= NOT (((NOT N_PZ_1002 AND NOT fl_tms_r) OR (fl_vme(1) AND NOT fl_vme(0) AND fl_vme(2) AND NOT U5/flash_tms AND NOT U5/flash_tms_reg) OR (fl_vme(1) AND fl_switch(2) AND fl_switch(1) AND NOT fl_switch(0) AND fl_vme(2) AND NOT U5/flash_tms AND NOT U5/flash_tms_reg)));
db(7) <= ((ack_int AND U5/int_vect(7)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/tdi_bits(7)) OR (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND int_lev(2))
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/flash_tms_reg)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND sff(2))
OR (NOT add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/gol_notready_reg)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/tdo_bits(7)));FDCPE_U5/flash_tms_reg: FDCPE port map (U5/flash_tms_reg,db(7).PIN,clk,U5/local_reset,'0',U5/flash_tms_reg_CE);
U5/flash_tms_reg_CE <= (add_p(1) AND NOT add_p(0) AND N_PZ_941);
FDCPE_fl_tms_r: FDCPE port map (fl_tms_r,fl_tms,clk,NOT N_PZ_930,'0','1');
FDCPE_fpga_init0: FDCPE port map (fpga_init(0),db(0).PIN,clk,U5/local_reset,'0',N_PZ_944);
FDCPE_fpga_init2: FDCPE port map (fpga_init(2),db(2).PIN,clk,U5/local_reset,'0',N_PZ_944);
g245_p <= (NOT U1/q1 AND tp2 AND NOT ack_int AND NOT flash_ena_5_rosmem AND g245_mem);
FDCPE_gol_off: FDCPE port map (gol_off,db(2).PIN,clk,'0',U5/local_reset,N_PZ_953);
gol_reset <= NOT (((NOT N_PZ_930) OR (N_PZ_953 AND db(11).PIN)));
FDCPE_i2c_ce_gol: FDCPE port map (i2c_ce_gol,i2c_ce_gol_D,clk,U5/local_reset,'0','1'); i2c_ce_gol_D <= ((NOT N_PZ_953 AND i2c_ce_gol) OR (NOT db(1).PIN AND db(0).PIN AND N_PZ_953));
i2c_ce_p <= NOT ((NOT add_p(5) AND add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6)));
i2c_rd <= NOT ((NOT tp2 AND NOT i2c_ce_p));
i2c_reset <= (NOT U5/reset_1 AND NOT U5/reset_2);
i2c_wr <= NOT ((U1/q2 AND NOT U1/q4 AND NOT i2c_ce_p));
iackout <= (iackin AND U3/r8);
FDCPE_U3/r8: FDCPE port map (U3/r8,U3/r8_D,clk,'0',as,'1'); U3/r8_D <= ((N_PZ_1042 AND U3/r7) OR (NOT U3/r7 AND U3/r8));
FDCPE_intrpt_led: FDCPE port map (intrpt_led,NOT ULED1/q1,clk_slow,'0',NOT N_PZ_930,'1');
FTCPE_ULED1/q1: FTCPE port map (ULED1/q1,ULED1/q1_T,clk,ULED1/q3,'0','1'); ULED1/q1_T <= (int_rst AND NOT ULED1/q1);
FDCPE_ULED1/q3: FDCPE port map (ULED1/q3,NOT intrpt_led,clk_slow,NOT N_PZ_930,'0','1');
irq(1) <= (int_rst AND int_lev(0) AND NOT int_lev(1) AND NOT int_lev(2));
irq(2) <= (int_rst AND NOT int_lev(0) AND int_lev(1) AND NOT int_lev(2));
irq(3) <= (int_rst AND int_lev(0) AND int_lev(1) AND NOT int_lev(2));
irq(4) <= (int_rst AND NOT int_lev(0) AND NOT int_lev(1) AND int_lev(2));
irq(5) <= (int_rst AND int_lev(0) AND NOT int_lev(1) AND int_lev(2));
irq(6) <= (int_rst AND NOT int_lev(0) AND int_lev(1) AND int_lev(2));
irq(7) <= (int_rst AND int_lev(0) AND int_lev(1) AND int_lev(2));
ldpreg <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4 AND db(11).PIN);
mrs <= ((U5/local_reset) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4 AND db(13).PIN));
mspare_0 <= NOT ('0');
mspare_1 <= NOT ('0');
mspare_2 <= NOT ('0');
mspare_3 <= NOT ('0');
on_244 <= '0';
prgm_fpga_p(0) <= (NOT prgm_fpga(0) AND NOT N_PZ_966);
FDCPE_prgm_fpga0: FDCPE port map (prgm_fpga(0),prgm_fpga_D(0),clk,'0',U5/_n0041,'1'); prgm_fpga_D(0) <= NOT (((N_PZ_944 AND NOT db(5).PIN) OR (NOT N_PZ_944 AND NOT prgm_fpga(0)) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
U5/cuenta_prgm_0_4)));
FTCPE_U5/cuenta_prgm_0_0: FTCPE port map (U5/cuenta_prgm_0_0,U5/cuenta_prgm_0_0_T,clk,U5/_n0041,'0','1'); U5/cuenta_prgm_0_0_T <= NOT (((N_PZ_944 AND NOT U5/cuenta_prgm_0_0) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
U5/cuenta_prgm_0_4)));
FTCPE_U5/cuenta_prgm_0_1: FTCPE port map (U5/cuenta_prgm_0_1,U5/cuenta_prgm_0_1_T,clk,U5/_n0041,'0','1'); U5/cuenta_prgm_0_1_T <= NOT (((N_PZ_944 AND NOT U5/cuenta_prgm_0_1) OR (NOT N_PZ_944 AND NOT U5/cuenta_prgm_0_0) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_1 AND
U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND U5/cuenta_prgm_0_4)));
FTCPE_U5/cuenta_prgm_0_2: FTCPE port map (U5/cuenta_prgm_0_2,U5/cuenta_prgm_0_2_T,clk,U5/_n0041,'0','1'); U5/cuenta_prgm_0_2_T <= NOT (((N_PZ_944 AND NOT U5/cuenta_prgm_0_2) OR (NOT N_PZ_944 AND NOT U5/cuenta_prgm_0_0) OR (NOT N_PZ_944 AND NOT U5/cuenta_prgm_0_1)
OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_2 AND
U5/cuenta_prgm_0_3 AND U5/cuenta_prgm_0_4)));
FDCPE_U5/cuenta_prgm_0_3: FDCPE port map (U5/cuenta_prgm_0_3,U5/cuenta_prgm_0_3_D,clk,U5/_n0041,'0','1'); U5/cuenta_prgm_0_3_D <= NOT (NOT U5/cuenta_prgm_0_3 XOR ((N_PZ_944 AND U5/cuenta_prgm_0_3) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND NOT U5/cuenta_prgm_0_3)
OR (U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND
U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND NOT U5/cuenta_prgm_0_4)));
FDCPE_U5/cuenta_prgm_0_4: FDCPE port map (U5/cuenta_prgm_0_4,U5/cuenta_prgm_0_4_D,clk,U5/_n0041,'0','1'); U5/cuenta_prgm_0_4_D <= ((NOT N_PZ_944 AND U5/cuenta_prgm_0_4) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3));
U5/_n0041 <= ((evcnt_res AND ena_evres_prgm) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4 AND db(15).PIN AND U5/ena_rst_prgm));
FDCPE_ena_evres_prgm: FDCPE port map (ena_evres_prgm,db(13).PIN,clk,U5/local_reset,'0',N_PZ_944);
db(14) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(6)) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND U5/ena_rst_prgm)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND flash_tdo_p(5) AND N_PZ_957));FDCPE_U5/ena_rst_prgm: FDCPE port map (U5/ena_rst_prgm,db(14).PIN,clk,U5/local_reset,'0',N_PZ_944);
N_PZ_966 <= (evcnt_res AND ena_evres_prgm);
prgm_fpga_p(1) <= (NOT N_PZ_966 AND NOT prgm_fpga(1));
FDCPE_prgm_fpga1: FDCPE port map (prgm_fpga(1),prgm_fpga_D(1),clk,'0',U5/_n0041,'1'); prgm_fpga_D(1) <= NOT (((N_PZ_944 AND NOT db(6).PIN) OR (NOT N_PZ_944 AND NOT prgm_fpga(1)) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
U5/cuenta_prgm_0_4)));
prgm_fpga_p(2) <= (NOT N_PZ_966 AND NOT prgm_fpga(2));
FDCPE_prgm_fpga2: FDCPE port map (prgm_fpga(2),prgm_fpga_D(2),clk,'0',U5/_n0041,'1'); prgm_fpga_D(2) <= NOT (((N_PZ_944 AND NOT db(7).PIN) OR (NOT N_PZ_944 AND NOT prgm_fpga(2)) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
U5/cuenta_prgm_0_4)));
prgm_fpga_p(3) <= (NOT N_PZ_966 AND NOT prgm_fpga(3));
FDCPE_prgm_fpga3: FDCPE port map (prgm_fpga(3),prgm_fpga_D(3),clk,'0',U5/_n0041,'1'); prgm_fpga_D(3) <= NOT (((N_PZ_944 AND NOT db(8).PIN) OR (NOT N_PZ_944 AND NOT prgm_fpga(3)) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
U5/cuenta_prgm_0_4)));
prgm_fpga_p(4) <= (NOT N_PZ_966 AND NOT prgm_fpga(4));
FDCPE_prgm_fpga4: FDCPE port map (prgm_fpga(4),prgm_fpga_D(4),clk,'0',U5/_n0041,'1'); prgm_fpga_D(4) <= NOT (((N_PZ_944 AND NOT db(9).PIN) OR (NOT N_PZ_944 AND NOT prgm_fpga(4)) OR (NOT N_PZ_944 AND U5/cuenta_prgm_0_0 AND U5/cuenta_prgm_0_1 AND U5/cuenta_prgm_0_2 AND U5/cuenta_prgm_0_3 AND
U5/cuenta_prgm_0_4)));
prs <= ((U5/local_reset) OR (U5/ena_evres AND evcnt_res) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND add_p(6) AND U1/q2 AND NOT U1/q4 AND db(15).PIN)
OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND db(12).PIN));
qpll_reset <= NOT (((NOT N_PZ_930) OR (N_PZ_953 AND db(8).PIN)));
reset_p <= NOT ((NOT U5/reset_1 AND NOT U5/reset_2));
FDCPE_sel_tim_clk0: FDCPE port map (sel_tim_clk(0),db(9).PIN,clk,U5/local_reset,'0',sel_tim_clk_CE(0)); sel_tim_clk_CE(0) <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4);
FDCPE_sel_tim_clk1: FDCPE port map (sel_tim_clk(1),db(10).PIN,clk,U5/local_reset,'0',sel_tim_clk_CE(1)); sel_tim_clk_CE(1) <= (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4);
FDCPE_spare_led: FDCPE port map (spare_led,ULED3/q1,clk_slow,NOT N_PZ_930,'0','1');
FTCPE_ULED3/q1: FTCPE port map (ULED3/q1,ULED3/q1_T,clk,ULED3/q3,'0','1'); ULED3/q1_T <= (U1/q2 AND NOT U1/q4 AND NOT ULED3/q1);
FDCPE_ULED3/q3: FDCPE port map (ULED3/q3,spare_led,clk_slow,NOT N_PZ_930,'0','1');
tp3 <= NOT ((NOT U5/reset_1 AND NOT U5/reset_2));
tp4 <= clk;
vspare_0 <= NOT ((NOT U5/s_reset_1 AND NOT U5/s_reset_2));
FDCPE_U5/s_reset_1: FDCPE port map (U5/s_reset_1,U5/s_reset_1_D,clk,'0','0','1'); U5/s_reset_1_D <= ((U5/local_reset) OR (U5/ena_evres AND evcnt_res) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND db(15).PIN));
FDCPE_U5/s_reset_2: FDCPE port map (U5/s_reset_2,U5/s_reset_1,clk,'0','0','1');
vspare_1 <= NOT ('0');
FDCPE_U5/int_vect2: FDCPE port map (U5/int_vect(2),db(10).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(2)); U5/int_vect_CE(2) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_U5/not_sel_tim_reg: FDCPE port map (U5/not_sel_tim_reg,U5/not_sel_tim_reg_D,clk,U5/local_reset,'0','1'); U5/not_sel_tim_reg_D <= NOT (((N_PZ_953 AND NOT db(10).PIN) OR (NOT N_PZ_953 AND NOT U5/not_sel_tim_reg AND sel_tim_p)));
FDCPE_U5/int_vect6: FDCPE port map (U5/int_vect(6),db(14).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(6)); U5/int_vect_CE(6) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_U5/qpll_hasunlock_reg: FDCPE port map (U5/qpll_hasunlock_reg,U5/qpll_hasunlock_reg_D,clk,U5/local_reset,'0','1'); U5/qpll_hasunlock_reg_D <= NOT (((NOT db(6).PIN AND N_PZ_953) OR (NOT N_PZ_953 AND NOT U5/qpll_hasunlock_reg AND qpll_locked)));
FDCPE_U5/gol_notready_reg: FDCPE port map (U5/gol_notready_reg,U5/gol_notready_reg_D,clk,U5/local_reset,'0','1'); U5/gol_notready_reg_D <= NOT (((NOT db(7).PIN AND N_PZ_953) OR (NOT N_PZ_953 AND gol_ready AND NOT U5/gol_notready_reg)));
db(13) <= ((add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND NOT add_p(2) AND NOT ack_int AND U5/int_vect(5)) OR (NOT add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND NOT add_p(3) AND add_p(2) AND NOT ack_int AND ena_evres_prgm)
OR (add_p(1) AND NOT add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND add_p(2) AND NOT ack_int AND N_PZ_957 AND flash_tdo_p(4)));FDCPE_U5/int_vect5: FDCPE port map (U5/int_vect(5),db(13).PIN,clk,U5/local_reset,'0',U5/int_vect_CE(5));
U5/int_vect_CE(5) <= (add_p(1) AND add_p(0) AND NOT add_p(5) AND NOT add_p(4) AND
NOT add_p(3) AND NOT add_p(2) AND NOT brd_sel_16 AND add_p(8) AND add_p(7) AND
add_p(6) AND U1/q2 AND NOT U1/q4 AND NOT int_rst);
FDCPE_U5/tdo_bits0: FDCPE port map (U5/tdo_bits(0),U5/tdo_bits_D(0),clk,U5/local_reset,'0','1'); U5/tdo_bits_D(0) <= ((U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(1)) OR (NOT U5/jtag_shift AND NOT U5/jtag_start AND U5/tdo_bits(0)));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);