library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_misc.all;

entity trclk20 is

port(
clk, reset: in std_logic;
clk20, seu: out std_logic
);
end trclk20;

architecture archi of trclk20 is

signal ff1, ff2, ff3, clk20_i: std_logic;

begin

clk20 <= clk20_i;

clk20_i <=	
	'0' when ff1='0' and ff2='0' else
	ff3 when ff1='0' and ff2='1' else
	ff3 when ff1='1' and ff2='0' else
	'1' when ff1='1' and ff2='1' else
	'0'; --'-';
seu <= ff3 when ff1='0' and ff2='0' else
	'1' when ff1='0' and ff2='1' else
	'1' when ff1='1' and ff2='0' else
	not ff3 when ff1='1' and ff2='1' else
	'0'; --'-';

PFF: process (clk, reset)
begin
	if reset ='0' then
	  ff1 <= '0';
	  ff2 <= '0';
	  ff3 <= '0';
	elsif clk'event and clk='1' then
	  ff1 <= not clk20_i;
	  ff2 <= not clk20_i;
	  ff3 <= not clk20_i;
	end if;
end process PFF;

end archi;
