library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity trcnt2 is

--clock, count enable, reset
port(
clk, cnt_ena, reset: in std_logic;
seu: out std_logic;
q: out std_logic_vector(1 downto 0)
);
end trcnt2;

architecture archi of trcnt2 is

COMPONENT SOFT
   PORT (a_in : IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;

signal q_int, c_1, c_2, c_3, s: std_logic_vector (1 downto 0);
signal q_soft: std_logic_vector (1 downto 0);
begin
q <= q_int;

seu <= s(0) or s(1);

Q_generate: FOR i IN q'range GENERATE
--scnt2: SOFT port map (q_int(i), q(i));
q_int(i) <=	'0' 	when c_1(i)='0' and c_2(i)='0' else
			c_3(i) 	when c_1(i)='0' and c_2(i)='1' else
			c_3(i)	when c_1(i)='1' and c_2(i)='0' else
			'1' 	when c_1(i)='1' and c_2(i)='1' else
			'0'; --'-';
END GENERATE;

SEU_generate: for i in q'range generate
s(i) <= 	c_3(i)	when c_1(i)='0' and c_2(i)='0' else
			'1'		when c_1(i)='0' and c_2(i)='1' else
			'1' 	when c_1(i)='1' and c_2(i)='0' else
		not c_3(i)	when c_1(i)='1' and c_2(i)='1' else
			'0'; --'-';
end generate;

CNT1: process (clk, reset)
begin
	if reset ='0' then
	  c_1 <= (others => '0');
	elsif clk'event and clk='1' then
	  if cnt_ena='1' then
	    c_1 <= c_1 + 1;
	  else
	    c_1 <= q_int;
	  end if;
	end if;
end process CNT1;

CNT2: process (clk, reset)
begin
	if reset ='0' then
	  c_2 <= (others => '0');
	elsif clk'event and clk='1' then
	  if cnt_ena='1' then
	    c_2 <= c_2 + 1;
	  else
	    c_2 <= q_int;
	  end if;
	end if;
end process CNT2;

CNT3: process (clk, reset)
begin
	if reset ='0' then
	  c_3 <= (others => '0');
	elsif clk'event and clk='1' then
	  if cnt_ena='1' then
	    c_3 <= c_3 + 1;
	  else
	    c_3 <= q_int;
	  end if;
	end if;
end process CNT3;

end archi;
