library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_misc.all;

entity trff is

port(
clk, ce, reset, d: in std_logic;
q, seu: out std_logic
);
end trff;

architecture archi of trff is

signal ff1, ff2, ff3, q_i: std_logic;

begin

q <= q_i;
q_i <=	'0' when ff1='0' and ff2='0' else
	ff3 when ff1='0' and ff2='1' else
	ff3 when ff1='1' and ff2='0' else
	'1' when ff1='1' and ff2='1' else
	'0'; --'-';
seu <= ff3 when ff1='0' and ff2='0' else
	'1' when ff1='0' and ff2='1' else
	'1' when ff1='1' and ff2='0' else
	not ff3 when ff1='1' and ff2='1' else
	'0'; --'-';

PFF: process (clk, reset)
begin
	if reset ='0' then
	  ff1 <= '0';
	  ff2 <= '0';
	  ff3 <= '0';
	elsif clk'event and clk='1' then
	  if ce='1' then
	    ff1 <= d;
	    ff2 <= d;
	    ff3 <= d;
	  else
	    ff1 <= q_i;
	    ff2 <= q_i;
	    ff3 <= q_i;
	  end if;
	end if;
end process PFF;

end archi;
