-- MAX+plus II VHDL Template
-- Clearable loadable enablable counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY counter2 IS PORT (
		clear	: IN	STD_LOGIC;
		clk		: IN	STD_LOGIC;
		q		: OUT 	std_logic_vector (4 downto 0)
);
end counter2 ;

ARCHITECTURE a OF counter2 IS
signal q_i : std_logic_vector (4 downto 0);
BEGIN
q <= q_i;

PROCESS (clk, clear)
begin
	if clear = '1' then
		q_i <= (others => '0');
	elsif clk'event and clk= '1' then
		q_i <= q_i + 1 ;
		end if;
	END PROCESS;
END a;

