JDF G
// Created by Project Navigator ver 1.0
PROJECT tim_ttc_apr_v1
DESIGN tim_ttc_apr_v1
DEVFAM xc9500xl
DEVFAMTIME 0
DEVICE xc95288xl
DEVICETIME 0
DEVPKG TQ144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE timttc_1_fit_carlos.vhd
DEPASSOC timttc timttc.ucf
[STATUS-ALL]
timttc.ngcFile=WARNINGS,1221550740
[STRATEGY-LIST]
Normal=True
