### Equations

FDCPE_add0: FDCPE port map (add(0),'0','0',add_CLR(0),add_PRE(0)); add_CLR(0) <= (NOT ttc_sel_p AND NOT add_p(0)); add_PRE(0) <= (NOT ttc_sel_p AND add_p(0));
FDCPE_add1: FDCPE port map (add(1),'0','0',add_CLR(1),add_PRE(1)); add_CLR(1) <= (NOT ttc_sel_p AND NOT add_p(1)); add_PRE(1) <= (NOT ttc_sel_p AND add_p(1));
FDCPE_add2: FDCPE port map (add(2),'0','0',add_CLR(2),add_PRE(2)); add_CLR(2) <= (NOT ttc_sel_p AND NOT add_p(2)); add_PRE(2) <= (NOT ttc_sel_p AND add_p(2));
FDCPE_add3: FDCPE port map (add(3),'0','0',add_CLR(3),add_PRE(3)); add_CLR(3) <= (NOT ttc_sel_p AND NOT add_p(3)); add_PRE(3) <= (NOT ttc_sel_p AND add_p(3));
FDCPE_add4: FDCPE port map (add(4),'0','0',add_CLR(4),add_PRE(4)); add_CLR(4) <= (NOT ttc_sel_p AND NOT add_p(4)); add_PRE(4) <= (NOT ttc_sel_p AND add_p(4));
FDCPE_bcnt_reg0: FDCPE port map (bcnt_reg(0),bcnt(0),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg10: FDCPE port map (bcnt_reg(10),bcnt(10),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg11: FDCPE port map (bcnt_reg(11),bcnt(11),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg1: FDCPE port map (bcnt_reg(1),bcnt(1),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg2: FDCPE port map (bcnt_reg(2),bcnt(2),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg3: FDCPE port map (bcnt_reg(3),bcnt(3),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg4: FDCPE port map (bcnt_reg(4),bcnt(4),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg5: FDCPE port map (bcnt_reg(5),bcnt(5),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg6: FDCPE port map (bcnt_reg(6),bcnt(6),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg7: FDCPE port map (bcnt_reg(7),bcnt(7),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg8: FDCPE port map (bcnt_reg(8),bcnt(8),NOT clk,reset,'0',bcnt_str);
FDCPE_bcnt_reg9: FDCPE port map (bcnt_reg(9),bcnt(9),NOT clk,reset,'0',bcnt_str);
FDCPE_brcst1_reg2: FDCPE port map (brcst1_reg(2),brcst(4),NOT clk,reset,'0',brcst_str_1);
FDCPE_brcst1_reg3: FDCPE port map (brcst1_reg(3),brcst(5),NOT clk,reset,'0',brcst_str_1);
FDCPE_brcst1_reg4: FDCPE port map (brcst1_reg(4),brcst(6),NOT clk,reset,'0',brcst_str_1);
FDCPE_brcst1_reg5: FDCPE port map (brcst1_reg(5),brcst(7),NOT clk,reset,'0',brcst_str_1);
FDCPE_brcst1_reg_0: FDCPE port map (brcst1_reg_0,brcst(2),NOT clk,reset,'0',brcst_str_1);
FDCPE_brcst1_reg_1: FDCPE port map (brcst1_reg_1,brcst(3),NOT clk,reset,'0',brcst_str_1);
FDCPE_brcst2_reg2: FDCPE port map (brcst2_reg(2),brcst(4),NOT clk,reset,'0',brcst_str_2);
FDCPE_brcst2_reg3: FDCPE port map (brcst2_reg(3),brcst(5),NOT clk,reset,'0',brcst_str_2);
FDCPE_brcst2_reg4: FDCPE port map (brcst2_reg(4),brcst(6),NOT clk,reset,'0',brcst_str_2);
FDCPE_brcst2_reg5: FDCPE port map (brcst2_reg(5),brcst(7),NOT clk,reset,'0',brcst_str_2);
FDCPE_brcst2_reg_0: FDCPE port map (brcst2_reg_0,brcst(2),NOT clk,reset,'0',brcst_str_2);
FDCPE_brcst2_reg_1: FDCPE port map (brcst2_reg_1,brcst(3),NOT clk,reset,'0',brcst_str_2);
cmd(0) <= (brcst_str_1 AND brcst(2));
cmd(1) <= rst_counter(6).EXP;
cmd(2) <= (brcst(4) AND brcst_str_1);
cmd(3) <= brcst2_reg_1.EXP;
ttc_on <= '1';
cmy <= '1';
db_I(0) <= NOT (((EXP30_.EXP) OR (EXP31_.EXP) OR (NOT bcnt_reg(0) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT reg_DQ_54(0) AND NOT add(0) AND add(1) AND NOT add(2) AND
NOT add(4))
OR (NOT add(0) AND add(1) AND NOT add(3) AND NOT add(4) AND
NOT qpll_locked)
OR (NOT add(0) AND NOT add(2) AND NOT add(3) AND NOT add(4) AND NOT ttc_ready)));
db(0) <= db_I(0) when db_OE(0) = '1' else 'Z';
db_OE(0) <= (ttc_sel_p AND NOT etr);
db_I(10) <= NOT (((EXP32_.EXP) OR (EXP33_.EXP) OR (NOT bcnt_reg(10) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT reg_DQ_52(10) AND add(0) AND NOT add(2) AND add(3) AND
NOT add(4))
OR (NOT reg_DQ_54(10) AND add(1) AND NOT add(2) AND add(3) AND
NOT add(4))
OR (NOT seu_counter(7) AND NOT add(0) AND add(1) AND NOT add(3) AND
NOT add(4))));
db(10) <= db_I(10) when db_OE(10) = '1' else 'Z';
db_OE(10) <= (ttc_sel_p AND NOT etr);
db_I(11) <= NOT (((EXP48_.EXP) OR (EXP49_.EXP) OR (NOT bcnt_reg(11) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT reg_DQ_4E(11) AND add(1) AND add(2) AND NOT add(3) AND
NOT add(4))
OR (NOT reg_DQ_50(11) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(4))
OR (NOT reg_DQ_54(11) AND NOT add(0) AND add(1) AND NOT add(2) AND
NOT add(4))));
db(11) <= db_I(11) when db_OE(11) = '1' else 'Z';
db_OE(11) <= (ttc_sel_p AND NOT etr);
db_I(12) <= NOT (((EXP65_.EXP) OR (add(1) AND NOT add(2) AND NOT add(4)))); db(12) <= db_I(12) when db_OE(12) = '1' else 'Z'; db_OE(12) <= (ttc_sel_p AND NOT etr);
db_I(13) <= NOT (((EXP20_.EXP) OR (add(1) AND NOT add(2) AND NOT add(4)))); db(13) <= db_I(13) when db_OE(13) = '1' else 'Z'; db_OE(13) <= (ttc_sel_p AND NOT etr);
db_I(14) <= NOT (EXP24_.EXP); db(14) <= db_I(14) when db_OE(14) = '1' else 'Z'; db_OE(14) <= (ttc_sel_p AND NOT etr);
db_I(15) <= NOT (((EXP52_.EXP) OR (NOT iac_subadd(7) AND NOT add(2) AND NOT add(4)) OR (add(1) AND NOT add(2) AND NOT add(4)) OR (add(2) AND NOT add(3) AND NOT add(4)) OR (NOT add(2) AND add(3) AND NOT add(4))));
db(15) <= db_I(15) when db_OE(15) = '1' else 'Z';
db_OE(15) <= (ttc_sel_p AND NOT etr);
db_I(1) <= NOT (((EXP34_.EXP) OR (EXP35_.EXP) OR (NOT qpll_unlocked_reg AND NOT add(0) AND add(1) AND NOT add(3) AND NOT add(4)) OR (NOT bcnt_reg(1) AND add(1) AND NOT add(2) AND NOT add(3) AND
NOT add(4))
OR (NOT reg_DQ_54(1) AND NOT add(0) AND add(1) AND NOT add(2) AND
NOT add(4))
OR (NOT add(0) AND NOT add(2) AND NOT add(3) AND NOT add(4) AND
NOT qpll_locked)));
db(1) <= db_I(1) when db_OE(1) = '1' else 'Z';
db_OE(1) <= (ttc_sel_p AND NOT etr);
db_I(2) <= NOT (((EXP85_.EXP) OR (NOT brcst1_reg_0 AND NOT add(0) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT brcst2_reg_0 AND NOT add(0) AND NOT add(1) AND NOT add(2) AND NOT add(3) AND add(4))
OR (NOT evcntl_reg(2) AND NOT add(0) AND NOT add(1) AND add(2) AND
NOT add(3) AND NOT add(4))
OR (NOT iac_data(2) AND add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND NOT add(4))));
db(2) <= db_I(2) when db_OE(2) = '1' else 'Z';
db_OE(2) <= (ttc_sel_p AND NOT etr);
db_I(3) <= NOT (((EXP46_.EXP) OR (EXP47_.EXP) OR (NOT brcst1_reg_1 AND NOT add(0) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT brcst2_reg_1 AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND add(4))
OR (NOT evcntl_reg(3) AND NOT add(0) AND NOT add(1) AND add(2) AND
NOT add(3) AND NOT add(4))
OR (NOT iac_data(3) AND add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND NOT add(4))));
db(3) <= db_I(3) when db_OE(3) = '1' else 'Z';
db_OE(3) <= (ttc_sel_p AND NOT etr);
db_I(4) <= NOT (((EXP83_.EXP) OR (EXP84_.EXP) OR (NOT brcst1_reg(2) AND NOT add(0) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT brcst2_reg(2) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND add(4))
OR (NOT evcntl_reg(4) AND NOT add(0) AND NOT add(1) AND add(2) AND
NOT add(3) AND NOT add(4))
OR (NOT iac_data(4) AND add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND NOT add(4))));
db(4) <= db_I(4) when db_OE(4) = '1' else 'Z';
db_OE(4) <= (ttc_sel_p AND NOT etr);
db_I(5) <= NOT (((iac_subadd(4).EXP) OR (EXP62_.EXP) OR (NOT brcst1_reg(3) AND NOT add(0) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT brcst2_reg(3) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND add(4))
OR (NOT evcntl_reg(5) AND NOT add(0) AND NOT add(1) AND add(2) AND
NOT add(3) AND NOT add(4))
OR (NOT iac_data(5) AND add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND NOT add(4))));
db(5) <= db_I(5) when db_OE(5) = '1' else 'Z';
db_OE(5) <= (ttc_sel_p AND NOT etr);
db_I(6) <= NOT (((EXP39_.EXP) OR (NOT brcst2_reg(4) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND NOT add(3) AND add(4)) OR (NOT evcntl_reg(6) AND NOT add(0) AND NOT add(1) AND add(2) AND NOT add(3) AND NOT add(4))
OR (NOT iac_data(6) AND add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND NOT add(4))));
db(6) <= db_I(6) when db_OE(6) = '1' else 'Z';
db_OE(6) <= (ttc_sel_p AND NOT etr);
db_I(7) <= NOT (((EXP28_.EXP) OR (EXP29_.EXP) OR (NOT brcst1_reg(5) AND NOT add(0) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT brcst2_reg(5) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND add(4))
OR (NOT evcntl_reg(7) AND NOT add(0) AND NOT add(1) AND add(2) AND
NOT add(3) AND NOT add(4))
OR (NOT iac_data(7) AND add(0) AND NOT add(1) AND NOT add(2) AND
NOT add(3) AND NOT add(4))));
db(7) <= db_I(7) when db_OE(7) = '1' else 'Z';
db_OE(7) <= (ttc_sel_p AND NOT etr);
db_I(8) <= NOT (((EXP78_.EXP) OR (EXP79_.EXP) OR (NOT bcnt_reg(8) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT reg_DQ_50(8) AND NOT add(0) AND NOT add(1) AND add(3) AND
NOT add(4))
OR (NOT reg_DQ_54(8) AND NOT add(0) AND add(1) AND NOT add(2) AND
NOT add(4))
OR (NOT seu_counter(5) AND NOT add(0) AND add(1) AND NOT add(3) AND
NOT add(4))));
db(8) <= db_I(8) when db_OE(8) = '1' else 'Z';
db_OE(8) <= (ttc_sel_p AND NOT etr);
db_I(9) <= NOT (((EXP80_.EXP) OR (EXP81_.EXP) OR (NOT bcnt_reg(9) AND add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4)) OR (NOT reg_DQ_52(9) AND add(0) AND NOT add(2) AND add(3) AND
NOT add(4))
OR (NOT ttc_notready_reg AND NOT add(0) AND NOT add(2) AND NOT add(3) AND
NOT add(4))
OR (NOT seu_counter(6) AND NOT add(0) AND add(1) AND NOT add(3) AND
NOT add(4))));
db(9) <= db_I(9) when db_OE(9) = '1' else 'Z';
db_OE(9) <= (ttc_sel_p AND NOT etr);
FDCPE_dberr_str_reg: FDCPE port map (dberr_str_reg,dberr_str_reg_D,NOT clk,reset,'0'); dberr_str_reg_D <= ((EXP87_.EXP) OR (NOT dberr_str_reg AND add(0) AND NOT dberr_str) OR (NOT dberr_str_reg AND add(1) AND NOT dberr_str) OR (NOT dberr_str_reg AND add(2) AND NOT dberr_str)
OR (NOT dberr_str_reg AND add(3) AND NOT dberr_str));
FDCPE_evcnth_reg0: FDCPE port map (evcnth_reg(0),bcnt(0),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg10: FDCPE port map (evcnth_reg(10),bcnt(10),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg11: FDCPE port map (evcnth_reg(11),bcnt(11),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg1: FDCPE port map (evcnth_reg(1),bcnt(1),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg2: FDCPE port map (evcnth_reg(2),bcnt(2),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg3: FDCPE port map (evcnth_reg(3),bcnt(3),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg4: FDCPE port map (evcnth_reg(4),bcnt(4),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg5: FDCPE port map (evcnth_reg(5),bcnt(5),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg6: FDCPE port map (evcnth_reg(6),bcnt(6),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg7: FDCPE port map (evcnth_reg(7),bcnt(7),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg8: FDCPE port map (evcnth_reg(8),bcnt(8),NOT clk,'0',reset,evcnth_str);
FDCPE_evcnth_reg9: FDCPE port map (evcnth_reg(9),bcnt(9),NOT clk,'0',reset,evcnth_str);
FDCPE_evcntl_reg0: FDCPE port map (evcntl_reg(0),bcnt(0),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg10: FDCPE port map (evcntl_reg(10),bcnt(10),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg11: FDCPE port map (evcntl_reg(11),bcnt(11),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg1: FDCPE port map (evcntl_reg(1),bcnt(1),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg2: FDCPE port map (evcntl_reg(2),bcnt(2),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg3: FDCPE port map (evcntl_reg(3),bcnt(3),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg4: FDCPE port map (evcntl_reg(4),bcnt(4),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg5: FDCPE port map (evcntl_reg(5),bcnt(5),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg6: FDCPE port map (evcntl_reg(6),bcnt(6),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg7: FDCPE port map (evcntl_reg(7),bcnt(7),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg8: FDCPE port map (evcntl_reg(8),bcnt(8),NOT clk,'0',reset,evcntl_str);
FDCPE_evcntl_reg9: FDCPE port map (evcntl_reg(9),bcnt(9),NOT clk,'0',reset,evcntl_str);
i2c_rst <= NOT (((reset) OR (ttc_sel_p AND enw AND NOT add(0) AND NOT add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4) AND db(14).PIN)));
i2c_wr <= NOT enw;
FDCPE_iac_data0: FDCPE port map (iac_data(0),iac_data_D(0),NOT clk,reset,'0'); iac_data_D(0) <= ((EXP57_.EXP) OR (EXP58_.EXP) OR (dout_str AND dout(0) AND NOT add(0)) OR (dout_str AND dout(0) AND add(1))
OR (dout_str AND dout(0) AND add(2))
OR (dout_str AND dout(0) AND add(3)));
FDCPE_iac_data1: FDCPE port map (iac_data(1),iac_data_D(1),NOT clk,reset,'0'); iac_data_D(1) <= ((EXP37_.EXP) OR (dout_str AND dout(1) AND NOT add(0)) OR (dout_str AND dout(1) AND add(1)) OR (dout_str AND dout(1) AND add(2)));
FDCPE_iac_data2: FDCPE port map (iac_data(2),iac_data_D(2),NOT clk,reset,'0'); iac_data_D(2) <= ((EXP40_.EXP) OR (EXP41_.EXP) OR (dout_str AND dout(2) AND NOT add(0)) OR (dout_str AND dout(2) AND add(1))
OR (dout_str AND dout(2) AND add(2))
OR (dout_str AND dout(2) AND add(3)));
FDCPE_iac_data3: FDCPE port map (iac_data(3),iac_data_D(3),NOT clk,reset,'0'); iac_data_D(3) <= ((EXP42_.EXP) OR (EXP43_.EXP) OR (dout_str AND dout(3) AND NOT add(0)) OR (dout_str AND dout(3) AND add(1))
OR (dout_str AND dout(3) AND add(2))
OR (dout_str AND dout(3) AND add(3)));
FDCPE_iac_data4: FDCPE port map (iac_data(4),iac_data_D(4),NOT clk,reset,'0'); iac_data_D(4) <= ((EXP25_.EXP) OR (dout_str AND dout(4) AND NOT add(0)) OR (dout_str AND dout(4) AND add(1)) OR (dout_str AND dout(4) AND add(2)));
FDCPE_iac_data5: FDCPE port map (iac_data(5),iac_data_D(5),NOT clk,reset,'0'); iac_data_D(5) <= ((EXP63_.EXP) OR (dout_str AND dout(5) AND NOT add(0)) OR (dout_str AND dout(5) AND add(1)));
FDCPE_iac_data6: FDCPE port map (iac_data(6),iac_data_D(6),NOT clk,reset,'0'); iac_data_D(6) <= ((EXP44_.EXP) OR (dout_str AND dout(6) AND NOT add(0)) OR (dout_str AND dout(6) AND add(1)) OR (dout_str AND dout(6) AND add(2)));
FDCPE_iac_data7: FDCPE port map (iac_data(7),iac_data_D(7),NOT clk,reset,'0'); iac_data_D(7) <= ((EXP23_.EXP) OR (db_out(14).EXP) OR (dout_str AND dout(7) AND NOT add(0)) OR (dout_str AND dout(7) AND add(1))
OR (dout_str AND dout(7) AND add(2))
OR (dout_str AND dout(7) AND add(3)));
FDCPE_iac_subadd0: FDCPE port map (iac_subadd(0),iac_subadd_D(0),NOT clk,reset,'0'); iac_subadd_D(0) <= ((EXP75_.EXP) OR (EXP76_.EXP) OR (dout_str AND NOT add(0) AND subaddr(0)) OR (dout_str AND add(1) AND subaddr(0))
OR (dout_str AND add(2) AND subaddr(0))
OR (dout_str AND add(3) AND subaddr(0)));
FDCPE_iac_subadd1: FDCPE port map (iac_subadd(1),iac_subadd_D(1),NOT clk,reset,'0'); iac_subadd_D(1) <= ((seu_counter(6)/seu_counter(6)_RSTF.EXP) OR (EXP82_.EXP) OR (dout_str AND NOT add(0) AND subaddr(1)) OR (dout_str AND add(1) AND subaddr(1))
OR (dout_str AND add(2) AND subaddr(1))
OR (dout_str AND add(3) AND subaddr(1)));
FDCPE_iac_subadd2: FDCPE port map (iac_subadd(2),iac_subadd_D(2),NOT clk,reset,'0'); iac_subadd_D(2) <= ((EXP66_.EXP) OR (cmd_3_OBUF.EXP) OR (dout_str AND NOT add(0) AND subaddr(2)) OR (dout_str AND add(1) AND subaddr(2))
OR (dout_str AND add(2) AND subaddr(2))
OR (dout_str AND add(3) AND subaddr(2)));
FDCPE_iac_subadd3: FDCPE port map (iac_subadd(3),iac_subadd_D(3),NOT clk,reset,'0'); iac_subadd_D(3) <= ((EXP69_.EXP) OR (EXP70_.EXP) OR (dout_str AND NOT add(0) AND subaddr(3)) OR (dout_str AND add(1) AND subaddr(3))
OR (dout_str AND add(2) AND subaddr(3))
OR (dout_str AND add(3) AND subaddr(3)));
FDCPE_iac_subadd4: FDCPE port map (iac_subadd(4),iac_subadd_D(4),NOT clk,reset,'0'); iac_subadd_D(4) <= ((EXP61_.EXP) OR (dout_str AND NOT add(0) AND subaddr(4)));
FDCPE_iac_subadd5: FDCPE port map (iac_subadd(5),iac_subadd_D(5),NOT clk,reset,'0'); iac_subadd_D(5) <= ((EXP22_.EXP) OR (dout_str AND NOT add(0) AND subaddr(5)) OR (dout_str AND add(1) AND subaddr(5)));
FDCPE_iac_subadd6: FDCPE port map (iac_subadd(6),iac_subadd_D(6),NOT clk,reset,'0'); iac_subadd_D(6) <= ((EXP18_.EXP) OR (EXP19_.EXP) OR (dout_str AND NOT add(0) AND subaddr(6)) OR (dout_str AND add(1) AND subaddr(6))
OR (dout_str AND add(2) AND subaddr(6))
OR (dout_str AND add(3) AND subaddr(6)));
FDCPE_iac_subadd7: FDCPE port map (iac_subadd(7),iac_subadd_D(7),NOT clk,reset,'0'); iac_subadd_D(7) <= ((EXP68_.EXP) OR (dout_str AND NOT add(0) AND subaddr(7)) OR (dout_str AND add(1) AND subaddr(7)) OR (dout_str AND add(2) AND subaddr(7)));
int_led <= (NOT qpll_error AND NOT sinerr_str AND NOT dberr_str AND qpll_locked AND ttc_ready);
interrupt <= NOT ((NOT qpll_error AND NOT sinerr_str AND NOT dberr_str AND qpll_locked AND ttc_ready));
qpll_reset <= NOT ((ttc_sel_p AND enw AND db(15).PIN AND NOT add(0) AND add(1) AND add(2) AND NOT add(3) AND NOT add(4)));
FDCPE_qpll_unlocked_reg: FDCPE port map (qpll_unlocked_reg,qpll_unlocked_reg_D,NOT clk,reset,'0'); qpll_unlocked_reg_D <= ((EXP27_.EXP) OR (NOT qpll_unlocked_reg AND add(0) AND qpll_locked) OR (NOT qpll_unlocked_reg AND add(1) AND qpll_locked) OR (NOT qpll_unlocked_reg AND add(2) AND qpll_locked));
FDCPE_reg_DQ_4E0: FDCPE port map (reg_DQ_4E(0),dout(0),NOT clk,reset,'0',reg_DQ_4E_CE(0)); reg_DQ_4E_CE(0) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E10: FDCPE port map (reg_DQ_4E(10),dq(2),NOT clk,reset,'0',reg_DQ_4E_CE(10)); reg_DQ_4E_CE(10) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E11: FDCPE port map (reg_DQ_4E(11),dq(3),NOT clk,reset,'0',reg_DQ_4E_CE(11)); reg_DQ_4E_CE(11) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E1: FDCPE port map (reg_DQ_4E(1),dout(1),NOT clk,reset,'0',reg_DQ_4E_CE(1)); reg_DQ_4E_CE(1) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E2: FDCPE port map (reg_DQ_4E(2),dout(2),NOT clk,reset,'0',reg_DQ_4E_CE(2)); reg_DQ_4E_CE(2) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E3: FDCPE port map (reg_DQ_4E(3),dout(3),NOT clk,reset,'0',reg_DQ_4E_CE(3)); reg_DQ_4E_CE(3) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E4: FDCPE port map (reg_DQ_4E(4),dout(4),NOT clk,reset,'0',reg_DQ_4E_CE(4)); reg_DQ_4E_CE(4) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E5: FDCPE port map (reg_DQ_4E(5),dout(5),NOT clk,reset,'0',reg_DQ_4E_CE(5)); reg_DQ_4E_CE(5) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E6: FDCPE port map (reg_DQ_4E(6),dout(6),NOT clk,reset,'0',reg_DQ_4E_CE(6)); reg_DQ_4E_CE(6) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E7: FDCPE port map (reg_DQ_4E(7),dout(7),NOT clk,reset,'0',reg_DQ_4E_CE(7)); reg_DQ_4E_CE(7) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E8: FDCPE port map (reg_DQ_4E(8),dq(0),NOT clk,reset,'0',reg_DQ_4E_CE(8)); reg_DQ_4E_CE(8) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_4E9: FDCPE port map (reg_DQ_4E(9),dq(1),NOT clk,reset,'0',reg_DQ_4E_CE(9)); reg_DQ_4E_CE(9) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_500: FDCPE port map (reg_DQ_50(0),dout(0),NOT clk,reset,'0',reg_DQ_50_CE(0)); reg_DQ_50_CE(0) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_5010: FDCPE port map (reg_DQ_50(10),dq(2),NOT clk,reset,'0',reg_DQ_50_CE(10)); reg_DQ_50_CE(10) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_5011: FDCPE port map (reg_DQ_50(11),dq(3),NOT clk,reset,'0',reg_DQ_50_CE(11)); reg_DQ_50_CE(11) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_501: FDCPE port map (reg_DQ_50(1),dout(1),NOT clk,reset,'0',reg_DQ_50_CE(1)); reg_DQ_50_CE(1) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_502: FDCPE port map (reg_DQ_50(2),dout(2),NOT clk,reset,'0',reg_DQ_50_CE(2)); reg_DQ_50_CE(2) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_503: FDCPE port map (reg_DQ_50(3),dout(3),NOT clk,reset,'0',reg_DQ_50_CE(3)); reg_DQ_50_CE(3) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_504: FDCPE port map (reg_DQ_50(4),dout(4),NOT clk,reset,'0',reg_DQ_50_CE(4)); reg_DQ_50_CE(4) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_505: FDCPE port map (reg_DQ_50(5),dout(5),NOT clk,reset,'0',reg_DQ_50_CE(5)); reg_DQ_50_CE(5) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_506: FDCPE port map (reg_DQ_50(6),dout(6),NOT clk,reset,'0',reg_DQ_50_CE(6)); reg_DQ_50_CE(6) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_507: FDCPE port map (reg_DQ_50(7),dout(7),NOT clk,reset,'0',reg_DQ_50_CE(7)); reg_DQ_50_CE(7) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_508: FDCPE port map (reg_DQ_50(8),dq(0),NOT clk,reset,'0',reg_DQ_50_CE(8)); reg_DQ_50_CE(8) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_509: FDCPE port map (reg_DQ_50(9),dq(1),NOT clk,reset,'0',reg_DQ_50_CE(9)); reg_DQ_50_CE(9) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));
FDCPE_reg_DQ_520: FDCPE port map (reg_DQ_52(0),dout(0),NOT clk,reset,'0',reg_DQ_52_CE(0)); reg_DQ_52_CE(0) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_5210: FDCPE port map (reg_DQ_52(10),dq(2),NOT clk,reset,'0',reg_DQ_52_CE(10)); reg_DQ_52_CE(10) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_5211: FDCPE port map (reg_DQ_52(11),dq(3),NOT clk,reset,'0',reg_DQ_52_CE(11)); reg_DQ_52_CE(11) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_521: FDCPE port map (reg_DQ_52(1),dout(1),NOT clk,reset,'0',reg_DQ_52_CE(1)); reg_DQ_52_CE(1) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_522: FDCPE port map (reg_DQ_52(2),dout(2),NOT clk,reset,'0',reg_DQ_52_CE(2)); reg_DQ_52_CE(2) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_523: FDCPE port map (reg_DQ_52(3),dout(3),NOT clk,reset,'0',reg_DQ_52_CE(3)); reg_DQ_52_CE(3) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_524: FDCPE port map (reg_DQ_52(4),dout(4),NOT clk,reset,'0',reg_DQ_52_CE(4)); reg_DQ_52_CE(4) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_525: FDCPE port map (reg_DQ_52(5),dout(5),NOT clk,reset,'0',reg_DQ_52_CE(5)); reg_DQ_52_CE(5) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_526: FDCPE port map (reg_DQ_52(6),dout(6),NOT clk,reset,'0',reg_DQ_52_CE(6)); reg_DQ_52_CE(6) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_527: FDCPE port map (reg_DQ_52(7),dout(7),NOT clk,reset,'0',reg_DQ_52_CE(7)); reg_DQ_52_CE(7) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_528: FDCPE port map (reg_DQ_52(8),dq(0),NOT clk,reset,'0',reg_DQ_52_CE(8)); reg_DQ_52_CE(8) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FDCPE_reg_DQ_529: FDCPE port map (reg_DQ_52(9),dq(1),NOT clk,reset,'0',reg_DQ_52_CE(9)); reg_DQ_52_CE(9) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));
FTCPE_reg_DQ_540: FTCPE port map (reg_DQ_54(0),reg_DQ_54_T(0),NOT clk,reset,'0'); reg_DQ_54_T(0) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dout(0) AND dq(2) AND NOT dq(3) AND NOT reg_DQ_54(0)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dout(0) AND NOT dq(2) AND
dq(3) AND NOT reg_DQ_54(0))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dout(0) AND dq(2) AND
NOT dq(3) AND reg_DQ_54(0))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dout(0) AND NOT dq(2) AND
dq(3) AND reg_DQ_54(0)));
FTCPE_reg_DQ_5410: FTCPE port map (reg_DQ_54(10),reg_DQ_54_T(10),NOT clk,reset,'0'); reg_DQ_54_T(10) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND NOT reg_DQ_54(10)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
reg_DQ_54(10)));
FTCPE_reg_DQ_5411: FTCPE port map (reg_DQ_54(11),reg_DQ_54_T(11),NOT clk,reset,'0'); reg_DQ_54_T(11) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND reg_DQ_54(11)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT reg_DQ_54(11)));
FTCPE_reg_DQ_541: FTCPE port map (reg_DQ_54(1),reg_DQ_54_T(1),NOT clk,reset,'0'); reg_DQ_54_T(1) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND dout(1) AND NOT reg_DQ_54(1)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
NOT dout(1) AND reg_DQ_54(1))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
dout(1) AND NOT reg_DQ_54(1))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT dout(1) AND reg_DQ_54(1)));
FTCPE_reg_DQ_542: FTCPE port map (reg_DQ_54(2),reg_DQ_54_T(2),NOT clk,reset,'0'); reg_DQ_54_T(2) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND dout(2) AND NOT reg_DQ_54(2)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
NOT dout(2) AND reg_DQ_54(2))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
dout(2) AND NOT reg_DQ_54(2))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT dout(2) AND reg_DQ_54(2)));
FTCPE_reg_DQ_543: FTCPE port map (reg_DQ_54(3),reg_DQ_54_T(3),NOT clk,reset,'0'); reg_DQ_54_T(3) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND dout(3) AND NOT reg_DQ_54(3)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
NOT dout(3) AND reg_DQ_54(3))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
dout(3) AND NOT reg_DQ_54(3))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT dout(3) AND reg_DQ_54(3)));
FTCPE_reg_DQ_544: FTCPE port map (reg_DQ_54(4),reg_DQ_54_T(4),NOT clk,reset,'0'); reg_DQ_54_T(4) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND dout(4) AND NOT reg_DQ_54(4)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
NOT dout(4) AND reg_DQ_54(4))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
dout(4) AND NOT reg_DQ_54(4))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT dout(4) AND reg_DQ_54(4)));
FTCPE_reg_DQ_545: FTCPE port map (reg_DQ_54(5),reg_DQ_54_T(5),NOT clk,reset,'0'); reg_DQ_54_T(5) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND dout(5) AND NOT reg_DQ_54(5)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
NOT dout(5) AND reg_DQ_54(5))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
dout(5) AND NOT reg_DQ_54(5))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT dout(5) AND reg_DQ_54(5)));
FTCPE_reg_DQ_546: FTCPE port map (reg_DQ_54(6),reg_DQ_54_T(6),NOT clk,reset,'0'); reg_DQ_54_T(6) <= ((reg_DQ_56(1).EXP) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND NOT dout(6) AND reg_DQ_54(6)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT dout(6) AND reg_DQ_54(6)));
FTCPE_reg_DQ_547: FTCPE port map (reg_DQ_54(7),reg_DQ_54_T(7),NOT clk,reset,'0'); reg_DQ_54_T(7) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND dout(7) AND NOT reg_DQ_54(7)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
NOT dout(7) AND reg_DQ_54(7))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
dout(7) AND NOT reg_DQ_54(7))
OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
NOT dout(7) AND reg_DQ_54(7)));
FTCPE_reg_DQ_548: FTCPE port map (reg_DQ_54(8),reg_DQ_54_T(8),NOT clk,reset,'0'); reg_DQ_54_T(8) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND reg_DQ_54(8)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
reg_DQ_54(8)));
FTCPE_reg_DQ_549: FTCPE port map (reg_DQ_54(9),reg_DQ_54_T(9),NOT clk,reset,'0'); reg_DQ_54_T(9) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND reg_DQ_54(9)) OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
reg_DQ_54(9)));
FDCPE_reg_DQ_560: FDCPE port map (reg_DQ_56(0),dout(0),NOT clk,reset,'0',reg_DQ_56_CE(0)); reg_DQ_56_CE(0) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_561: FDCPE port map (reg_DQ_56(1),dout(1),NOT clk,reset,'0',reg_DQ_56_CE(1)); reg_DQ_56_CE(1) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_562: FDCPE port map (reg_DQ_56(2),dout(2),NOT clk,reset,'0',reg_DQ_56_CE(2)); reg_DQ_56_CE(2) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_563: FDCPE port map (reg_DQ_56(3),dout(3),NOT clk,reset,'0',reg_DQ_56_CE(3)); reg_DQ_56_CE(3) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_564: FDCPE port map (reg_DQ_56(4),dout(4),NOT clk,reset,'0',reg_DQ_56_CE(4)); reg_DQ_56_CE(4) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_565: FDCPE port map (reg_DQ_56(5),dout(5),NOT clk,reset,'0',reg_DQ_56_CE(5)); reg_DQ_56_CE(5) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_566: FDCPE port map (reg_DQ_56(6),dout(6),NOT clk,reset,'0',reg_DQ_56_CE(6)); reg_DQ_56_CE(6) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_567: FDCPE port map (reg_DQ_56(7),dout(7),NOT clk,reset,'0',reg_DQ_56_CE(7)); reg_DQ_56_CE(7) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_580: FDCPE port map (reg_DQ_58(0),dout(0),NOT clk,reset,'0',reg_DQ_58_CE(0)); reg_DQ_58_CE(0) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_581: FDCPE port map (reg_DQ_58(1),dout(1),NOT clk,reset,'0',reg_DQ_58_CE(1)); reg_DQ_58_CE(1) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_582: FDCPE port map (reg_DQ_58(2),dout(2),NOT clk,reset,'0',reg_DQ_58_CE(2)); reg_DQ_58_CE(2) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_583: FDCPE port map (reg_DQ_58(3),dout(3),NOT clk,reset,'0',reg_DQ_58_CE(3)); reg_DQ_58_CE(3) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_584: FDCPE port map (reg_DQ_58(4),dout(4),NOT clk,reset,'0',reg_DQ_58_CE(4)); reg_DQ_58_CE(4) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_585: FDCPE port map (reg_DQ_58(5),dout(5),NOT clk,reset,'0',reg_DQ_58_CE(5)); reg_DQ_58_CE(5) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_586: FDCPE port map (reg_DQ_58(6),dout(6),NOT clk,reset,'0',reg_DQ_58_CE(6)); reg_DQ_58_CE(6) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reg_DQ_587: FDCPE port map (reg_DQ_58(7),dout(7),NOT clk,reset,'0',reg_DQ_58_CE(7)); reg_DQ_58_CE(7) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));
FDCPE_reset: FDCPE port map (reset,reset_p,NOT clk,'0','0');
FDCPE_reset_b: FDCPE port map (reset_b,reset_b_D,clk,'0',reset); reset_b_D <= ((EXP50_.EXP) OR (EXP51_.EXP) OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
rst_counter(10) AND add(0))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
rst_counter(10) AND add(1))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
rst_counter(10) AND add(2))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
rst_counter(10) AND add(3)));
FTCPE_rst_counter0: FTCPE port map (rst_counter(0),rst_counter_T(0),clk,'0',reset); rst_counter_T(0) <= ((EXP71_.EXP) OR (ttc_sel_p AND enw AND db(15).PIN AND NOT rst_counter(0) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
rst_counter(10) AND add(0))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
rst_counter(10) AND add(1))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
rst_counter(10) AND add(2)));
FTCPE_rst_counter10: FTCPE port map (rst_counter(10),rst_counter_T(10),clk,'0',reset); rst_counter_T(10) <= ((spare_OBUF$BUF0.EXP) OR (ttc_sel_p AND enw AND db(15).PIN AND rst_counter(10) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
NOT rst_counter(10) AND add(0))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
NOT rst_counter(10) AND add(1))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
NOT rst_counter(10) AND add(2)));
FDCPE_rst_counter1: FDCPE port map (rst_counter(1),rst_counter_D(1),clk,'0',reset); rst_counter_D(1) <= ((brcst1_reg_0.EXP) OR (tp2_OBUF$BUF0.EXP) OR (NOT rst_counter(0) AND NOT rst_counter(1)) OR (rst_counter(0) AND rst_counter(1) AND NOT rst_counter(2))
OR (rst_counter(0) AND rst_counter(1) AND NOT rst_counter(3))
OR (rst_counter(0) AND rst_counter(1) AND NOT rst_counter(4)));
FDCPE_rst_counter2: FDCPE port map (rst_counter(2),rst_counter_D(2),clk,'0',reset); rst_counter_D(2) <= ((EXP56_.EXP) OR (brcst1_reg_1.EXP) OR (NOT rst_counter(0) AND NOT rst_counter(2)) OR (NOT rst_counter(1) AND NOT rst_counter(2))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
NOT rst_counter(3))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
NOT rst_counter(4)));
FDCPE_rst_counter3: FDCPE port map (rst_counter(3),rst_counter_D(3),clk,'0',reset); rst_counter_D(3) <= ((brcst1_reg(2).EXP) OR (EXP55_.EXP) OR (NOT rst_counter(0) AND NOT rst_counter(3)) OR (NOT rst_counter(1) AND NOT rst_counter(3))
OR (NOT rst_counter(2) AND NOT rst_counter(3))
OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
rst_counter(3) AND NOT rst_counter(4)));
FDCPE_rst_counter4: FDCPE port map (rst_counter(4),rst_counter_D(4),clk,'0',reset); rst_counter_D(4) <= ((cmd_1_OBUF.EXP) OR (rst_counter(5).EXP) OR (NOT rst_counter(0) AND NOT rst_counter(4)) OR (NOT rst_counter(1) AND NOT rst_counter(4))
OR (NOT rst_counter(2) AND NOT rst_counter(4))
OR (NOT rst_counter(3) AND NOT rst_counter(4)));
FDCPE_rst_counter5: FDCPE port map (rst_counter(5),rst_counter_D(5),clk,'0',reset); rst_counter_D(5) <= ((EXP54_.EXP) OR (NOT rst_counter(0) AND NOT rst_counter(5)) OR (NOT rst_counter(1) AND NOT rst_counter(5)));
FDCPE_rst_counter6: FDCPE port map (rst_counter(6),rst_counter_D(6),clk,'0',reset); rst_counter_D(6) <= ((EXP53_.EXP) OR (NOT rst_counter(0) AND NOT rst_counter(6)) OR (NOT rst_counter(1) AND NOT rst_counter(6)) OR (NOT rst_counter(2) AND NOT rst_counter(6)));
FDCPE_rst_counter7: FDCPE port map (rst_counter(7),rst_counter_D(7),clk,'0',reset); rst_counter_D(7) <= ((seu_counter(7).EXP) OR (seu_counter(6).EXP) OR (NOT rst_counter(0) AND NOT rst_counter(7)) OR (NOT rst_counter(1) AND NOT rst_counter(7))
OR (NOT rst_counter(2) AND NOT rst_counter(7))
OR (NOT rst_counter(3) AND NOT rst_counter(7)));
FDCPE_rst_counter8: FDCPE port map (rst_counter(8),rst_counter_D(8),clk,'0',reset); rst_counter_D(8) <= ((rst_counter(9).EXP) OR (seu_counter(0).EXP) OR (NOT rst_counter(0) AND NOT rst_counter(8)) OR (NOT rst_counter(1) AND NOT rst_counter(8))
OR (NOT rst_counter(2) AND NOT rst_counter(8))
OR (NOT rst_counter(3) AND NOT rst_counter(8)));
FTCPE_rst_counter9: FTCPE port map (rst_counter(9),rst_counter_T(9),clk,'0',reset); rst_counter_T(9) <= ((EXP73_.EXP) OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
NOT rst_counter(10)));
FTCPE_seu_counter0: FTCPE port map (seu_counter(0),'1',qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
FTCPE_seu_counter1: FTCPE port map (seu_counter(1),seu_counter(0),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
FTCPE_seu_counter2: FTCPE port map (seu_counter(2),seu_counter_T(2),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0'); seu_counter_T(2) <= (seu_counter(0) AND seu_counter(1));
FTCPE_seu_counter3: FTCPE port map (seu_counter(3),seu_counter_T(3),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0'); seu_counter_T(3) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2));
FTCPE_seu_counter4: FTCPE port map (seu_counter(4),seu_counter_T(4),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0'); seu_counter_T(4) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2) AND seu_counter(3));
FTCPE_seu_counter5: FTCPE port map (seu_counter(5),seu_counter_T(5),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0'); seu_counter_T(5) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2) AND seu_counter(3) AND seu_counter(4));
FTCPE_seu_counter6: FTCPE port map (seu_counter(6),seu_counter(5).EXP,qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
seu_counter(6)/seu_counter(6)_RSTF <= int_led_OBUF.EXP;
FTCPE_seu_counter7: FTCPE port map (seu_counter(7),seu_counter_T(7),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0'); seu_counter_T(7) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2) AND seu_counter(3) AND seu_counter(4) AND seu_counter(5) AND seu_counter(6));
FDCPE_sinerr_str_reg: FDCPE port map (sinerr_str_reg,sinerr_str_reg_D,NOT clk,reset,'0'); sinerr_str_reg_D <= ((EXP59_.EXP) OR (NOT sinerr_str_reg AND add(0) AND NOT sinerr_str) OR (NOT sinerr_str_reg AND add(1) AND NOT sinerr_str) OR (NOT sinerr_str_reg AND add(2) AND NOT sinerr_str)
OR (NOT sinerr_str_reg AND add(3) AND NOT sinerr_str));
spare <= '0';
on_245 <= seu_counter(1).EXP;
tp1 <= etr;
i2c_rd <= etr;
tp2 <= brcst1_reg(3).EXP;
tp3 <= brcst_str_2;
FDCPE_ttc_notready_reg: FDCPE port map (ttc_notready_reg,ttc_notready_reg_D,NOT clk,reset,'0'); ttc_notready_reg_D <= ((EXP74_.EXP) OR (NOT ttc_notready_reg AND add(0) AND ttc_ready) OR (NOT ttc_notready_reg AND add(1) AND ttc_ready) OR (NOT ttc_notready_reg AND add(2) AND ttc_ready));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);