    cpldfit:  version G.35                              Xilinx Inc.
                                      Fitter Report
    Design Name: timttc                              Date:  9-16-2008,  9:39AM
    Device Used: XC95288XL-6-TQ144
    Fitting Status: Successful

    ****************************  Resource Summary  ****************************

    Macrocells     Product Terms    Registers      Pins           Function Block
    Used           Used             Used           Used           Inputs Used
    192/288 ( 67%) 1023/1440 ( 71%) 158/288 ( 55%) 94 /117 ( 80%) 455/864 ( 53%)

    PIN RESOURCES:

    Signal Type    Required     Mapped  |  Pin Type            Used   Remaining
    ------------------------------------|---------------------------------------
    Input         :   58          58    |  I/O              :    87       22
    Output        :   18          18    |  GCK/IO           :     3        0
    Bidirectional :   16          16    |  GTS/IO           :     3        1
    GCK           :    2           2    |  GSR/IO           :     1        0
    GTS           :    0           0    |
    GSR           :    0           0    |
                     ----        ----
            Total     94          94

    MACROCELL RESOURCES:

    Total Macrocells Available                   288
    Registered Macrocells                        158
    Non-registered Macrocell driving I/O          33

    GLOBAL RESOURCES:

    Signal 'clk' mapped onto global clock net GCK1.
    Signal 'qpll_error' mapped onto global clock net GCK2.
    Global output enable net(s) unused.
    Global set/reset net(s) unused.

    POWER DATA:

    There are 192 macrocells in high performance mode (MCHP).
    There are 0 macrocells in low power mode (MCLP).
    There are a total of 192 macrocells used (MC).

    End of Resource Summary
    *************** Summary of Required Resources ******************

    ** LOGIC **
    Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
    Name                Pt      Used            Mode Rate #    Type      Use       State
    add<0>              2       2       FB15_18 STD            (b)       (b)       RESET
    add<1>              2       2       FB15_17 STD       88   I/O       I         RESET
    add<2>              2       2       FB15_16 STD            (b)       (b)       RESET
    add<3>              2       2       FB15_15 STD       87   I/O       I         RESET
    add<4>              2       2       FB15_14 STD       86   I/O       I         RESET
    bcnt_reg<0>         3       3       FB3_18  STD            (b)       (b)       RESET
    bcnt_reg<10>        3       3       FB3_17  STD            (b)       (b)       RESET
    bcnt_reg<11>        3       3       FB3_16  STD            (b)       (b)       RESET
    bcnt_reg<1>         3       3       FB3_15  STD       33   I/O       (b)       RESET
    bcnt_reg<2>         3       3       FB3_14  STD       32   GCK/I/O   GCK/I     RESET
    bcnt_reg<3>         3       3       FB3_13  STD            (b)       (b)       RESET
    bcnt_reg<4>         3       3       FB3_12  STD       31   I/O       (b)       RESET
    bcnt_reg<5>         3       3       FB3_11  STD            (b)       (b)       RESET
    bcnt_reg<6>         3       3       FB3_10  STD       30   GCK/I/O   GCK       RESET
    bcnt_reg<7>         3       3       FB3_9   STD            (b)       (b)       RESET
    bcnt_reg<8>         3       3       FB13_18 STD            (b)       (b)       RESET
    bcnt_reg<9>         3       3       FB13_17 STD       78   I/O       I         RESET
    brcst1_reg<2>       3       3       FB9_13  STD            (b)       (b)       RESET
    brcst1_reg<3>       3       3       FB9_4   STD            (b)       (b)       RESET
    brcst1_reg<4>       3       3       FB11_11 STD       66   I/O       I         RESET
    brcst1_reg<5>       3       3       FB11_18 STD            (b)       (b)       RESET
    brcst1_reg_0        3       3       FB9_1   STD            (b)       (b)       RESET
    brcst1_reg_1        3       3       FB9_18  STD            (b)       (b)       RESET
    brcst2_reg<2>       3       3       FB11_9  STD            (b)       (b)       RESET
    brcst2_reg<3>       3       3       FB11_8  STD            (b)       (b)       RESET
    brcst2_reg<4>       3       3       FB11_7  STD            (b)       (b)       RESET
    brcst2_reg<5>       3       3       FB11_6  STD            (b)       (b)       RESET
    brcst2_reg_0        3       3       FB11_5  STD       61   I/O       I         RESET
    brcst2_reg_1        3       3       FB11_4  STD            (b)       (b)       RESET
    cmd<0>              1       2       FB9_5   STD  FAST 52   I/O       O
    cmd<1>              1       2       FB9_8   STD  FAST 54   I/O       O
    cmd<2>              1       2       FB9_12  STD  FAST 57   I/O       O
    cmd<3>              1       2       FB11_3  STD  FAST 60   I/O       O
    cmy                 0       0       FB11_10 STD  FAST 64   I/O       O
    db<0>               15      19      FB2_5   STD  FAST 11   I/O       I/O
    db<10>              14      16      FB2_12  STD  FAST 15   I/O       I/O
    db<11>              11      15      FB5_10  STD  FAST 39   I/O       I/O
    db<12>              7       8       FB10_17 STD  FAST 129  I/O       I/O
    db<13>              7       8       FB1_6   STD  FAST 21   I/O       I/O
    db<14>              7       8       FB1_12  STD  FAST 24   I/O       I/O
    db<15>              7       8       FB5_17  STD  FAST 44   I/O       I/O
    db<1>               15      19      FB2_17  STD  FAST 19   I/O       I/O
    db<2>               15      21      FB16_8  STD  FAST 95   I/O       I/O
    db<3>               15      21      FB5_5   STD  FAST 35   I/O       I/O
    db<4>               15      21      FB16_6  STD  FAST 94   I/O       I/O
    db<5>               15      21      FB10_12 STD  FAST 126  I/O       I/O
    db<6>               15      21      FB4_6   STD  FAST 4    I/O       I/O
    db<7>               15      21      FB2_2   STD  FAST 9    I/O       I/O
    db<8>               13      16      FB14_8  STD  FAST 103  I/O       I/O
    db<9>               14      17      FB14_11 STD  FAST 105  I/O       I/O
    dberr_str_reg       9       11      FB16_18 STD            (b)       (b)       RESET
    evcnth_reg<0>       3       3       FB13_16 STD            (b)       (b)       RESET
    evcnth_reg<10>      3       3       FB13_15 STD       77   I/O       I         RESET
    evcnth_reg<11>      3       3       FB13_14 STD       76   I/O       I         RESET
    evcnth_reg<1>       3       3       FB13_13 STD            (b)       (b)       RESET
    evcnth_reg<2>       3       3       FB13_12 STD            (b)       (b)       RESET
    evcnth_reg<3>       3       3       FB13_11 STD       75   I/O       I         RESET
    evcnth_reg<4>       3       3       FB13_10 STD            (b)       (b)       RESET
    evcnth_reg<5>       3       3       FB13_9  STD            (b)       (b)       RESET
    evcnth_reg<6>       3       3       FB13_8  STD       74   I/O       (b)       RESET
    evcnth_reg<7>       3       3       FB13_7  STD            (b)       (b)       RESET
    evcnth_reg<8>       3       3       FB13_6  STD            (b)       (b)       RESET
    evcnth_reg<9>       3       3       FB13_5  STD            (b)       (b)       RESET
    evcntl_reg<0>       3       3       FB13_4  STD            (b)       (b)       RESET
    evcntl_reg<10>      3       3       FB13_3  STD            (b)       (b)       RESET
    evcntl_reg<11>      3       3       FB13_2  STD       71   I/O       I         RESET
    evcntl_reg<1>       3       3       FB13_1  STD            (b)       (b)       RESET
    evcntl_reg<2>       3       3       FB15_13 STD            (b)       (b)       RESET
    evcntl_reg<3>       3       3       FB15_12 STD       85   I/O       (b)       RESET
    evcntl_reg<4>       3       3       FB15_11 STD       83   I/O       I         RESET
    evcntl_reg<5>       3       3       FB15_10 STD       82   I/O       I         RESET
    evcntl_reg<6>       3       3       FB15_9  STD            (b)       (b)       RESET
    evcntl_reg<7>       3       3       FB15_8  STD       81   I/O       I         RESET
    evcntl_reg<8>       3       3       FB15_7  STD            (b)       (b)       RESET
    evcntl_reg<9>       3       3       FB15_6  STD            (b)       (b)       RESET
    i2c_rd              1       1       FB1_17  STD  FAST 27   I/O       O
    i2c_rst             2       9       FB5_2   STD  FAST 34   I/O       O
    i2c_wr              1       1       FB7_15  STD  FAST 49   I/O       O
    iac_data<0>         16      12      FB10_2  STD       117  I/O       (b)       RESET
    iac_data<1>         16      12      FB4_3   STD            (b)       (b)       RESET
    iac_data<2>         16      12      FB4_8   STD       5    GTS/I/O   I         RESET
    iac_data<3>         16      12      FB4_11  STD            (b)       (b)       RESET
    iac_data<4>         16      12      FB1_14  STD       25   I/O       I         RESET
    iac_data<5>         16      12      FB10_14 STD       128  I/O       I         RESET
    iac_data<6>         16      12      FB4_13  STD            (b)       (b)       RESET
    iac_data<7>         16      12      FB1_11  STD            (b)       (b)       RESET
    iac_subadd<0>       16      12      FB14_3  STD       100  I/O       (b)       RESET
    iac_subadd<1>       16      12      FB14_16 STD            (b)       (b)       RESET
    iac_subadd<2>       16      12      FB11_2  STD            (b)       (b)       RESET
    iac_subadd<3>       16      12      FB11_16 STD            (b)       (b)       RESET
    iac_subadd<4>       16      12      FB10_11 STD       125  I/O       I         RESET
    iac_subadd<5>       16      12      FB1_9   STD            (b)       (b)       RESET
    iac_subadd<6>       16      12      FB1_3   STD            (b)       (b)       RESET
    iac_subadd<7>       16      12      FB11_14 STD       69   I/O       (b)       RESET
    int_led             1       5       FB14_14 STD  FAST 106  I/O       O
    interrupt           1       5       FB12_5  STD  FAST 112  I/O       O
    on_245              1       0       FB12_10 STD  FAST 115  I/O       O
    qpll_reset          1       8       FB5_12  STD  FAST 40   I/O       O
    qpll_unlocked_reg   9       11      FB1_1   STD            (b)       (b)       RESET
    reg_DQ_4E<0>        3       6       FB7_18  STD            (b)       (b)       RESET
    reg_DQ_4E<10>       3       6       FB7_17  STD            (b)       (b)       RESET
    reg_DQ_4E<11>       3       5       FB8_18  STD            (b)       (b)       RESET
    reg_DQ_4E<1>        3       6       FB8_17  STD            (b)       (b)       RESET
    reg_DQ_4E<2>        3       6       FB8_16  STD            (b)       (b)       RESET
    reg_DQ_4E<3>        3       6       FB8_15  STD            (b)       (b)       RESET
    reg_DQ_4E<4>        3       6       FB8_14  STD            (b)       (b)       RESET
    reg_DQ_4E<5>        3       6       FB7_16  STD            (b)       (b)       RESET
    reg_DQ_4E<6>        3       6       FB7_14  STD            (b)       (b)       RESET
    reg_DQ_4E<7>        3       6       FB8_13  STD            (b)       (b)       RESET
    reg_DQ_4E<8>        3       5       FB3_8   STD            (b)       (b)       RESET
    reg_DQ_4E<9>        3       5       FB3_7   STD            (b)       (b)       RESET
    reg_DQ_50<0>        3       6       FB7_13  STD            (b)       (b)       RESET
    reg_DQ_50<10>       3       6       FB7_12  STD       48   I/O       I         RESET
    reg_DQ_50<11>       3       5       FB3_6   STD            (b)       (b)       RESET
    reg_DQ_50<1>        3       6       FB8_12  STD            (b)       (b)       RESET
    reg_DQ_50<2>        3       6       FB8_11  STD            (b)       (b)       RESET
    reg_DQ_50<3>        3       6       FB8_10  STD       134  I/O       I         RESET
    reg_DQ_50<4>        3       6       FB8_9   STD            (b)       (b)       RESET
    reg_DQ_50<5>        3       6       FB7_11  STD            (b)       (b)       RESET
    reg_DQ_50<6>        3       6       FB7_10  STD            (b)       (b)       RESET
    reg_DQ_50<7>        3       6       FB8_8   STD       133  I/O       (b)       RESET
    reg_DQ_50<8>        3       5       FB3_5   STD            (b)       (b)       RESET
    reg_DQ_50<9>        3       5       FB3_4   STD            (b)       (b)       RESET
    reg_DQ_52<0>        3       6       FB8_7   STD            (b)       (b)       RESET
    reg_DQ_52<10>       3       6       FB7_9   STD            (b)       (b)       RESET
    reg_DQ_52<11>       3       5       FB3_3   STD            (b)       (b)       RESET
    reg_DQ_52<1>        3       6       FB8_6   STD            (b)       (b)       RESET
    reg_DQ_52<2>        3       6       FB8_4   STD            (b)       (b)       RESET
    reg_DQ_52<3>        3       6       FB8_3   STD       131  I/O       I         RESET
    reg_DQ_52<4>        3       6       FB8_2   STD       130  I/O       I         RESET
    reg_DQ_52<5>        3       6       FB7_8   STD            (b)       (b)       RESET
    reg_DQ_52<6>        3       6       FB7_7   STD            (b)       (b)       RESET
    reg_DQ_52<7>        3       6       FB8_1   STD            (b)       (b)       RESET
    reg_DQ_52<8>        3       5       FB3_2   STD       28   I/O       I         RESET
    reg_DQ_52<9>        3       5       FB3_1   STD            (b)       (b)       RESET
    reg_DQ_54<0>        5       8       FB6_18  STD            (b)       (b)       RESET
    reg_DQ_54<10>       3       7       FB6_12  STD            (b)       (b)       RESET
    reg_DQ_54<11>       3       7       FB6_11  STD            (b)       (b)       RESET
    reg_DQ_54<1>        5       8       FB6_17  STD            (b)       (b)       RESET
    reg_DQ_54<2>        5       8       FB6_16  STD            (b)       (b)       RESET
    reg_DQ_54<3>        5       8       FB6_15  STD       143  GSR/I/O   I         RESET
    reg_DQ_54<4>        5       8       FB6_14  STD       142  I/O       (b)       RESET
    reg_DQ_54<5>        5       8       FB10_5  STD       119  I/O       (b)       RESET
    reg_DQ_54<6>        5       8       FB4_16  STD            (b)       (b)       RESET
    reg_DQ_54<7>        5       8       FB6_13  STD            (b)       (b)       RESET
    reg_DQ_54<8>        3       7       FB7_6   STD            (b)       (b)       RESET
    reg_DQ_54<9>        3       7       FB7_5   STD       46   I/O       I         RESET
    reg_DQ_56<0>        3       7       FB10_4  STD            (b)       (b)       RESET
    reg_DQ_56<1>        3       7       FB4_17  STD            (b)       (b)       RESET
    reg_DQ_56<2>        3       7       FB4_18  STD            (b)       (b)       RESET
    reg_DQ_56<3>        3       7       FB6_10  STD       140  I/O       I         RESET
    reg_DQ_56<4>        3       7       FB6_9   STD            (b)       (b)       RESET
    reg_DQ_56<5>        3       7       FB7_4   STD            (b)       (b)       RESET
    reg_DQ_56<6>        3       7       FB7_3   STD       45   I/O       (b)       RESET
    reg_DQ_56<7>        3       7       FB6_8   STD       139  I/O       I         RESET
    reg_DQ_58<0>        3       7       FB6_7   STD            (b)       (b)       RESET
    reg_DQ_58<1>        3       7       FB6_5   STD       137  I/O       I         RESET
    reg_DQ_58<2>        3       7       FB6_4   STD            (b)       (b)       RESET
    reg_DQ_58<3>        3       7       FB6_3   STD       136  I/O       I         RESET
    reg_DQ_58<4>        3       7       FB6_2   STD       135  I/O       I         RESET
    reg_DQ_58<5>        3       7       FB7_2   STD            (b)       (b)       RESET
    reg_DQ_58<6>        3       7       FB7_1   STD            (b)       (b)       RESET
    reg_DQ_58<7>        3       7       FB6_1   STD            (b)       (b)       RESET
    reset               1       1       FB15_5  STD            (b)       (b)       RESET
    reset_b             9       20      FB5_15  STD  FAST 43   I/O       O         RESET
    rst_counter<0>      10      20      FB12_13 STD            (b)       (b)       RESET
    rst_counter<10>     10      20      FB12_11 STD            (b)       (b)       RESET
    rst_counter<1>      12      20      FB9_2   STD       50   I/O       (b)       RESET
    rst_counter<2>      12      20      FB9_17  STD       59   I/O       I         RESET
    rst_counter<3>      12      20      FB9_14  STD       58   I/O       I         RESET
    rst_counter<4>      12      20      FB9_9   STD            (b)       (b)       RESET
    rst_counter<5>      12      20      FB9_10  STD            (b)       (b)       RESET
    rst_counter<6>      12      20      FB9_7   STD            (b)       (b)       RESET
    rst_counter<7>      12      20      FB12_2  STD       110  I/O       I         RESET
    rst_counter<8>      12      20      FB12_17 STD            (b)       (b)       RESET
    rst_counter<9>      11      20      FB12_16 STD            (b)       (b)       RESET
    seu_counter<0>      1       1       FB12_18 STD            (b)       (b)       RESET
    seu_counter<1>      2       2       FB12_9  STD            (b)       (b)       RESET
    seu_counter<2>      2       3       FB12_8  STD       113  I/O       I         RESET
    seu_counter<3>      2       4       FB12_7  STD            (b)       (b)       RESET
    seu_counter<4>      2       5       FB12_6  STD            (b)       (b)       RESET
    seu_counter<5>      2       6       FB12_4  STD            (b)       (b)       RESET
    seu_counter<6>      2       7       FB12_3  STD       111  I/O       I         RESET
    seu_counter<6>/seu_counter<6>_RSTF                    2       9       FB14_15 STD       107  I/O       I
    seu_counter<7>      2       8       FB12_1  STD            (b)       (b)       RESET
    sinerr_str_reg      9       11      FB10_7  STD            (b)       (b)       RESET
    spare               0       0       FB2_14  STD  FAST 16   I/O       O
    tp1                 1       1       FB8_5   STD  FAST 132  I/O       O
    tp2                 1       1       FB9_3   STD  FAST 51   I/O       O
    tp3                 1       1       FB6_6   STD  FAST 138  I/O       O
    ttc_notready_reg    9       11      FB14_18 STD            (b)       (b)       RESET
    ttc_on              0       0       FB10_8  STD  FAST 121  I/O       O

    ** INPUTS **
    Signal                              Loc               Pin  Pin       Pin
    Name                                                  #    Type      Use
    add_p<0>                            FB6_5             137  I/O       I
    add_p<1>                            FB10_6            120  I/O       I
    add_p<2>                            FB15_15           87   I/O       I
    add_p<3>                            FB6_10            140  I/O       I
    add_p<4>                            FB15_11           83   I/O       I
    bcnt<0>                             FB12_3            111  I/O       I
    bcnt<10>                            FB2_10            14   I/O       I
    bcnt<11>                            FB4_2             2    GTS/I/O   I
    bcnt<1>                             FB9_14            58   I/O       I
    bcnt<2>                             FB16_11           97   I/O       I
    bcnt<3>                             FB12_8            113  I/O       I
    bcnt<4>                             FB7_5             46   I/O       I
    bcnt<5>                             FB13_15           77   I/O       I
    bcnt<6>                             FB13_17           78   I/O       I
    bcnt<7>                             FB12_12           116  I/O       I
    bcnt<8>                             FB10_14           128  I/O       I
    bcnt<9>                             FB13_2            71   I/O       I
    bcnt_str                            FB14_15           107  I/O       I
    brcst<2>                            FB10_3            118  I/O       I
    brcst<3>                            FB14_6            102  I/O       I
    brcst<4>                            FB13_14           76   I/O       I
    brcst<5>                            FB6_3             136  I/O       I
    brcst<6>                            FB15_10           82   I/O       I
    brcst<7>                            FB16_10           96   I/O       I
    brcst_str_1                         FB4_8             5    GTS/I/O   I
    brcst_str_2                         FB11_11           66   I/O       I
    clk                                 FB3_10            30   GCK/I/O   GCK
    dberr_str                           FB15_8            81   I/O       I
    dout<0>                             FB12_2            110  I/O       I
    dout<1>                             FB11_5            61   I/O       I
    dout<2>                             FB16_3            92   I/O       I
    dout<3>                             FB16_5            93   I/O       I
    dout<4>                             FB9_17            59   I/O       I
    dout<5>                             FB3_2             28   I/O       I
    dout<6>                             FB11_17           70   I/O       I
    dout<7>                             FB10_10           124  I/O       I
    dout_str                            FB6_2             135  I/O       I
    dq<0>                               FB8_10            134  I/O       I
    dq<1>                               FB16_2            91   I/O       I
    dq<2>                               FB4_5             3    GTS/I/O   I
    dq<3>                               FB14_10           104  I/O       I
    enw                                 FB2_8             13   I/O       I
    etr                                 FB15_14           86   I/O       I
    evcnth_str                          FB1_14            25   I/O       I
    evcntl_str                          FB2_3             10   I/O       I
    i2c_int                             FB13_11           75   I/O       I
    qpll_error                          FB3_14            32   GCK/I/O   GCK/I
    qpll_locked                         FB16_12           98   I/O       I
    reset_p                             FB6_15            143  GSR/I/O   I
    sinerr_str                          FB10_11           125  I/O       I
    subaddr<0>                          FB5_8             38   GCK/I/O   I
    subaddr<1>                          FB6_8             139  I/O       I
    subaddr<2>                          FB1_10            23   I/O       I
    subaddr<3>                          FB4_14            7    I/O       I
    subaddr<4>                          FB15_2            79   I/O       I
    subaddr<5>                          FB8_2             130  I/O       I
    subaddr<6>                          FB9_6             53   I/O       I
    subaddr<7>                          FB15_17           88   I/O       I
    ttc_ready                           FB7_12            48   I/O       I
    ttc_sel_p                           FB8_3             131  I/O       I

    End of Resources

    *********************Function Block Resource Summary***********************
    Function    # of        FB Inputs   Signals     Total       O/IO      IO
    Block       Macrocells  Used        Used        Pt Used     Req       Avail
    FB1           8          25          25           88         1/2        8
    FB2           5          53          53           59         1/4       10
    FB3          18          16          16           54         0/0        5
    FB4           8          39          39           90         0/1        6
    FB5           6          45          45           45         3/3        8
    FB6          18          21          21           64         1/0        8
    FB7          18          12          12           52         1/0        4
    FB8          18          12          12           52         1/0        5
    FB9          14          25          25           88         4/0        9
    FB10          9          37          37           87         1/2       10
    FB11         13          26          26           73         2/0        7
    FB12         15          33          33           72         2/0        6
    FB13         18          16          16           54         0/0        6
    FB14          7          39          39           71         1/2        8
    FB15         14          17          17           35         0/0        9
    FB16          3          39          39           39         0/2        8
                ----                                -----       -----     -----
                192                                 1023        18/16     117
    *********************************** FB1 ***********************************
    Number of function block inputs used/remaining:               25/29
    Number of signals used by logic mapping into function block:  25
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    qpll_unlocked_reg     9       5<- \/1   0     FB1_1   STD         (b)     (b)
    (unused)              0       0   \/5   0     FB1_2               (b)     (b)
    iac_subadd<6>        16      11<-   0   0     FB1_3   STD         (b)     (b)
    (unused)              0       0   /\5   0     FB1_4               (b)     (b)
    (unused)              0       0   \/5   0     FB1_5         20    I/O     (b)
    db<13>                7       5<- \/3   0     FB1_6   STD   21    I/O     I/O
    (unused)              0       0   \/5   0     FB1_7               (b)     (b)
    (unused)              0       0   \/5   0     FB1_8         22    I/O     (b)
    iac_subadd<5>        16      13<- \/2   0     FB1_9   STD         (b)     (b)
    (unused)              0       0   \/5   0     FB1_10        23    I/O     I
    iac_data<7>          16      11<-   0   0     FB1_11  STD         (b)     (b)
    db<14>                7       6<- /\4   0     FB1_12  STD   24    I/O     I/O
    (unused)              0       0   /\5   0     FB1_13              (b)     (b)
    iac_data<4>          16      12<- /\1   0     FB1_14  STD   25    I/O     I
    (unused)              0       0   /\5   0     FB1_15        26    I/O     (b)
    (unused)              0       0   /\5   0     FB1_16              (b)     (b)
    i2c_rd                1       0   /\2   2     FB1_17  STD   27    I/O     O
    (unused)              0       0   \/5   0     FB1_18              (b)     (b)

    Signals Used by Logic in Function Block
      1: db<2>.PIN         10: add<4>            18: qpll_locked
      2: db<4>.PIN         11: dout<4>           19: qpll_unlocked_reg
      3: db<7>.PIN         12: dout<7>           20: reset
      4: db<13>.PIN        13: dout_str          21: subaddr<5>
      5: db<14>.PIN        14: iac_data<4>       22: subaddr<6>
      6: add<0>            15: iac_data<7>       23: etr
      7: add<1>            16: iac_subadd<5>     24: enw
      8: add<2>            17: iac_subadd<6>     25: ttc_sel_p
      9: add<3>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    qpll_unlocked_reg    X....XXXXX.......XXX...XX............... 11      11
    iac_subadd<6>        ....XXXXXX..X...X..X.X.XX............... 12      12
    db<13>               .....XXXXX.....X......X.X............... 8       8
    iac_subadd<5>        ...X.XXXXX..X..X...XX..XX............... 12      12
    iac_data<7>          ..X..XXXXX.XX.X....X...XX............... 12      12
    db<14>               .....XXXXX......X.....X.X............... 8       8
    iac_data<4>          .X...XXXXXX.XX.....X...XX............... 12      12
    i2c_rd               ......................X................. 1       1
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB2 ***********************************
    Number of function block inputs used/remaining:               53/1
    Number of signals used by logic mapping into function block:  53
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   \/5   0     FB2_1               (b)     (b)
    db<7>                15      10<-   0   0     FB2_2   STD   9     I/O     I/O
    (unused)              0       0   /\5   0     FB2_3         10    I/O     I
    (unused)              0       0   \/5   0     FB2_4               (b)     (b)
    db<0>                15      10<-   0   0     FB2_5   STD   11    I/O     I/O
    (unused)              0       0   /\5   0     FB2_6         12    I/O     (b)
    (unused)              0       0     0   5     FB2_7               (b)
    (unused)              0       0     0   5     FB2_8         13    I/O     I
    (unused)              0       0     0   5     FB2_9               (b)
    (unused)              0       0     0   5     FB2_10        14    I/O     I
    (unused)              0       0   \/5   0     FB2_11              (b)     (b)
    db<10>               14       9<-   0   0     FB2_12  STD   15    I/O     I/O
    (unused)              0       0   /\4   1     FB2_13              (b)     (b)
    spare                 0       0     0   5     FB2_14  STD   16    I/O     O
    (unused)              0       0     0   5     FB2_15        17    I/O
    (unused)              0       0   \/5   0     FB2_16              (b)     (b)
    db<1>                15      10<-   0   0     FB2_17  STD   19    I/O     I/O
    (unused)              0       0   /\5   0     FB2_18              (b)     (b)

    Signals Used by Logic in Function Block
      1: add<0>            19: evcntl_reg<7>     37: reg_DQ_52<1>
      2: add<1>            20: i2c_int           38: reg_DQ_52<7>
      3: add<2>            21: iac_data<0>       39: reg_DQ_54<0>
      4: add<3>            22: iac_data<1>       40: reg_DQ_54<10>
      5: add<4>            23: iac_data<7>       41: reg_DQ_54<1>
      6: bcnt_reg<0>       24: iac_subadd<2>     42: reg_DQ_54<7>
      7: bcnt_reg<10>      25: qpll_locked       43: reg_DQ_56<0>
      8: bcnt_reg<1>       26: qpll_unlocked_reg 44: reg_DQ_56<1>
      9: bcnt_reg<7>       27: reg_DQ_4E<0>      45: reg_DQ_56<7>
     10: brcst1_reg<5>     28: reg_DQ_4E<10>     46: reg_DQ_58<0>
     11: brcst2_reg<5>     29: reg_DQ_4E<1>      47: reg_DQ_58<1>
     12: evcnth_reg<0>     30: reg_DQ_4E<7>      48: reg_DQ_58<7>
     13: evcnth_reg<10>    31: reg_DQ_50<0>      49: seu_counter<4>
     14: evcnth_reg<1>     32: reg_DQ_50<10>     50: seu_counter<7>
     15: evcnth_reg<7>     33: reg_DQ_50<1>      51: etr
     16: evcntl_reg<0>     34: reg_DQ_50<7>      52: ttc_ready
     17: evcntl_reg<10>    35: reg_DQ_52<0>      53: ttc_sel_p
     18: evcntl_reg<1>     36: reg_DQ_52<10>

    Signal                        1         2         3         4         5         6 Signals FB
    Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
    db<7>                XXXXX...XXX...X...XX..X......X...X...X...X..X..XX.X.X....... 21      21
    db<0>                XXXXXX.....X...X....X...X.X...X...X...X...X..X....XXX....... 19      19
    db<10>               XXXXX.X.....X...X......X...X...X...X...X.........XX.X....... 16      16
    spare                ............................................................ 0       0
    db<1>                XXXXX..X.....X...X...X..XX..X...X...X...X..X..X...X.X....... 19      19
                        0----+----1----+----2----+----3----+----4----+----5----+----6
                                  0         0         0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB3 ***********************************
    Number of function block inputs used/remaining:               16/38
    Number of signals used by logic mapping into function block:  16
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    reg_DQ_52<9>          3       0     0   2     FB3_1   STD         (b)     (b)
    reg_DQ_52<8>          3       0     0   2     FB3_2   STD   28    I/O     I
    reg_DQ_52<11>         3       0     0   2     FB3_3   STD         (b)     (b)
    reg_DQ_50<9>          3       0     0   2     FB3_4   STD         (b)     (b)
    reg_DQ_50<8>          3       0     0   2     FB3_5   STD         (b)     (b)
    reg_DQ_50<11>         3       0     0   2     FB3_6   STD         (b)     (b)
    reg_DQ_4E<9>          3       0     0   2     FB3_7   STD         (b)     (b)
    reg_DQ_4E<8>          3       0     0   2     FB3_8   STD         (b)     (b)
    bcnt_reg<7>           3       0     0   2     FB3_9   STD         (b)     (b)
    bcnt_reg<6>           3       0     0   2     FB3_10  STD   30    GCK/I/O GCK
    bcnt_reg<5>           3       0     0   2     FB3_11  STD         (b)     (b)
    bcnt_reg<4>           3       0     0   2     FB3_12  STD   31    I/O     (b)
    bcnt_reg<3>           3       0     0   2     FB3_13  STD         (b)     (b)
    bcnt_reg<2>           3       0     0   2     FB3_14  STD   32    GCK/I/O GCK/I
    bcnt_reg<1>           3       0     0   2     FB3_15  STD   33    I/O     (b)
    bcnt_reg<11>          3       0     0   2     FB3_16  STD         (b)     (b)
    bcnt_reg<10>          3       0     0   2     FB3_17  STD         (b)     (b)
    bcnt_reg<0>           3       0     0   2     FB3_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: bcnt<0>            7: bcnt<4>           12: dout_str
      2: bcnt<10>           8: bcnt<5>           13: dq<0>
      3: bcnt<11>           9: bcnt<6>           14: dq<1>
      4: bcnt<1>           10: bcnt<7>           15: dq<3>
      5: bcnt<2>           11: bcnt_str          16: reset
      6: bcnt<3>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    reg_DQ_52<9>         ...........XXXXX........................ 5       5
    reg_DQ_52<8>         ...........XXXXX........................ 5       5
    reg_DQ_52<11>        ...........XXXXX........................ 5       5
    reg_DQ_50<9>         ...........XXXXX........................ 5       5
    reg_DQ_50<8>         ...........XXXXX........................ 5       5
    reg_DQ_50<11>        ...........XXXXX........................ 5       5
    reg_DQ_4E<9>         ...........XXXXX........................ 5       5
    reg_DQ_4E<8>         ...........XXXXX........................ 5       5
    bcnt_reg<7>          .........XX....X........................ 3       3
    bcnt_reg<6>          ........X.X....X........................ 3       3
    bcnt_reg<5>          .......X..X....X........................ 3       3
    bcnt_reg<4>          ......X...X....X........................ 3       3
    bcnt_reg<3>          .....X....X....X........................ 3       3
    bcnt_reg<2>          ....X.....X....X........................ 3       3
    bcnt_reg<1>          ...X......X....X........................ 3       3
    bcnt_reg<11>         ..X.......X....X........................ 3       3
    bcnt_reg<10>         .X........X....X........................ 3       3
    bcnt_reg<0>          X.........X....X........................ 3       3
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB4 ***********************************
    Number of function block inputs used/remaining:               39/15
    Number of signals used by logic mapping into function block:  39
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   \/5   0     FB4_1               (b)     (b)
    (unused)              0       0   \/5   0     FB4_2         2     GTS/I/O I
    iac_data<1>          16      12<- \/1   0     FB4_3   STD         (b)     (b)
    (unused)              0       0   \/5   0     FB4_4               (b)     (b)
    (unused)              0       0   \/5   0     FB4_5         3     GTS/I/O I
    db<6>                15      11<- \/1   0     FB4_6   STD   4     I/O     I/O
    (unused)              0       0   \/5   0     FB4_7               (b)     (b)
    iac_data<2>          16      11<-   0   0     FB4_8   STD   5     GTS/I/O I
    (unused)              0       0   /\5   0     FB4_9               (b)     (b)
    (unused)              0       0   \/5   0     FB4_10              (b)     (b)
    iac_data<3>          16      11<-   0   0     FB4_11  STD         (b)     (b)
    (unused)              0       0   /\5   0     FB4_12        6     GTS/I/O (b)
    iac_data<6>          16      12<- /\1   0     FB4_13  STD         (b)     (b)
    (unused)              0       0   /\5   0     FB4_14        7     I/O     I
    (unused)              0       0   /\5   0     FB4_15              (b)     (b)
    reg_DQ_54<6>          5       2<- /\2   0     FB4_16  STD         (b)     (b)
    reg_DQ_56<1>          3       0   /\2   0     FB4_17  STD         (b)     (b)
    reg_DQ_56<2>          3       0   \/2   0     FB4_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<1>.PIN         14: dout<1>           27: iac_data<3>
      2: db<2>.PIN         15: dout<2>           28: iac_data<6>
      3: db<3>.PIN         16: dout<3>           29: reg_DQ_4E<6>
      4: db<6>.PIN         17: dout<6>           30: reg_DQ_50<6>
      5: add<0>            18: dout_str          31: reg_DQ_52<6>
      6: add<1>            19: dq<0>             32: reg_DQ_54<6>
      7: add<2>            20: dq<1>             33: reg_DQ_56<6>
      8: add<3>            21: dq<2>             34: reg_DQ_58<6>
      9: add<4>            22: dq<3>             35: reset
     10: bcnt_reg<6>       23: evcnth_reg<6>     36: seu_counter<3>
     11: brcst1_reg<4>     24: evcntl_reg<6>     37: etr
     12: brcst2_reg<4>     25: iac_data<1>       38: enw
     13: dberr_str_reg     26: iac_data<2>       39: ttc_sel_p

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    iac_data<1>          X...XXXXX....X...X......X.........X..XX. 12      12
    db<6>                ....XXXXXXXXX.........XX...XXXXXXX.XX.X. 21      21
    iac_data<2>          .X..XXXXX.....X..X.......X........X..XX. 12      12
    iac_data<3>          ..X.XXXXX......X.X........X.......X..XX. 12      12
    iac_data<6>          ...XXXXXX.......XX.........X......X..XX. 12      12
    reg_DQ_54<6>         ................XXXXXX.........X..X..... 8       8
    reg_DQ_56<1>         .............X...XXXXX............X..... 7       7
    reg_DQ_56<2>         ..............X..XXXXX............X..... 7       7
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB5 ***********************************
    Number of function block inputs used/remaining:               45/9
    Number of signals used by logic mapping into function block:  45
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB5_1               (b)
    i2c_rst               2       0     0   3     FB5_2   STD   34    I/O     O
    (unused)              0       0     0   5     FB5_3               (b)
    (unused)              0       0   \/5   0     FB5_4               (b)     (b)
    db<3>                15      10<-   0   0     FB5_5   STD   35    I/O     I/O
    (unused)              0       0   /\5   0     FB5_6               (b)     (b)
    (unused)              0       0     0   5     FB5_7               (b)
    (unused)              0       0     0   5     FB5_8         38    GCK/I/O I
    (unused)              0       0   \/3   2     FB5_9               (b)     (b)
    db<11>               11       6<-   0   0     FB5_10  STD   39    I/O     I/O
    (unused)              0       0   /\3   2     FB5_11              (b)     (b)
    qpll_reset            1       0     0   4     FB5_12  STD   40    I/O     O
    (unused)              0       0     0   5     FB5_13              (b)
    (unused)              0       0   \/2   3     FB5_14        41    I/O     (b)
    reset_b               9       4<-   0   0     FB5_15  STD   43    I/O     O
    (unused)              0       0   /\2   3     FB5_16              (b)     (b)
    db<15>                7       2<-   0   0     FB5_17  STD   44    I/O     I/O
    (unused)              0       0   /\2   3     FB5_18              (b)     (b)

    Signals Used by Logic in Function Block
      1: db<14>.PIN        16: iac_data<3>       31: rst_counter<10>
      2: db<15>.PIN        17: iac_subadd<3>     32: rst_counter<1>
      3: add<0>            18: iac_subadd<7>     33: rst_counter<2>
      4: add<1>            19: reg_DQ_4E<11>     34: rst_counter<3>
      5: add<2>            20: reg_DQ_4E<3>      35: rst_counter<4>
      6: add<3>            21: reg_DQ_50<11>     36: rst_counter<5>
      7: add<4>            22: reg_DQ_50<3>      37: rst_counter<6>
      8: bcnt_reg<11>      23: reg_DQ_52<11>     38: rst_counter<7>
      9: bcnt_reg<3>       24: reg_DQ_52<3>      39: rst_counter<8>
     10: brcst1_reg_1      25: reg_DQ_54<11>     40: rst_counter<9>
     11: brcst2_reg_1      26: reg_DQ_54<3>      41: seu_counter<0>
     12: evcnth_reg<11>    27: reg_DQ_56<3>      42: sinerr_str
     13: evcnth_reg<3>     28: reg_DQ_58<3>      43: etr
     14: evcntl_reg<11>    29: reset             44: enw
     15: evcntl_reg<3>     30: rst_counter<0>    45: ttc_sel_p

    Signal                        1         2         3         4         5 Signals FB
    Name                0----+----0----+----0----+----0----+----0----+----0 Used    Inputs
    i2c_rst              X.XXXXX.....................X..............XX..... 9       9
    db<3>                ..XXXXX.XXX.X.XX...X.X.X.XXX............XXX.X..... 21      21
    db<11>               ..XXXXXX...X.X..X.X.X.X.X.................X.X..... 15      15
    qpll_reset           .XXXXXX....................................XX..... 8       8
    reset_b              .XXXXXX.....................XXXXXXXXXXXX...XX..... 20      20
    db<15>               ..XXXXX..........X........................X.X..... 8       8
                        0----+----1----+----2----+----3----+----4----+----5
                                  0         0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB6 ***********************************
    Number of function block inputs used/remaining:               21/33
    Number of signals used by logic mapping into function block:  21
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    reg_DQ_58<7>          3       0     0   2     FB6_1   STD         (b)     (b)
    reg_DQ_58<4>          3       0     0   2     FB6_2   STD   135   I/O     I
    reg_DQ_58<3>          3       0     0   2     FB6_3   STD   136   I/O     I
    reg_DQ_58<2>          3       0     0   2     FB6_4   STD         (b)     (b)
    reg_DQ_58<1>          3       0     0   2     FB6_5   STD   137   I/O     I
    tp3                   1       0     0   4     FB6_6   STD   138   I/O     O
    reg_DQ_58<0>          3       0     0   2     FB6_7   STD         (b)     (b)
    reg_DQ_56<7>          3       0     0   2     FB6_8   STD   139   I/O     I
    reg_DQ_56<4>          3       0     0   2     FB6_9   STD         (b)     (b)
    reg_DQ_56<3>          3       0     0   2     FB6_10  STD   140   I/O     I
    reg_DQ_54<11>         3       0     0   2     FB6_11  STD         (b)     (b)
    reg_DQ_54<10>         3       0     0   2     FB6_12  STD         (b)     (b)
    reg_DQ_54<7>          5       0     0   0     FB6_13  STD         (b)     (b)
    reg_DQ_54<4>          5       0     0   0     FB6_14  STD   142   I/O     (b)
    reg_DQ_54<3>          5       0     0   0     FB6_15  STD   143   GSR/I/O I
    reg_DQ_54<2>          5       0     0   0     FB6_16  STD         (b)     (b)
    reg_DQ_54<1>          5       0     0   0     FB6_17  STD         (b)     (b)
    reg_DQ_54<0>          5       0     0   0     FB6_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: dout<0>            8: dq<0>             15: reg_DQ_54<1>
      2: dout<1>            9: dq<1>             16: reg_DQ_54<2>
      3: dout<2>           10: dq<2>             17: reg_DQ_54<3>
      4: dout<3>           11: dq<3>             18: reg_DQ_54<4>
      5: dout<4>           12: reg_DQ_54<0>      19: reg_DQ_54<7>
      6: dout<7>           13: reg_DQ_54<10>     20: reset
      7: dout_str          14: reg_DQ_54<11>     21: brcst_str_2

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    reg_DQ_58<7>         .....XXXXXX........X.................... 7       7
    reg_DQ_58<4>         ....X.XXXXX........X.................... 7       7
    reg_DQ_58<3>         ...X..XXXXX........X.................... 7       7
    reg_DQ_58<2>         ..X...XXXXX........X.................... 7       7
    reg_DQ_58<1>         .X....XXXXX........X.................... 7       7
    tp3                  ....................X................... 1       1
    reg_DQ_58<0>         X.....XXXXX........X.................... 7       7
    reg_DQ_56<7>         .....XXXXXX........X.................... 7       7
    reg_DQ_56<4>         ....X.XXXXX........X.................... 7       7
    reg_DQ_56<3>         ...X..XXXXX........X.................... 7       7
    reg_DQ_54<11>        ......XXXXX..X.....X.................... 7       7
    reg_DQ_54<10>        ......XXXXX.X......X.................... 7       7
    reg_DQ_54<7>         .....XXXXXX.......XX.................... 8       8
    reg_DQ_54<4>         ....X.XXXXX......X.X.................... 8       8
    reg_DQ_54<3>         ...X..XXXXX.....X..X.................... 8       8
    reg_DQ_54<2>         ..X...XXXXX....X...X.................... 8       8
    reg_DQ_54<1>         .X....XXXXX...X....X.................... 8       8
    reg_DQ_54<0>         X.....XXXXXX.......X.................... 8       8
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB7 ***********************************
    Number of function block inputs used/remaining:               12/42
    Number of signals used by logic mapping into function block:  12
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    reg_DQ_58<6>          3       0     0   2     FB7_1   STD         (b)     (b)
    reg_DQ_58<5>          3       0     0   2     FB7_2   STD         (b)     (b)
    reg_DQ_56<6>          3       0     0   2     FB7_3   STD   45    I/O     (b)
    reg_DQ_56<5>          3       0     0   2     FB7_4   STD         (b)     (b)
    reg_DQ_54<9>          3       0     0   2     FB7_5   STD   46    I/O     I
    reg_DQ_54<8>          3       0     0   2     FB7_6   STD         (b)     (b)
    reg_DQ_52<6>          3       0     0   2     FB7_7   STD         (b)     (b)
    reg_DQ_52<5>          3       0     0   2     FB7_8   STD         (b)     (b)
    reg_DQ_52<10>         3       0     0   2     FB7_9   STD         (b)     (b)
    reg_DQ_50<6>          3       0     0   2     FB7_10  STD         (b)     (b)
    reg_DQ_50<5>          3       0     0   2     FB7_11  STD         (b)     (b)
    reg_DQ_50<10>         3       0     0   2     FB7_12  STD   48    I/O     I
    reg_DQ_50<0>          3       0     0   2     FB7_13  STD         (b)     (b)
    reg_DQ_4E<6>          3       0     0   2     FB7_14  STD         (b)     (b)
    i2c_wr                1       0     0   4     FB7_15  STD   49    I/O     O
    reg_DQ_4E<5>          3       0     0   2     FB7_16  STD         (b)     (b)
    reg_DQ_4E<10>         3       0     0   2     FB7_17  STD         (b)     (b)
    reg_DQ_4E<0>          3       0     0   2     FB7_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: dout<0>            5: dq<0>              9: reg_DQ_54<8>
      2: dout<5>            6: dq<1>             10: reg_DQ_54<9>
      3: dout<6>            7: dq<2>             11: reset
      4: dout_str           8: dq<3>             12: enw

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    reg_DQ_58<6>         ..XXXXXX..X............................. 7       7
    reg_DQ_58<5>         .X.XXXXX..X............................. 7       7
    reg_DQ_56<6>         ..XXXXXX..X............................. 7       7
    reg_DQ_56<5>         .X.XXXXX..X............................. 7       7
    reg_DQ_54<9>         ...XXXXX.XX............................. 7       7
    reg_DQ_54<8>         ...XXXXXX.X............................. 7       7
    reg_DQ_52<6>         ..XXXX.X..X............................. 6       6
    reg_DQ_52<5>         .X.XXX.X..X............................. 6       6
    reg_DQ_52<10>        ...XXXXX..X............................. 6       6
    reg_DQ_50<6>         ..XXXX.X..X............................. 6       6
    reg_DQ_50<5>         .X.XXX.X..X............................. 6       6
    reg_DQ_50<10>        ...XXXXX..X............................. 6       6
    reg_DQ_50<0>         X..XXX.X..X............................. 6       6
    reg_DQ_4E<6>         ..XXXX.X..X............................. 6       6
    i2c_wr               ...........X............................ 1       1
    reg_DQ_4E<5>         .X.XXX.X..X............................. 6       6
    reg_DQ_4E<10>        ...XXXXX..X............................. 6       6
    reg_DQ_4E<0>         X..XXX.X..X............................. 6       6
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB8 ***********************************
    Number of function block inputs used/remaining:               12/42
    Number of signals used by logic mapping into function block:  12
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    reg_DQ_52<7>          3       0     0   2     FB8_1   STD         (b)     (b)
    reg_DQ_52<4>          3       0     0   2     FB8_2   STD   130   I/O     I
    reg_DQ_52<3>          3       0     0   2     FB8_3   STD   131   I/O     I
    reg_DQ_52<2>          3       0     0   2     FB8_4   STD         (b)     (b)
    tp1                   1       0     0   4     FB8_5   STD   132   I/O     O
    reg_DQ_52<1>          3       0     0   2     FB8_6   STD         (b)     (b)
    reg_DQ_52<0>          3       0     0   2     FB8_7   STD         (b)     (b)
    reg_DQ_50<7>          3       0     0   2     FB8_8   STD   133   I/O     (b)
    reg_DQ_50<4>          3       0     0   2     FB8_9   STD         (b)     (b)
    reg_DQ_50<3>          3       0     0   2     FB8_10  STD   134   I/O     I
    reg_DQ_50<2>          3       0     0   2     FB8_11  STD         (b)     (b)
    reg_DQ_50<1>          3       0     0   2     FB8_12  STD         (b)     (b)
    reg_DQ_4E<7>          3       0     0   2     FB8_13  STD         (b)     (b)
    reg_DQ_4E<4>          3       0     0   2     FB8_14  STD         (b)     (b)
    reg_DQ_4E<3>          3       0     0   2     FB8_15  STD         (b)     (b)
    reg_DQ_4E<2>          3       0     0   2     FB8_16  STD         (b)     (b)
    reg_DQ_4E<1>          3       0     0   2     FB8_17  STD         (b)     (b)
    reg_DQ_4E<11>         3       0     0   2     FB8_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: dout<0>            5: dout<4>            9: dq<1>
      2: dout<1>            6: dout<7>           10: dq<3>
      3: dout<2>            7: dout_str          11: reset
      4: dout<3>            8: dq<0>             12: etr

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    reg_DQ_52<7>         .....XXXXXX............................. 6       6
    reg_DQ_52<4>         ....X.XXXXX............................. 6       6
    reg_DQ_52<3>         ...X..XXXXX............................. 6       6
    reg_DQ_52<2>         ..X...XXXXX............................. 6       6
    tp1                  ...........X............................ 1       1
    reg_DQ_52<1>         .X....XXXXX............................. 6       6
    reg_DQ_52<0>         X.....XXXXX............................. 6       6
    reg_DQ_50<7>         .....XXXXXX............................. 6       6
    reg_DQ_50<4>         ....X.XXXXX............................. 6       6
    reg_DQ_50<3>         ...X..XXXXX............................. 6       6
    reg_DQ_50<2>         ..X...XXXXX............................. 6       6
    reg_DQ_50<1>         .X....XXXXX............................. 6       6
    reg_DQ_4E<7>         .....XXXXXX............................. 6       6
    reg_DQ_4E<4>         ....X.XXXXX............................. 6       6
    reg_DQ_4E<3>         ...X..XXXXX............................. 6       6
    reg_DQ_4E<2>         ..X...XXXXX............................. 6       6
    reg_DQ_4E<1>         .X....XXXXX............................. 6       6
    reg_DQ_4E<11>        ......XXXXX............................. 5       5
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB9 ***********************************
    Number of function block inputs used/remaining:               25/29
    Number of signals used by logic mapping into function block:  25
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    brcst1_reg_0          3       0   \/2   0     FB9_1   STD         (b)     (b)
    rst_counter<1>       12       7<-   0   0     FB9_2   STD   50    I/O     (b)
    tp2                   1       1<- /\5   0     FB9_3   STD   51    I/O     O
    brcst1_reg<3>         3       0   /\1   1     FB9_4   STD         (b)     (b)
    cmd<0>                1       0   \/3   1     FB9_5   STD   52    I/O     O
    (unused)              0       0   \/5   0     FB9_6         53    I/O     I
    rst_counter<6>       12       8<- \/1   0     FB9_7   STD         (b)     (b)
    cmd<1>                1       1<- \/5   0     FB9_8   STD   54    I/O     O
    rst_counter<4>       12       7<-   0   0     FB9_9   STD         (b)     (b)
    rst_counter<5>       12       9<- /\2   0     FB9_10  STD         (b)     (b)
    (unused)              0       0   /\5   0     FB9_11        56    I/O     (b)
    cmd<2>                1       0   /\4   0     FB9_12  STD   57    I/O     O
    brcst1_reg<2>         3       0   \/2   0     FB9_13  STD         (b)     (b)
    rst_counter<3>       12       7<-   0   0     FB9_14  STD   58    I/O     I
    (unused)              0       0   /\5   0     FB9_15              (b)     (b)
    (unused)              0       0   \/5   0     FB9_16              (b)     (b)
    rst_counter<2>       12       7<-   0   0     FB9_17  STD   59    I/O     I
    brcst1_reg_1          3       0   /\2   0     FB9_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<15>.PIN        10: brcst<5>          18: rst_counter<4>
      2: add<0>            11: brcst_str_1       19: rst_counter<5>
      3: add<1>            12: reset             20: rst_counter<6>
      4: add<2>            13: rst_counter<0>    21: rst_counter<7>
      5: add<3>            14: rst_counter<10>   22: rst_counter<8>
      6: add<4>            15: rst_counter<1>    23: rst_counter<9>
      7: brcst<2>          16: rst_counter<2>    24: enw
      8: brcst<3>          17: rst_counter<3>    25: ttc_sel_p
      9: brcst<4>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    brcst1_reg_0         ......X...XX............................ 3       3
    rst_counter<1>       XXXXXX.....XXXXXXXXXXXXXX............... 20      20
    tp2                  .......................X................ 1       1
    brcst1_reg<3>        .........XXX............................ 3       3
    cmd<0>               ......X...X............................. 2       2
    rst_counter<6>       XXXXXX.....XXXXXXXXXXXXXX............... 20      20
    cmd<1>               .......X..X............................. 2       2
    rst_counter<4>       XXXXXX.....XXXXXXXXXXXXXX............... 20      20
    rst_counter<5>       XXXXXX.....XXXXXXXXXXXXXX............... 20      20
    cmd<2>               ........X.X............................. 2       2
    brcst1_reg<2>        ........X.XX............................ 3       3
    rst_counter<3>       XXXXXX.....XXXXXXXXXXXXXX............... 20      20
    rst_counter<2>       XXXXXX.....XXXXXXXXXXXXXX............... 20      20
    brcst1_reg_1         .......X..XX............................ 3       3
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB10 ***********************************
    Number of function block inputs used/remaining:               37/17
    Number of signals used by logic mapping into function block:  37
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   \/5   0     FB10_1              (b)     (b)
    iac_data<0>          16      11<-   0   0     FB10_2  STD   117   I/O     (b)
    (unused)              0       0   /\5   0     FB10_3        118   I/O     I
    reg_DQ_56<0>          3       0   /\1   1     FB10_4  STD         (b)     (b)
    reg_DQ_54<5>          5       0     0   0     FB10_5  STD   119   I/O     (b)
    (unused)              0       0   \/4   1     FB10_6        120   I/O     I
    sinerr_str_reg        9       4<-   0   0     FB10_7  STD         (b)     (b)
    ttc_on                0       0   \/4   1     FB10_8  STD   121   I/O     O
    (unused)              0       0   \/5   0     FB10_9              (b)     (b)
    (unused)              0       0   \/5   0     FB10_10       124   I/O     I
    iac_subadd<4>        16      14<- \/3   0     FB10_11 STD   125   I/O     I
    db<5>                15      10<-   0   0     FB10_12 STD   126   I/O     I/O
    (unused)              0       0   /\5   0     FB10_13             (b)     (b)
    iac_data<5>          16      13<- /\2   0     FB10_14 STD   128   I/O     I
    (unused)              0       0   /\5   0     FB10_15             (b)     (b)
    (unused)              0       0   /\5   0     FB10_16             (b)     (b)
    db<12>                7       5<- /\3   0     FB10_17 STD   129   I/O     I/O
    (unused)              0       0   /\5   0     FB10_18             (b)     (b)

    Signals Used by Logic in Function Block
      1: db<0>.PIN         14: dout_str          26: reg_DQ_52<5>
      2: db<5>.PIN         15: dq<0>             27: reg_DQ_54<5>
      3: db<12>.PIN        16: dq<1>             28: reg_DQ_56<5>
      4: add<0>            17: dq<2>             29: reg_DQ_58<5>
      5: add<1>            18: dq<3>             30: reset
      6: add<2>            19: evcnth_reg<5>     31: seu_counter<2>
      7: add<3>            20: evcntl_reg<5>     32: sinerr_str
      8: add<4>            21: iac_data<0>       33: sinerr_str_reg
      9: bcnt_reg<5>       22: iac_data<5>       34: subaddr<4>
     10: brcst1_reg<3>     23: iac_subadd<4>     35: etr
     11: brcst2_reg<3>     24: reg_DQ_4E<5>      36: enw
     12: dout<0>           25: reg_DQ_50<5>      37: ttc_sel_p
     13: dout<5>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    iac_data<0>          X..XXXXX...X.X......X........X.....XX... 12      12
    reg_DQ_56<0>         ...........X.XXXXX...........X.......... 7       7
    reg_DQ_54<5>         ............XXXXXX........X..X.......... 8       8
    sinerr_str_reg       .X.XXXXX.....................X.XX..XX... 11      11
    ttc_on               ........................................ 0       0
    iac_subadd<4>        ..XXXXXX.....X........X......X...X.XX... 12      12
    db<5>                ...XXXXXXXX.......XX.X.XXXXXX.X.X.X.X... 21      21
    iac_data<5>          .X.XXXXX....XX.......X.......X.....XX... 12      12
    db<12>               ...XXXXX..............X...........X.X... 8       8
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB11 ***********************************
    Number of function block inputs used/remaining:               26/28
    Number of signals used by logic mapping into function block:  26
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   \/5   0     FB11_1              (b)     (b)
    iac_subadd<2>        16      11<-   0   0     FB11_2  STD         (b)     (b)
    cmd<3>                1       1<- /\5   0     FB11_3  STD   60    I/O     O
    brcst2_reg_1          3       0   /\1   1     FB11_4  STD         (b)     (b)
    brcst2_reg_0          3       0     0   2     FB11_5  STD   61    I/O     I
    brcst2_reg<5>         3       0     0   2     FB11_6  STD         (b)     (b)
    brcst2_reg<4>         3       0     0   2     FB11_7  STD         (b)     (b)
    brcst2_reg<3>         3       0     0   2     FB11_8  STD         (b)     (b)
    brcst2_reg<2>         3       0     0   2     FB11_9  STD         (b)     (b)
    cmy                   0       0     0   5     FB11_10 STD   64    I/O     O
    brcst1_reg<4>         3       0   \/2   0     FB11_11 STD   66    I/O     I
    (unused)              0       0   \/5   0     FB11_12       68    I/O     (b)
    (unused)              0       0   \/5   0     FB11_13             (b)     (b)
    iac_subadd<7>        16      12<- \/1   0     FB11_14 STD   69    I/O     (b)
    (unused)              0       0   \/5   0     FB11_15             (b)     (b)
    iac_subadd<3>        16      11<-   0   0     FB11_16 STD         (b)     (b)
    (unused)              0       0   /\5   0     FB11_17       70    I/O     I
    brcst1_reg<5>         3       0   \/1   1     FB11_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<10>.PIN        10: brcst<3>          19: iac_subadd<7>
      2: db<11>.PIN        11: brcst<4>          20: reset
      3: db<15>.PIN        12: brcst<5>          21: subaddr<2>
      4: add<0>            13: brcst<6>          22: subaddr<3>
      5: add<1>            14: brcst<7>          23: subaddr<7>
      6: add<2>            15: brcst_str_1       24: enw
      7: add<3>            16: dout_str          25: brcst_str_2
      8: add<4>            17: iac_subadd<2>     26: ttc_sel_p
      9: brcst<2>          18: iac_subadd<3>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    iac_subadd<2>        X..XXXXX.......XX..XX..X.X.............. 12      12
    cmd<3>               ...........X..X......................... 2       2
    brcst2_reg_1         .........X.........X....X............... 3       3
    brcst2_reg_0         ........X..........X....X............... 3       3
    brcst2_reg<5>        .............X.....X....X............... 3       3
    brcst2_reg<4>        ............X......X....X............... 3       3
    brcst2_reg<3>        ...........X.......X....X............... 3       3
    brcst2_reg<2>        ..........X........X....X............... 3       3
    cmy                  ........................................ 0       0
    brcst1_reg<4>        ............X.X....X.................... 3       3
    iac_subadd<7>        ..XXXXXX.......X..XX..XX.X.............. 12      12
    iac_subadd<3>        .X.XXXXX.......X.X.X.X.X.X.............. 12      12
    brcst1_reg<5>        .............XX....X.................... 3       3
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB12 ***********************************
    Number of function block inputs used/remaining:               33/21
    Number of signals used by logic mapping into function block:  33
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    seu_counter<7>        2       0   \/3   0     FB12_1  STD         (b)     (b)
    rst_counter<7>       12       7<-   0   0     FB12_2  STD   110   I/O     I
    seu_counter<6>        2       1<- /\4   0     FB12_3  STD   111   I/O     I
    seu_counter<5>        2       0   /\1   2     FB12_4  STD         (b)     (b)
    interrupt             1       0     0   4     FB12_5  STD   112   I/O     O
    seu_counter<4>        2       0     0   3     FB12_6  STD         (b)     (b)
    seu_counter<3>        2       0     0   3     FB12_7  STD         (b)     (b)
    seu_counter<2>        2       0     0   3     FB12_8  STD   113   I/O     I
    seu_counter<1>        2       0   \/1   2     FB12_9  STD         (b)     (b)
    on_245                1       1<- \/5   0     FB12_10 STD   115   I/O     O
    rst_counter<10>      10       5<-   0   0     FB12_11 STD         (b)     (b)
    (unused)              0       0   \/5   0     FB12_12       116   I/O     I
    rst_counter<0>       10       5<-   0   0     FB12_13 STD         (b)     (b)
    (unused)              0       0   \/4   1     FB12_14             (b)     (b)
    (unused)              0       0   \/5   0     FB12_15             (b)     (b)
    rst_counter<9>       11       9<- \/3   0     FB12_16 STD         (b)     (b)
    rst_counter<8>       12       7<-   0   0     FB12_17 STD         (b)     (b)
    seu_counter<0>        1       0   /\4   0     FB12_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<15>.PIN        12: rst_counter<10>   23: seu_counter<1>
      2: add<0>            13: rst_counter<1>    24: seu_counter<2>
      3: add<1>            14: rst_counter<2>    25: seu_counter<3>
      4: add<2>            15: rst_counter<3>    26: seu_counter<4>
      5: add<3>            16: rst_counter<4>    27: seu_counter<5>
      6: add<4>            17: rst_counter<5>    28: seu_counter<6>
      7: dberr_str         18: rst_counter<6>    29: seu_counter<6>/seu_counter<6>_RSTF
      8: qpll_error        19: rst_counter<7>    30: sinerr_str
      9: qpll_locked       20: rst_counter<8>    31: enw
     10: reset             21: rst_counter<9>    32: ttc_ready
     11: rst_counter<0>    22: seu_counter<0>    33: ttc_sel_p

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    seu_counter<7>       .....................XXXXXXXX........... 8       8
    rst_counter<7>       XXXXXX...XXXXXXXXXXXX.........X.X....... 20      20
    seu_counter<6>       .....................XXXXXX.X........... 7       7
    seu_counter<5>       .....................XXXXX..X........... 6       6
    interrupt            ......XXX....................X.X........ 5       5
    seu_counter<4>       .....................XXXX...X........... 5       5
    seu_counter<3>       .....................XXX....X........... 4       4
    seu_counter<2>       .....................XX.....X........... 3       3
    seu_counter<1>       .....................X......X........... 2       2
    on_245               ........................................ 0       0
    rst_counter<10>      XXXXXX...XXXXXXXXXXXX.........X.X....... 20      20
    rst_counter<0>       XXXXXX...XXXXXXXXXXXX.........X.X....... 20      20
    rst_counter<9>       XXXXXX...XXXXXXXXXXXX.........X.X....... 20      20
    rst_counter<8>       XXXXXX...XXXXXXXXXXXX.........X.X....... 20      20
    seu_counter<0>       ............................X........... 1       1
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB13 ***********************************
    Number of function block inputs used/remaining:               16/38
    Number of signals used by logic mapping into function block:  16
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    evcntl_reg<1>         3       0     0   2     FB13_1  STD         (b)     (b)
    evcntl_reg<11>        3       0     0   2     FB13_2  STD   71    I/O     I
    evcntl_reg<10>        3       0     0   2     FB13_3  STD         (b)     (b)
    evcntl_reg<0>         3       0     0   2     FB13_4  STD         (b)     (b)
    evcnth_reg<9>         3       0     0   2     FB13_5  STD         (b)     (b)
    evcnth_reg<8>         3       0     0   2     FB13_6  STD         (b)     (b)
    evcnth_reg<7>         3       0     0   2     FB13_7  STD         (b)     (b)
    evcnth_reg<6>         3       0     0   2     FB13_8  STD   74    I/O     (b)
    evcnth_reg<5>         3       0     0   2     FB13_9  STD         (b)     (b)
    evcnth_reg<4>         3       0     0   2     FB13_10 STD         (b)     (b)
    evcnth_reg<3>         3       0     0   2     FB13_11 STD   75    I/O     I
    evcnth_reg<2>         3       0     0   2     FB13_12 STD         (b)     (b)
    evcnth_reg<1>         3       0     0   2     FB13_13 STD         (b)     (b)
    evcnth_reg<11>        3       0     0   2     FB13_14 STD   76    I/O     I
    evcnth_reg<10>        3       0     0   2     FB13_15 STD   77    I/O     I
    evcnth_reg<0>         3       0     0   2     FB13_16 STD         (b)     (b)
    bcnt_reg<9>           3       0     0   2     FB13_17 STD   78    I/O     I
    bcnt_reg<8>           3       0     0   2     FB13_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: bcnt<0>            7: bcnt<4>           12: bcnt<9>
      2: bcnt<10>           8: bcnt<5>           13: bcnt_str
      3: bcnt<11>           9: bcnt<6>           14: evcnth_str
      4: bcnt<1>           10: bcnt<7>           15: evcntl_str
      5: bcnt<2>           11: bcnt<8>           16: reset
      6: bcnt<3>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    evcntl_reg<1>        ...X..........XX........................ 3       3
    evcntl_reg<11>       ..X...........XX........................ 3       3
    evcntl_reg<10>       .X............XX........................ 3       3
    evcntl_reg<0>        X.............XX........................ 3       3
    evcnth_reg<9>        ...........X.X.X........................ 3       3
    evcnth_reg<8>        ..........X..X.X........................ 3       3
    evcnth_reg<7>        .........X...X.X........................ 3       3
    evcnth_reg<6>        ........X....X.X........................ 3       3
    evcnth_reg<5>        .......X.....X.X........................ 3       3
    evcnth_reg<4>        ......X......X.X........................ 3       3
    evcnth_reg<3>        .....X.......X.X........................ 3       3
    evcnth_reg<2>        ....X........X.X........................ 3       3
    evcnth_reg<1>        ...X.........X.X........................ 3       3
    evcnth_reg<11>       ..X..........X.X........................ 3       3
    evcnth_reg<10>       .X...........X.X........................ 3       3
    evcnth_reg<0>        X............X.X........................ 3       3
    bcnt_reg<9>          ...........XX..X........................ 3       3
    bcnt_reg<8>          ..........X.X..X........................ 3       3
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB14 ***********************************
    Number of function block inputs used/remaining:               39/15
    Number of signals used by logic mapping into function block:  39
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   /\5   0     FB14_1              (b)     (b)
    (unused)              0       0   \/5   0     FB14_2              (b)     (b)
    iac_subadd<0>        16      11<-   0   0     FB14_3  STD   100   I/O     (b)
    (unused)              0       0   /\5   0     FB14_4              (b)     (b)
    (unused)              0       0   /\1   4     FB14_5        101   I/O     (b)
    (unused)              0       0     0   5     FB14_6        102   I/O     I
    (unused)              0       0   \/4   1     FB14_7              (b)     (b)
    db<8>                13       8<-   0   0     FB14_8  STD   103   I/O     I/O
    (unused)              0       0   /\4   1     FB14_9              (b)     (b)
    (unused)              0       0   \/5   0     FB14_10       104   I/O     I
    db<9>                14       9<-   0   0     FB14_11 STD   105   I/O     I/O
    (unused)              0       0   /\4   1     FB14_12             (b)     (b)
    (unused)              0       0     0   5     FB14_13             (b)
    int_led               1       0   \/2   2     FB14_14 STD   106   I/O     O
    seu_counter<6>/seu_counter<6>_RSTF
                          2       2<- \/5   0     FB14_15 STD   107   I/O     I
    iac_subadd<1>        16      11<-   0   0     FB14_16 STD         (b)     (b)
    (unused)              0       0   /\5   0     FB14_17             (b)     (b)
    ttc_notready_reg      9       5<- /\1   0     FB14_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<8>.PIN         14: evcnth_reg<9>     27: reg_DQ_54<8>
      2: db<9>.PIN         15: evcntl_reg<8>     28: reg_DQ_54<9>
      3: db<14>.PIN        16: evcntl_reg<9>     29: reset
      4: add<0>            17: iac_subadd<0>     30: seu_counter<5>
      5: add<1>            18: iac_subadd<1>     31: seu_counter<6>
      6: add<2>            19: qpll_error        32: sinerr_str
      7: add<3>            20: qpll_locked       33: subaddr<0>
      8: add<4>            21: reg_DQ_4E<8>      34: subaddr<1>
      9: bcnt_reg<8>       22: reg_DQ_4E<9>      35: etr
     10: bcnt_reg<9>       23: reg_DQ_50<8>      36: enw
     11: dberr_str         24: reg_DQ_50<9>      37: ttc_notready_reg
     12: dout_str          25: reg_DQ_52<8>      38: ttc_ready
     13: evcnth_reg<8>     26: reg_DQ_52<9>      39: ttc_sel_p

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    iac_subadd<0>        X..XXXXX...X....X...........X...X..X..X. 12      12
    db<8>                ...XXXXXX...X.X.X...X.X.X.X..X....X...X. 16      16
    db<9>                ...XXXXX.X...X.X.X...X.X.X.X..X...X.X.X. 17      17
    int_led              ..........X.......XX...........X.....X.. 5       5
    seu_counter<6>/seu_counter<6>_RSTF
                         ..XXXXXX....................X......X..X. 9       9
    iac_subadd<1>        .X.XXXXX...X.....X..........X....X.X..X. 12      12
    ttc_notready_reg     .X.XXXXX....................X......XXXX. 11      11
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB15 ***********************************
    Number of function block inputs used/remaining:               17/37
    Number of signals used by logic mapping into function block:  17
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB15_1              (b)
    (unused)              0       0     0   5     FB15_2        79    I/O     I
    (unused)              0       0     0   5     FB15_3        80    I/O
    (unused)              0       0     0   5     FB15_4              (b)
    reset                 1       0     0   4     FB15_5  STD         (b)     (b)
    evcntl_reg<9>         3       0     0   2     FB15_6  STD         (b)     (b)
    evcntl_reg<8>         3       0     0   2     FB15_7  STD         (b)     (b)
    evcntl_reg<7>         3       0     0   2     FB15_8  STD   81    I/O     I
    evcntl_reg<6>         3       0     0   2     FB15_9  STD         (b)     (b)
    evcntl_reg<5>         3       0     0   2     FB15_10 STD   82    I/O     I
    evcntl_reg<4>         3       0     0   2     FB15_11 STD   83    I/O     I
    evcntl_reg<3>         3       0     0   2     FB15_12 STD   85    I/O     (b)
    evcntl_reg<2>         3       0     0   2     FB15_13 STD         (b)     (b)
    add<4>                2       0     0   3     FB15_14 STD   86    I/O     I
    add<3>                2       0     0   3     FB15_15 STD   87    I/O     I
    add<2>                2       0     0   3     FB15_16 STD         (b)     (b)
    add<1>                2       0     0   3     FB15_17 STD   88    I/O     I
    add<0>                2       0     0   3     FB15_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: add_p<0>           7: bcnt<3>           13: bcnt<9>
      2: add_p<1>           8: bcnt<4>           14: evcntl_str
      3: add_p<2>           9: bcnt<5>           15: reset
      4: add_p<3>          10: bcnt<6>           16: reset_p
      5: add_p<4>          11: bcnt<7>           17: ttc_sel_p
      6: bcnt<2>           12: bcnt<8>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    reset                ...............X........................ 1       1
    evcntl_reg<9>        ............XXX......................... 3       3
    evcntl_reg<8>        ...........X.XX......................... 3       3
    evcntl_reg<7>        ..........X..XX......................... 3       3
    evcntl_reg<6>        .........X...XX......................... 3       3
    evcntl_reg<5>        ........X....XX......................... 3       3
    evcntl_reg<4>        .......X.....XX......................... 3       3
    evcntl_reg<3>        ......X......XX......................... 3       3
    evcntl_reg<2>        .....X.......XX......................... 3       3
    add<4>               ....X...........X....................... 2       2
    add<3>               ...X............X....................... 2       2
    add<2>               ..X.............X....................... 2       2
    add<1>               .X..............X....................... 2       2
    add<0>               X...............X....................... 2       2
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB16 ***********************************
    Number of function block inputs used/remaining:               39/15
    Number of signals used by logic mapping into function block:  39
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB16_1              (b)
    (unused)              0       0     0   5     FB16_2        91    I/O     I
    (unused)              0       0     0   5     FB16_3        92    I/O     I
    (unused)              0       0     0   5     FB16_4              (b)
    (unused)              0       0   \/5   0     FB16_5        93    I/O     I
    db<4>                15      10<-   0   0     FB16_6  STD   94    I/O     I/O
    (unused)              0       0   /\5   0     FB16_7              (b)     (b)
    db<2>                15      10<-   0   0     FB16_8  STD   95    I/O     I/O
    (unused)              0       0   /\5   0     FB16_9              (b)     (b)
    (unused)              0       0   /\5   0     FB16_10       96    I/O     I
    (unused)              0       0     0   5     FB16_11       97    I/O     I
    (unused)              0       0     0   5     FB16_12       98    I/O     I
    (unused)              0       0     0   5     FB16_13             (b)
    (unused)              0       0     0   5     FB16_14             (b)
    (unused)              0       0     0   5     FB16_15             (b)
    (unused)              0       0     0   5     FB16_16             (b)
    (unused)              0       0   \/4   1     FB16_17             (b)     (b)
    dberr_str_reg         9       4<-   0   0     FB16_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<6>.PIN         14: dberr_str_reg     27: reg_DQ_52<2>
      2: add<0>            15: evcnth_reg<2>     28: reg_DQ_52<4>
      3: add<1>            16: evcnth_reg<4>     29: reg_DQ_54<2>
      4: add<2>            17: evcntl_reg<2>     30: reg_DQ_54<4>
      5: add<3>            18: evcntl_reg<4>     31: reg_DQ_56<2>
      6: add<4>            19: iac_data<2>       32: reg_DQ_56<4>
      7: bcnt_reg<2>       20: iac_data<4>       33: reg_DQ_58<2>
      8: bcnt_reg<4>       21: qpll_error        34: reg_DQ_58<4>
      9: brcst1_reg<2>     22: qpll_unlocked_reg 35: reset
     10: brcst1_reg_0      23: reg_DQ_4E<2>      36: seu_counter<1>
     11: brcst2_reg<2>     24: reg_DQ_4E<4>      37: etr
     12: brcst2_reg_0      25: reg_DQ_50<2>      38: enw
     13: dberr_str         26: reg_DQ_50<4>      39: ttc_sel_p

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    db<4>                .XXXXX.XX.X.X..X.X.X...X.X.X.X.X.X.XX.X. 21      21
    db<2>                .XXXXXX..X.X..X.X.X.XXX.X.X.X.X.X...X.X. 21      21
    dberr_str_reg        XXXXXX......XX....................X..XX. 11      11
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    ;;-----------------------------------------------------------------;;
    ; Implemented Equations.

    FDCPE_add0: FDCPE port map (add(0),'0','0',add_CLR(0),add_PRE(0));
    add_CLR(0) <= (NOT ttc_sel_p AND NOT add_p(0));
    add_PRE(0) <= (NOT ttc_sel_p AND add_p(0));

    FDCPE_add1: FDCPE port map (add(1),'0','0',add_CLR(1),add_PRE(1));
    add_CLR(1) <= (NOT ttc_sel_p AND NOT add_p(1));
    add_PRE(1) <= (NOT ttc_sel_p AND add_p(1));

    FDCPE_add2: FDCPE port map (add(2),'0','0',add_CLR(2),add_PRE(2));
    add_CLR(2) <= (NOT ttc_sel_p AND NOT add_p(2));
    add_PRE(2) <= (NOT ttc_sel_p AND add_p(2));

    FDCPE_add3: FDCPE port map (add(3),'0','0',add_CLR(3),add_PRE(3));
    add_CLR(3) <= (NOT ttc_sel_p AND NOT add_p(3));
    add_PRE(3) <= (NOT ttc_sel_p AND add_p(3));

    FDCPE_add4: FDCPE port map (add(4),'0','0',add_CLR(4),add_PRE(4));
    add_CLR(4) <= (NOT ttc_sel_p AND NOT add_p(4));
    add_PRE(4) <= (NOT ttc_sel_p AND add_p(4));

    FDCPE_bcnt_reg0: FDCPE port map (bcnt_reg(0),bcnt(0),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg10: FDCPE port map (bcnt_reg(10),bcnt(10),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg11: FDCPE port map (bcnt_reg(11),bcnt(11),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg1: FDCPE port map (bcnt_reg(1),bcnt(1),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg2: FDCPE port map (bcnt_reg(2),bcnt(2),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg3: FDCPE port map (bcnt_reg(3),bcnt(3),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg4: FDCPE port map (bcnt_reg(4),bcnt(4),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg5: FDCPE port map (bcnt_reg(5),bcnt(5),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg6: FDCPE port map (bcnt_reg(6),bcnt(6),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg7: FDCPE port map (bcnt_reg(7),bcnt(7),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg8: FDCPE port map (bcnt_reg(8),bcnt(8),NOT clk,reset,'0',bcnt_str);

    FDCPE_bcnt_reg9: FDCPE port map (bcnt_reg(9),bcnt(9),NOT clk,reset,'0',bcnt_str);

    FDCPE_brcst1_reg2: FDCPE port map (brcst1_reg(2),brcst(4),NOT clk,reset,'0',brcst_str_1);

    FDCPE_brcst1_reg3: FDCPE port map (brcst1_reg(3),brcst(5),NOT clk,reset,'0',brcst_str_1);

    FDCPE_brcst1_reg4: FDCPE port map (brcst1_reg(4),brcst(6),NOT clk,reset,'0',brcst_str_1);

    FDCPE_brcst1_reg5: FDCPE port map (brcst1_reg(5),brcst(7),NOT clk,reset,'0',brcst_str_1);

    FDCPE_brcst1_reg_0: FDCPE port map (brcst1_reg_0,brcst(2),NOT clk,reset,'0',brcst_str_1);

    FDCPE_brcst1_reg_1: FDCPE port map (brcst1_reg_1,brcst(3),NOT clk,reset,'0',brcst_str_1);

    FDCPE_brcst2_reg2: FDCPE port map (brcst2_reg(2),brcst(4),NOT clk,reset,'0',brcst_str_2);

    FDCPE_brcst2_reg3: FDCPE port map (brcst2_reg(3),brcst(5),NOT clk,reset,'0',brcst_str_2);

    FDCPE_brcst2_reg4: FDCPE port map (brcst2_reg(4),brcst(6),NOT clk,reset,'0',brcst_str_2);

    FDCPE_brcst2_reg5: FDCPE port map (brcst2_reg(5),brcst(7),NOT clk,reset,'0',brcst_str_2);

    FDCPE_brcst2_reg_0: FDCPE port map (brcst2_reg_0,brcst(2),NOT clk,reset,'0',brcst_str_2);

    FDCPE_brcst2_reg_1: FDCPE port map (brcst2_reg_1,brcst(3),NOT clk,reset,'0',brcst_str_2);

    cmd(0) <= (brcst_str_1 AND brcst(2));

    cmd(1) <= rst_counter(6).EXP;

    cmd(2) <= (brcst(4) AND brcst_str_1);

    cmd(3) <= brcst2_reg_1.EXP;

    ttc_on <= '1';

    cmy <= '1';

    db_I(0) <= NOT (((EXP30_.EXP)
    	OR (EXP31_.EXP)
    	OR (NOT bcnt_reg(0) AND add(1) AND NOT add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_54(0) AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(4))
    	OR (NOT add(0) AND add(1) AND NOT add(3) AND NOT add(4) AND
    	NOT qpll_locked)
    	OR (NOT add(0) AND NOT add(2) AND NOT add(3) AND NOT add(4) AND NOT ttc_ready)));
    db(0) <= db_I(0) when db_OE(0) = '1' else 'Z';
    db_OE(0) <= (ttc_sel_p AND NOT etr);

    db_I(10) <= NOT (((EXP32_.EXP)
    	OR (EXP33_.EXP)
    	OR (NOT bcnt_reg(10) AND add(1) AND NOT add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_52(10) AND add(0) AND NOT add(2) AND add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_54(10) AND add(1) AND NOT add(2) AND add(3) AND
    	NOT add(4))
    	OR (NOT seu_counter(7) AND NOT add(0) AND add(1) AND NOT add(3) AND
    	NOT add(4))));
    db(10) <= db_I(10) when db_OE(10) = '1' else 'Z';
    db_OE(10) <= (ttc_sel_p AND NOT etr);

    db_I(11) <= NOT (((EXP48_.EXP)
    	OR (EXP49_.EXP)
    	OR (NOT bcnt_reg(11) AND add(1) AND NOT add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_4E(11) AND add(1) AND add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_50(11) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(4))
    	OR (NOT reg_DQ_54(11) AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(4))));
    db(11) <= db_I(11) when db_OE(11) = '1' else 'Z';
    db_OE(11) <= (ttc_sel_p AND NOT etr);

    db_I(12) <= NOT (((EXP65_.EXP)
    	OR (add(1) AND NOT add(2) AND NOT add(4))));
    db(12) <= db_I(12) when db_OE(12) = '1' else 'Z';
    db_OE(12) <= (ttc_sel_p AND NOT etr);

    db_I(13) <= NOT (((EXP20_.EXP)
    	OR (add(1) AND NOT add(2) AND NOT add(4))));
    db(13) <= db_I(13) when db_OE(13) = '1' else 'Z';
    db_OE(13) <= (ttc_sel_p AND NOT etr);

    db_I(14) <= NOT (EXP24_.EXP);
    db(14) <= db_I(14) when db_OE(14) = '1' else 'Z';
    db_OE(14) <= (ttc_sel_p AND NOT etr);

    db_I(15) <= NOT (((EXP52_.EXP)
    	OR (NOT iac_subadd(7) AND NOT add(2) AND NOT add(4))
    	OR (add(1) AND NOT add(2) AND NOT add(4))
    	OR (add(2) AND NOT add(3) AND NOT add(4))
    	OR (NOT add(2) AND add(3) AND NOT add(4))));
    db(15) <= db_I(15) when db_OE(15) = '1' else 'Z';
    db_OE(15) <= (ttc_sel_p AND NOT etr);

    db_I(1) <= NOT (((EXP34_.EXP)
    	OR (EXP35_.EXP)
    	OR (NOT qpll_unlocked_reg AND NOT add(0) AND add(1) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT bcnt_reg(1) AND add(1) AND NOT add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_54(1) AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(4))
    	OR (NOT add(0) AND NOT add(2) AND NOT add(3) AND NOT add(4) AND
    	NOT qpll_locked)));
    db(1) <= db_I(1) when db_OE(1) = '1' else 'Z';
    db_OE(1) <= (ttc_sel_p AND NOT etr);

    db_I(2) <= NOT (((EXP85_.EXP)
    	OR (NOT brcst1_reg_0 AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT brcst2_reg_0 AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND add(4))
    	OR (NOT evcntl_reg(2) AND NOT add(0) AND NOT add(1) AND add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT iac_data(2) AND add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))));
    db(2) <= db_I(2) when db_OE(2) = '1' else 'Z';
    db_OE(2) <= (ttc_sel_p AND NOT etr);

    db_I(3) <= NOT (((EXP46_.EXP)
    	OR (EXP47_.EXP)
    	OR (NOT brcst1_reg_1 AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT brcst2_reg_1 AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND add(4))
    	OR (NOT evcntl_reg(3) AND NOT add(0) AND NOT add(1) AND add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT iac_data(3) AND add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))));
    db(3) <= db_I(3) when db_OE(3) = '1' else 'Z';
    db_OE(3) <= (ttc_sel_p AND NOT etr);

    db_I(4) <= NOT (((EXP83_.EXP)
    	OR (EXP84_.EXP)
    	OR (NOT brcst1_reg(2) AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT brcst2_reg(2) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND add(4))
    	OR (NOT evcntl_reg(4) AND NOT add(0) AND NOT add(1) AND add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT iac_data(4) AND add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))));
    db(4) <= db_I(4) when db_OE(4) = '1' else 'Z';
    db_OE(4) <= (ttc_sel_p AND NOT etr);

    db_I(5) <= NOT (((iac_subadd(4).EXP)
    	OR (EXP62_.EXP)
    	OR (NOT brcst1_reg(3) AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT brcst2_reg(3) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND add(4))
    	OR (NOT evcntl_reg(5) AND NOT add(0) AND NOT add(1) AND add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT iac_data(5) AND add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))));
    db(5) <= db_I(5) when db_OE(5) = '1' else 'Z';
    db_OE(5) <= (ttc_sel_p AND NOT etr);

    db_I(6) <= NOT (((EXP39_.EXP)
    	OR (NOT brcst2_reg(4) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND add(4))
    	OR (NOT evcntl_reg(6) AND NOT add(0) AND NOT add(1) AND add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT iac_data(6) AND add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))));
    db(6) <= db_I(6) when db_OE(6) = '1' else 'Z';
    db_OE(6) <= (ttc_sel_p AND NOT etr);

    db_I(7) <= NOT (((EXP28_.EXP)
    	OR (EXP29_.EXP)
    	OR (NOT brcst1_reg(5) AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT brcst2_reg(5) AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND add(4))
    	OR (NOT evcntl_reg(7) AND NOT add(0) AND NOT add(1) AND add(2) AND
    	NOT add(3) AND NOT add(4))
    	OR (NOT iac_data(7) AND add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4))));
    db(7) <= db_I(7) when db_OE(7) = '1' else 'Z';
    db_OE(7) <= (ttc_sel_p AND NOT etr);

    db_I(8) <= NOT (((EXP78_.EXP)
    	OR (EXP79_.EXP)
    	OR (NOT bcnt_reg(8) AND add(1) AND NOT add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_50(8) AND NOT add(0) AND NOT add(1) AND add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_54(8) AND NOT add(0) AND add(1) AND NOT add(2) AND
    	NOT add(4))
    	OR (NOT seu_counter(5) AND NOT add(0) AND add(1) AND NOT add(3) AND
    	NOT add(4))));
    db(8) <= db_I(8) when db_OE(8) = '1' else 'Z';
    db_OE(8) <= (ttc_sel_p AND NOT etr);

    db_I(9) <= NOT (((EXP80_.EXP)
    	OR (EXP81_.EXP)
    	OR (NOT bcnt_reg(9) AND add(1) AND NOT add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT reg_DQ_52(9) AND add(0) AND NOT add(2) AND add(3) AND
    	NOT add(4))
    	OR (NOT ttc_notready_reg AND NOT add(0) AND NOT add(2) AND NOT add(3) AND
    	NOT add(4))
    	OR (NOT seu_counter(6) AND NOT add(0) AND add(1) AND NOT add(3) AND
    	NOT add(4))));
    db(9) <= db_I(9) when db_OE(9) = '1' else 'Z';
    db_OE(9) <= (ttc_sel_p AND NOT etr);

    FDCPE_dberr_str_reg: FDCPE port map (dberr_str_reg,dberr_str_reg_D,NOT clk,reset,'0');
    dberr_str_reg_D <= ((EXP87_.EXP)
    	OR (NOT dberr_str_reg AND add(0) AND NOT dberr_str)
    	OR (NOT dberr_str_reg AND add(1) AND NOT dberr_str)
    	OR (NOT dberr_str_reg AND add(2) AND NOT dberr_str)
    	OR (NOT dberr_str_reg AND add(3) AND NOT dberr_str));

    FDCPE_evcnth_reg0: FDCPE port map (evcnth_reg(0),bcnt(0),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg10: FDCPE port map (evcnth_reg(10),bcnt(10),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg11: FDCPE port map (evcnth_reg(11),bcnt(11),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg1: FDCPE port map (evcnth_reg(1),bcnt(1),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg2: FDCPE port map (evcnth_reg(2),bcnt(2),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg3: FDCPE port map (evcnth_reg(3),bcnt(3),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg4: FDCPE port map (evcnth_reg(4),bcnt(4),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg5: FDCPE port map (evcnth_reg(5),bcnt(5),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg6: FDCPE port map (evcnth_reg(6),bcnt(6),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg7: FDCPE port map (evcnth_reg(7),bcnt(7),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg8: FDCPE port map (evcnth_reg(8),bcnt(8),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcnth_reg9: FDCPE port map (evcnth_reg(9),bcnt(9),NOT clk,'0',reset,evcnth_str);

    FDCPE_evcntl_reg0: FDCPE port map (evcntl_reg(0),bcnt(0),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg10: FDCPE port map (evcntl_reg(10),bcnt(10),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg11: FDCPE port map (evcntl_reg(11),bcnt(11),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg1: FDCPE port map (evcntl_reg(1),bcnt(1),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg2: FDCPE port map (evcntl_reg(2),bcnt(2),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg3: FDCPE port map (evcntl_reg(3),bcnt(3),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg4: FDCPE port map (evcntl_reg(4),bcnt(4),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg5: FDCPE port map (evcntl_reg(5),bcnt(5),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg6: FDCPE port map (evcntl_reg(6),bcnt(6),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg7: FDCPE port map (evcntl_reg(7),bcnt(7),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg8: FDCPE port map (evcntl_reg(8),bcnt(8),NOT clk,'0',reset,evcntl_str);

    FDCPE_evcntl_reg9: FDCPE port map (evcntl_reg(9),bcnt(9),NOT clk,'0',reset,evcntl_str);

    i2c_rst <= NOT (((reset)
    	OR (ttc_sel_p AND enw AND NOT add(0) AND NOT add(1) AND NOT add(2) AND
    	NOT add(3) AND NOT add(4) AND db(14).PIN)));

    i2c_wr <= NOT enw;

    FDCPE_iac_data0: FDCPE port map (iac_data(0),iac_data_D(0),NOT clk,reset,'0');
    iac_data_D(0) <= ((EXP57_.EXP)
    	OR (EXP58_.EXP)
    	OR (dout_str AND dout(0) AND NOT add(0))
    	OR (dout_str AND dout(0) AND add(1))
    	OR (dout_str AND dout(0) AND add(2))
    	OR (dout_str AND dout(0) AND add(3)));

    FDCPE_iac_data1: FDCPE port map (iac_data(1),iac_data_D(1),NOT clk,reset,'0');
    iac_data_D(1) <= ((EXP37_.EXP)
    	OR (dout_str AND dout(1) AND NOT add(0))
    	OR (dout_str AND dout(1) AND add(1))
    	OR (dout_str AND dout(1) AND add(2)));

    FDCPE_iac_data2: FDCPE port map (iac_data(2),iac_data_D(2),NOT clk,reset,'0');
    iac_data_D(2) <= ((EXP40_.EXP)
    	OR (EXP41_.EXP)
    	OR (dout_str AND dout(2) AND NOT add(0))
    	OR (dout_str AND dout(2) AND add(1))
    	OR (dout_str AND dout(2) AND add(2))
    	OR (dout_str AND dout(2) AND add(3)));

    FDCPE_iac_data3: FDCPE port map (iac_data(3),iac_data_D(3),NOT clk,reset,'0');
    iac_data_D(3) <= ((EXP42_.EXP)
    	OR (EXP43_.EXP)
    	OR (dout_str AND dout(3) AND NOT add(0))
    	OR (dout_str AND dout(3) AND add(1))
    	OR (dout_str AND dout(3) AND add(2))
    	OR (dout_str AND dout(3) AND add(3)));

    FDCPE_iac_data4: FDCPE port map (iac_data(4),iac_data_D(4),NOT clk,reset,'0');
    iac_data_D(4) <= ((EXP25_.EXP)
    	OR (dout_str AND dout(4) AND NOT add(0))
    	OR (dout_str AND dout(4) AND add(1))
    	OR (dout_str AND dout(4) AND add(2)));

    FDCPE_iac_data5: FDCPE port map (iac_data(5),iac_data_D(5),NOT clk,reset,'0');
    iac_data_D(5) <= ((EXP63_.EXP)
    	OR (dout_str AND dout(5) AND NOT add(0))
    	OR (dout_str AND dout(5) AND add(1)));

    FDCPE_iac_data6: FDCPE port map (iac_data(6),iac_data_D(6),NOT clk,reset,'0');
    iac_data_D(6) <= ((EXP44_.EXP)
    	OR (dout_str AND dout(6) AND NOT add(0))
    	OR (dout_str AND dout(6) AND add(1))
    	OR (dout_str AND dout(6) AND add(2)));

    FDCPE_iac_data7: FDCPE port map (iac_data(7),iac_data_D(7),NOT clk,reset,'0');
    iac_data_D(7) <= ((EXP23_.EXP)
    	OR (db_out(14).EXP)
    	OR (dout_str AND dout(7) AND NOT add(0))
    	OR (dout_str AND dout(7) AND add(1))
    	OR (dout_str AND dout(7) AND add(2))
    	OR (dout_str AND dout(7) AND add(3)));

    FDCPE_iac_subadd0: FDCPE port map (iac_subadd(0),iac_subadd_D(0),NOT clk,reset,'0');
    iac_subadd_D(0) <= ((EXP75_.EXP)
    	OR (EXP76_.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(0))
    	OR (dout_str AND add(1) AND subaddr(0))
    	OR (dout_str AND add(2) AND subaddr(0))
    	OR (dout_str AND add(3) AND subaddr(0)));

    FDCPE_iac_subadd1: FDCPE port map (iac_subadd(1),iac_subadd_D(1),NOT clk,reset,'0');
    iac_subadd_D(1) <= ((seu_counter(6)/seu_counter(6)_RSTF.EXP)
    	OR (EXP82_.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(1))
    	OR (dout_str AND add(1) AND subaddr(1))
    	OR (dout_str AND add(2) AND subaddr(1))
    	OR (dout_str AND add(3) AND subaddr(1)));

    FDCPE_iac_subadd2: FDCPE port map (iac_subadd(2),iac_subadd_D(2),NOT clk,reset,'0');
    iac_subadd_D(2) <= ((EXP66_.EXP)
    	OR (cmd_3_OBUF.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(2))
    	OR (dout_str AND add(1) AND subaddr(2))
    	OR (dout_str AND add(2) AND subaddr(2))
    	OR (dout_str AND add(3) AND subaddr(2)));

    FDCPE_iac_subadd3: FDCPE port map (iac_subadd(3),iac_subadd_D(3),NOT clk,reset,'0');
    iac_subadd_D(3) <= ((EXP69_.EXP)
    	OR (EXP70_.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(3))
    	OR (dout_str AND add(1) AND subaddr(3))
    	OR (dout_str AND add(2) AND subaddr(3))
    	OR (dout_str AND add(3) AND subaddr(3)));

    FDCPE_iac_subadd4: FDCPE port map (iac_subadd(4),iac_subadd_D(4),NOT clk,reset,'0');
    iac_subadd_D(4) <= ((EXP61_.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(4)));

    FDCPE_iac_subadd5: FDCPE port map (iac_subadd(5),iac_subadd_D(5),NOT clk,reset,'0');
    iac_subadd_D(5) <= ((EXP22_.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(5))
    	OR (dout_str AND add(1) AND subaddr(5)));

    FDCPE_iac_subadd6: FDCPE port map (iac_subadd(6),iac_subadd_D(6),NOT clk,reset,'0');
    iac_subadd_D(6) <= ((EXP18_.EXP)
    	OR (EXP19_.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(6))
    	OR (dout_str AND add(1) AND subaddr(6))
    	OR (dout_str AND add(2) AND subaddr(6))
    	OR (dout_str AND add(3) AND subaddr(6)));

    FDCPE_iac_subadd7: FDCPE port map (iac_subadd(7),iac_subadd_D(7),NOT clk,reset,'0');
    iac_subadd_D(7) <= ((EXP68_.EXP)
    	OR (dout_str AND NOT add(0) AND subaddr(7))
    	OR (dout_str AND add(1) AND subaddr(7))
    	OR (dout_str AND add(2) AND subaddr(7)));

    int_led <= (NOT qpll_error AND NOT sinerr_str AND NOT dberr_str AND
    	qpll_locked AND ttc_ready);

    interrupt <= NOT ((NOT qpll_error AND NOT sinerr_str AND NOT dberr_str AND
    	qpll_locked AND ttc_ready));

    qpll_reset <= NOT ((ttc_sel_p AND enw AND db(15).PIN AND NOT add(0) AND add(1) AND
    	add(2) AND NOT add(3) AND NOT add(4)));

    FDCPE_qpll_unlocked_reg: FDCPE port map (qpll_unlocked_reg,qpll_unlocked_reg_D,NOT clk,reset,'0');
    qpll_unlocked_reg_D <= ((EXP27_.EXP)
    	OR (NOT qpll_unlocked_reg AND add(0) AND qpll_locked)
    	OR (NOT qpll_unlocked_reg AND add(1) AND qpll_locked)
    	OR (NOT qpll_unlocked_reg AND add(2) AND qpll_locked));

    FDCPE_reg_DQ_4E0: FDCPE port map (reg_DQ_4E(0),dout(0),NOT clk,reset,'0',reg_DQ_4E_CE(0));
    reg_DQ_4E_CE(0) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E10: FDCPE port map (reg_DQ_4E(10),dq(2),NOT clk,reset,'0',reg_DQ_4E_CE(10));
    reg_DQ_4E_CE(10) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E11: FDCPE port map (reg_DQ_4E(11),dq(3),NOT clk,reset,'0',reg_DQ_4E_CE(11));
    reg_DQ_4E_CE(11) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E1: FDCPE port map (reg_DQ_4E(1),dout(1),NOT clk,reset,'0',reg_DQ_4E_CE(1));
    reg_DQ_4E_CE(1) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E2: FDCPE port map (reg_DQ_4E(2),dout(2),NOT clk,reset,'0',reg_DQ_4E_CE(2));
    reg_DQ_4E_CE(2) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E3: FDCPE port map (reg_DQ_4E(3),dout(3),NOT clk,reset,'0',reg_DQ_4E_CE(3));
    reg_DQ_4E_CE(3) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E4: FDCPE port map (reg_DQ_4E(4),dout(4),NOT clk,reset,'0',reg_DQ_4E_CE(4));
    reg_DQ_4E_CE(4) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E5: FDCPE port map (reg_DQ_4E(5),dout(5),NOT clk,reset,'0',reg_DQ_4E_CE(5));
    reg_DQ_4E_CE(5) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E6: FDCPE port map (reg_DQ_4E(6),dout(6),NOT clk,reset,'0',reg_DQ_4E_CE(6));
    reg_DQ_4E_CE(6) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E7: FDCPE port map (reg_DQ_4E(7),dout(7),NOT clk,reset,'0',reg_DQ_4E_CE(7));
    reg_DQ_4E_CE(7) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E8: FDCPE port map (reg_DQ_4E(8),dq(0),NOT clk,reset,'0',reg_DQ_4E_CE(8));
    reg_DQ_4E_CE(8) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_4E9: FDCPE port map (reg_DQ_4E(9),dq(1),NOT clk,reset,'0',reg_DQ_4E_CE(9));
    reg_DQ_4E_CE(9) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_500: FDCPE port map (reg_DQ_50(0),dout(0),NOT clk,reset,'0',reg_DQ_50_CE(0));
    reg_DQ_50_CE(0) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_5010: FDCPE port map (reg_DQ_50(10),dq(2),NOT clk,reset,'0',reg_DQ_50_CE(10));
    reg_DQ_50_CE(10) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_5011: FDCPE port map (reg_DQ_50(11),dq(3),NOT clk,reset,'0',reg_DQ_50_CE(11));
    reg_DQ_50_CE(11) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_501: FDCPE port map (reg_DQ_50(1),dout(1),NOT clk,reset,'0',reg_DQ_50_CE(1));
    reg_DQ_50_CE(1) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_502: FDCPE port map (reg_DQ_50(2),dout(2),NOT clk,reset,'0',reg_DQ_50_CE(2));
    reg_DQ_50_CE(2) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_503: FDCPE port map (reg_DQ_50(3),dout(3),NOT clk,reset,'0',reg_DQ_50_CE(3));
    reg_DQ_50_CE(3) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_504: FDCPE port map (reg_DQ_50(4),dout(4),NOT clk,reset,'0',reg_DQ_50_CE(4));
    reg_DQ_50_CE(4) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_505: FDCPE port map (reg_DQ_50(5),dout(5),NOT clk,reset,'0',reg_DQ_50_CE(5));
    reg_DQ_50_CE(5) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_506: FDCPE port map (reg_DQ_50(6),dout(6),NOT clk,reset,'0',reg_DQ_50_CE(6));
    reg_DQ_50_CE(6) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_507: FDCPE port map (reg_DQ_50(7),dout(7),NOT clk,reset,'0',reg_DQ_50_CE(7));
    reg_DQ_50_CE(7) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_508: FDCPE port map (reg_DQ_50(8),dq(0),NOT clk,reset,'0',reg_DQ_50_CE(8));
    reg_DQ_50_CE(8) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_509: FDCPE port map (reg_DQ_50(9),dq(1),NOT clk,reset,'0',reg_DQ_50_CE(9));
    reg_DQ_50_CE(9) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_520: FDCPE port map (reg_DQ_52(0),dout(0),NOT clk,reset,'0',reg_DQ_52_CE(0));
    reg_DQ_52_CE(0) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_5210: FDCPE port map (reg_DQ_52(10),dq(2),NOT clk,reset,'0',reg_DQ_52_CE(10));
    reg_DQ_52_CE(10) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_5211: FDCPE port map (reg_DQ_52(11),dq(3),NOT clk,reset,'0',reg_DQ_52_CE(11));
    reg_DQ_52_CE(11) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_521: FDCPE port map (reg_DQ_52(1),dout(1),NOT clk,reset,'0',reg_DQ_52_CE(1));
    reg_DQ_52_CE(1) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_522: FDCPE port map (reg_DQ_52(2),dout(2),NOT clk,reset,'0',reg_DQ_52_CE(2));
    reg_DQ_52_CE(2) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_523: FDCPE port map (reg_DQ_52(3),dout(3),NOT clk,reset,'0',reg_DQ_52_CE(3));
    reg_DQ_52_CE(3) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_524: FDCPE port map (reg_DQ_52(4),dout(4),NOT clk,reset,'0',reg_DQ_52_CE(4));
    reg_DQ_52_CE(4) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_525: FDCPE port map (reg_DQ_52(5),dout(5),NOT clk,reset,'0',reg_DQ_52_CE(5));
    reg_DQ_52_CE(5) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_526: FDCPE port map (reg_DQ_52(6),dout(6),NOT clk,reset,'0',reg_DQ_52_CE(6));
    reg_DQ_52_CE(6) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_527: FDCPE port map (reg_DQ_52(7),dout(7),NOT clk,reset,'0',reg_DQ_52_CE(7));
    reg_DQ_52_CE(7) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_528: FDCPE port map (reg_DQ_52(8),dq(0),NOT clk,reset,'0',reg_DQ_52_CE(8));
    reg_DQ_52_CE(8) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FDCPE_reg_DQ_529: FDCPE port map (reg_DQ_52(9),dq(1),NOT clk,reset,'0',reg_DQ_52_CE(9));
    reg_DQ_52_CE(9) <= (dout_str AND dq(1) AND dq(0) AND NOT dq(3));

    FTCPE_reg_DQ_540: FTCPE port map (reg_DQ_54(0),reg_DQ_54_T(0),NOT clk,reset,'0');
    reg_DQ_54_T(0) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dout(0) AND dq(2) AND
    	NOT dq(3) AND NOT reg_DQ_54(0))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dout(0) AND NOT dq(2) AND
    	dq(3) AND NOT reg_DQ_54(0))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dout(0) AND dq(2) AND
    	NOT dq(3) AND reg_DQ_54(0))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dout(0) AND NOT dq(2) AND
    	dq(3) AND reg_DQ_54(0)));

    FTCPE_reg_DQ_5410: FTCPE port map (reg_DQ_54(10),reg_DQ_54_T(10),NOT clk,reset,'0');
    reg_DQ_54_T(10) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT reg_DQ_54(10))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	reg_DQ_54(10)));

    FTCPE_reg_DQ_5411: FTCPE port map (reg_DQ_54(11),reg_DQ_54_T(11),NOT clk,reset,'0');
    reg_DQ_54_T(11) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	reg_DQ_54(11))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT reg_DQ_54(11)));

    FTCPE_reg_DQ_541: FTCPE port map (reg_DQ_54(1),reg_DQ_54_T(1),NOT clk,reset,'0');
    reg_DQ_54_T(1) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	dout(1) AND NOT reg_DQ_54(1))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT dout(1) AND reg_DQ_54(1))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	dout(1) AND NOT reg_DQ_54(1))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT dout(1) AND reg_DQ_54(1)));

    FTCPE_reg_DQ_542: FTCPE port map (reg_DQ_54(2),reg_DQ_54_T(2),NOT clk,reset,'0');
    reg_DQ_54_T(2) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	dout(2) AND NOT reg_DQ_54(2))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT dout(2) AND reg_DQ_54(2))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	dout(2) AND NOT reg_DQ_54(2))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT dout(2) AND reg_DQ_54(2)));

    FTCPE_reg_DQ_543: FTCPE port map (reg_DQ_54(3),reg_DQ_54_T(3),NOT clk,reset,'0');
    reg_DQ_54_T(3) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	dout(3) AND NOT reg_DQ_54(3))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT dout(3) AND reg_DQ_54(3))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	dout(3) AND NOT reg_DQ_54(3))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT dout(3) AND reg_DQ_54(3)));

    FTCPE_reg_DQ_544: FTCPE port map (reg_DQ_54(4),reg_DQ_54_T(4),NOT clk,reset,'0');
    reg_DQ_54_T(4) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	dout(4) AND NOT reg_DQ_54(4))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT dout(4) AND reg_DQ_54(4))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	dout(4) AND NOT reg_DQ_54(4))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT dout(4) AND reg_DQ_54(4)));

    FTCPE_reg_DQ_545: FTCPE port map (reg_DQ_54(5),reg_DQ_54_T(5),NOT clk,reset,'0');
    reg_DQ_54_T(5) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	dout(5) AND NOT reg_DQ_54(5))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT dout(5) AND reg_DQ_54(5))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	dout(5) AND NOT reg_DQ_54(5))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT dout(5) AND reg_DQ_54(5)));

    FTCPE_reg_DQ_546: FTCPE port map (reg_DQ_54(6),reg_DQ_54_T(6),NOT clk,reset,'0');
    reg_DQ_54_T(6) <= ((reg_DQ_56(1).EXP)
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT dout(6) AND reg_DQ_54(6))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT dout(6) AND reg_DQ_54(6)));

    FTCPE_reg_DQ_547: FTCPE port map (reg_DQ_54(7),reg_DQ_54_T(7),NOT clk,reset,'0');
    reg_DQ_54_T(7) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	dout(7) AND NOT reg_DQ_54(7))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	NOT dout(7) AND reg_DQ_54(7))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	dout(7) AND NOT reg_DQ_54(7))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	NOT dout(7) AND reg_DQ_54(7)));

    FTCPE_reg_DQ_548: FTCPE port map (reg_DQ_54(8),reg_DQ_54_T(8),NOT clk,reset,'0');
    reg_DQ_54_T(8) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	reg_DQ_54(8))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	reg_DQ_54(8)));

    FTCPE_reg_DQ_549: FTCPE port map (reg_DQ_54(9),reg_DQ_54_T(9),NOT clk,reset,'0');
    reg_DQ_54_T(9) <= ((dout_str AND NOT dq(1) AND NOT dq(0) AND dq(2) AND NOT dq(3) AND
    	reg_DQ_54(9))
    	OR (dout_str AND NOT dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3) AND
    	reg_DQ_54(9)));

    FDCPE_reg_DQ_560: FDCPE port map (reg_DQ_56(0),dout(0),NOT clk,reset,'0',reg_DQ_56_CE(0));
    reg_DQ_56_CE(0) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_561: FDCPE port map (reg_DQ_56(1),dout(1),NOT clk,reset,'0',reg_DQ_56_CE(1));
    reg_DQ_56_CE(1) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_562: FDCPE port map (reg_DQ_56(2),dout(2),NOT clk,reset,'0',reg_DQ_56_CE(2));
    reg_DQ_56_CE(2) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_563: FDCPE port map (reg_DQ_56(3),dout(3),NOT clk,reset,'0',reg_DQ_56_CE(3));
    reg_DQ_56_CE(3) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_564: FDCPE port map (reg_DQ_56(4),dout(4),NOT clk,reset,'0',reg_DQ_56_CE(4));
    reg_DQ_56_CE(4) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_565: FDCPE port map (reg_DQ_56(5),dout(5),NOT clk,reset,'0',reg_DQ_56_CE(5));
    reg_DQ_56_CE(5) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_566: FDCPE port map (reg_DQ_56(6),dout(6),NOT clk,reset,'0',reg_DQ_56_CE(6));
    reg_DQ_56_CE(6) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_567: FDCPE port map (reg_DQ_56(7),dout(7),NOT clk,reset,'0',reg_DQ_56_CE(7));
    reg_DQ_56_CE(7) <= (dout_str AND NOT dq(1) AND dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_580: FDCPE port map (reg_DQ_58(0),dout(0),NOT clk,reset,'0',reg_DQ_58_CE(0));
    reg_DQ_58_CE(0) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_581: FDCPE port map (reg_DQ_58(1),dout(1),NOT clk,reset,'0',reg_DQ_58_CE(1));
    reg_DQ_58_CE(1) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_582: FDCPE port map (reg_DQ_58(2),dout(2),NOT clk,reset,'0',reg_DQ_58_CE(2));
    reg_DQ_58_CE(2) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_583: FDCPE port map (reg_DQ_58(3),dout(3),NOT clk,reset,'0',reg_DQ_58_CE(3));
    reg_DQ_58_CE(3) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_584: FDCPE port map (reg_DQ_58(4),dout(4),NOT clk,reset,'0',reg_DQ_58_CE(4));
    reg_DQ_58_CE(4) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_585: FDCPE port map (reg_DQ_58(5),dout(5),NOT clk,reset,'0',reg_DQ_58_CE(5));
    reg_DQ_58_CE(5) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_586: FDCPE port map (reg_DQ_58(6),dout(6),NOT clk,reset,'0',reg_DQ_58_CE(6));
    reg_DQ_58_CE(6) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reg_DQ_587: FDCPE port map (reg_DQ_58(7),dout(7),NOT clk,reset,'0',reg_DQ_58_CE(7));
    reg_DQ_58_CE(7) <= (dout_str AND dq(1) AND NOT dq(0) AND NOT dq(2) AND dq(3));

    FDCPE_reset: FDCPE port map (reset,reset_p,NOT clk,'0','0');

    FDCPE_reset_b: FDCPE port map (reset_b,reset_b_D,clk,'0',reset);
    reset_b_D <= ((EXP50_.EXP)
    	OR (EXP51_.EXP)
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	rst_counter(10) AND add(0))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	rst_counter(10) AND add(1))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	rst_counter(10) AND add(2))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	rst_counter(10) AND add(3)));

    FTCPE_rst_counter0: FTCPE port map (rst_counter(0),rst_counter_T(0),clk,'0',reset);
    rst_counter_T(0) <= ((EXP71_.EXP)
    	OR (ttc_sel_p AND enw AND db(15).PIN AND NOT rst_counter(0) AND
    	NOT add(0) AND NOT add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	rst_counter(10) AND add(0))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	rst_counter(10) AND add(1))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	rst_counter(10) AND add(2)));

    FTCPE_rst_counter10: FTCPE port map (rst_counter(10),rst_counter_T(10),clk,'0',reset);
    rst_counter_T(10) <= ((spare_OBUF$BUF0.EXP)
    	OR (ttc_sel_p AND enw AND db(15).PIN AND rst_counter(10) AND
    	NOT add(0) AND NOT add(1) AND NOT add(2) AND NOT add(3) AND NOT add(4))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	NOT rst_counter(10) AND add(0))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	NOT rst_counter(10) AND add(1))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	NOT rst_counter(10) AND add(2)));

    FDCPE_rst_counter1: FDCPE port map (rst_counter(1),rst_counter_D(1),clk,'0',reset);
    rst_counter_D(1) <= ((brcst1_reg_0.EXP)
    	OR (tp2_OBUF$BUF0.EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(1))
    	OR (rst_counter(0) AND rst_counter(1) AND NOT rst_counter(2))
    	OR (rst_counter(0) AND rst_counter(1) AND NOT rst_counter(3))
    	OR (rst_counter(0) AND rst_counter(1) AND NOT rst_counter(4)));

    FDCPE_rst_counter2: FDCPE port map (rst_counter(2),rst_counter_D(2),clk,'0',reset);
    rst_counter_D(2) <= ((EXP56_.EXP)
    	OR (brcst1_reg_1.EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(2))
    	OR (NOT rst_counter(1) AND NOT rst_counter(2))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	NOT rst_counter(3))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	NOT rst_counter(4)));

    FDCPE_rst_counter3: FDCPE port map (rst_counter(3),rst_counter_D(3),clk,'0',reset);
    rst_counter_D(3) <= ((brcst1_reg(2).EXP)
    	OR (EXP55_.EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(3))
    	OR (NOT rst_counter(1) AND NOT rst_counter(3))
    	OR (NOT rst_counter(2) AND NOT rst_counter(3))
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND NOT rst_counter(4)));

    FDCPE_rst_counter4: FDCPE port map (rst_counter(4),rst_counter_D(4),clk,'0',reset);
    rst_counter_D(4) <= ((cmd_1_OBUF.EXP)
    	OR (rst_counter(5).EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(4))
    	OR (NOT rst_counter(1) AND NOT rst_counter(4))
    	OR (NOT rst_counter(2) AND NOT rst_counter(4))
    	OR (NOT rst_counter(3) AND NOT rst_counter(4)));

    FDCPE_rst_counter5: FDCPE port map (rst_counter(5),rst_counter_D(5),clk,'0',reset);
    rst_counter_D(5) <= ((EXP54_.EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(5))
    	OR (NOT rst_counter(1) AND NOT rst_counter(5)));

    FDCPE_rst_counter6: FDCPE port map (rst_counter(6),rst_counter_D(6),clk,'0',reset);
    rst_counter_D(6) <= ((EXP53_.EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(6))
    	OR (NOT rst_counter(1) AND NOT rst_counter(6))
    	OR (NOT rst_counter(2) AND NOT rst_counter(6)));

    FDCPE_rst_counter7: FDCPE port map (rst_counter(7),rst_counter_D(7),clk,'0',reset);
    rst_counter_D(7) <= ((seu_counter(7).EXP)
    	OR (seu_counter(6).EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(7))
    	OR (NOT rst_counter(1) AND NOT rst_counter(7))
    	OR (NOT rst_counter(2) AND NOT rst_counter(7))
    	OR (NOT rst_counter(3) AND NOT rst_counter(7)));

    FDCPE_rst_counter8: FDCPE port map (rst_counter(8),rst_counter_D(8),clk,'0',reset);
    rst_counter_D(8) <= ((rst_counter(9).EXP)
    	OR (seu_counter(0).EXP)
    	OR (NOT rst_counter(0) AND NOT rst_counter(8))
    	OR (NOT rst_counter(1) AND NOT rst_counter(8))
    	OR (NOT rst_counter(2) AND NOT rst_counter(8))
    	OR (NOT rst_counter(3) AND NOT rst_counter(8)));

    FTCPE_rst_counter9: FTCPE port map (rst_counter(9),rst_counter_T(9),clk,'0',reset);
    rst_counter_T(9) <= ((EXP73_.EXP)
    	OR (rst_counter(0) AND rst_counter(1) AND rst_counter(2) AND
    	rst_counter(3) AND rst_counter(4) AND rst_counter(5) AND rst_counter(6) AND
    	rst_counter(7) AND rst_counter(8) AND rst_counter(9) AND
    	NOT rst_counter(10)));

    FTCPE_seu_counter0: FTCPE port map (seu_counter(0),'1',qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');

    FTCPE_seu_counter1: FTCPE port map (seu_counter(1),seu_counter(0),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');

    FTCPE_seu_counter2: FTCPE port map (seu_counter(2),seu_counter_T(2),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
    seu_counter_T(2) <= (seu_counter(0) AND seu_counter(1));

    FTCPE_seu_counter3: FTCPE port map (seu_counter(3),seu_counter_T(3),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
    seu_counter_T(3) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2));

    FTCPE_seu_counter4: FTCPE port map (seu_counter(4),seu_counter_T(4),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
    seu_counter_T(4) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2) AND
    	seu_counter(3));

    FTCPE_seu_counter5: FTCPE port map (seu_counter(5),seu_counter_T(5),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
    seu_counter_T(5) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2) AND
    	seu_counter(3) AND seu_counter(4));

    FTCPE_seu_counter6: FTCPE port map (seu_counter(6),seu_counter(5).EXP,qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');

    seu_counter(6)/seu_counter(6)_RSTF <= int_led_OBUF.EXP;

    FTCPE_seu_counter7: FTCPE port map (seu_counter(7),seu_counter_T(7),qpll_error,seu_counter(6)/seu_counter(6)_RSTF,'0');
    seu_counter_T(7) <= (seu_counter(0) AND seu_counter(1) AND seu_counter(2) AND
    	seu_counter(3) AND seu_counter(4) AND seu_counter(5) AND seu_counter(6));

    FDCPE_sinerr_str_reg: FDCPE port map (sinerr_str_reg,sinerr_str_reg_D,NOT clk,reset,'0');
    sinerr_str_reg_D <= ((EXP59_.EXP)
    	OR (NOT sinerr_str_reg AND add(0) AND NOT sinerr_str)
    	OR (NOT sinerr_str_reg AND add(1) AND NOT sinerr_str)
    	OR (NOT sinerr_str_reg AND add(2) AND NOT sinerr_str)
    	OR (NOT sinerr_str_reg AND add(3) AND NOT sinerr_str));

    spare <= '0';

    on_245 <= seu_counter(1).EXP;

    tp1 <= etr;

    i2c_rd <= etr;

    tp2 <= brcst1_reg(3).EXP;

    tp3 <= brcst_str_2;

    FDCPE_ttc_notready_reg: FDCPE port map (ttc_notready_reg,ttc_notready_reg_D,NOT clk,reset,'0');
    ttc_notready_reg_D <= ((EXP74_.EXP)
    	OR (NOT ttc_notready_reg AND add(0) AND ttc_ready)
    	OR (NOT ttc_notready_reg AND add(1) AND ttc_ready)
    	OR (NOT ttc_notready_reg AND add(2) AND ttc_ready));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ****************************  Device Pin Out ****************************

    Device : XC95288XL-6-TQ144

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 VCC                              73 VCC
      2 bcnt<11>                         74 TIE
      3 dq<2>                            75 i2c_int
      4 db<6>                            76 brcst<4>
      5 brcst_str_1                      77 bcnt<5>
      6 TIE                              78 bcnt<6>
      7 subaddr<3>                       79 subaddr<4>
      8 VCC                              80 TIE
      9 db<7>                            81 dberr_str
     10 evcntl_str                       82 brcst<6>
     11 db<0>                            83 add_p<4>
     12 TIE                              84 VCC
     13 enw                              85 TIE
     14 bcnt<10>                         86 etr
     15 db<10>                           87 add_p<2>
     16 spare                            88 subaddr<7>
     17 TIE                              89 GND
     18 GND                              90 GND
     19 db<1>                            91 dq<1>
     20 TIE                              92 dout<2>
     21 db<13>                           93 dout<3>
     22 TIE                              94 db<4>
     23 subaddr<2>                       95 db<2>
     24 db<14>                           96 brcst<7>
     25 evcnth_str                       97 bcnt<2>
     26 TIE                              98 qpll_locked
     27 i2c_rd                           99 GND
     28 dout<5>                         100 TIE
     29 GND                             101 TIE
     30 clk                             102 brcst<3>
     31 TIE                             103 db<8>
     32 qpll_error                      104 dq<3>
     33 TIE                             105 db<9>
     34 i2c_rst                         106 int_led
     35 db<3>                           107 bcnt_str
     36 GND                             108 GND
     37 VCC                             109 VCC
     38 subaddr<0>                      110 dout<0>
     39 db<11>                          111 bcnt<0>
     40 qpll_reset                      112 interrupt
     41 TIE                             113 bcnt<3>
     42 VCC                             114 GND
     43 reset_b                         115 on_245
     44 db<15>                          116 bcnt<7>
     45 TIE                             117 TIE
     46 bcnt<4>                         118 brcst<2>
     47 GND                             119 TIE
     48 ttc_ready                       120 add_p<1>
     49 i2c_wr                          121 ttc_on
     50 TIE                             122 TDO
     51 tp2                             123 GND
     52 cmd<0>                          124 dout<7>
     53 subaddr<6>                      125 sinerr_str
     54 cmd<1>                          126 db<5>
     55 VCC                             127 VCC
     56 TIE                             128 bcnt<8>
     57 cmd<2>                          129 db<12>
     58 bcnt<1>                         130 subaddr<5>
     59 dout<4>                         131 ttc_sel_p
     60 cmd<3>                          132 tp1
     61 dout<1>                         133 TIE
     62 GND                             134 dq<0>
     63 TDI                             135 dout_str
     64 cmy                             136 brcst<5>
     65 TMS                             137 add_p<0>
     66 brcst_str_2                     138 tp3
     67 TCK                             139 subaddr<1>
     68 TIE                             140 add_p<3>
     69 TIE                             141 VCC
     70 dout<6>                         142 TIE
     71 bcnt<9>                         143 reset_p
     72 GND                             144 GND

    Legend :  NC  = Not Connected, unbonded pin
             PGND = Unused I/O configured as additional Ground pin
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
             PE   = Port Enable pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc95288xl-6-TQ144
    Optimization Method                         : SPEED
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Power Mode                                  : STD
    Set Unused I/O Pin Termination              : FLOAT
    Set I/O Pin Termination                     : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Input Limit                                 : 54
    Pterm Limit                                 : 25