### Legends

Acronym | Verbose Description
--- | ---
CLK | Global Clock
GCK0 | Global clock zero
GCK1 | Global clock one
GCK2 | Global clock two
GND | Dedicated Ground Pin
GSR | Global set-reset
GTS0 | Global tristate zero (output enable)
GTS1 | Global tristate one (output enable)
GTS2 | Global tristate two (output enable)
GTS3 | Global tristate three (output enable)
I/O | Input/Output
INIT | Initial state
ISP | The use of the JTAG port to program the chip while it is powered in a system.
JTAG | IEEE Standard 1149 (JTAG) boundary-scan test standard.
KPR | Unused I/O with weak keeper (leave unconnected)
NC | Not Connected, unbonded pin
PGND | Programmable ground pin
PROHIBITED | User reserved pin
R | Reset
S | Set
TCK | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.
TDI | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.
TDO | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.
TIE | Unused I/O floating -- must tie to VCC, GND or other signal
TMS | One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.
LVCMOS | Low Voltage Complementary Metal Oxide Semiconductor 3.3 Volts
LVCMOS25 | External I/O supply voltage for LVCMOS25
LVCMOS33 | External I/O supply voltage for LVCMOS33
LVTTL | Low Voltage Transistor Transistor Logic 3.3Volts
VCCIO | External power for Inputs/Outputs
VCC | Dedicated Power Pin, Internal supply voltage for the device
WPU | Unused I/O with Internal Weak Pull Up (leave unconnected)