JDF G
// Created by Project Navigator ver 1.0
PROJECT tim_vme_v2_ago07
DESIGN tim_vme_v2_ago07
DEVFAM xc9500xl
DEVFAMTIME 0
DEVICE xc95288xl
DEVICETIME 0
DEVPKG TQ144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE VMEINT.VHD
SOURCE FFP.VHD
SOURCE FFR.VHD
SOURCE FFRP.VHD
SOURCE timvme.vhd
SOURCE VMEIFC.VHD
DEPASSOC timvme1 timvme.ucf
[STATUS-ALL]
timvme1.ngcFile=WARNINGS,1186682488
[STRATEGY-LIST]
Normal=True
