library ieee;
use ieee.std_logic_1164.all;

entity vmeifc is
	port (
	clk: in std_logic;
	iack, ack_int, dtack_int, ds0, ds1: in std_logic;
	write, brd_sel, lword: in std_logic;
	am0, am1, am3, am4, am5: in std_logic;
	etr, enw, dtack, g245: out std_logic 
	);
end vmeifc;

architecture arch of vmeifc is
component ffrp port (
	d, clk, ce, cr, pr: in std_logic;
	q: out std_logic);
end component;

signal ds_rst, q1, q2, q3, q4, q5, q8, q7, q6, q9: std_logic;
signal md, acc, d_lec, d_esc, ena_d: std_logic;
signal one, zero, not_ds0, dssync: std_logic;
--signal m_2d_29,enw1,enw2: std_logic;
--signal dtack_i,dtack_ii: std_logic;


begin
one <= '1';
zero <= '0';
-- interface (A16)
--m_2d_29 <= am0 and not am1 and am3 and not am4 and am5; --10 1x01
--md <= m_2d_29;
md <= '1' when (am0='1' and am1='0' and am3='1' and am4='0' and am5='1') else '0'; --10 1001
acc <= not brd_sel and lword and iack and md;
d_lec <= acc and     write and dssync; --ds_lec;
d_esc <= acc and not write and dssync; --ds_esc;
--Nicola vme ena_d <= q2 or q5;
ena_d <= q2 or q7;

--Nicola vme g245 <= not (ack_int or q1 or q5);
--Nicola vme etr <= not q5;
g245 <= not (ack_int or q1 or q5);
--g245 <= not (ack_int or d_esc or q5);

etr <= not q5;
--enw1 <= q2 and not q4;
enw <= q2 and not q4; --LINCO ago 07

--dtack_i <= q4 or dtack_int;
dtack <= q4 or dtack_int; --LINCO ago07

--not_ds0 <= not ds0; --LINCO ago07
not_ds0 <= not (ds0 or ds1);
--ds_rst <= ds0 or ds1;
ds_rst <= ds0 and ds1;   --LINco ago 07

fq1:  ffrp port map (clk => clk, d => one,     ce => d_esc, cr => ds_rst, pr => zero, q => q1);
--fq2:  ffrp port map (clk => clk, d => q1,      ce => one,   cr => ds_rst, pr => zero, q => q2);
-- asi esta en el esquematico 

--LINCO agos07
fq3:  ffrp port map (clk => clk, d => q1,      ce => d_esc,   cr => ds_rst, pr => zero, q => q3); 
--LINCO agos07
fq2:  ffrp port map (clk => clk, d => q3,      ce => d_esc,   cr => ds_rst, pr => zero, q => q2); 

fq4:  ffrp port map (clk => clk, d => ena_d,   ce => one,   cr => zero,   pr => zero, q => q4);
fq5:  ffrp port map (clk => clk, d => one,     ce => d_lec, cr => ds_rst, pr => zero, q => q5);
--problem Nicola vme, retraso el dtack
fq6:  ffrp port map (clk => clk, d => q5,     ce => one, cr => ds_rst, pr => zero, q => q6);
--fq7:  ffrp port map (clk => clk, d => q6,     ce => one, cr => ds_rst, pr => zero, q => q7);
fq7:  ffrp port map (clk => clk, d => q6,     ce => one, cr => ds_rst, pr => zero, q => q9);
fq9:  ffrp port map (clk => clk, d => q9,     ce => one, cr => ds_rst, pr => zero, q => q7);

fq8:  ffrp port map (clk => clk, d => not_ds0, ce => one,   cr => zero,   pr => zero, q => q8);
fds:  ffrp port map (clk => clk, d => q8,      ce => one,   cr => ds0,    pr => zero, q => dssync);

--process(clk)
--begin
--	if	clk'event and clk='1' then
--		enw2 <= enw1;
--		dtack_ii <= dtack_i;
--		dtack <= dtack_ii;
--	end if;  		
--end process;
--enw <= enw1 or enw2;	

end arch;

