### Equations

FDCPE_U1/dssync: FDCPE port map (U1/dssync,U1/q8,clk,ds0,'0');
FTCPE_U1/q1: FTCPE port map (U1/q1,U1/q1_T,clk,U1/q1_CLR,'0'); U1/q1_T <= (iack AND lword AND am3 AND NOT write AND NOT U1/q1 AND U1/dssync AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1); U1/q1_CLR <= (ds0 AND ds1);
FTCPE_U1/q2: FTCPE port map (U1/q2,U1/q2_T,clk,U1/q2_CLR,'0'); U1/q2_T <= ((iack AND lword AND am3 AND NOT write AND U1/q2 AND U1/dssync AND NOT U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1) OR (iack AND lword AND am3 AND NOT write AND NOT U1/q2 AND
U1/dssync AND U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1));
U1/q2_CLR <= (ds0 AND ds1);
FTCPE_U1/q3: FTCPE port map (U1/q3,U1/q3_T,clk,U1/q3_CLR,'0'); U1/q3_T <= ((iack AND lword AND am3 AND NOT write AND U1/q1 AND U1/dssync AND NOT U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1) OR (iack AND lword AND am3 AND NOT write AND NOT U1/q1 AND
U1/dssync AND U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1));
U1/q3_CLR <= (ds0 AND ds1);
FDCPE_U1/q4: FDCPE port map (U1/q4,U1/q4_D,clk,'0','0'); U1/q4_D <= (NOT U1/q2 AND NOT U1/q7);
FDCPE_U1/q6: FDCPE port map (U1/q6,NOT etr_p,clk,U1/q6_CLR,'0'); U1/q6_CLR <= (ds0 AND ds1);
FDCPE_U1/q7: FDCPE port map (U1/q7,U1/q9,clk,U1/q7_CLR,'0'); U1/q7_CLR <= (ds0 AND ds1);
FDCPE_U1/q8: FDCPE port map (U1/q8,U1/q8_D,clk,'0','0'); U1/q8_D <= (NOT ds0 AND NOT ds1);
FDCPE_U1/q9: FDCPE port map (U1/q9,U1/q6,clk,U1/q9_CLR,'0'); U1/q9_CLR <= (ds0 AND ds1);
FDCPE_U2/r3: FDCPE port map (U2/r3,ds0,clk,reset_p_OBUF$Q53,'0');
FDCPE_U2/r4: FDCPE port map (U2/r4,NOT intled,clk,reset_p_OBUF$Q53,'0',U2/r3);
FDCPE_U2/r5: FDCPE port map (U2/r5,NOT iackin,clk,ds0,'0');
FDCPE_U2/r6: FDCPE port map (U2/r6,U2/r5,clk,ds0,'0');
FDCPE_U2/r7: FDCPE port map (U2/r7,U2/r6,clk,ds0,'0');
FDCPE_ack_int: FDCPE port map (ack_int,ack_int_D,clk,ds0,'0',U2/r6); ack_int_D <= ((EXP29_.EXP) OR (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND U2/r4 AND add_in(0) AND add_in(1) AND add_in(2)) OR (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT iack AND
U2/r4 AND add_in(0) AND NOT add_in(1) AND add_in(2))
OR (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
U2/r4 AND NOT add_in(0) AND add_in(1) AND add_in(2)));
FDCPE_brd_sel_r: FDCPE port map (brd_sel_r,'0','0',brd_sel_r_CLR,brd_sel_r_PRE); brd_sel_r_CLR <= (ds0 AND ds1 AND NOT brd_sel); brd_sel_r_PRE <= (ds0 AND ds1 AND brd_sel);
db_I(0) <= NOT (((EXP39_.EXP) OR (db_7_IOBUFE.EXP) OR (ack_int AND NOT int_vec(0) AND brd_sel_r) OR (ack_int AND NOT int_vec(0) AND glb_add(5)) OR (ack_int AND NOT int_vec(0) AND glb_add(6))
OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT etr_p)));
db(0) <= db_I(0) when db_OE(0) = '1' else 'Z';
db_OE(0) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_I(1) <= NOT (((EXP24_.EXP) OR (ack_int AND NOT int_vec(1) AND brd_sel_r) OR (ack_int AND NOT int_vec(1) AND glb_add(5)) OR (ack_int AND NOT int_vec(1) AND glb_add(6)) OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT etr_p)));
db(1) <= db_I(1) when db_OE(1) = '1' else 'Z';
db_OE(1) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_I(2) <= NOT (((EXP20_.EXP) OR (EXP21_.EXP) OR (ack_int AND NOT int_vec(2) AND brd_sel_r) OR (ack_int AND NOT int_vec(2) AND glb_add(5)) OR (ack_int AND NOT int_vec(2) AND glb_add(6))
OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT etr_p)));
db(2) <= db_I(2) when db_OE(2) = '1' else 'Z';
db_OE(2) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_I(3) <= NOT (((EXP22_.EXP) OR (EXP23_.EXP) OR (ack_int AND NOT int_vec(3) AND brd_sel_r) OR (ack_int AND NOT int_vec(3) AND glb_add(5)) OR (ack_int AND NOT int_vec(3) AND glb_add(6))
OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT etr_p)));
db(3) <= db_I(3) when db_OE(3) = '1' else 'Z';
db_OE(3) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_I(4) <= NOT (((EXP26_.EXP) OR (EXP27_.EXP) OR (ack_int AND NOT int_vec(4) AND brd_sel_r) OR (ack_int AND NOT int_vec(4) AND glb_add(5)) OR (ack_int AND NOT int_vec(4) AND glb_add(6))
OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT etr_p)));
db(4) <= db_I(4) when db_OE(4) = '1' else 'Z';
db_OE(4) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_I(5) <= NOT (((EXP30_.EXP) OR (EXP31_.EXP) OR (ack_int AND NOT int_vec(5) AND brd_sel_r) OR (ack_int AND NOT int_vec(5) AND glb_add(5)) OR (ack_int AND NOT int_vec(5) AND glb_add(6))
OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT etr_p)));
db(5) <= db_I(5) when db_OE(5) = '1' else 'Z';
db_OE(5) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_I(6) <= NOT (((int_vec(3).EXP) OR (EXP33_.EXP) OR (ack_int AND NOT int_vec(6) AND brd_sel_r) OR (ack_int AND NOT int_vec(6) AND glb_add(5)) OR (ack_int AND NOT int_vec(6) AND glb_add(6))
OR (NOT pca_add(0) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT etr_p)));
db(6) <= db_I(6) when db_OE(6) = '1' else 'Z';
db_OE(6) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_6_IOBUFE/db_6_IOBUFE_TRST <= ((ack_int) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p) OR (NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND NOT etr_p));
db_I(7) <= NOT (((EXP40_.EXP) OR (ack_int AND NOT int_vec(7) AND brd_sel_r) OR (ack_int AND NOT int_vec(7) AND glb_add(5)) OR (ack_int AND NOT int_vec(7) AND glb_add(6)))); db(7) <= db_I(7) when db_OE(7) = '1' else 'Z';
db_OE(7) <= db_6_IOBUFE/db_6_IOBUFE_TRST;
db_I(10) <= ((EXP42_.EXP) OR (NOT ack_int AND brd_sel_r) OR (NOT ack_int AND glb_add(5)) OR (NOT ack_int AND glb_add(6)) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND etr_p));
db(10) <= db_I(10) when db_OE(10) = '1' else 'Z';
db_OE(10) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
db_I(11) <= NOT (((ack_int AND brd_sel_r) OR (ack_int AND glb_add(5)) OR (ack_int AND glb_add(6)) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p))); db(11) <= db_I(11) when db_OE(11) = '1' else 'Z';
db_OE(11) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
db_I(12) <= NOT (((ack_int AND brd_sel_r) OR (ack_int AND glb_add(5)) OR (ack_int AND glb_add(6)) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p))); db(12) <= db_I(12) when db_OE(12) = '1' else 'Z';
db_OE(12) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
db_I(13) <= NOT (((ack_int AND brd_sel_r) OR (ack_int AND glb_add(5)) OR (ack_int AND glb_add(6)) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p))); db(13) <= db_I(13) when db_OE(13) = '1' else 'Z';
db_OE(13) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
db_I(14) <= NOT (((ack_int AND brd_sel_r) OR (ack_int AND glb_add(5)) OR (ack_int AND glb_add(6)) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p))); db(14) <= db_I(14) when db_OE(14) = '1' else 'Z';
db_OE(14) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
db_I(15) <= NOT (((ack_int AND brd_sel_r) OR (ack_int AND glb_add(5)) OR (ack_int AND glb_add(6)) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p))); db(15) <= db_I(15) when db_OE(15) = '1' else 'Z';
db_OE(15) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
db_I(8) <= ((EXP36_.EXP) OR (EXP37_.EXP) OR (NOT ack_int AND brd_sel_r) OR (NOT ack_int AND glb_add(5)) OR (NOT ack_int AND glb_add(6))
OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND etr_p));
db(8) <= db_I(8) when db_OE(8) = '1' else 'Z';
db_OE(8) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
db_I(9) <= ((EXP38_.EXP) OR (NOT ack_int AND brd_sel_r) OR (NOT ack_int AND glb_add(5)) OR (NOT ack_int AND glb_add(6)) OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND etr_p));
db(9) <= db_I(9) when db_OE(9) = '1' else 'Z';
db_OE(9) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);
dtack <= NOT ((NOT dtack_int AND NOT U1/q4));
FDCPE_dtack_int: FDCPE port map (dtack_int,dtack_int_D,clk,ds0,'0',U2/r7); dtack_int_D <= ((EXP28_.EXP) OR (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND U2/r4 AND add_in(0) AND add_in(1) AND add_in(2)) OR (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT iack AND
U2/r4 AND add_in(0) AND NOT add_in(1) AND add_in(2))
OR (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
U2/r4 AND NOT add_in(0) AND add_in(1) AND add_in(2)));
FTCPE_etr_p: FTCPE port map (etr_p,etr_p_T,clk,'0',etr_p_PRE); etr_p_T <= (iack AND lword AND am3 AND write AND U1/dssync AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1 AND etr_p); etr_p_PRE <= (ds0 AND ds1);
g245 <= (NOT ack_int AND NOT U1/q1 AND etr_p);
FDCPE_pca_add0: FDCPE port map (pca_add(0),'0','0',pca_add_CLR(0),pca_add_PRE(0)); pca_add_CLR(0) <= (ds0 AND ds1 AND NOT add_in(0)); pca_add_PRE(0) <= (ds0 AND ds1 AND add_in(0));
FDCPE_pca_add1: FDCPE port map (pca_add(1),'0','0',pca_add_CLR(1),pca_add_PRE(1)); pca_add_CLR(1) <= (ds0 AND ds1 AND NOT add_in(1)); pca_add_PRE(1) <= (ds0 AND ds1 AND add_in(1));
FDCPE_glb_add2: FDCPE port map (glb_add(2),'0','0',glb_add_CLR(2),glb_add_PRE(2)); glb_add_CLR(2) <= (ds0 AND ds1 AND NOT add_in(2)); glb_add_PRE(2) <= (ds0 AND ds1 AND add_in(2));
FDCPE_glb_add3: FDCPE port map (glb_add(3),'0','0',glb_add_CLR(3),glb_add_PRE(3)); glb_add_CLR(3) <= (ds0 AND ds1 AND NOT add_in(3)); glb_add_PRE(3) <= (ds0 AND ds1 AND add_in(3));
FDCPE_glb_add4: FDCPE port map (glb_add(4),'0','0',glb_add_CLR(4),glb_add_PRE(4)); glb_add_CLR(4) <= (ds0 AND ds1 AND NOT add_in(4)); glb_add_PRE(4) <= (ds0 AND ds1 AND add_in(4));
FDCPE_glb_add5: FDCPE port map (glb_add(5),'0','0',glb_add_CLR(5),glb_add_PRE(5)); glb_add_CLR(5) <= (ds0 AND ds1 AND NOT add_in(5)); glb_add_PRE(5) <= (ds0 AND ds1 AND add_in(5));
FDCPE_glb_add6: FDCPE port map (glb_add(6),'0','0',glb_add_CLR(6),glb_add_PRE(6)); glb_add_CLR(6) <= (ds0 AND ds1 AND NOT add_in(6)); glb_add_PRE(6) <= (ds0 AND ds1 AND add_in(6));
i2c_ce0 <= NOT ((NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6)));
i2c_ce1 <= NOT ((glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6)));
i2c_rd <= NOT ((NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT etr_p));
i2c_rst <= NOT (((NOT sysreset) OR (db(6).PIN AND U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT U1/q4) OR (U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4 AND db(15).PIN)));
i2c_wr <= NOT ((U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4));
FDCPE_iackout: FDCPE port map (iackout,iackout_D,clk,'0',as,U2/r7); iackout_D <= ((tp1_OBUF.EXP) OR (EXP32_.EXP) OR (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND U2/r4 AND add_in(0) AND add_in(1) AND add_in(2))
OR (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT iack AND
U2/r4 AND add_in(0) AND NOT add_in(1) AND add_in(2))
OR (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
U2/r4 AND NOT add_in(0) AND add_in(1) AND add_in(2)));
FDCPE_int_ena: FDCPE port map (int_ena,int_ena_D,clk,reset_p_OBUF$Q53,'0'); int_ena_D <= ((int_vec(0).EXP) OR (EXP18_.EXP) OR (NOT U1/q2 AND int_ena AND intled) OR (int_ena AND brd_sel_r AND intled)
OR (int_ena AND glb_add(5) AND intled)
OR (int_ena AND glb_add(6) AND intled));
FDCPE_int_lev0: FDCPE port map (int_lev(0),db(8).PIN,clk,'0',reset_p_OBUF$Q53,int_lev_CE(0)); int_lev_CE(0) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_lev1: FDCPE port map (int_lev(1),db(9).PIN,clk,reset_p_OBUF$Q53,'0',int_lev_CE(1)); int_lev_CE(1) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_lev2: FDCPE port map (int_lev(2),db(10).PIN,clk,reset_p_OBUF$Q53,'0',int_lev_CE(2)); int_lev_CE(2) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec0: FDCPE port map (int_vec(0),db(0).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(0)); int_vec_CE(0) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec1: FDCPE port map (int_vec(1),db(1).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(1)); int_vec_CE(1) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec2: FDCPE port map (int_vec(2),db(2).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(2)); int_vec_CE(2) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec3: FDCPE port map (int_vec(3),db(3).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(3)); int_vec_CE(3) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec4: FDCPE port map (int_vec(4),db(4).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(4)); int_vec_CE(4) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec5: FDCPE port map (int_vec(5),db(5).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(5)); int_vec_CE(5) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec6: FDCPE port map (int_vec(6),db(6).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(6)); int_vec_CE(6) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_int_vec7: FDCPE port map (int_vec(7),db(7).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(7)); int_vec_CE(7) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
NOT glb_add(6) AND NOT U1/q4);
FDCPE_intled: FDCPE port map (intled,intled_D,clk,'0',reset_p_OBUF$Q53); intled_D <= ((NOT dtack_int AND NOT intled) OR (NOT dtack_int AND int_ena AND int_ttc));
irq(1) <= (int_lev(0) AND NOT int_lev(1) AND NOT int_lev(2) AND NOT intled);
irq(2) <= (NOT int_lev(0) AND int_lev(1) AND NOT int_lev(2) AND NOT intled);
irq(3) <= (int_lev(0) AND int_lev(1) AND NOT int_lev(2) AND NOT intled);
irq(4) <= (NOT int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT intled);
irq(5) <= (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT intled);
irq(6) <= (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT intled);
irq(7) <= (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT intled);
FDCPE_local_clk_reg: FDCPE port map (local_clk_reg,local_clk_reg_D,clk,reset_p_OBUF$Q53,'0'); local_clk_reg_D <= ((EXP19_.EXP) OR (U1/q6.EXP) OR (NOT local_clk_reg AND NOT U1/q2 AND NOT local_clk) OR (NOT local_clk_reg AND brd_sel_r AND NOT local_clk)
OR (NOT local_clk_reg AND glb_add(5) AND NOT local_clk)
OR (NOT local_clk_reg AND glb_add(6) AND NOT local_clk));
spare <= '0';
on245 <= '0';
pca_db_I(0) <= db(0).PIN; pca_db(0) <= pca_db_I(0) when pca_db_OE(0) = '1' else 'Z'; pca_db_OE(0) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
pca_db_I(1) <= db(1).PIN; pca_db(1) <= pca_db_I(1) when pca_db_OE(1) = '1' else 'Z'; pca_db_OE(1) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
pca_db_I(2) <= db(2).PIN; pca_db(2) <= pca_db_I(2) when pca_db_OE(2) = '1' else 'Z'; pca_db_OE(2) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
pca_db_I(3) <= db(3).PIN; pca_db(3) <= pca_db_I(3) when pca_db_OE(3) = '1' else 'Z'; pca_db_OE(3) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
pca_db_I(4) <= db(4).PIN; pca_db(4) <= pca_db_I(4) when pca_db_OE(4) = '1' else 'Z'; pca_db_OE(4) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
pca_db_I(5) <= db(5).PIN; pca_db(5) <= pca_db_I(5) when pca_db_OE(5) = '1' else 'Z'; pca_db_OE(5) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
pca_db_I(6) <= db(6).PIN; pca_db(6) <= pca_db_I(6) when pca_db_OE(6) = '1' else 'Z'; pca_db_OE(6) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
pca_db_I(7) <= db(7).PIN; pca_db(7) <= pca_db_I(7) when pca_db_OE(7) = '1' else 'Z'; pca_db_OE(7) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);
reset_p <= ((NOT sysreset) OR (U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT U1/q4 AND db(15).PIN));
reset_p_OBUF$Q53 <= ((NOT sysreset) OR (U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT U1/q4 AND db(15).PIN));
tp1 <= (U1/q2 AND NOT U1/q4);
enw_p <= (U1/q2 AND NOT U1/q4);
tp3 <= NOT ((NOT db(15).PIN AND NOT db(14).PIN AND NOT db(13).PIN AND NOT db(12).PIN AND NOT db(11).PIN));
ttc_sel <= ((NOT ds0 AND NOT brd_sel_r AND glb_add(5) AND NOT glb_add(6)) OR (NOT ds1 AND NOT brd_sel_r AND glb_add(5) AND NOT glb_add(6)));
w245 <= write;
FDCPE_was_off: FDCPE port map (was_off,was_off_D,clk,reset_p_OBUF$Q53,'0'); was_off_D <= ((EXP34_.EXP) OR (EXP35_.EXP) OR (NOT was_off AND NOT U1/q2 AND ttc_on) OR (NOT was_off AND brd_sel_r AND ttc_on)
OR (NOT was_off AND glb_add(5) AND ttc_on)
OR (NOT was_off AND glb_add(6) AND ttc_on));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);