library ieee;
use ieee.std_logic_1164.all;

entity vmeint is
	port (
	--interrupt
	interrupt, int_ena: in std_logic;  
	add, int_lev: in std_logic_vector(2 downto 0);
	iack, iackin, ds0, as, reset, clk: in std_logic;
	etr_ivec, rst_int, iackout: out std_logic;
	dtack_int, ack_int: out std_logic;
	irq: out std_logic_vector(7 downto 1)); 
end vmeint;

architecture arch of vmeint is

component ffr port (
	d, clk, ce, cr: in std_logic;
	q: out std_logic);
end component;

component ffp port (
	d, clk, ce, pr: in std_logic;
	q: out std_logic);
end component;

signal r1, r2, r3, r4, r5, r6, r7, r8, r9: std_logic;
signal y, int_sel, s1, s2, s3, one: std_logic;
begin

one <= '1';

-- interrupt
y <= interrupt and int_ena; 

ack_int <= r1;
int_sel <= '1' when add=int_lev and iack='0' else '0'; 
s1 <= int_sel and r4;
s2 <= not r2 and (r9 or y);
s3 <= not iackin;

etr_ivec <= not r1;
rst_int <= r9;
dtack_int <= r2;
iackout <= r8;
irq(1) <= r9 when int_lev="001" else '0';
irq(2) <= r9 when int_lev="010" else '0';
irq(3) <= r9 when int_lev="011" else '0';
irq(4) <= r9 when int_lev="100" else '0';
irq(5) <= r9 when int_lev="101" else '0';
irq(6) <= r9 when int_lev="110" else '0';
irq(7) <= r9 when int_lev="111" else '0';

fr1:  ffr port map (clk => clk, d => s1,  ce => r6,  cr => ds0,   q => r1);
fr2:  ffr port map (clk => clk, d => s1,  ce => r7,  cr => ds0,   q => r2);
fr3:  ffr port map (clk => clk, d => ds0, ce => one, cr => reset, q => r3);
fr4:  ffr port map (clk => clk, d => r9,  ce => r3,  cr => reset, q => r4);
fr5:  ffr port map (clk => clk, d => s3,  ce => one, cr => ds0,   q => r5);
fr6:  ffr port map (clk => clk, d => r5,  ce => one, cr => ds0,   q => r6);
fr7:  ffr port map (clk => clk, d => r6,  ce => one, cr => ds0,   q => r7);
fr8:  ffp port map (clk => clk, d => s1,  ce => r7,  pr => as,    q => r8);
fr9:  ffr port map (clk => clk, d => s2,  ce => one, cr => reset, q => r9);

end arch;
	
