    cpldfit:  version G.35                              Xilinx Inc.
                                      Fitter Report
    Design Name: timvme1                             Date:  8- 9-2007,  8:01PM
    Device Used: XC95288XL-6-TQ144
    Fitting Status: Successful

    ****************************  Resource Summary  ****************************

    Macrocells     Product Terms    Registers      Pins           Function Block
    Used           Used             Used           Used           Inputs Used
    89 /288 ( 31%) 326 /1440 ( 23%) 41 /288 ( 14%) 77 /117 ( 66%) 315/864 ( 36%)

    PIN RESOURCES:

    Signal Type    Required     Mapped  |  Pin Type            Used   Remaining
    ------------------------------------|---------------------------------------
    Input         :   25          25    |  I/O              :    72       37
    Output        :   27          27    |  GCK/IO           :     1        2
    Bidirectional :   24          24    |  GTS/IO           :     3        1
    GCK           :    1           1    |  GSR/IO           :     1        0
    GTS           :    0           0    |
    GSR           :    0           0    |
                     ----        ----
            Total     77          77

    MACROCELL RESOURCES:

    Total Macrocells Available                   288
    Registered Macrocells                         41
    Non-registered Macrocell driving I/O          46

    GLOBAL RESOURCES:

    Signal 'clk' mapped onto global clock net GCK1.
    Global output enable net(s) unused.
    Global set/reset net(s) unused.

    POWER DATA:

    There are 89 macrocells in high performance mode (MCHP).
    There are 0 macrocells in low power mode (MCLP).
    There are a total of 89 macrocells used (MC).

    End of Resource Summary
    *************** Summary of Required Resources ******************

    ** LOGIC **
    Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
    Name                Pt      Used            Mode Rate #    Type      Use       State
    U1/dssync           2       2       FB4_16  STD            (b)       (b)       RESET
    U1/q1               2       13      FB12_16 STD            (b)       (b)       RESET
    U1/q2               3       14      FB12_18 STD            (b)       (b)       RESET
    U1/q3               3       14      FB12_17 STD            (b)       (b)       RESET
    U1/q4               1       2       FB4_15  STD            (b)       (b)       RESET
    U1/q6               2       3       FB2_17  STD       19   I/O       (b)       RESET
    U1/q7               2       3       FB12_15 STD            (b)       (b)       RESET
    U1/q8               1       2       FB2_15  STD       17   I/O       (b)       RESET
    U1/q9               2       3       FB12_14 STD            (b)       (b)       RESET
    U2/r3               2       2       FB2_16  STD            (b)       (b)       RESET
    U2/r4               3       3       FB4_18  STD            (b)       (b)       RESET
    U2/r5               2       2       FB3_12  STD       31   I/O       (b)       RESET
    U2/r6               2       2       FB8_14  STD            (b)       (b)       RESET
    U2/r7               2       2       FB8_1   STD            (b)       (b)       RESET
    ack_int             10      10      FB8_18  STD            (b)       (b)       RESET
    brd_sel_r           2       3       FB3_18  STD            (b)       (b)       RESET
    db<0>               11      14      FB16_2  STD  FAST 91   I/O       I/O
    db<10>              6       11      FB16_10 STD  FAST 96   I/O       I/O
    db<11>              5       5       FB6_14  STD  FAST 142  I/O       I/O
    db<12>              5       5       FB4_6   STD  FAST 4    I/O       I/O
    db<13>              5       5       FB2_12  STD  FAST 15   I/O       I/O
    db<14>              5       5       FB1_6   STD  FAST 21   I/O       I/O
    db<15>              5       5       FB13_14 STD  FAST 76   I/O       I/O
    db<1>               11      14      FB5_14  STD  FAST 41   I/O       I/O
    db<2>               11      14      FB5_2   STD  FAST 34   I/O       I/O
    db<3>               11      14      FB5_12  STD  FAST 40   I/O       I/O
    db<4>               11      14      FB7_3   STD  FAST 45   I/O       I/O
    db<5>               11      14      FB9_3   STD  FAST 51   I/O       I/O
    db<6>               11      13      FB13_2  STD  FAST 71   I/O       I/O
    db<7>               11      14      FB16_3  STD  FAST 92   I/O       I/O
    db<8>               7       12      FB14_3  STD  FAST 100  I/O       I/O
    db<9>               6       11      FB14_10 STD  FAST 104  I/O       I/O
    db_6_IOBUFE/db_6_IOBUFE_TRST                    3       8       FB9_18  STD            (b)       (b)
    dtack               1       2       FB12_5  STD  FAST 112  I/O       O
    dtack_int           10      10      FB8_16  STD            (b)       (b)       RESET
    enw_p               1       2       FB12_10 STD  FAST 115  I/O       O
    etr_p               2       13      FB10_17 STD  FAST 129  I/O       O         SET
    g245                1       3       FB15_3  STD  FAST 80   I/O       O
    glb_add<2>          2       3       FB3_17  STD            (b)       (b)       RESET
    glb_add<3>          2       3       FB3_16  STD            (b)       (b)       RESET
    glb_add<4>          2       3       FB3_15  STD       33   I/O       I         RESET
    glb_add<5>          2       3       FB3_14  STD       32   GCK/I/O   (b)       RESET
    glb_add<6>          2       3       FB3_13  STD            (b)       (b)       RESET
    i2c_ce0             1       6       FB2_2   STD  FAST 9    I/O       O
    i2c_ce1             1       6       FB1_12  STD  FAST 24   I/O       O
    i2c_rd              1       7       FB8_5   STD  FAST 132  I/O       O
    i2c_rst             3       13      FB1_10  STD  FAST 23   I/O       O
    i2c_wr              1       8       FB10_8  STD  FAST 121  I/O       O
    iackout             10      10      FB10_12 STD  FAST 126  I/O       O         RESET
    int_ena             12      14      FB1_17  STD       27   I/O       (b)       RESET
    int_lev<0>          3       12      FB7_18  STD            (b)       (b)       RESET
    int_lev<1>          3       12      FB6_18  STD            (b)       (b)       RESET
    int_lev<2>          3       12      FB11_18 STD            (b)       (b)       RESET
    int_vec<0>          3       12      FB1_16  STD            (b)       (b)       RESET
    int_vec<1>          3       12      FB11_16 STD            (b)       (b)       RESET
    int_vec<2>          3       12      FB11_15 STD            (b)       (b)       RESET
    int_vec<3>          3       12      FB13_1  STD            (b)       (b)       RESET
    int_vec<4>          3       12      FB6_17  STD            (b)       (b)       RESET
    int_vec<5>          3       12      FB7_17  STD            (b)       (b)       RESET
    int_vec<6>          3       12      FB1_1   STD            (b)       (b)       RESET
    int_vec<7>          3       12      FB4_17  STD            (b)       (b)       RESET
    intled              3       5       FB14_14 STD  FAST 106  I/O       O         SET
    irq<1>              1       4       FB9_5   STD  FAST 52   I/O       O
    irq<2>              1       4       FB9_6   STD  FAST 53   I/O       O
    irq<3>              1       4       FB11_14 STD  FAST 69   I/O       O
    irq<4>              1       4       FB6_6   STD  FAST 138  I/O       O
    irq<5>              1       4       FB9_11  STD  FAST 56   I/O       O
    irq<6>              1       4       FB9_14  STD  FAST 58   I/O       O
    irq<7>              1       4       FB11_5  STD  FAST 61   I/O       O
    local_clk_reg       12      14      FB2_18  STD            (b)       (b)       RESET
    on245               0       0       FB5_5   STD  FAST 35   I/O       O
    pca_add<0>          2       3       FB14_6  STD  FAST 102  I/O       O         RESET
    pca_add<1>          2       3       FB16_11 STD  FAST 97   I/O       O         RESET
    pca_db<0>           2       9       FB1_8   STD  FAST 22   I/O       I/O
    pca_db<1>           2       9       FB5_10  STD  FAST 39   I/O       I/O
    pca_db<2>           2       9       FB11_17 STD  FAST 70   I/O       I/O
    pca_db<3>           2       9       FB16_6  STD  FAST 94   I/O       I/O
    pca_db<4>           2       9       FB6_3   STD  FAST 136  I/O       I/O
    pca_db<5>           2       9       FB7_5   STD  FAST 46   I/O       I/O
    pca_db<6>           2       9       FB11_12 STD  FAST 68   I/O       I/O
    pca_db<7>           2       9       FB15_8  STD  FAST 81   I/O       I/O
    reset_p             2       12      FB1_14  STD  FAST 25   I/O       O
    reset_p_OBUF$Q53    2       12      FB15_18 STD            (b)       (b)
    spare               0       0       FB9_17  STD  FAST 59   I/O       O
    tp1                 1       2       FB10_11 STD  FAST 125  I/O       O
    tp3                 1       5       FB15_15 STD  FAST 87   I/O       O
    ttc_sel             2       5       FB2_5   STD  FAST 11   I/O       O
    w245                1       1       FB2_10  STD  FAST 14   I/O       O
    was_off             12      14      FB13_17 STD       78   I/O       (b)       RESET

    ** INPUTS **
    Signal                              Loc               Pin  Pin       Pin
    Name                                                  #    Type      Use
    add_in<0>                           FB11_3            60   I/O       I
    add_in<1>                           FB15_10           82   I/O       I
    add_in<2>                           FB13_15           77   I/O       I
    add_in<3>                           FB3_15            33   I/O       I
    add_in<4>                           FB10_10           124  I/O       I
    add_in<5>                           FB10_3            118  I/O       I
    add_in<6>                           FB2_3             10   I/O       I
    am0                                 FB1_5             20   I/O       I
    am1                                 FB4_2             2    GTS/I/O   I
    am3                                 FB6_2             135  I/O       I
    am4                                 FB6_8             139  I/O       I
    am5                                 FB2_6             12   I/O       I
    as                                  FB10_5            119  I/O       I
    brd_sel                             FB4_12            6    GTS/I/O   I
    clk                                 FB3_10            30   GCK/I/O   GCK
    ds0                                 FB6_15            143  GSR/I/O   I
    ds1                                 FB14_8            103  I/O       I
    i2c_int                             FB8_3             131  I/O       I
    iack                                FB8_2             130  I/O       I
    iackin                              FB14_11           105  I/O       I
    int_ttc                             FB15_14           86   I/O       I
    local_clk                           FB3_2             28   I/O       I
    lword                               FB12_8            113  I/O       I
    sysreset                            FB4_5             3    GTS/I/O   I
    ttc_on                              FB12_12           116  I/O       I
    write                               FB15_2            79   I/O       I

    End of Resources

    *********************Function Block Resource Summary***********************
    Function    # of        FB Inputs   Signals     Total       O/IO      IO
    Block       Macrocells  Used        Used        Pt Used     Req       Avail
    FB1           8          19          19           31         3/2        8
    FB2           8          19          19           26         3/1       10
    FB3           7           9           9           14         0/0        5
    FB4           5          19          19           14         0/1        6
    FB5           5          23          23           35         1/4        8
    FB6           5          19          19           14         1/2        8
    FB7           4          19          19           19         0/2        4
    FB8           5          19          19           25         1/0        5
    FB9           7          18          18           18         5/1        9
    FB10          4          29          29           14         4/0       10
    FB11          7          19          19           15         2/2        7
    FB12          7          19          19           14         2/0        6
    FB13          4          19          19           31         0/2        6
    FB14          4          21          21           18         2/2        8
    FB15          4          20          20            6         2/1        9
    FB16          5          24          24           32         1/4        8
                ----                                -----       -----     -----
                 89                                  326        27/24     117
    *********************************** FB1 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    int_vec<6>            3       0     0   2     FB1_1   STD         (b)     (b)
    (unused)              0       0     0   5     FB1_2               (b)
    (unused)              0       0     0   5     FB1_3               (b)
    (unused)              0       0     0   5     FB1_4               (b)
    (unused)              0       0     0   5     FB1_5         20    I/O     I
    db<14>                5       0     0   0     FB1_6   STD   21    I/O     I/O
    (unused)              0       0     0   5     FB1_7               (b)
    pca_db<0>             2       0     0   3     FB1_8   STD   22    I/O     I/O
    (unused)              0       0     0   5     FB1_9               (b)
    i2c_rst               3       0     0   2     FB1_10  STD   23    I/O     O
    (unused)              0       0     0   5     FB1_11              (b)
    i2c_ce1               1       0     0   4     FB1_12  STD   24    I/O     O
    (unused)              0       0     0   5     FB1_13              (b)
    reset_p               2       0     0   3     FB1_14  STD   25    I/O     O
    (unused)              0       0     0   5     FB1_15        26    I/O
    int_vec<0>            3       0   \/2   0     FB1_16  STD         (b)     (b)
    int_ena              12       7<-   0   0     FB1_17  STD   27    I/O     (b)
    (unused)              0       0   /\5   0     FB1_18              (b)     (b)

    Signals Used by Logic in Function Block
      1: db<15>.PIN         8: glb_add<3>        14: pca_add<0>
      2: U1/q2              9: glb_add<4>        15: pca_add<1>
      3: U1/q4             10: glb_add<5>        16: db<0>.PIN
      4: ack_int           11: glb_add<6>        17: db<6>.PIN
      5: brd_sel_r         12: int_ena           18: reset_p_OBUF$Q53
      6: etr_p             13: intled            19: sysreset
      7: glb_add<2>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    int_vec<6>           .XX.X.XXXXX..XX.XX...................... 12      12
    db<14>               ...XXX...XX............................. 5       5
    pca_db<0>            .XX.X.XXXXX....X........................ 9       9
    i2c_rst              XXX.X.XXXXX..XX.X.X..................... 13      13
    i2c_ce1              ....X.XXXXX............................. 6       6
    reset_p              XXX.X.XXXXX..XX...X..................... 12      12
    int_vec<0>           .XX.X.XXXXX..XXX.X...................... 12      12
    int_ena              .XX.X.XXXXXXXXXX.X...................... 14      14
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB2 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   /\5   0     FB2_1               (b)     (b)
    i2c_ce0               1       0     0   4     FB2_2   STD   9     I/O     O
    (unused)              0       0     0   5     FB2_3         10    I/O     I
    (unused)              0       0     0   5     FB2_4               (b)
    ttc_sel               2       0     0   3     FB2_5   STD   11    I/O     O
    (unused)              0       0     0   5     FB2_6         12    I/O     I
    (unused)              0       0     0   5     FB2_7               (b)
    (unused)              0       0     0   5     FB2_8         13    I/O
    (unused)              0       0     0   5     FB2_9               (b)
    w245                  1       0     0   4     FB2_10  STD   14    I/O     O
    (unused)              0       0     0   5     FB2_11              (b)
    db<13>                5       0     0   0     FB2_12  STD   15    I/O     I/O
    (unused)              0       0     0   5     FB2_13              (b)
    (unused)              0       0     0   5     FB2_14        16    I/O
    U1/q8                 1       0     0   4     FB2_15  STD   17    I/O     (b)
    U2/r3                 2       0     0   3     FB2_16  STD         (b)     (b)
    U1/q6                 2       0   \/2   1     FB2_17  STD   19    I/O     (b)
    local_clk_reg        12       7<-   0   0     FB2_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<8>.PIN          8: etr_p             14: local_clk
      2: U1/q2              9: glb_add<2>        15: local_clk_reg
      3: U1/q4             10: glb_add<3>        16: pca_add<0>
      4: ack_int           11: glb_add<4>        17: pca_add<1>
      5: brd_sel_r         12: glb_add<5>        18: reset_p_OBUF$Q53
      6: ds0               13: glb_add<6>        19: write
      7: ds1

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    i2c_ce0              ....X...XXXXX........................... 6       6
    ttc_sel              ....XXX....XX........................... 5       5
    w245                 ..................X..................... 1       1
    db<13>               ...XX..X...XX........................... 5       5
    U1/q8                .....XX................................. 2       2
    U2/r3                .....X...........X...................... 2       2
    U1/q6                .....XXX................................ 3       3
    local_clk_reg        XXX.X...XXXXXXXXXX...................... 14      14
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB3 ***********************************
    Number of function block inputs used/remaining:               9/45
    Number of signals used by logic mapping into function block:  9
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB3_1               (b)
    (unused)              0       0     0   5     FB3_2         28    I/O     I
    (unused)              0       0     0   5     FB3_3               (b)
    (unused)              0       0     0   5     FB3_4               (b)
    (unused)              0       0     0   5     FB3_5               (b)
    (unused)              0       0     0   5     FB3_6               (b)
    (unused)              0       0     0   5     FB3_7               (b)
    (unused)              0       0     0   5     FB3_8               (b)
    (unused)              0       0     0   5     FB3_9               (b)
    (unused)              0       0     0   5     FB3_10        30    GCK/I/O GCK
    (unused)              0       0     0   5     FB3_11              (b)
    U2/r5                 2       0     0   3     FB3_12  STD   31    I/O     (b)
    glb_add<6>            2       0     0   3     FB3_13  STD         (b)     (b)
    glb_add<5>            2       0     0   3     FB3_14  STD   32    GCK/I/O (b)
    glb_add<4>            2       0     0   3     FB3_15  STD   33    I/O     I
    glb_add<3>            2       0     0   3     FB3_16  STD         (b)     (b)
    glb_add<2>            2       0     0   3     FB3_17  STD         (b)     (b)
    brd_sel_r             2       0     0   3     FB3_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: add_in<2>          4: add_in<5>          7: ds0
      2: add_in<3>          5: add_in<6>          8: ds1
      3: add_in<4>          6: brd_sel            9: iackin

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    U2/r5                ......X.X............................... 2       2
    glb_add<6>           ....X.XX................................ 3       3
    glb_add<5>           ...X..XX................................ 3       3
    glb_add<4>           ..X...XX................................ 3       3
    glb_add<3>           .X....XX................................ 3       3
    glb_add<2>           X.....XX................................ 3       3
    brd_sel_r            .....XXX................................ 3       3
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB4 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB4_1               (b)
    (unused)              0       0     0   5     FB4_2         2     GTS/I/O I
    (unused)              0       0     0   5     FB4_3               (b)
    (unused)              0       0     0   5     FB4_4               (b)
    (unused)              0       0     0   5     FB4_5         3     GTS/I/O I
    db<12>                5       0     0   0     FB4_6   STD   4     I/O     I/O
    (unused)              0       0     0   5     FB4_7               (b)
    (unused)              0       0     0   5     FB4_8         5     GTS/I/O
    (unused)              0       0     0   5     FB4_9               (b)
    (unused)              0       0     0   5     FB4_10              (b)
    (unused)              0       0     0   5     FB4_11              (b)
    (unused)              0       0     0   5     FB4_12        6     GTS/I/O I
    (unused)              0       0     0   5     FB4_13              (b)
    (unused)              0       0     0   5     FB4_14        7     I/O
    U1/q4                 1       0     0   4     FB4_15  STD         (b)     (b)
    U1/dssync             2       0     0   3     FB4_16  STD         (b)     (b)
    int_vec<7>            3       0     0   2     FB4_17  STD         (b)     (b)
    U2/r4                 3       0     0   2     FB4_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: U1/q2              8: ds0               14: glb_add<6>
      2: U1/q4              9: etr_p             15: intled
      3: U1/q7             10: glb_add<2>        16: pca_add<0>
      4: U1/q8             11: glb_add<3>        17: pca_add<1>
      5: U2/r3             12: glb_add<4>        18: db<7>.PIN
      6: ack_int           13: glb_add<5>        19: reset_p_OBUF$Q53
      7: brd_sel_r

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    db<12>               .....XX.X...XX.......................... 5       5
    U1/q4                X.X..................................... 2       2
    U1/dssync            ...X...X................................ 2       2
    int_vec<7>           XX....X..XXXXX.XXXX..................... 12      12
    U2/r4                ....X.........X...X..................... 3       3
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB5 ***********************************
    Number of function block inputs used/remaining:               23/31
    Number of signals used by logic mapping into function block:  23
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   \/3   2     FB5_1               (b)     (b)
    db<2>                11       6<-   0   0     FB5_2   STD   34    I/O     I/O
    (unused)              0       0   /\3   2     FB5_3               (b)     (b)
    (unused)              0       0     0   5     FB5_4               (b)
    on245                 0       0     0   5     FB5_5   STD   35    I/O     O
    (unused)              0       0     0   5     FB5_6               (b)
    (unused)              0       0     0   5     FB5_7               (b)
    (unused)              0       0     0   5     FB5_8         38    GCK/I/O
    (unused)              0       0     0   5     FB5_9               (b)
    pca_db<1>             2       0     0   3     FB5_10  STD   39    I/O     I/O
    (unused)              0       0   \/3   2     FB5_11              (b)     (b)
    db<3>                11       6<-   0   0     FB5_12  STD   40    I/O     I/O
    (unused)              0       0   /\3   2     FB5_13              (b)     (b)
    db<1>                11       6<-   0   0     FB5_14  STD   41    I/O     I/O
    (unused)              0       0   /\5   0     FB5_15        43    I/O     (b)
    (unused)              0       0   /\1   4     FB5_16              (b)     (b)
    (unused)              0       0     0   5     FB5_17        44    I/O
    (unused)              0       0     0   5     FB5_18              (b)

    Signals Used by Logic in Function Block
      1: pca_db<1>.PIN      9: etr_p             17: int_vec<3>
      2: pca_db<2>.PIN     10: glb_add<2>        18: intled
      3: pca_db<3>.PIN     11: glb_add<3>        19: pca_add<0>
      4: U1/q2             12: glb_add<4>        20: pca_add<1>
      5: U1/q4             13: glb_add<5>        21: db<1>.PIN
      6: ack_int           14: glb_add<6>        22: ttc_on
      7: brd_sel_r         15: int_vec<1>        23: was_off
      8: db_6_IOBUFE/db_6_IOBUFE_TRST
                           16: int_vec<2>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    db<2>                .X...XXXXXXXXX.X..XX.X.................. 14      14
    on245                ........................................ 0       0
    pca_db<1>            ...XX.X..XXXXX......X................... 9       9
    db<3>                ..X..XXXXXXXXX..X.XX..X................. 14      14
    db<1>                X....XXXXXXXXXX..XXX.................... 14      14
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB6 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB6_1               (b)
    (unused)              0       0     0   5     FB6_2         135   I/O     I
    pca_db<4>             2       0     0   3     FB6_3   STD   136   I/O     I/O
    (unused)              0       0     0   5     FB6_4               (b)
    (unused)              0       0     0   5     FB6_5         137   I/O
    irq<4>                1       0     0   4     FB6_6   STD   138   I/O     O
    (unused)              0       0     0   5     FB6_7               (b)
    (unused)              0       0     0   5     FB6_8         139   I/O     I
    (unused)              0       0     0   5     FB6_9               (b)
    (unused)              0       0     0   5     FB6_10        140   I/O
    (unused)              0       0     0   5     FB6_11              (b)
    (unused)              0       0     0   5     FB6_12              (b)
    (unused)              0       0     0   5     FB6_13              (b)
    db<11>                5       0     0   0     FB6_14  STD   142   I/O     I/O
    (unused)              0       0     0   5     FB6_15        143   GSR/I/O I
    (unused)              0       0     0   5     FB6_16              (b)
    int_vec<4>            3       0     0   2     FB6_17  STD         (b)     (b)
    int_lev<1>            3       0     0   2     FB6_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<9>.PIN          8: glb_add<3>        14: int_lev<2>
      2: U1/q2              9: glb_add<4>        15: intled
      3: U1/q4             10: glb_add<5>        16: pca_add<0>
      4: ack_int           11: glb_add<6>        17: pca_add<1>
      5: brd_sel_r         12: int_lev<0>        18: db<4>.PIN
      6: etr_p             13: int_lev<1>        19: reset_p_OBUF$Q53
      7: glb_add<2>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    pca_db<4>            .XX.X.XXXXX......X...................... 9       9
    irq<4>               ...........XXXX......................... 4       4
    db<11>               ...XXX...XX............................. 5       5
    int_vec<4>           .XX.X.XXXXX....XXXX..................... 12      12
    int_lev<1>           XXX.X.XXXXX....XX.X..................... 12      12
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB7 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB7_1               (b)
    (unused)              0       0   \/3   2     FB7_2               (b)     (b)
    db<4>                11       6<-   0   0     FB7_3   STD   45    I/O     I/O
    (unused)              0       0   /\3   2     FB7_4               (b)     (b)
    pca_db<5>             2       0     0   3     FB7_5   STD   46    I/O     I/O
    (unused)              0       0     0   5     FB7_6               (b)
    (unused)              0       0     0   5     FB7_7               (b)
    (unused)              0       0     0   5     FB7_8               (b)
    (unused)              0       0     0   5     FB7_9               (b)
    (unused)              0       0     0   5     FB7_10              (b)
    (unused)              0       0     0   5     FB7_11              (b)
    (unused)              0       0     0   5     FB7_12        48    I/O
    (unused)              0       0     0   5     FB7_13              (b)
    (unused)              0       0     0   5     FB7_14              (b)
    (unused)              0       0     0   5     FB7_15        49    I/O
    (unused)              0       0     0   5     FB7_16              (b)
    int_vec<5>            3       0     0   2     FB7_17  STD         (b)     (b)
    int_lev<0>            3       0     0   2     FB7_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: pca_db<4>.PIN      8: etr_p             14: int_ttc
      2: db<8>.PIN          9: glb_add<2>        15: int_vec<4>
      3: U1/q2             10: glb_add<3>        16: pca_add<0>
      4: U1/q4             11: glb_add<4>        17: pca_add<1>
      5: ack_int           12: glb_add<5>        18: db<5>.PIN
      6: brd_sel_r         13: glb_add<6>        19: reset_p_OBUF$Q53
      7: db_6_IOBUFE/db_6_IOBUFE_TRST

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    db<4>                X...XXXXXXXXXXXXX....................... 14      14
    pca_db<5>            ..XX.X..XXXXX....X...................... 9       9
    int_vec<5>           ..XX.X..XXXXX..XXXX..................... 12      12
    int_lev<0>           .XXX.X..XXXXX..XX.X..................... 12      12
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB8 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    U2/r7                 2       0     0   3     FB8_1   STD         (b)     (b)
    (unused)              0       0     0   5     FB8_2         130   I/O     I
    (unused)              0       0     0   5     FB8_3         131   I/O     I
    (unused)              0       0     0   5     FB8_4               (b)
    i2c_rd                1       0     0   4     FB8_5   STD   132   I/O     O
    (unused)              0       0     0   5     FB8_6               (b)
    (unused)              0       0     0   5     FB8_7               (b)
    (unused)              0       0     0   5     FB8_8         133   I/O
    (unused)              0       0     0   5     FB8_9               (b)
    (unused)              0       0     0   5     FB8_10        134   I/O
    (unused)              0       0     0   5     FB8_11              (b)
    (unused)              0       0     0   5     FB8_12              (b)
    (unused)              0       0     0   5     FB8_13              (b)
    U2/r6                 2       0     0   3     FB8_14  STD         (b)     (b)
    (unused)              0       0   \/5   0     FB8_15              (b)     (b)
    dtack_int            10       5<-   0   0     FB8_16  STD         (b)     (b)
    (unused)              0       0   \/5   0     FB8_17              (b)     (b)
    ack_int              10       5<-   0   0     FB8_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: U2/r4              8: brd_sel_r         14: glb_add<5>
      2: U2/r5              9: ds0               15: glb_add<6>
      3: U2/r6             10: etr_p             16: iack
      4: U2/r7             11: glb_add<2>        17: int_lev<0>
      5: add_in<0>         12: glb_add<3>        18: int_lev<1>
      6: add_in<1>         13: glb_add<4>        19: int_lev<2>
      7: add_in<2>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    U2/r7                ..X.....X............................... 2       2
    i2c_rd               .......X.XXXXXX......................... 7       7
    U2/r6                .X......X............................... 2       2
    dtack_int            X..XXXX.X......XXXX..................... 10      10
    ack_int              X.X.XXX.X......XXXX..................... 10      10
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB9 ***********************************
    Number of function block inputs used/remaining:               18/36
    Number of signals used by logic mapping into function block:  18
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB9_1               (b)
    (unused)              0       0   \/3   2     FB9_2         50    I/O     (b)
    db<5>                11       6<-   0   0     FB9_3   STD   51    I/O     I/O
    (unused)              0       0   /\3   2     FB9_4               (b)     (b)
    irq<1>                1       0     0   4     FB9_5   STD   52    I/O     O
    irq<2>                1       0     0   4     FB9_6   STD   53    I/O     O
    (unused)              0       0     0   5     FB9_7               (b)
    (unused)              0       0     0   5     FB9_8         54    I/O
    (unused)              0       0     0   5     FB9_9               (b)
    (unused)              0       0     0   5     FB9_10              (b)
    irq<5>                1       0     0   4     FB9_11  STD   56    I/O     O
    (unused)              0       0     0   5     FB9_12        57    I/O
    (unused)              0       0     0   5     FB9_13              (b)
    irq<6>                1       0     0   4     FB9_14  STD   58    I/O     O
    (unused)              0       0     0   5     FB9_15              (b)
    (unused)              0       0     0   5     FB9_16              (b)
    spare                 0       0     0   5     FB9_17  STD   59    I/O     O
    db_6_IOBUFE/db_6_IOBUFE_TRST
                          3       0     0   2     FB9_18  STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: pca_db<5>.PIN      7: glb_add<3>        13: int_lev<1>
      2: ack_int            8: glb_add<4>        14: int_lev<2>
      3: brd_sel_r          9: glb_add<5>        15: int_vec<5>
      4: db_6_IOBUFE/db_6_IOBUFE_TRST
                           10: glb_add<6>        16: intled
      5: etr_p             11: i2c_int           17: pca_add<0>
      6: glb_add<2>        12: int_lev<0>        18: pca_add<1>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    db<5>                XXXXXXXXXXX...X.XX...................... 14      14
    irq<1>               ...........XXX.X........................ 4       4
    irq<2>               ...........XXX.X........................ 4       4
    irq<5>               ...........XXX.X........................ 4       4
    irq<6>               ...........XXX.X........................ 4       4
    spare                ........................................ 0       0
    db_6_IOBUFE/db_6_IOBUFE_TRST
                         .XX.XXXXXX.............................. 8       8
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB10 ***********************************
    Number of function block inputs used/remaining:               29/25
    Number of signals used by logic mapping into function block:  29
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB10_1              (b)
    (unused)              0       0     0   5     FB10_2        117   I/O
    (unused)              0       0     0   5     FB10_3        118   I/O     I
    (unused)              0       0     0   5     FB10_4              (b)
    (unused)              0       0     0   5     FB10_5        119   I/O     I
    (unused)              0       0     0   5     FB10_6        120   I/O
    (unused)              0       0     0   5     FB10_7              (b)
    i2c_wr                1       0     0   4     FB10_8  STD   121   I/O     O
    (unused)              0       0     0   5     FB10_9              (b)
    (unused)              0       0     0   5     FB10_10       124   I/O     I
    tp1                   1       0   \/2   2     FB10_11 STD   125   I/O     O
    iackout              10       5<-   0   0     FB10_12 STD   126   I/O     O
    (unused)              0       0   /\3   2     FB10_13             (b)     (b)
    (unused)              0       0     0   5     FB10_14       128   I/O
    (unused)              0       0     0   5     FB10_15             (b)
    (unused)              0       0     0   5     FB10_16             (b)
    etr_p                 2       0     0   3     FB10_17 STD   129   I/O     O
    (unused)              0       0     0   5     FB10_18             (b)

    Signals Used by Logic in Function Block
      1: U1/dssync         11: am3               21: glb_add<4>
      2: U1/q2             12: am4               22: glb_add<5>
      3: U1/q4             13: am5               23: glb_add<6>
      4: U2/r4             14: as                24: iack
      5: U2/r7             15: brd_sel_r         25: int_lev<0>
      6: add_in<0>         16: ds0               26: int_lev<1>
      7: add_in<1>         17: ds1               27: int_lev<2>
      8: add_in<2>         18: etr_p             28: lword
      9: am0               19: glb_add<2>        29: write
     10: am1               20: glb_add<3>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    i2c_wr               .XX...........X...XXXXX................. 8       8
    tp1                  .XX..................................... 2       2
    iackout              ...XXXXX.....X.........XXXX............. 10      10
    etr_p                X.......XXXXX.XXXX.....X...XX........... 13      13
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB11 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB11_1              (b)
    (unused)              0       0     0   5     FB11_2              (b)
    (unused)              0       0     0   5     FB11_3        60    I/O     I
    (unused)              0       0     0   5     FB11_4              (b)
    irq<7>                1       0     0   4     FB11_5  STD   61    I/O     O
    (unused)              0       0     0   5     FB11_6              (b)
    (unused)              0       0     0   5     FB11_7              (b)
    (unused)              0       0     0   5     FB11_8              (b)
    (unused)              0       0     0   5     FB11_9              (b)
    (unused)              0       0     0   5     FB11_10       64    I/O
    (unused)              0       0     0   5     FB11_11       66    I/O
    pca_db<6>             2       0     0   3     FB11_12 STD   68    I/O     I/O
    (unused)              0       0     0   5     FB11_13             (b)
    irq<3>                1       0     0   4     FB11_14 STD   69    I/O     O
    int_vec<2>            3       0     0   2     FB11_15 STD         (b)     (b)
    int_vec<1>            3       0     0   2     FB11_16 STD         (b)     (b)
    pca_db<2>             2       0     0   3     FB11_17 STD   70    I/O     I/O
    int_lev<2>            3       0     0   2     FB11_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<10>.PIN         8: glb_add<5>        14: pca_add<0>
      2: U1/q2              9: glb_add<6>        15: pca_add<1>
      3: U1/q4             10: int_lev<0>        16: db<1>.PIN
      4: brd_sel_r         11: int_lev<1>        17: db<2>.PIN
      5: glb_add<2>        12: int_lev<2>        18: db<6>.PIN
      6: glb_add<3>        13: intled            19: reset_p_OBUF$Q53
      7: glb_add<4>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    irq<7>               .........XXXX........................... 4       4
    pca_db<6>            .XXXXXXXX........X...................... 9       9
    irq<3>               .........XXXX........................... 4       4
    int_vec<2>           .XXXXXXXX....XX.X.X..................... 12      12
    int_vec<1>           .XXXXXXXX....XXX..X..................... 12      12
    pca_db<2>            .XXXXXXXX.......X....................... 9       9
    int_lev<2>           XXXXXXXXX....XX...X..................... 12      12
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB12 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB12_1              (b)
    (unused)              0       0     0   5     FB12_2        110   I/O
    (unused)              0       0     0   5     FB12_3        111   I/O
    (unused)              0       0     0   5     FB12_4              (b)
    dtack                 1       0     0   4     FB12_5  STD   112   I/O     O
    (unused)              0       0     0   5     FB12_6              (b)
    (unused)              0       0     0   5     FB12_7              (b)
    (unused)              0       0     0   5     FB12_8        113   I/O     I
    (unused)              0       0     0   5     FB12_9              (b)
    enw_p                 1       0     0   4     FB12_10 STD   115   I/O     O
    (unused)              0       0     0   5     FB12_11             (b)
    (unused)              0       0     0   5     FB12_12       116   I/O     I
    (unused)              0       0     0   5     FB12_13             (b)
    U1/q9                 2       0     0   3     FB12_14 STD         (b)     (b)
    U1/q7                 2       0     0   3     FB12_15 STD         (b)     (b)
    U1/q1                 2       0     0   3     FB12_16 STD         (b)     (b)
    U1/q3                 3       0     0   2     FB12_17 STD         (b)     (b)
    U1/q2                 3       0     0   2     FB12_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: U1/dssync          8: am0               14: ds0
      2: U1/q1              9: am1               15: ds1
      3: U1/q2             10: am3               16: dtack_int
      4: U1/q3             11: am4               17: iack
      5: U1/q4             12: am5               18: lword
      6: U1/q6             13: brd_sel_r         19: write
      7: U1/q9

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    dtack                ....X..........X........................ 2       2
    enw_p                ..X.X................................... 2       2
    U1/q9                .....X.......XX......................... 3       3
    U1/q7                ......X......XX......................... 3       3
    U1/q1                XX.....XXXXXXXX.XXX..................... 13      13
    U1/q3                XX.X...XXXXXXXX.XXX..................... 14      14
    U1/q2                X.XX...XXXXXXXX.XXX..................... 14      14
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB13 ***********************************
    Number of function block inputs used/remaining:               19/35
    Number of signals used by logic mapping into function block:  19
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    int_vec<3>            3       0   \/1   1     FB13_1  STD         (b)     (b)
    db<6>                11       6<-   0   0     FB13_2  STD   71    I/O     I/O
    (unused)              0       0   /\5   0     FB13_3              (b)     (b)
    (unused)              0       0     0   5     FB13_4              (b)
    (unused)              0       0     0   5     FB13_5              (b)
    (unused)              0       0     0   5     FB13_6              (b)
    (unused)              0       0     0   5     FB13_7              (b)
    (unused)              0       0     0   5     FB13_8        74    I/O
    (unused)              0       0     0   5     FB13_9              (b)
    (unused)              0       0     0   5     FB13_10             (b)
    (unused)              0       0     0   5     FB13_11       75    I/O
    (unused)              0       0     0   5     FB13_12             (b)
    (unused)              0       0     0   5     FB13_13             (b)
    db<15>                5       0     0   0     FB13_14 STD   76    I/O     I/O
    (unused)              0       0     0   5     FB13_15       77    I/O     I
    (unused)              0       0   \/2   3     FB13_16             (b)     (b)
    was_off              12       7<-   0   0     FB13_17 STD   78    I/O     (b)
    (unused)              0       0   /\5   0     FB13_18             (b)     (b)

    Signals Used by Logic in Function Block
      1: pca_db<6>.PIN      8: glb_add<2>        14: pca_add<0>
      2: U1/q2              9: glb_add<3>        15: pca_add<1>
      3: U1/q4             10: glb_add<4>        16: db<3>.PIN
      4: ack_int           11: glb_add<5>        17: reset_p_OBUF$Q53
      5: brd_sel_r         12: glb_add<6>        18: ttc_on
      6: db_6_IOBUFE/db_6_IOBUFE_TRST
                           13: int_vec<6>        19: was_off
      7: etr_p

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    int_vec<3>           .XX.X..XXXXX.XXXX....................... 12      12
    db<6>                X..XXXXXXXXXXXX......................... 13      13
    db<15>               ...XX.X...XX............................ 5       5
    was_off              .XX.X..XXXXX.XXXXXX..................... 14      14
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB14 ***********************************
    Number of function block inputs used/remaining:               21/33
    Number of signals used by logic mapping into function block:  21
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB14_1              (b)
    (unused)              0       0   \/1   4     FB14_2              (b)     (b)
    db<8>                 7       2<-   0   0     FB14_3  STD   100   I/O     I/O
    (unused)              0       0   /\1   4     FB14_4              (b)     (b)
    (unused)              0       0     0   5     FB14_5        101   I/O
    pca_add<0>            2       0     0   3     FB14_6  STD   102   I/O     O
    (unused)              0       0     0   5     FB14_7              (b)
    (unused)              0       0     0   5     FB14_8        103   I/O     I
    (unused)              0       0   \/1   4     FB14_9              (b)     (b)
    db<9>                 6       1<-   0   0     FB14_10 STD   104   I/O     I/O
    (unused)              0       0     0   5     FB14_11       105   I/O     I
    (unused)              0       0     0   5     FB14_12             (b)
    (unused)              0       0     0   5     FB14_13             (b)
    intled                3       0     0   2     FB14_14 STD   106   I/O     O
    (unused)              0       0     0   5     FB14_15       107   I/O
    (unused)              0       0     0   5     FB14_16             (b)
    (unused)              0       0     0   5     FB14_17             (b)
    (unused)              0       0     0   5     FB14_18             (b)

    Signals Used by Logic in Function Block
      1: ack_int            8: glb_add<2>        15: int_lev<1>
      2: add_in<0>          9: glb_add<3>        16: int_ttc
      3: brd_sel_r         10: glb_add<4>        17: intled
      4: ds0               11: glb_add<5>        18: local_clk_reg
      5: ds1               12: glb_add<6>        19: pca_add<0>
      6: dtack_int         13: int_ena           20: pca_add<1>
      7: etr_p             14: int_lev<0>        21: reset_p_OBUF$Q53

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    db<8>                X.X...XXXXXX.X...XXX.................... 12      12
    pca_add<0>           .X.XX................................... 3       3
    db<9>                X.X...XXXXXX..X...XX.................... 11      11
    intled               .....X......X..XX...X................... 5       5
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB15 ***********************************
    Number of function block inputs used/remaining:               20/34
    Number of signals used by logic mapping into function block:  20
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0     0   5     FB15_1              (b)
    (unused)              0       0     0   5     FB15_2        79    I/O     I
    g245                  1       0     0   4     FB15_3  STD   80    I/O     O
    (unused)              0       0     0   5     FB15_4              (b)
    (unused)              0       0     0   5     FB15_5              (b)
    (unused)              0       0     0   5     FB15_6              (b)
    (unused)              0       0     0   5     FB15_7              (b)
    pca_db<7>             2       0     0   3     FB15_8  STD   81    I/O     I/O
    (unused)              0       0     0   5     FB15_9              (b)
    (unused)              0       0     0   5     FB15_10       82    I/O     I
    (unused)              0       0     0   5     FB15_11       83    I/O
    (unused)              0       0     0   5     FB15_12       85    I/O
    (unused)              0       0     0   5     FB15_13             (b)
    (unused)              0       0     0   5     FB15_14       86    I/O     I
    tp3                   1       0     0   4     FB15_15 STD   87    I/O     O
    (unused)              0       0     0   5     FB15_16             (b)
    (unused)              0       0     0   5     FB15_17       88    I/O
    reset_p_OBUF$Q53      2       0     0   3     FB15_18 STD         (b)     (b)

    Signals Used by Logic in Function Block
      1: db<11>.PIN         8: U1/q4             15: glb_add<5>
      2: db<12>.PIN         9: ack_int           16: glb_add<6>
      3: db<13>.PIN        10: brd_sel_r         17: pca_add<0>
      4: db<14>.PIN        11: etr_p             18: pca_add<1>
      5: db<15>.PIN        12: glb_add<2>        19: db<7>.PIN
      6: U1/q1             13: glb_add<3>        20: sysreset
      7: U1/q2             14: glb_add<4>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    g245                 .....X..X.X............................. 3       3
    pca_db<7>            ......XX.X.XXXXX..X..................... 9       9
    tp3                  XXXXX................................... 5       5
    reset_p_OBUF$Q53     ....X.XX.X.XXXXXXX.X.................... 12      12
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    *********************************** FB16 ***********************************
    Number of function block inputs used/remaining:               24/30
    Number of signals used by logic mapping into function block:  24
    Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
    (unused)              0       0   \/5   0     FB16_1              (b)     (b)
    db<0>                11       6<-   0   0     FB16_2  STD   91    I/O     I/O
    db<7>                11       7<- /\1   0     FB16_3  STD   92    I/O     I/O
    (unused)              0       0   /\5   0     FB16_4              (b)     (b)
    (unused)              0       0   /\2   3     FB16_5        93    I/O     (b)
    pca_db<3>             2       0     0   3     FB16_6  STD   94    I/O     I/O
    (unused)              0       0     0   5     FB16_7              (b)
    (unused)              0       0     0   5     FB16_8        95    I/O
    (unused)              0       0   \/1   4     FB16_9              (b)     (b)
    db<10>                6       1<-   0   0     FB16_10 STD   96    I/O     I/O
    pca_add<1>            2       0     0   3     FB16_11 STD   97    I/O     O
    (unused)              0       0     0   5     FB16_12       98    I/O
    (unused)              0       0     0   5     FB16_13             (b)
    (unused)              0       0     0   5     FB16_14             (b)
    (unused)              0       0     0   5     FB16_15             (b)
    (unused)              0       0     0   5     FB16_16             (b)
    (unused)              0       0     0   5     FB16_17             (b)
    (unused)              0       0     0   5     FB16_18             (b)

    Signals Used by Logic in Function Block
      1: pca_db<0>.PIN      9: ds0               17: int_ena
      2: pca_db<7>.PIN     10: ds1               18: int_lev<2>
      3: U1/q2             11: etr_p             19: int_vec<0>
      4: U1/q4             12: glb_add<2>        20: int_vec<7>
      5: ack_int           13: glb_add<3>        21: local_clk
      6: add_in<1>         14: glb_add<4>        22: pca_add<0>
      7: brd_sel_r         15: glb_add<5>        23: pca_add<1>
      8: db_6_IOBUFE/db_6_IOBUFE_TRST
                           16: glb_add<6>        24: db<3>.PIN

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    db<0>                X...X.XX..XXXXXXX.X..XX................. 14      14
    db<7>                .X..X.XX..XXXXXX...XXXX................. 14      14
    pca_db<3>            ..XX..X....XXXXX.......X................ 9       9
    db<10>               ....X.X...XXXXXX.X...XX................. 11      11
    pca_add<1>           .....X..XX.............................. 3       3
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pwr Mode     - Macrocell power mode
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@) - Signal used as input (wire-AND input) to the macrocell logic.
        The number of Signals Used may exceed the number of FB Inputs Used due
        to wire-ANDing in the switch matrix.
    ;;-----------------------------------------------------------------;;
    ; Implemented Equations.

    FDCPE_U1/dssync: FDCPE port map (U1/dssync,U1/q8,clk,ds0,'0');

    FTCPE_U1/q1: FTCPE port map (U1/q1,U1/q1_T,clk,U1/q1_CLR,'0');
    U1/q1_T <= (iack AND lword AND am3 AND NOT write AND NOT U1/q1 AND
    	U1/dssync AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1);
    U1/q1_CLR <= (ds0 AND ds1);

    FTCPE_U1/q2: FTCPE port map (U1/q2,U1/q2_T,clk,U1/q2_CLR,'0');
    U1/q2_T <= ((iack AND lword AND am3 AND NOT write AND U1/q2 AND
    	U1/dssync AND NOT U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1)
    	OR (iack AND lword AND am3 AND NOT write AND NOT U1/q2 AND
    	U1/dssync AND U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1));
    U1/q2_CLR <= (ds0 AND ds1);

    FTCPE_U1/q3: FTCPE port map (U1/q3,U1/q3_T,clk,U1/q3_CLR,'0');
    U1/q3_T <= ((iack AND lword AND am3 AND NOT write AND U1/q1 AND
    	U1/dssync AND NOT U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1)
    	OR (iack AND lword AND am3 AND NOT write AND NOT U1/q1 AND
    	U1/dssync AND U1/q3 AND NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1));
    U1/q3_CLR <= (ds0 AND ds1);

    FDCPE_U1/q4: FDCPE port map (U1/q4,U1/q4_D,clk,'0','0');
    U1/q4_D <= (NOT U1/q2 AND NOT U1/q7);

    FDCPE_U1/q6: FDCPE port map (U1/q6,NOT etr_p,clk,U1/q6_CLR,'0');
    U1/q6_CLR <= (ds0 AND ds1);

    FDCPE_U1/q7: FDCPE port map (U1/q7,U1/q9,clk,U1/q7_CLR,'0');
    U1/q7_CLR <= (ds0 AND ds1);

    FDCPE_U1/q8: FDCPE port map (U1/q8,U1/q8_D,clk,'0','0');
    U1/q8_D <= (NOT ds0 AND NOT ds1);

    FDCPE_U1/q9: FDCPE port map (U1/q9,U1/q6,clk,U1/q9_CLR,'0');
    U1/q9_CLR <= (ds0 AND ds1);

    FDCPE_U2/r3: FDCPE port map (U2/r3,ds0,clk,reset_p_OBUF$Q53,'0');

    FDCPE_U2/r4: FDCPE port map (U2/r4,NOT intled,clk,reset_p_OBUF$Q53,'0',U2/r3);

    FDCPE_U2/r5: FDCPE port map (U2/r5,NOT iackin,clk,ds0,'0');

    FDCPE_U2/r6: FDCPE port map (U2/r6,U2/r5,clk,ds0,'0');

    FDCPE_U2/r7: FDCPE port map (U2/r7,U2/r6,clk,ds0,'0');

    FDCPE_ack_int: FDCPE port map (ack_int,ack_int_D,clk,ds0,'0',U2/r6);
    ack_int_D <= ((EXP29_.EXP)
    	OR (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND add_in(0) AND add_in(1) AND add_in(2))
    	OR (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND add_in(0) AND NOT add_in(1) AND add_in(2))
    	OR (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND NOT add_in(0) AND add_in(1) AND add_in(2)));

    FDCPE_brd_sel_r: FDCPE port map (brd_sel_r,'0','0',brd_sel_r_CLR,brd_sel_r_PRE);
    brd_sel_r_CLR <= (ds0 AND ds1 AND NOT brd_sel);
    brd_sel_r_PRE <= (ds0 AND ds1 AND brd_sel);

    db_I(0) <= NOT (((EXP39_.EXP)
    	OR (db_7_IOBUFE.EXP)
    	OR (ack_int AND NOT int_vec(0) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(0) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(0) AND glb_add(6))
    	OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT etr_p)));
    db(0) <= db_I(0) when db_OE(0) = '1' else 'Z';
    db_OE(0) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_I(1) <= NOT (((EXP24_.EXP)
    	OR (ack_int AND NOT int_vec(1) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(1) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(1) AND glb_add(6))
    	OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT etr_p)));
    db(1) <= db_I(1) when db_OE(1) = '1' else 'Z';
    db_OE(1) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_I(2) <= NOT (((EXP20_.EXP)
    	OR (EXP21_.EXP)
    	OR (ack_int AND NOT int_vec(2) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(2) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(2) AND glb_add(6))
    	OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT etr_p)));
    db(2) <= db_I(2) when db_OE(2) = '1' else 'Z';
    db_OE(2) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_I(3) <= NOT (((EXP22_.EXP)
    	OR (EXP23_.EXP)
    	OR (ack_int AND NOT int_vec(3) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(3) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(3) AND glb_add(6))
    	OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT etr_p)));
    db(3) <= db_I(3) when db_OE(3) = '1' else 'Z';
    db_OE(3) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_I(4) <= NOT (((EXP26_.EXP)
    	OR (EXP27_.EXP)
    	OR (ack_int AND NOT int_vec(4) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(4) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(4) AND glb_add(6))
    	OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT etr_p)));
    db(4) <= db_I(4) when db_OE(4) = '1' else 'Z';
    db_OE(4) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_I(5) <= NOT (((EXP30_.EXP)
    	OR (EXP31_.EXP)
    	OR (ack_int AND NOT int_vec(5) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(5) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(5) AND glb_add(6))
    	OR (glb_add(2) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT etr_p)));
    db(5) <= db_I(5) when db_OE(5) = '1' else 'Z';
    db_OE(5) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_I(6) <= NOT (((int_vec(3).EXP)
    	OR (EXP33_.EXP)
    	OR (ack_int AND NOT int_vec(6) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(6) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(6) AND glb_add(6))
    	OR (NOT pca_add(0) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT etr_p)));
    db(6) <= db_I(6) when db_OE(6) = '1' else 'Z';
    db_OE(6) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_6_IOBUFE/db_6_IOBUFE_TRST <= ((ack_int)
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p)
    	OR (NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND NOT etr_p));

    db_I(7) <= NOT (((EXP40_.EXP)
    	OR (ack_int AND NOT int_vec(7) AND brd_sel_r)
    	OR (ack_int AND NOT int_vec(7) AND glb_add(5))
    	OR (ack_int AND NOT int_vec(7) AND glb_add(6))));
    db(7) <= db_I(7) when db_OE(7) = '1' else 'Z';
    db_OE(7) <= db_6_IOBUFE/db_6_IOBUFE_TRST;

    db_I(10) <= ((EXP42_.EXP)
    	OR (NOT ack_int AND brd_sel_r)
    	OR (NOT ack_int AND glb_add(5))
    	OR (NOT ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND etr_p));
    db(10) <= db_I(10) when db_OE(10) = '1' else 'Z';
    db_OE(10) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    db_I(11) <= NOT (((ack_int AND brd_sel_r)
    	OR (ack_int AND glb_add(5))
    	OR (ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p)));
    db(11) <= db_I(11) when db_OE(11) = '1' else 'Z';
    db_OE(11) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    db_I(12) <= NOT (((ack_int AND brd_sel_r)
    	OR (ack_int AND glb_add(5))
    	OR (ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p)));
    db(12) <= db_I(12) when db_OE(12) = '1' else 'Z';
    db_OE(12) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    db_I(13) <= NOT (((ack_int AND brd_sel_r)
    	OR (ack_int AND glb_add(5))
    	OR (ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p)));
    db(13) <= db_I(13) when db_OE(13) = '1' else 'Z';
    db_OE(13) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    db_I(14) <= NOT (((ack_int AND brd_sel_r)
    	OR (ack_int AND glb_add(5))
    	OR (ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p)));
    db(14) <= db_I(14) when db_OE(14) = '1' else 'Z';
    db_OE(14) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    db_I(15) <= NOT (((ack_int AND brd_sel_r)
    	OR (ack_int AND glb_add(5))
    	OR (ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p)));
    db(15) <= db_I(15) when db_OE(15) = '1' else 'Z';
    db_OE(15) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    db_I(8) <= ((EXP36_.EXP)
    	OR (EXP37_.EXP)
    	OR (NOT ack_int AND brd_sel_r)
    	OR (NOT ack_int AND glb_add(5))
    	OR (NOT ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND etr_p));
    db(8) <= db_I(8) when db_OE(8) = '1' else 'Z';
    db_OE(8) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    db_I(9) <= ((EXP38_.EXP)
    	OR (NOT ack_int AND brd_sel_r)
    	OR (NOT ack_int AND glb_add(5))
    	OR (NOT ack_int AND glb_add(6))
    	OR (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND etr_p));
    db(9) <= db_I(9) when db_OE(9) = '1' else 'Z';
    db_OE(9) <= (NOT brd_sel_r AND NOT glb_add(5) AND NOT glb_add(6) AND NOT etr_p);

    dtack <= NOT ((NOT dtack_int AND NOT U1/q4));

    FDCPE_dtack_int: FDCPE port map (dtack_int,dtack_int_D,clk,ds0,'0',U2/r7);
    dtack_int_D <= ((EXP28_.EXP)
    	OR (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND add_in(0) AND add_in(1) AND add_in(2))
    	OR (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND add_in(0) AND NOT add_in(1) AND add_in(2))
    	OR (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND NOT add_in(0) AND add_in(1) AND add_in(2)));

    FTCPE_etr_p: FTCPE port map (etr_p,etr_p_T,clk,'0',etr_p_PRE);
    etr_p_T <= (iack AND lword AND am3 AND write AND U1/dssync AND
    	NOT brd_sel_r AND am5 AND am0 AND NOT am4 AND NOT am1 AND etr_p);
    etr_p_PRE <= (ds0 AND ds1);

    g245 <= (NOT ack_int AND NOT U1/q1 AND etr_p);

    FDCPE_pca_add0: FDCPE port map (pca_add(0),'0','0',pca_add_CLR(0),pca_add_PRE(0));
    pca_add_CLR(0) <= (ds0 AND ds1 AND NOT add_in(0));
    pca_add_PRE(0) <= (ds0 AND ds1 AND add_in(0));

    FDCPE_pca_add1: FDCPE port map (pca_add(1),'0','0',pca_add_CLR(1),pca_add_PRE(1));
    pca_add_CLR(1) <= (ds0 AND ds1 AND NOT add_in(1));
    pca_add_PRE(1) <= (ds0 AND ds1 AND add_in(1));

    FDCPE_glb_add2: FDCPE port map (glb_add(2),'0','0',glb_add_CLR(2),glb_add_PRE(2));
    glb_add_CLR(2) <= (ds0 AND ds1 AND NOT add_in(2));
    glb_add_PRE(2) <= (ds0 AND ds1 AND add_in(2));

    FDCPE_glb_add3: FDCPE port map (glb_add(3),'0','0',glb_add_CLR(3),glb_add_PRE(3));
    glb_add_CLR(3) <= (ds0 AND ds1 AND NOT add_in(3));
    glb_add_PRE(3) <= (ds0 AND ds1 AND add_in(3));

    FDCPE_glb_add4: FDCPE port map (glb_add(4),'0','0',glb_add_CLR(4),glb_add_PRE(4));
    glb_add_CLR(4) <= (ds0 AND ds1 AND NOT add_in(4));
    glb_add_PRE(4) <= (ds0 AND ds1 AND add_in(4));

    FDCPE_glb_add5: FDCPE port map (glb_add(5),'0','0',glb_add_CLR(5),glb_add_PRE(5));
    glb_add_CLR(5) <= (ds0 AND ds1 AND NOT add_in(5));
    glb_add_PRE(5) <= (ds0 AND ds1 AND add_in(5));

    FDCPE_glb_add6: FDCPE port map (glb_add(6),'0','0',glb_add_CLR(6),glb_add_PRE(6));
    glb_add_CLR(6) <= (ds0 AND ds1 AND NOT add_in(6));
    glb_add_PRE(6) <= (ds0 AND ds1 AND add_in(6));

    i2c_ce0 <= NOT ((NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6)));

    i2c_ce1 <= NOT ((glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6)));

    i2c_rd <= NOT ((NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT etr_p));

    i2c_rst <= NOT (((NOT sysreset)
    	OR (db(6).PIN AND U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND
    	NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND
    	NOT glb_add(5) AND NOT glb_add(6) AND NOT U1/q4)
    	OR (U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4 AND db(15).PIN)));

    i2c_wr <= NOT ((U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4));

    FDCPE_iackout: FDCPE port map (iackout,iackout_D,clk,'0',as,U2/r7);
    iackout_D <= ((tp1_OBUF.EXP)
    	OR (EXP32_.EXP)
    	OR (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND add_in(0) AND add_in(1) AND add_in(2))
    	OR (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND add_in(0) AND NOT add_in(1) AND add_in(2))
    	OR (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT iack AND
    	U2/r4 AND NOT add_in(0) AND add_in(1) AND add_in(2)));

    FDCPE_int_ena: FDCPE port map (int_ena,int_ena_D,clk,reset_p_OBUF$Q53,'0');
    int_ena_D <= ((int_vec(0).EXP)
    	OR (EXP18_.EXP)
    	OR (NOT U1/q2 AND int_ena AND intled)
    	OR (int_ena AND brd_sel_r AND intled)
    	OR (int_ena AND glb_add(5) AND intled)
    	OR (int_ena AND glb_add(6) AND intled));

    FDCPE_int_lev0: FDCPE port map (int_lev(0),db(8).PIN,clk,'0',reset_p_OBUF$Q53,int_lev_CE(0));
    int_lev_CE(0) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_lev1: FDCPE port map (int_lev(1),db(9).PIN,clk,reset_p_OBUF$Q53,'0',int_lev_CE(1));
    int_lev_CE(1) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_lev2: FDCPE port map (int_lev(2),db(10).PIN,clk,reset_p_OBUF$Q53,'0',int_lev_CE(2));
    int_lev_CE(2) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec0: FDCPE port map (int_vec(0),db(0).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(0));
    int_vec_CE(0) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec1: FDCPE port map (int_vec(1),db(1).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(1));
    int_vec_CE(1) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec2: FDCPE port map (int_vec(2),db(2).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(2));
    int_vec_CE(2) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec3: FDCPE port map (int_vec(3),db(3).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(3));
    int_vec_CE(3) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec4: FDCPE port map (int_vec(4),db(4).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(4));
    int_vec_CE(4) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec5: FDCPE port map (int_vec(5),db(5).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(5));
    int_vec_CE(5) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec6: FDCPE port map (int_vec(6),db(6).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(6));
    int_vec_CE(6) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_int_vec7: FDCPE port map (int_vec(7),db(7).PIN,clk,reset_p_OBUF$Q53,'0',int_vec_CE(7));
    int_vec_CE(7) <= (U1/q2 AND pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4);

    FDCPE_intled: FDCPE port map (intled,intled_D,clk,'0',reset_p_OBUF$Q53);
    intled_D <= ((NOT dtack_int AND NOT intled)
    	OR (NOT dtack_int AND int_ena AND int_ttc));

    irq(1) <= (int_lev(0) AND NOT int_lev(1) AND NOT int_lev(2) AND NOT intled);

    irq(2) <= (NOT int_lev(0) AND int_lev(1) AND NOT int_lev(2) AND NOT intled);

    irq(3) <= (int_lev(0) AND int_lev(1) AND NOT int_lev(2) AND NOT intled);

    irq(4) <= (NOT int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT intled);

    irq(5) <= (int_lev(0) AND NOT int_lev(1) AND int_lev(2) AND NOT intled);

    irq(6) <= (NOT int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT intled);

    irq(7) <= (int_lev(0) AND int_lev(1) AND int_lev(2) AND NOT intled);

    FDCPE_local_clk_reg: FDCPE port map (local_clk_reg,local_clk_reg_D,clk,reset_p_OBUF$Q53,'0');
    local_clk_reg_D <= ((EXP19_.EXP)
    	OR (U1/q6.EXP)
    	OR (NOT local_clk_reg AND NOT U1/q2 AND NOT local_clk)
    	OR (NOT local_clk_reg AND brd_sel_r AND NOT local_clk)
    	OR (NOT local_clk_reg AND glb_add(5) AND NOT local_clk)
    	OR (NOT local_clk_reg AND glb_add(6) AND NOT local_clk));

    spare <= '0';

    on245 <= '0';

    pca_db_I(0) <= db(0).PIN;
    pca_db(0) <= pca_db_I(0) when pca_db_OE(0) = '1' else 'Z';
    pca_db_OE(0) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    pca_db_I(1) <= db(1).PIN;
    pca_db(1) <= pca_db_I(1) when pca_db_OE(1) = '1' else 'Z';
    pca_db_OE(1) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    pca_db_I(2) <= db(2).PIN;
    pca_db(2) <= pca_db_I(2) when pca_db_OE(2) = '1' else 'Z';
    pca_db_OE(2) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    pca_db_I(3) <= db(3).PIN;
    pca_db(3) <= pca_db_I(3) when pca_db_OE(3) = '1' else 'Z';
    pca_db_OE(3) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    pca_db_I(4) <= db(4).PIN;
    pca_db(4) <= pca_db_I(4) when pca_db_OE(4) = '1' else 'Z';
    pca_db_OE(4) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    pca_db_I(5) <= db(5).PIN;
    pca_db(5) <= pca_db_I(5) when pca_db_OE(5) = '1' else 'Z';
    pca_db_OE(5) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    pca_db_I(6) <= db(6).PIN;
    pca_db(6) <= pca_db_I(6) when pca_db_OE(6) = '1' else 'Z';
    pca_db_OE(6) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    pca_db_I(7) <= db(7).PIN;
    pca_db(7) <= pca_db_I(7) when pca_db_OE(7) = '1' else 'Z';
    pca_db_OE(7) <= (U1/q2 AND NOT glb_add(2) AND NOT glb_add(3) AND NOT glb_add(4) AND
    	NOT brd_sel_r AND NOT glb_add(5) AND glb_add(6) AND NOT U1/q4);

    reset_p <= ((NOT sysreset)
    	OR (U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4 AND db(15).PIN));

    reset_p_OBUF$Q53 <= ((NOT sysreset)
    	OR (U1/q2 AND NOT pca_add(0) AND NOT pca_add(1) AND NOT glb_add(2) AND
    	NOT glb_add(3) AND NOT glb_add(4) AND NOT brd_sel_r AND NOT glb_add(5) AND
    	NOT glb_add(6) AND NOT U1/q4 AND db(15).PIN));

    tp1 <= (U1/q2 AND NOT U1/q4);

    enw_p <= (U1/q2 AND NOT U1/q4);

    tp3 <= NOT ((NOT db(15).PIN AND NOT db(14).PIN AND NOT db(13).PIN AND
    	NOT db(12).PIN AND NOT db(11).PIN));

    ttc_sel <= ((NOT ds0 AND NOT brd_sel_r AND glb_add(5) AND NOT glb_add(6))
    	OR (NOT ds1 AND NOT brd_sel_r AND glb_add(5) AND NOT glb_add(6)));

    w245 <= write;

    FDCPE_was_off: FDCPE port map (was_off,was_off_D,clk,reset_p_OBUF$Q53,'0');
    was_off_D <= ((EXP34_.EXP)
    	OR (EXP35_.EXP)
    	OR (NOT was_off AND NOT U1/q2 AND ttc_on)
    	OR (NOT was_off AND brd_sel_r AND ttc_on)
    	OR (NOT was_off AND glb_add(5) AND ttc_on)
    	OR (NOT was_off AND glb_add(6) AND ttc_on));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ****************************  Device Pin Out ****************************

    Device : XC95288XL-6-TQ144

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 VCC                              73 VCC
      2 am1                              74 TIE
      3 sysreset                         75 TIE
      4 db<12>                           76 db<15>
      5 TIE                              77 add_in<2>
      6 brd_sel                          78 TIE
      7 TIE                              79 write
      8 VCC                              80 g245
      9 i2c_ce0                          81 pca_db<7>
     10 add_in<6>                        82 add_in<1>
     11 ttc_sel                          83 TIE
     12 am5                              84 VCC
     13 TIE                              85 TIE
     14 w245                             86 int_ttc
     15 db<13>                           87 tp3
     16 TIE                              88 TIE
     17 TIE                              89 GND
     18 GND                              90 GND
     19 TIE                              91 db<0>
     20 am0                              92 db<7>
     21 db<14>                           93 TIE
     22 pca_db<0>                        94 pca_db<3>
     23 i2c_rst                          95 TIE
     24 i2c_ce1                          96 db<10>
     25 reset_p                          97 pca_add<1>
     26 TIE                              98 TIE
     27 TIE                              99 GND
     28 local_clk                       100 db<8>
     29 GND                             101 TIE
     30 clk                             102 pca_add<0>
     31 TIE                             103 ds1
     32 TIE                             104 db<9>
     33 add_in<3>                       105 iackin
     34 db<2>                           106 intled
     35 on245                           107 TIE
     36 GND                             108 GND
     37 VCC                             109 VCC
     38 TIE                             110 TIE
     39 pca_db<1>                       111 TIE
     40 db<3>                           112 dtack
     41 db<1>                           113 lword
     42 VCC                             114 GND
     43 TIE                             115 enw_p
     44 TIE                             116 ttc_on
     45 db<4>                           117 TIE
     46 pca_db<5>                       118 add_in<5>
     47 GND                             119 as
     48 TIE                             120 TIE
     49 TIE                             121 i2c_wr
     50 TIE                             122 TDO
     51 db<5>                           123 GND
     52 irq<1>                          124 add_in<4>
     53 irq<2>                          125 tp1
     54 TIE                             126 iackout
     55 VCC                             127 VCC
     56 irq<5>                          128 TIE
     57 TIE                             129 etr_p
     58 irq<6>                          130 iack
     59 spare                           131 i2c_int
     60 add_in<0>                       132 i2c_rd
     61 irq<7>                          133 TIE
     62 GND                             134 TIE
     63 TDI                             135 am3
     64 TIE                             136 pca_db<4>
     65 TMS                             137 TIE
     66 TIE                             138 irq<4>
     67 TCK                             139 am4
     68 pca_db<6>                       140 TIE
     69 irq<3>                          141 VCC
     70 pca_db<2>                       142 db<11>
     71 db<6>                           143 ds0
     72 GND                             144 GND

    Legend :  NC  = Not Connected, unbonded pin
             PGND = Unused I/O configured as additional Ground pin
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
             PE   = Port Enable pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc95288xl-6-TQ144
    Optimization Method                         : SPEED
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Power Mode                                  : STD
    Set Unused I/O Pin Termination              : FLOAT
    Set I/O Pin Termination                     : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Input Limit                                 : 54
    Pterm Limit                                 : 25